[Qemu-devel] [PULL 0/2] target-arm queue
[PULL 0/3] target-arm queue
1
Couple of minor patches to sneak in before rc0. The PSCI return
1
Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
2
values fix is the most important one.
3
2
4
-- PMM
3
-- PMM
5
4
6
The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9:
5
The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
7
6
8
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000)
7
Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
9
8
10
are available in the git repository at:
9
are available in the Git repository at:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
13
12
14
for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02:
13
for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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14
16
target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000)
15
target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
target-arm queue:
18
target-arm queue:
20
* arm-powerctl: Fix psci info return values
19
* Fix KVM SVE ID register probe code
21
* implement armv8 PMUSERENR (user-mode enable bits)
22
20
23
----------------------------------------------------------------
21
----------------------------------------------------------------
24
Andrew Baumann (1):
22
Richard Henderson (3):
25
target/arm: implement armv8 PMUSERENR (user-mode enable bits)
23
target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
24
target/arm: Set KVM_ARM_VCPU_SVE while probing the host
25
target/arm: Move sve probe inside kvm >= 4.15 branch
26
26
27
Andrew Jones (1):
27
target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
28
target/arm/arm-powerctl: Fix psci info return values
28
1 file changed, 22 insertions(+), 23 deletions(-)
29
30
target/arm/cpu.h | 4 +--
31
target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
32
2 files changed, 73 insertions(+), 10 deletions(-)
33
diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Indication for support for SVE will not depend on whether we
4
perform the query on the main kvm_state or the temp vcpu.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/kvm64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/kvm64.c
17
+++ b/target/arm/kvm64.c
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
20
}
21
22
- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
23
+ sve_supported = kvm_arm_sve_supported();
24
25
/* Add feature bits that can't appear until after VCPU init. */
26
if (sve_supported) {
27
--
28
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits)
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
1
From: Andrew Baumann <Andrew.Baumann@microsoft.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In armv8, this register implements more than a single bit, with
3
Because we weren't setting this flag, our probe of ID_AA64ZFR0
4
fine-grained enables for read access to event counters, cycles
4
was always returning zero. This also obviates the adjustment
5
counters, and write access to the software increment. This change
5
of ID_AA64PFR0, which had sanitized the SVE field.
6
implements those checks using custom access functions for the relevant
7
registers.
8
6
9
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
7
The effects of the bug are not visible, because the only thing that
10
Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com
8
ID_AA64ZFR0 is used for within qemu at present is tcg translation.
9
The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
10
11
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: move a couple of access functions to be only compiled
13
ifndef CONFIG_USER_ONLY to avoid compiler warnings]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
---
16
target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
17
target/arm/kvm64.c | 27 +++++++++++++--------------
17
1 file changed, 71 insertions(+), 8 deletions(-)
18
1 file changed, 13 insertions(+), 14 deletions(-)
18
19
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
20
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
--- a/target/arm/kvm64.c
22
+++ b/target/arm/helper.c
23
+++ b/target/arm/kvm64.c
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
24
*/
25
bool sve_supported;
25
int el = arm_current_el(env);
26
bool pmu_supported = false;
26
27
uint64_t features = 0;
27
- if (el == 0 && !env->cp15.c9_pmuserenr) {
28
- uint64_t t;
28
+ if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
29
int err;
29
return CP_ACCESS_TRAP;
30
30
}
31
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
31
if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
32
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
33
struct kvm_vcpu_init init = { .target = -1, };
33
return CP_ACCESS_OK;
34
34
}
35
/*
35
36
- * Ask for Pointer Authentication if supported. We can't play the
36
+static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
37
- * SVE trick of synthesising the ID reg as KVM won't tell us
37
+ const ARMCPRegInfo *ri,
38
- * whether we have the architected or IMPDEF version of PAuth, so
38
+ bool isread)
39
- * we have to use the actual ID regs.
39
+{
40
+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
40
+ /* ER: event counter read trap control */
41
+ * which is otherwise RAZ.
41
+ if (arm_feature(env, ARM_FEATURE_V8)
42
+ */
42
+ && arm_current_el(env) == 0
43
+ sve_supported = kvm_arm_sve_supported();
43
+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
44
+ if (sve_supported) {
44
+ && isread) {
45
+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
45
+ return CP_ACCESS_OK;
46
+ }
46
+ }
47
+
47
+
48
+ return pmreg_access(env, ri, isread);
48
+ /*
49
+}
49
+ * Ask for Pointer Authentication if supported, so that we get
50
+
50
+ * the unsanitized field values for AA64ISAR1_EL1.
51
+static CPAccessResult pmreg_access_swinc(CPUARMState *env,
51
*/
52
+ const ARMCPRegInfo *ri,
52
if (kvm_arm_pauth_supported()) {
53
+ bool isread)
53
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
54
+{
54
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
55
+ /* SW: software increment write trap control */
55
}
56
+ if (arm_feature(env, ARM_FEATURE_V8)
56
}
57
+ && arm_current_el(env) == 0
57
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+ && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
58
- sve_supported = kvm_arm_sve_supported();
59
+ && !isread) {
59
-
60
+ return CP_ACCESS_OK;
60
- /* Add feature bits that can't appear until after VCPU init. */
61
+ }
61
if (sve_supported) {
62
+
62
- t = ahcf->isar.id_aa64pfr0;
63
+ return pmreg_access(env, ri, isread);
63
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
64
+}
64
- ahcf->isar.id_aa64pfr0 = t;
65
+
65
-
66
#ifndef CONFIG_USER_ONLY
66
/*
67
67
* There is a range of kernels between kernel commit 73433762fcae
68
+static CPAccessResult pmreg_access_selr(CPUARMState *env,
68
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
69
+ const ARMCPRegInfo *ri,
69
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
70
+ bool isread)
70
- * SVE support, so we only read it here, rather than together with all
71
+{
71
- * the other ID registers earlier.
72
+ /* ER: event counter read trap control */
72
+ * SVE support, which resulted in an error rather than RAZ.
73
+ if (arm_feature(env, ARM_FEATURE_V8)
73
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
74
+ && arm_current_el(env) == 0
74
*/
75
+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
75
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
76
+ return CP_ACCESS_OK;
76
ARM64_SYS_REG(3, 0, 0, 4, 4));
77
+ }
78
+
79
+ return pmreg_access(env, ri, isread);
80
+}
81
+
82
+static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
83
+ const ARMCPRegInfo *ri,
84
+ bool isread)
85
+{
86
+ /* CR: cycle counter read trap control */
87
+ if (arm_feature(env, ARM_FEATURE_V8)
88
+ && arm_current_el(env) == 0
89
+ && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
90
+ && isread) {
91
+ return CP_ACCESS_OK;
92
+ }
93
+
94
+ return pmreg_access(env, ri, isread);
95
+}
96
+
97
static inline bool arm_ccnt_enabled(CPUARMState *env)
98
{
99
/* This does not support checking PMCCFILTR_EL0 register */
100
@@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
101
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
102
uint64_t value)
103
{
104
- env->cp15.c9_pmuserenr = value & 1;
105
+ if (arm_feature(env, ARM_FEATURE_V8)) {
106
+ env->cp15.c9_pmuserenr = value & 0xf;
107
+ } else {
108
+ env->cp15.c9_pmuserenr = value & 1;
109
+ }
110
}
111
112
static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
113
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
114
.raw_writefn = raw_write },
115
/* Unimplemented so WI. */
116
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
117
- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
118
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
119
#ifndef CONFIG_USER_ONLY
120
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
121
.access = PL0_RW, .type = ARM_CP_ALIAS,
122
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
123
- .accessfn = pmreg_access, .writefn = pmselr_write,
124
+ .accessfn = pmreg_access_selr, .writefn = pmselr_write,
125
.raw_writefn = raw_write},
126
{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
128
- .access = PL0_RW, .accessfn = pmreg_access,
129
+ .access = PL0_RW, .accessfn = pmreg_access_selr,
130
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
131
.writefn = pmselr_write, .raw_writefn = raw_write, },
132
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
133
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
134
.readfn = pmccntr_read, .writefn = pmccntr_write32,
135
- .accessfn = pmreg_access },
136
+ .accessfn = pmreg_access_ccntr },
137
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
138
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
139
- .access = PL0_RW, .accessfn = pmreg_access,
140
+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
141
.type = ARM_CP_IO,
142
.readfn = pmccntr_read, .writefn = pmccntr_write, },
143
#endif
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
145
/* Unimplemented, RAZ/WI. */
146
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
147
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
148
- .accessfn = pmreg_access },
149
+ .accessfn = pmreg_access_xevcntr },
150
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
151
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
152
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
153
--
77
--
154
2.7.4
78
2.25.1
155
156
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The power state spec section 5.1.5 AFFINITY_INFO defines the
3
The test for the IF block indicates no ID registers are exposed, much
4
affinity info return values as
4
less host support for SVE. Move the SVE probe into the ELSE block.
5
5
6
0 ON
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
1 OFF
7
Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
8
2 ON_PENDING
9
10
I grepped QEMU for power_state to ensure that no assumptions
11
of OFF=0 were being made.
12
13
Signed-off-by: Andrew Jones <drjones@redhat.com>
14
Message-id: 20170303123232.4967-1-drjones@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
10
---
18
target/arm/cpu.h | 4 ++--
11
target/arm/kvm64.c | 22 +++++++++++-----------
19
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 11 insertions(+), 11 deletions(-)
20
13
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
16
--- a/target/arm/kvm64.c
24
+++ b/target/arm/cpu.h
17
+++ b/target/arm/kvm64.c
25
@@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
18
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
26
/* These values map onto the return values for
19
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
27
* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
20
ARM64_SYS_REG(3, 3, 9, 12, 0));
28
typedef enum ARMPSCIState {
21
}
29
- PSCI_OFF = 0,
22
- }
30
- PSCI_ON = 1,
23
31
+ PSCI_ON = 0,
24
- if (sve_supported) {
32
+ PSCI_OFF = 1,
25
- /*
33
PSCI_ON_PENDING = 2
26
- * There is a range of kernels between kernel commit 73433762fcae
34
} ARMPSCIState;
27
- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
35
28
- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
29
- * SVE support, which resulted in an error rather than RAZ.
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
31
- */
32
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
33
- ARM64_SYS_REG(3, 0, 0, 4, 4));
34
+ if (sve_supported) {
35
+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
37
+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
38
+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
39
+ * enabled SVE support, which resulted in an error rather than RAZ.
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
44
+ }
45
}
46
47
kvm_arm_destroy_scratch_host_vcpu(fdarray);
36
--
48
--
37
2.7.4
49
2.25.1
38
39
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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