1 | Couple of minor patches to sneak in before rc0. The PSCI return | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
---|---|---|---|
2 | values fix is the most important one. | 2 | ethernet device failed 'make check' on big-endian hosts. |
3 | 3 | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9: | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) |
9 | 9 | ||
10 | are available in the git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
13 | 13 | ||
14 | for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
15 | 15 | ||
16 | target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * arm-powerctl: Fix psci info return values | 20 | * Correctly initialize MDCR_EL2.HPMN |
21 | * implement armv8 PMUSERENR (user-mode enable bits) | 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 |
22 | * accel/tcg: Add URL of clang bug to comment about our workaround | ||
23 | * Add support for FEAT_DIT, Data Independent Timing | ||
24 | * Remove GPIO from unimplemented NPCM7XX | ||
25 | * Fix SCR RES1 handling | ||
26 | * Don't migrate CPUARMState.features | ||
22 | 27 | ||
23 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
24 | Andrew Baumann (1): | 29 | Aaron Lindsay (1): |
25 | target/arm: implement armv8 PMUSERENR (user-mode enable bits) | 30 | target/arm: Don't migrate CPUARMState.features |
26 | 31 | ||
27 | Andrew Jones (1): | 32 | Daniel Müller (1): |
28 | target/arm/arm-powerctl: Fix psci info return values | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
29 | 34 | ||
30 | target/arm/cpu.h | 4 +-- | 35 | Edgar E. Iglesias (1): |
31 | target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------ | 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 |
32 | 2 files changed, 73 insertions(+), 10 deletions(-) | ||
33 | 37 | ||
38 | Hao Wu (1): | ||
39 | hw/arm: Remove GPIO from unimplemented NPCM7XX | ||
40 | |||
41 | Mike Nawrocki (1): | ||
42 | target/arm: Fix SCR RES1 handling | ||
43 | |||
44 | Peter Maydell (2): | ||
45 | arm: Update infocenter.arm.com URLs | ||
46 | accel/tcg: Add URL of clang bug to comment about our workaround | ||
47 | |||
48 | Rebecca Cran (4): | ||
49 | target/arm: Add support for FEAT_DIT, Data Independent Timing | ||
50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | ||
51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | ||
52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | ||
53 | |||
54 | include/hw/dma/pl080.h | 7 ++-- | ||
55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
56 | include/hw/ssi/pl022.h | 5 ++- | ||
57 | target/arm/cpu.h | 17 ++++++++ | ||
58 | target/arm/internals.h | 6 +++ | ||
59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
61 | hw/arm/musca.c | 4 +- | ||
62 | hw/arm/npcm7xx.c | 8 ---- | ||
63 | hw/arm/xlnx-versal.c | 4 +- | ||
64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
65 | hw/timer/arm_timer.c | 7 ++-- | ||
66 | target/arm/cpu.c | 4 ++ | ||
67 | target/arm/cpu64.c | 5 +++ | ||
68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
70 | target/arm/machine.c | 2 +- | ||
71 | target/arm/op_helper.c | 9 +---- | ||
72 | target/arm/translate-a64.c | 12 ++++++ | ||
73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
2 | 1 | ||
3 | In armv8, this register implements more than a single bit, with | ||
4 | fine-grained enables for read access to event counters, cycles | ||
5 | counters, and write access to the software increment. This change | ||
6 | implements those checks using custom access functions for the relevant | ||
7 | registers. | ||
8 | |||
9 | Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
10 | Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | [PMM: move a couple of access functions to be only compiled | ||
13 | ifndef CONFIG_USER_ONLY to avoid compiler warnings] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------ | ||
17 | 1 file changed, 71 insertions(+), 8 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/helper.c | ||
22 | +++ b/target/arm/helper.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
24 | */ | ||
25 | int el = arm_current_el(env); | ||
26 | |||
27 | - if (el == 0 && !env->cp15.c9_pmuserenr) { | ||
28 | + if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { | ||
29 | return CP_ACCESS_TRAP; | ||
30 | } | ||
31 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | ||
32 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
33 | return CP_ACCESS_OK; | ||
34 | } | ||
35 | |||
36 | +static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, | ||
37 | + const ARMCPRegInfo *ri, | ||
38 | + bool isread) | ||
39 | +{ | ||
40 | + /* ER: event counter read trap control */ | ||
41 | + if (arm_feature(env, ARM_FEATURE_V8) | ||
42 | + && arm_current_el(env) == 0 | ||
43 | + && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | ||
44 | + && isread) { | ||
45 | + return CP_ACCESS_OK; | ||
46 | + } | ||
47 | + | ||
48 | + return pmreg_access(env, ri, isread); | ||
49 | +} | ||
50 | + | ||
51 | +static CPAccessResult pmreg_access_swinc(CPUARMState *env, | ||
52 | + const ARMCPRegInfo *ri, | ||
53 | + bool isread) | ||
54 | +{ | ||
55 | + /* SW: software increment write trap control */ | ||
56 | + if (arm_feature(env, ARM_FEATURE_V8) | ||
57 | + && arm_current_el(env) == 0 | ||
58 | + && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | ||
59 | + && !isread) { | ||
60 | + return CP_ACCESS_OK; | ||
61 | + } | ||
62 | + | ||
63 | + return pmreg_access(env, ri, isread); | ||
64 | +} | ||
65 | + | ||
66 | #ifndef CONFIG_USER_ONLY | ||
67 | |||
68 | +static CPAccessResult pmreg_access_selr(CPUARMState *env, | ||
69 | + const ARMCPRegInfo *ri, | ||
70 | + bool isread) | ||
71 | +{ | ||
72 | + /* ER: event counter read trap control */ | ||
73 | + if (arm_feature(env, ARM_FEATURE_V8) | ||
74 | + && arm_current_el(env) == 0 | ||
75 | + && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | ||
76 | + return CP_ACCESS_OK; | ||
77 | + } | ||
78 | + | ||
79 | + return pmreg_access(env, ri, isread); | ||
80 | +} | ||
81 | + | ||
82 | +static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | ||
83 | + const ARMCPRegInfo *ri, | ||
84 | + bool isread) | ||
85 | +{ | ||
86 | + /* CR: cycle counter read trap control */ | ||
87 | + if (arm_feature(env, ARM_FEATURE_V8) | ||
88 | + && arm_current_el(env) == 0 | ||
89 | + && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | ||
90 | + && isread) { | ||
91 | + return CP_ACCESS_OK; | ||
92 | + } | ||
93 | + | ||
94 | + return pmreg_access(env, ri, isread); | ||
95 | +} | ||
96 | + | ||
97 | static inline bool arm_ccnt_enabled(CPUARMState *env) | ||
98 | { | ||
99 | /* This does not support checking PMCCFILTR_EL0 register */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
101 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
102 | uint64_t value) | ||
103 | { | ||
104 | - env->cp15.c9_pmuserenr = value & 1; | ||
105 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
106 | + env->cp15.c9_pmuserenr = value & 0xf; | ||
107 | + } else { | ||
108 | + env->cp15.c9_pmuserenr = value & 1; | ||
109 | + } | ||
110 | } | ||
111 | |||
112 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
113 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
114 | .raw_writefn = raw_write }, | ||
115 | /* Unimplemented so WI. */ | ||
116 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, | ||
117 | - .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, | ||
118 | + .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, | ||
119 | #ifndef CONFIG_USER_ONLY | ||
120 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | ||
121 | .access = PL0_RW, .type = ARM_CP_ALIAS, | ||
122 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | ||
123 | - .accessfn = pmreg_access, .writefn = pmselr_write, | ||
124 | + .accessfn = pmreg_access_selr, .writefn = pmselr_write, | ||
125 | .raw_writefn = raw_write}, | ||
126 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | ||
127 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | ||
128 | - .access = PL0_RW, .accessfn = pmreg_access, | ||
129 | + .access = PL0_RW, .accessfn = pmreg_access_selr, | ||
130 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), | ||
131 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | ||
132 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, | ||
133 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, | ||
134 | .readfn = pmccntr_read, .writefn = pmccntr_write32, | ||
135 | - .accessfn = pmreg_access }, | ||
136 | + .accessfn = pmreg_access_ccntr }, | ||
137 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, | ||
138 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | ||
139 | - .access = PL0_RW, .accessfn = pmreg_access, | ||
140 | + .access = PL0_RW, .accessfn = pmreg_access_ccntr, | ||
141 | .type = ARM_CP_IO, | ||
142 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | ||
143 | #endif | ||
144 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
145 | /* Unimplemented, RAZ/WI. */ | ||
146 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, | ||
147 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
148 | - .accessfn = pmreg_access }, | ||
149 | + .accessfn = pmreg_access_xevcntr }, | ||
150 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, | ||
151 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, | ||
152 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), | ||
153 | -- | ||
154 | 2.7.4 | ||
155 | |||
156 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
2 | 1 | ||
3 | The power state spec section 5.1.5 AFFINITY_INFO defines the | ||
4 | affinity info return values as | ||
5 | |||
6 | 0 ON | ||
7 | 1 OFF | ||
8 | 2 ON_PENDING | ||
9 | |||
10 | I grepped QEMU for power_state to ensure that no assumptions | ||
11 | of OFF=0 were being made. | ||
12 | |||
13 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
14 | Message-id: 20170303123232.4967-1-drjones@redhat.com | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | target/arm/cpu.h | 4 ++-- | ||
19 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
20 | |||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/cpu.h | ||
24 | +++ b/target/arm/cpu.h | ||
25 | @@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); | ||
26 | /* These values map onto the return values for | ||
27 | * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ | ||
28 | typedef enum ARMPSCIState { | ||
29 | - PSCI_OFF = 0, | ||
30 | - PSCI_ON = 1, | ||
31 | + PSCI_ON = 0, | ||
32 | + PSCI_OFF = 1, | ||
33 | PSCI_ON_PENDING = 2 | ||
34 | } ARMPSCIState; | ||
35 | |||
36 | -- | ||
37 | 2.7.4 | ||
38 | |||
39 | diff view generated by jsdifflib |