[Qemu-devel] [PULL 0/2] target-arm queue
[PULL 0/8] target-arm queue
1
Couple of minor patches to sneak in before rc0. The PSCI return
1
Handful of bugfixes for rc2. None of these are particularly critical
2
values fix is the most important one.
2
or exciting.
3
3
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9:
6
The following changes since commit 45a150aa2b3492acf6691c7bdbeb25a8545d8345:
7
7
8
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000)
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-03' into staging (2020-08-03 15:13:49 +0100)
9
9
10
are available in the git repository at:
10
are available in the Git repository at:
11
11
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200803
13
13
14
for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02:
14
for you to fetch changes up to 13557fd392890cbd985bceba7f717e01efd674b8:
15
15
16
target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000)
16
hw/timer/imx_epit: Avoid assertion when CR.SWR is written (2020-08-03 17:56:11 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* arm-powerctl: Fix psci info return values
20
* hw/timer/imx_epit: Avoid assertion when CR.SWR is written
21
* implement armv8 PMUSERENR (user-mode enable bits)
21
* netduino2, netduinoplus2, microbit: set system_clock_scale so that
22
SysTick running on the CPU clock works
23
* target/arm: Avoid maybe-uninitialized warning with gcc 4.9
24
* target/arm: Fix AddPAC error indication
25
* Make AIRCR.SYSRESETREQ actually reset the system for the
26
microbit, mps2-*, musca-*, netduino* boards
22
27
23
----------------------------------------------------------------
28
----------------------------------------------------------------
24
Andrew Baumann (1):
29
Kaige Li (1):
25
target/arm: implement armv8 PMUSERENR (user-mode enable bits)
30
target/arm: Avoid maybe-uninitialized warning with gcc 4.9
26
31
27
Andrew Jones (1):
32
Peter Maydell (6):
28
target/arm/arm-powerctl: Fix psci info return values
33
hw/arm/netduino2, netduinoplus2: Set system_clock_scale
34
include/hw/irq.h: New function qemu_irq_is_connected()
35
hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
36
msf2-soc, stellaris: Don't wire up SYSRESETREQ
37
hw/arm/nrf51_soc: Set system_clock_scale
38
hw/timer/imx_epit: Avoid assertion when CR.SWR is written
29
39
30
target/arm/cpu.h | 4 +--
40
Richard Henderson (1):
31
target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
41
target/arm: Fix AddPAC error indication
32
2 files changed, 73 insertions(+), 10 deletions(-)
33
42
43
include/hw/arm/armv7m.h | 4 +++-
44
include/hw/irq.h | 18 ++++++++++++++++++
45
hw/arm/msf2-soc.c | 11 -----------
46
hw/arm/netduino2.c | 10 ++++++++++
47
hw/arm/netduinoplus2.c | 10 ++++++++++
48
hw/arm/nrf51_soc.c | 5 +++++
49
hw/arm/stellaris.c | 12 ------------
50
hw/intc/armv7m_nvic.c | 17 ++++++++++++++++-
51
hw/timer/imx_epit.c | 13 ++++++++++---
52
target/arm/pauth_helper.c | 6 +++++-
53
target/arm/translate-a64.c | 2 +-
54
tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++++
55
tests/tcg/aarch64/Makefile.target | 2 +-
56
13 files changed, 112 insertions(+), 31 deletions(-)
57
create mode 100644 tests/tcg/aarch64/pauth-5.c
58
diff view generated by jsdifflib
New patch
[PULL 1/8] hw/arm/netduino2, netduinoplus2: Set system_clock_scale
1
The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
2
global, which meant that if guest code used the systick timer in "use
3
the processor clock" mode it would hang because time never advances.
1
4
5
Set the global to match the documented CPU clock speed of these boards.
6
Judging by the data sheet this is slightly simplistic because the
7
SoC allows configuration of the SYSCLK source and frequency via the
8
RCC (reset and clock control) module, but we don't model that.
9
10
Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200727162617.26227-1-peter.maydell@linaro.org
14
---
15
hw/arm/netduino2.c | 10 ++++++++++
16
hw/arm/netduinoplus2.c | 10 ++++++++++
17
2 files changed, 20 insertions(+)
18
19
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/netduino2.c
22
+++ b/hw/arm/netduino2.c
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/arm/stm32f205_soc.h"
25
#include "hw/arm/boot.h"
26
27
+/* Main SYSCLK frequency in Hz (120MHz) */
28
+#define SYSCLK_FRQ 120000000ULL
29
+
30
static void netduino2_init(MachineState *machine)
31
{
32
DeviceState *dev;
33
34
+ /*
35
+ * TODO: ideally we would model the SoC RCC and let it handle
36
+ * system_clock_scale, including its ability to define different
37
+ * possible SYSCLK sources.
38
+ */
39
+ system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
40
+
41
dev = qdev_new(TYPE_STM32F205_SOC);
42
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
43
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
44
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/netduinoplus2.c
47
+++ b/hw/arm/netduinoplus2.c
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/arm/stm32f405_soc.h"
50
#include "hw/arm/boot.h"
51
52
+/* Main SYSCLK frequency in Hz (168MHz) */
53
+#define SYSCLK_FRQ 168000000ULL
54
+
55
static void netduinoplus2_init(MachineState *machine)
56
{
57
DeviceState *dev;
58
59
+ /*
60
+ * TODO: ideally we would model the SoC RCC and let it handle
61
+ * system_clock_scale, including its ability to define different
62
+ * possible SYSCLK sources.
63
+ */
64
+ system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
65
+
66
dev = qdev_new(TYPE_STM32F405_SOC);
67
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
68
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
69
--
70
2.20.1
71
72
diff view generated by jsdifflib
New patch
[PULL 2/8] include/hw/irq.h: New function qemu_irq_is_connected()
1
Mostly devices don't need to care whether one of their output
2
qemu_irq lines is connected, because functions like qemu_set_irq()
3
silently do nothing if there is nothing on the other end. However
4
sometimes a device might want to implement default behaviour for the
5
case where the machine hasn't wired the line up to anywhere.
1
6
7
Provide a function qemu_irq_is_connected() that devices can use for
8
this purpose. (The test is trivial but encapsulating it in a
9
function makes it easier to see where we're doing it in case we need
10
to change the implementation later.)
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20200728103744.6909-2-peter.maydell@linaro.org
16
---
17
include/hw/irq.h | 18 ++++++++++++++++++
18
1 file changed, 18 insertions(+)
19
20
diff --git a/include/hw/irq.h b/include/hw/irq.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/irq.h
23
+++ b/include/hw/irq.h
24
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
25
on an existing vector of qemu_irq. */
26
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
27
28
+/**
29
+ * qemu_irq_is_connected: Return true if IRQ line is wired up
30
+ *
31
+ * If a qemu_irq has a device on the other (receiving) end of it,
32
+ * return true; otherwise return false.
33
+ *
34
+ * Usually device models don't need to care whether the machine model
35
+ * has wired up their outbound qemu_irq lines, because functions like
36
+ * qemu_set_irq() silently do nothing if there is nothing on the other
37
+ * end of the line. However occasionally a device model will want to
38
+ * provide default behaviour if its output is left floating, and
39
+ * it can use this function to identify when that is the case.
40
+ */
41
+static inline bool qemu_irq_is_connected(qemu_irq irq)
42
+{
43
+ return irq != NULL;
44
+}
45
+
46
#endif
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
New patch
[PULL 3/8] hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESETREQ
1
The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
2
when the guest sets the SYSRESETREQ bit in the AIRCR register. This
3
matches the hardware design (where the CPU has a signal of this name
4
and it is up to the SoC to connect that up to an actual reset
5
mechanism), but in QEMU it mostly results in duplicated code in SoC
6
objects and bugs where SoC model implementors forget to wire up the
7
SYSRESETREQ line.
1
8
9
Provide a default behaviour for the case where SYSRESETREQ is not
10
actually connected to anything: use qemu_system_reset_request() to
11
perform a system reset. This will allow us to remove the
12
implementations of SYSRESETREQ handling from the boards where that's
13
exactly what it does, and also fixes the bugs in the board models
14
which forgot to wire up the signal:
15
16
* microbit
17
* mps2-an385
18
* mps2-an505
19
* mps2-an511
20
* mps2-an521
21
* musca-a
22
* musca-b1
23
* netduino
24
* netduinoplus2
25
26
We still allow the board to wire up the signal if it needs to, in case
27
we need to model more complicated reset controller logic or to model
28
buggy SoC hardware which forgot to wire up the line itself. But
29
defaulting to "reset the system" is more often going to be correct
30
than defaulting to "do nothing".
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
35
Message-id: 20200728103744.6909-3-peter.maydell@linaro.org
36
---
37
include/hw/arm/armv7m.h | 4 +++-
38
hw/intc/armv7m_nvic.c | 17 ++++++++++++++++-
39
2 files changed, 19 insertions(+), 2 deletions(-)
40
41
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/armv7m.h
44
+++ b/include/hw/arm/armv7m.h
45
@@ -XXX,XX +XXX,XX @@ typedef struct {
46
47
/* ARMv7M container object.
48
* + Unnamed GPIO input lines: external IRQ lines for the NVIC
49
- * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
50
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
51
+ * If this GPIO is not wired up then the NVIC will default to performing
52
+ * a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
53
* + Property "cpu-type": CPU type to instantiate
54
* + Property "num-irq": number of external IRQ lines
55
* + Property "memory": MemoryRegion defining the physical address space
56
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/armv7m_nvic.c
59
+++ b/hw/intc/armv7m_nvic.c
60
@@ -XXX,XX +XXX,XX @@
61
#include "hw/intc/armv7m_nvic.h"
62
#include "hw/irq.h"
63
#include "hw/qdev-properties.h"
64
+#include "sysemu/runstate.h"
65
#include "target/arm/cpu.h"
66
#include "exec/exec-all.h"
67
#include "exec/memop.h"
68
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
69
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
70
};
71
72
+static void signal_sysresetreq(NVICState *s)
73
+{
74
+ if (qemu_irq_is_connected(s->sysresetreq)) {
75
+ qemu_irq_pulse(s->sysresetreq);
76
+ } else {
77
+ /*
78
+ * Default behaviour if the SoC doesn't need to wire up
79
+ * SYSRESETREQ (eg to a system reset controller of some kind):
80
+ * perform a system reset via the usual QEMU API.
81
+ */
82
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
83
+ }
84
+}
85
+
86
static int nvic_pending_prio(NVICState *s)
87
{
88
/* return the group priority of the current pending interrupt,
89
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
90
if (value & R_V7M_AIRCR_SYSRESETREQ_MASK) {
91
if (attrs.secure ||
92
!(cpu->env.v7m.aircr & R_V7M_AIRCR_SYSRESETREQS_MASK)) {
93
- qemu_irq_pulse(s->sysresetreq);
94
+ signal_sysresetreq(s);
95
}
96
}
97
if (value & R_V7M_AIRCR_VECTCLRACTIVE_MASK) {
98
--
99
2.20.1
100
101
diff view generated by jsdifflib
New patch
[PULL 4/8] msf2-soc, stellaris: Don't wire up SYSRESETREQ
1
The MSF2 SoC model and the Stellaris board code both wire
2
SYSRESETREQ up to a function that just invokes
3
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4
This is now the default action that the NVIC does if the line is
5
not connected, so we can delete the handling code.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20200728103744.6909-4-peter.maydell@linaro.org
11
---
12
hw/arm/msf2-soc.c | 11 -----------
13
hw/arm/stellaris.c | 12 ------------
14
2 files changed, 23 deletions(-)
15
16
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/msf2-soc.c
19
+++ b/hw/arm/msf2-soc.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/irq.h"
22
#include "hw/arm/msf2-soc.h"
23
#include "hw/misc/unimp.h"
24
-#include "sysemu/runstate.h"
25
#include "sysemu/sysemu.h"
26
27
#define MSF2_TIMER_BASE 0x40004000
28
@@ -XXX,XX +XXX,XX @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
29
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
30
static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
31
32
-static void do_sys_reset(void *opaque, int n, int level)
33
-{
34
- if (level) {
35
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
36
- }
37
-}
38
-
39
static void m2sxxx_soc_initfn(Object *obj)
40
{
41
MSF2State *s = MSF2_SOC(obj);
42
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
43
return;
44
}
45
46
- qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
47
- qemu_allocate_irq(&do_sys_reset, NULL, 0));
48
-
49
system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
50
51
for (i = 0; i < MSF2_NUM_UARTS; i++) {
52
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/stellaris.c
55
+++ b/hw/arm/stellaris.c
56
@@ -XXX,XX +XXX,XX @@
57
#include "hw/boards.h"
58
#include "qemu/log.h"
59
#include "exec/address-spaces.h"
60
-#include "sysemu/runstate.h"
61
#include "sysemu/sysemu.h"
62
#include "hw/arm/armv7m.h"
63
#include "hw/char/pl011.h"
64
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
65
qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
66
}
67
68
-static
69
-void do_sys_reset(void *opaque, int n, int level)
70
-{
71
- if (level) {
72
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
73
- }
74
-}
75
-
76
/* Board init. */
77
static stellaris_board_info stellaris_boards[] = {
78
{ "LM3S811EVB",
79
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
80
/* This will exit with an error if the user passed us a bad cpu_type */
81
sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
82
83
- qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0,
84
- qemu_allocate_irq(&do_sys_reset, NULL, 0));
85
-
86
if (board->dc1 & (1 << 16)) {
87
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
88
qdev_get_gpio_in(nvic, 14),
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
New patch
[PULL 5/8] target/arm: Fix AddPAC error indication
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The definition of top_bit used in this function is one higher
4
than that used in the Arm ARM psuedo-code, which put the error
5
indication at top_bit - 1 at the wrong place, which meant that
6
it wasn't visible to Auth.
7
8
Fixing the definition of top_bit requires more changes, because
9
its most common use is for the count of bits in top_bit:bot_bit,
10
which would then need to be computed as top_bit - bot_bit + 1.
11
12
For now, prefer the minimal fix to the error indication alone.
13
14
Fixes: 63ff0ca94cb
15
Reported-by: Derrick McKee <derrick.mckee@gmail.com>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200728195706.11087-1-richard.henderson@linaro.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
[PMM: added comment about the divergence from the pseudocode]
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
target/arm/pauth_helper.c | 6 +++++-
23
tests/tcg/aarch64/pauth-5.c | 33 +++++++++++++++++++++++++++++++
24
tests/tcg/aarch64/Makefile.target | 2 +-
25
3 files changed, 39 insertions(+), 2 deletions(-)
26
create mode 100644 tests/tcg/aarch64/pauth-5.c
27
28
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/pauth_helper.c
31
+++ b/target/arm/pauth_helper.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
33
*/
34
test = sextract64(ptr, bot_bit, top_bit - bot_bit);
35
if (test != 0 && test != -1) {
36
- pac ^= MAKE_64BIT_MASK(top_bit - 1, 1);
37
+ /*
38
+ * Note that our top_bit is one greater than the pseudocode's
39
+ * version, hence "- 2" here.
40
+ */
41
+ pac ^= MAKE_64BIT_MASK(top_bit - 2, 1);
42
}
43
44
/*
45
diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c
46
new file mode 100644
47
index XXXXXXX..XXXXXXX
48
--- /dev/null
49
+++ b/tests/tcg/aarch64/pauth-5.c
50
@@ -XXX,XX +XXX,XX @@
51
+#include <assert.h>
52
+
53
+static int x;
54
+
55
+int main()
56
+{
57
+ int *p0 = &x, *p1, *p2, *p3;
58
+ unsigned long salt = 0;
59
+
60
+ /*
61
+ * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so
62
+ * a 1/128 chance of auth = pac(ptr,key,salt) producing zero.
63
+ * Find a salt that creates auth != 0.
64
+ */
65
+ do {
66
+ salt++;
67
+ asm("pacda %0, %1" : "=r"(p1) : "r"(salt), "0"(p0));
68
+ } while (p0 == p1);
69
+
70
+ /*
71
+ * This pac must fail, because the input pointer bears an encryption,
72
+ * and so is not properly extended within bits [55:47]. This will
73
+ * toggle bit 54 in the output...
74
+ */
75
+ asm("pacda %0, %1" : "=r"(p2) : "r"(salt), "0"(p1));
76
+
77
+ /* ... so that the aut must fail, setting bit 53 in the output ... */
78
+ asm("autda %0, %1" : "=r"(p3) : "r"(salt), "0"(p2));
79
+
80
+ /* ... which means this equality must not hold. */
81
+ assert(p3 != p0);
82
+ return 0;
83
+}
84
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
85
index XXXXXXX..XXXXXXX 100644
86
--- a/tests/tcg/aarch64/Makefile.target
87
+++ b/tests/tcg/aarch64/Makefile.target
88
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
89
90
# Pauth Tests
91
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_3),)
92
-AARCH64_TESTS += pauth-1 pauth-2 pauth-4
93
+AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
94
pauth-%: CFLAGS += -march=armv8.3-a
95
run-pauth-%: QEMU_OPTS += -cpu max
96
run-plugin-pauth-%: QEMU_OPTS += -cpu max
97
--
98
2.20.1
99
100
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits)
[PULL 6/8] target/arm: Avoid maybe-uninitialized warning with gcc 4.9
1
From: Andrew Baumann <Andrew.Baumann@microsoft.com>
1
From: Kaige Li <likaige@loongson.cn>
2
2
3
In armv8, this register implements more than a single bit, with
3
GCC version 4.9.4 isn't clever enough to figure out that all
4
fine-grained enables for read access to event counters, cycles
4
execution paths in disas_ldst() that use 'fn' will have initialized
5
counters, and write access to the software increment. This change
5
it first, and so it warns:
6
implements those checks using custom access functions for the relevant
7
registers.
8
6
9
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
7
/home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’:
10
Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com
8
/home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
9
fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
10
^
11
/home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here
12
AtomicThreeOpFn *fn;
13
^
14
15
Make it happy by initializing the variable to NULL.
16
17
Signed-off-by: Kaige Li <likaige@loongson.cn>
18
Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: move a couple of access functions to be only compiled
20
[PMM: Clean up commit message and note which gcc version this was]
13
ifndef CONFIG_USER_ONLY to avoid compiler warnings]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
22
---
16
target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
23
target/arm/translate-a64.c | 2 +-
17
1 file changed, 71 insertions(+), 8 deletions(-)
24
1 file changed, 1 insertion(+), 1 deletion(-)
18
25
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
28
--- a/target/arm/translate-a64.c
22
+++ b/target/arm/helper.c
29
+++ b/target/arm/translate-a64.c
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
30
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
24
*/
31
bool r = extract32(insn, 22, 1);
25
int el = arm_current_el(env);
32
bool a = extract32(insn, 23, 1);
26
33
TCGv_i64 tcg_rs, clean_addr;
27
- if (el == 0 && !env->cp15.c9_pmuserenr) {
34
- AtomicThreeOpFn *fn;
28
+ if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
35
+ AtomicThreeOpFn *fn = NULL;
29
return CP_ACCESS_TRAP;
36
30
}
37
if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
31
if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
38
unallocated_encoding(s);
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
33
return CP_ACCESS_OK;
34
}
35
36
+static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
37
+ const ARMCPRegInfo *ri,
38
+ bool isread)
39
+{
40
+ /* ER: event counter read trap control */
41
+ if (arm_feature(env, ARM_FEATURE_V8)
42
+ && arm_current_el(env) == 0
43
+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
44
+ && isread) {
45
+ return CP_ACCESS_OK;
46
+ }
47
+
48
+ return pmreg_access(env, ri, isread);
49
+}
50
+
51
+static CPAccessResult pmreg_access_swinc(CPUARMState *env,
52
+ const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ /* SW: software increment write trap control */
56
+ if (arm_feature(env, ARM_FEATURE_V8)
57
+ && arm_current_el(env) == 0
58
+ && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
59
+ && !isread) {
60
+ return CP_ACCESS_OK;
61
+ }
62
+
63
+ return pmreg_access(env, ri, isread);
64
+}
65
+
66
#ifndef CONFIG_USER_ONLY
67
68
+static CPAccessResult pmreg_access_selr(CPUARMState *env,
69
+ const ARMCPRegInfo *ri,
70
+ bool isread)
71
+{
72
+ /* ER: event counter read trap control */
73
+ if (arm_feature(env, ARM_FEATURE_V8)
74
+ && arm_current_el(env) == 0
75
+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
76
+ return CP_ACCESS_OK;
77
+ }
78
+
79
+ return pmreg_access(env, ri, isread);
80
+}
81
+
82
+static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
83
+ const ARMCPRegInfo *ri,
84
+ bool isread)
85
+{
86
+ /* CR: cycle counter read trap control */
87
+ if (arm_feature(env, ARM_FEATURE_V8)
88
+ && arm_current_el(env) == 0
89
+ && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
90
+ && isread) {
91
+ return CP_ACCESS_OK;
92
+ }
93
+
94
+ return pmreg_access(env, ri, isread);
95
+}
96
+
97
static inline bool arm_ccnt_enabled(CPUARMState *env)
98
{
99
/* This does not support checking PMCCFILTR_EL0 register */
100
@@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
101
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
102
uint64_t value)
103
{
104
- env->cp15.c9_pmuserenr = value & 1;
105
+ if (arm_feature(env, ARM_FEATURE_V8)) {
106
+ env->cp15.c9_pmuserenr = value & 0xf;
107
+ } else {
108
+ env->cp15.c9_pmuserenr = value & 1;
109
+ }
110
}
111
112
static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
113
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
114
.raw_writefn = raw_write },
115
/* Unimplemented so WI. */
116
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
117
- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
118
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
119
#ifndef CONFIG_USER_ONLY
120
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
121
.access = PL0_RW, .type = ARM_CP_ALIAS,
122
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
123
- .accessfn = pmreg_access, .writefn = pmselr_write,
124
+ .accessfn = pmreg_access_selr, .writefn = pmselr_write,
125
.raw_writefn = raw_write},
126
{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
128
- .access = PL0_RW, .accessfn = pmreg_access,
129
+ .access = PL0_RW, .accessfn = pmreg_access_selr,
130
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
131
.writefn = pmselr_write, .raw_writefn = raw_write, },
132
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
133
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
134
.readfn = pmccntr_read, .writefn = pmccntr_write32,
135
- .accessfn = pmreg_access },
136
+ .accessfn = pmreg_access_ccntr },
137
{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
138
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
139
- .access = PL0_RW, .accessfn = pmreg_access,
140
+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
141
.type = ARM_CP_IO,
142
.readfn = pmccntr_read, .writefn = pmccntr_write, },
143
#endif
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
145
/* Unimplemented, RAZ/WI. */
146
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
147
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
148
- .accessfn = pmreg_access },
149
+ .accessfn = pmreg_access_xevcntr },
150
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
151
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
152
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
153
--
39
--
154
2.7.4
40
2.20.1
155
41
156
42
diff view generated by jsdifflib
New patch
[PULL 7/8] hw/arm/nrf51_soc: Set system_clock_scale
1
The nrf51 SoC model wasn't setting the system_clock_scale
2
global.which meant that if guest code used the systick timer in "use
3
the processor clock" mode it would hang because time never advances.
1
4
5
Set the global to match the documented CPU clock speed for this SoC.
6
7
This SoC in fact doesn't have a SysTick timer (which is the only thing
8
currently that cares about the system_clock_scale), because it's
9
a configurable option in the Cortex-M0. However our Cortex-M0 and
10
thus our nrf51 and our micro:bit board do provide a SysTick, so
11
we ought to provide a functional one rather than a broken one.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20200727193458.31250-1-peter.maydell@linaro.org
16
---
17
hw/arm/nrf51_soc.c | 5 +++++
18
1 file changed, 5 insertions(+)
19
20
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/nrf51_soc.c
23
+++ b/hw/arm/nrf51_soc.c
24
@@ -XXX,XX +XXX,XX @@
25
26
#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
27
28
+/* HCLK (the main CPU clock) on this SoC is always 16MHz */
29
+#define HCLK_FRQ 16000000
30
+
31
static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
32
{
33
qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
34
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
35
return;
36
}
37
38
+ system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
39
+
40
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
41
&error_abort);
42
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
43
--
44
2.20.1
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values
[PULL 8/8] hw/timer/imx_epit: Avoid assertion when CR.SWR is written
1
From: Andrew Jones <drjones@redhat.com>
1
The imx_epit device has a software-controllable reset triggered by
2
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
3
means that we will end up assert()ing if the guest does this, because
4
the code in imx_epit_write() starts ptimer transactions, and then
5
imx_epit_reset() also starts ptimer transactions, triggering
6
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".
2
7
3
The power state spec section 5.1.5 AFFINITY_INFO defines the
8
The cleanest way to avoid this double-transaction is to move the
4
affinity info return values as
9
start-transaction for the CR write handling down below the check of
10
the SWR bit.
5
11
6
0 ON
12
Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
7
1 OFF
13
Fixes: cc2722ec83ad944505fe
8
2 ON_PENDING
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
17
---
18
hw/timer/imx_epit.c | 13 ++++++++++---
19
1 file changed, 10 insertions(+), 3 deletions(-)
9
20
10
I grepped QEMU for power_state to ensure that no assumptions
21
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
11
of OFF=0 were being made.
12
13
Signed-off-by: Andrew Jones <drjones@redhat.com>
14
Message-id: 20170303123232.4967-1-drjones@redhat.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/cpu.h | 4 ++--
19
1 file changed, 2 insertions(+), 2 deletions(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
23
--- a/hw/timer/imx_epit.c
24
+++ b/target/arm/cpu.h
24
+++ b/hw/timer/imx_epit.c
25
@@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
25
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
26
/* These values map onto the return values for
26
27
* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
27
switch (offset >> 2) {
28
typedef enum ARMPSCIState {
28
case 0: /* CR */
29
- PSCI_OFF = 0,
29
- ptimer_transaction_begin(s->timer_cmp);
30
- PSCI_ON = 1,
30
- ptimer_transaction_begin(s->timer_reload);
31
+ PSCI_ON = 0,
31
32
+ PSCI_OFF = 1,
32
oldcr = s->cr;
33
PSCI_ON_PENDING = 2
33
s->cr = value & 0x03ffffff;
34
} ARMPSCIState;
34
if (s->cr & CR_SWR) {
35
/* handle the reset */
36
imx_epit_reset(DEVICE(s));
37
- } else {
38
+ /*
39
+ * TODO: could we 'break' here? following operations appear
40
+ * to duplicate the work imx_epit_reset() already did.
41
+ */
42
+ }
43
+
44
+ ptimer_transaction_begin(s->timer_cmp);
45
+ ptimer_transaction_begin(s->timer_reload);
46
+
47
+ if (!(s->cr & CR_SWR)) {
48
imx_epit_set_freq(s);
49
}
35
50
36
--
51
--
37
2.7.4
52
2.20.1
38
53
39
54
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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