[Qemu-devel] [PULL 0/2] target-arm queue
[Qemu-devel] [PULL v2 0/6] target-arm queue
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Couple of minor patches to sneak in before rc0. The PSCI return
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Respin to fix some accidental wrong Author lines, no content
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values fix is the most important one.
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changes.
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-- PMM
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-- PMM
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The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9:
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The following changes since commit 0bbba1665ca2e7f1c80d4797077fe57bad58898e:
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000)
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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-october-2018-part-4' into staging (2018-10-30 10:45:49 +0000)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181030
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for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02:
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for you to fetch changes up to 1f5a65a188210509bfb0c025fc91635c8436b98a:
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target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000)
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tests/boot-serial-test: Add microbit board testcase (2018-10-30 13:20:18 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* arm-powerctl: Fix psci info return values
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* microbit: Add the UART to our nRF51 SoC model
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* implement armv8 PMUSERENR (user-mode enable bits)
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* Add a virtual Xilinx Versal board "xlnx-versal-virt"
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* hw/arm/virt: Set VIRT_COMPAT_3_0 compat
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Baumann (1):
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Edgar E. Iglesias (2):
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target/arm: implement armv8 PMUSERENR (user-mode enable bits)
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hw/arm: versal: Add a model of Xilinx Versal SoC
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hw/arm: versal: Add a virtual Xilinx Versal board
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Andrew Jones (1):
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Eric Auger (1):
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target/arm/arm-powerctl: Fix psci info return values
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hw/arm/virt: Set VIRT_COMPAT_3_0 compat
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target/arm/cpu.h | 4 +--
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Julia Suvorova (3):
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target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
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hw/char: Implement nRF51 SoC UART
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2 files changed, 73 insertions(+), 10 deletions(-)
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hw/arm/nrf51_soc: Connect UART to nRF51 SoC
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tests/boot-serial-test: Add microbit board testcase
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hw/arm/Makefile.objs | 1 +
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hw/char/Makefile.objs | 1 +
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include/hw/arm/nrf51_soc.h | 3 +
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include/hw/arm/xlnx-versal.h | 122 +++++++++
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include/hw/char/nrf51_uart.h | 78 ++++++
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hw/arm/microbit.c | 2 +
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hw/arm/nrf51_soc.c | 20 ++
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hw/arm/virt.c | 4 +
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hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++
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hw/arm/xlnx-versal.c | 323 +++++++++++++++++++++++
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hw/char/nrf51_uart.c | 330 ++++++++++++++++++++++++
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tests/boot-serial-test.c | 19 ++
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default-configs/aarch64-softmmu.mak | 1 +
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hw/char/trace-events | 4 +
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14 files changed, 1401 insertions(+)
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create mode 100644 include/hw/arm/xlnx-versal.h
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create mode 100644 include/hw/char/nrf51_uart.h
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create mode 100644 hw/arm/xlnx-versal-virt.c
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create mode 100644 hw/arm/xlnx-versal.c
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create mode 100644 hw/char/nrf51_uart.c
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diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits)
Deleted patch
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From: Andrew Baumann <Andrew.Baumann@microsoft.com>
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In armv8, this register implements more than a single bit, with
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fine-grained enables for read access to event counters, cycles
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counters, and write access to the software increment. This change
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implements those checks using custom access functions for the relevant
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registers.
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Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
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Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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[PMM: move a couple of access functions to be only compiled
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ifndef CONFIG_USER_ONLY to avoid compiler warnings]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
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1 file changed, 71 insertions(+), 8 deletions(-)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
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@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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*/
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int el = arm_current_el(env);
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- if (el == 0 && !env->cp15.c9_pmuserenr) {
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+ if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
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return CP_ACCESS_TRAP;
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}
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if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
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@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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+static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* ER: event counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
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+ && isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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+static CPAccessResult pmreg_access_swinc(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* SW: software increment write trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
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+ && !isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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#ifndef CONFIG_USER_ONLY
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+static CPAccessResult pmreg_access_selr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* ER: event counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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+static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* CR: cycle counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
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+ && isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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static inline bool arm_ccnt_enabled(CPUARMState *env)
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{
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/* This does not support checking PMCCFILTR_EL0 register */
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@@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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- env->cp15.c9_pmuserenr = value & 1;
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+ if (arm_feature(env, ARM_FEATURE_V8)) {
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+ env->cp15.c9_pmuserenr = value & 0xf;
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+ } else {
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+ env->cp15.c9_pmuserenr = value & 1;
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+ }
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}
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static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.raw_writefn = raw_write },
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/* Unimplemented so WI. */
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
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+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
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- .accessfn = pmreg_access, .writefn = pmselr_write,
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+ .accessfn = pmreg_access_selr, .writefn = pmselr_write,
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.raw_writefn = raw_write},
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{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
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- .access = PL0_RW, .accessfn = pmreg_access,
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+ .access = PL0_RW, .accessfn = pmreg_access_selr,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
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.writefn = pmselr_write, .raw_writefn = raw_write, },
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write32,
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- .accessfn = pmreg_access },
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+ .accessfn = pmreg_access_ccntr },
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{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
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- .access = PL0_RW, .accessfn = pmreg_access,
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+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
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.type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write, },
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#endif
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* Unimplemented, RAZ/WI. */
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{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
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- .accessfn = pmreg_access },
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+ .accessfn = pmreg_access_xevcntr },
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{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
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.access = PL0_R | PL1_RW, .accessfn = access_tpm,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
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--
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2.7.4
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diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values
Deleted patch
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From: Andrew Jones <drjones@redhat.com>
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The power state spec section 5.1.5 AFFINITY_INFO defines the
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affinity info return values as
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0 ON
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1 OFF
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2 ON_PENDING
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I grepped QEMU for power_state to ensure that no assumptions
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of OFF=0 were being made.
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Signed-off-by: Andrew Jones <drjones@redhat.com>
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Message-id: 20170303123232.4967-1-drjones@redhat.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/cpu.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
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/* These values map onto the return values for
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* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
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typedef enum ARMPSCIState {
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- PSCI_OFF = 0,
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- PSCI_ON = 1,
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+ PSCI_ON = 0,
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+ PSCI_OFF = 1,
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PSCI_ON_PENDING = 2
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} ARMPSCIState;
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--
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2.7.4
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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