[Qemu-devel] [PULL 0/2] target-arm queue
[Qemu-devel] [PULL 00/17] target-arm queue
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Couple of minor patches to sneak in before rc0. The PSCI return
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v2: dropped a couple of cadence_gem changes to ID regs that
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values fix is the most important one.
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caused new clang sanitizer warnings.
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-- PMM
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-- PMM
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The following changes since commit 94b5d57d2f5a3c849cecd65e424bb6f50b998df9:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.9-20170314' into staging (2017-03-14 10:13:19 +0000)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170314
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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for you to fetch changes up to d5affb0d8677e1a8a8fe03fa25005b669e7cdc02:
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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target/arm/arm-powerctl: Fix psci info return values (2017-03-14 11:28:54 +0000)
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* arm-powerctl: Fix psci info return values
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* implement armv8 PMUSERENR (user-mode enable bits)
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Baumann (1):
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Aaron Lindsay (2):
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target/arm: implement armv8 PMUSERENR (user-mode enable bits)
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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target/arm: Mask PMOVSR writes based on supported counters
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Andrew Jones (1):
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Edgar E. Iglesias (8):
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target/arm/arm-powerctl: Fix psci info return values
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net: cadence_gem: Disable TSU feature bit
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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target/arm/cpu.h | 4 +--
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Jerome Forissier (1):
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target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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2 files changed, 73 insertions(+), 10 deletions(-)
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] target/arm: implement armv8 PMUSERENR (user-mode enable bits)
Deleted patch
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From: Andrew Baumann <Andrew.Baumann@microsoft.com>
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In armv8, this register implements more than a single bit, with
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fine-grained enables for read access to event counters, cycles
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counters, and write access to the software increment. This change
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implements those checks using custom access functions for the relevant
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registers.
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Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
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Message-id: 20170228215801.10472-2-Andrew.Baumann@microsoft.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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[PMM: move a couple of access functions to be only compiled
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ifndef CONFIG_USER_ONLY to avoid compiler warnings]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++------
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1 file changed, 71 insertions(+), 8 deletions(-)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
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@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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*/
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int el = arm_current_el(env);
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- if (el == 0 && !env->cp15.c9_pmuserenr) {
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+ if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
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return CP_ACCESS_TRAP;
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}
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if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
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@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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+static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* ER: event counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
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+ && isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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+static CPAccessResult pmreg_access_swinc(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* SW: software increment write trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
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+ && !isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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#ifndef CONFIG_USER_ONLY
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+static CPAccessResult pmreg_access_selr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* ER: event counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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+static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
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+ const ARMCPRegInfo *ri,
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+ bool isread)
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+{
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+ /* CR: cycle counter read trap control */
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+ if (arm_feature(env, ARM_FEATURE_V8)
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+ && arm_current_el(env) == 0
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+ && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
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+ && isread) {
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+ return CP_ACCESS_OK;
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+ }
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+
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+ return pmreg_access(env, ri, isread);
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+}
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+
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static inline bool arm_ccnt_enabled(CPUARMState *env)
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{
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/* This does not support checking PMCCFILTR_EL0 register */
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@@ -XXX,XX +XXX,XX @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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- env->cp15.c9_pmuserenr = value & 1;
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+ if (arm_feature(env, ARM_FEATURE_V8)) {
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+ env->cp15.c9_pmuserenr = value & 0xf;
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+ } else {
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+ env->cp15.c9_pmuserenr = value & 1;
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+ }
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}
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static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.raw_writefn = raw_write },
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/* Unimplemented so WI. */
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{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
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- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
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+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
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#ifndef CONFIG_USER_ONLY
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{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
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.access = PL0_RW, .type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
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- .accessfn = pmreg_access, .writefn = pmselr_write,
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+ .accessfn = pmreg_access_selr, .writefn = pmselr_write,
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.raw_writefn = raw_write},
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{ .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
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- .access = PL0_RW, .accessfn = pmreg_access,
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+ .access = PL0_RW, .accessfn = pmreg_access_selr,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
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.writefn = pmselr_write, .raw_writefn = raw_write, },
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{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
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.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write32,
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- .accessfn = pmreg_access },
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+ .accessfn = pmreg_access_ccntr },
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{ .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
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- .access = PL0_RW, .accessfn = pmreg_access,
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+ .access = PL0_RW, .accessfn = pmreg_access_ccntr,
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.type = ARM_CP_IO,
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.readfn = pmccntr_read, .writefn = pmccntr_write, },
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#endif
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@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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/* Unimplemented, RAZ/WI. */
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{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
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.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
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- .accessfn = pmreg_access },
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+ .accessfn = pmreg_access_xevcntr },
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{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
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.access = PL0_R | PL1_RW, .accessfn = access_tpm,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
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--
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2.7.4
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diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] target/arm/arm-powerctl: Fix psci info return values
Deleted patch
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From: Andrew Jones <drjones@redhat.com>
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The power state spec section 5.1.5 AFFINITY_INFO defines the
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affinity info return values as
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0 ON
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1 OFF
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2 ON_PENDING
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I grepped QEMU for power_state to ensure that no assumptions
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of OFF=0 were being made.
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Signed-off-by: Andrew Jones <drjones@redhat.com>
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Message-id: 20170303123232.4967-1-drjones@redhat.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/cpu.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -XXX,XX +XXX,XX @@ typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
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/* These values map onto the return values for
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* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
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typedef enum ARMPSCIState {
29
- PSCI_OFF = 0,
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- PSCI_ON = 1,
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+ PSCI_ON = 0,
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+ PSCI_OFF = 1,
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PSCI_ON_PENDING = 2
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} ARMPSCIState;
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--
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2.7.4
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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