[Qemu-devel] [PULL 00/21] target-arm queue
[PULL 00/14] target-arm queue
1
Second lot of ARM changes to sneak in before freeze:
1
The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
2
* fixed version of the raspi2 sd controller patches
3
* GICv3 save/restore
4
* v7M QOMify
5
2
6
I've also included the Linux header update patches stolen
3
Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
7
from Paolo's pullreq since it hasn't quite hit master yet.
8
4
9
thanks
5
are available in the Git repository at:
10
-- PMM
11
6
12
The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308
13
8
14
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging (2017-02-28 14:50:17 +0000)
9
for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:
15
10
16
are available in the git repository at:
11
target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)
17
18
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228-1
19
20
for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:
21
22
bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +0000)
23
12
24
----------------------------------------------------------------
13
----------------------------------------------------------------
25
target-arm queue:
14
target-arm queue:
26
* raspi2: add gpio controller and sdhost controller, with
15
* Implement FEAT_ECV
27
the wiring so the guest can switch which controller the
16
* STM32L4x5: Implement GPIO device
28
SD card is attached to
17
* Fix 32-bit SMOPA
29
(this is sufficient to get raspbian kernels to boot)
18
* Refactor v7m related code from cpu32.c into its own file
30
* GICv3: support state save/restore from KVM
19
* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
31
* update Linux headers to 4.11
32
* refactor and QOMify the ARMv7M container object
33
20
34
----------------------------------------------------------------
21
----------------------------------------------------------------
35
Clement Deschamps (3):
22
Inès Varhol (3):
36
hw/sd: add card-reparenting function
23
hw/gpio: Implement STM32L4x5 GPIO
37
bcm2835_gpio: add bcm2835 gpio controller
24
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
38
bcm2835: add sdhost and gpio controllers
25
tests/qtest: Add STM32L4x5 GPIO QTest testcase
39
26
40
Paolo Bonzini (2):
27
Peter Maydell (9):
41
update-linux-headers: update for 4.11
28
target/arm: Move some register related defines to internals.h
42
update Linux headers to 4.11
29
target/arm: Timer _EL02 registers UNDEF for E2H == 0
30
target/arm: use FIELD macro for CNTHCTL bit definitions
31
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
32
target/arm: Implement new FEAT_ECV trap bits
33
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
34
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
35
target/arm: Enable FEAT_ECV for 'max' CPU
36
hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
43
37
44
Peter Maydell (12):
38
Richard Henderson (1):
45
armv7m: Abstract out the "load kernel" code
39
target/arm: Fix 32-bit SMOPA
46
armv7m: Move NVICState struct definition into header
47
armv7m: QOMify the armv7m container
48
armv7m: Use QOMified armv7m object in armv7m_init()
49
armv7m: Make ARMv7M object take memory region link
50
armv7m: Make NVIC expose a memory region rather than mapping itself
51
armv7m: Make bitband device take the address space to access
52
armv7m: Don't put core v7M devices under CONFIG_STELLARIS
53
armv7m: Split systick out from NVIC
54
stm32f205: Create armv7m object without using armv7m_init()
55
stm32f205: Rename 'nvic' local to 'armv7m'
56
qdev: Have qdev_set_parent_bus() handle devices already on a bus
57
40
58
Vijaya Kumar K (4):
41
Thomas Huth (1):
59
hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
42
target/arm: Move v7m-related code from cpu32.c into a separate file
60
hw/intc/arm_gicv3_kvm: Implement get/put functions
61
target-arm: Add GICv3CPUState in CPUARMState struct
62
hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
63
43
64
hw/gpio/Makefile.objs | 1 +
44
MAINTAINERS | 1 +
65
hw/intc/Makefile.objs | 2 +-
45
docs/system/arm/b-l475e-iot01a.rst | 2 +-
66
hw/timer/Makefile.objs | 1 +
46
docs/system/arm/emulation.rst | 1 +
67
hw/intc/gicv3_internal.h | 3 +
47
include/hw/arm/stm32l4x5_soc.h | 2 +
68
include/hw/arm/arm.h | 12 +
48
include/hw/gpio/stm32l4x5_gpio.h | 71 +++++
69
include/hw/arm/armv7m.h | 63 +++
49
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
70
include/hw/arm/armv7m_nvic.h | 62 ++
50
include/hw/rtc/sun4v-rtc.h | 2 +-
71
include/hw/arm/bcm2835_peripherals.h | 4 +
51
target/arm/cpu-features.h | 10 +
72
include/hw/arm/stm32f205_soc.h | 4 +-
52
target/arm/cpu.h | 129 +--------
73
include/hw/gpio/bcm2835_gpio.h | 39 ++
53
target/arm/internals.h | 151 ++++++++++
74
include/hw/intc/arm_gicv3_common.h | 1 +
54
hw/arm/stm32l4x5_soc.c | 71 ++++-
75
include/hw/sd/sd.h | 11 +
55
hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++
76
include/hw/timer/armv7m_systick.h | 34 ++
56
hw/misc/stm32l4x5_syscfg.c | 1 +
77
include/standard-headers/asm-x86/hyperv.h | 8 +
57
hw/rtc/sun4v-rtc.c | 2 +-
78
include/standard-headers/linux/input-event-codes.h | 2 +-
58
target/arm/helper.c | 189 ++++++++++++-
79
include/standard-headers/linux/pci_regs.h | 25 +
59
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++
80
include/standard-headers/linux/virtio_ids.h | 1 +
60
target/arm/tcg/cpu32.c | 261 ------------------
81
linux-headers/asm-arm/kvm.h | 15 +
61
target/arm/tcg/cpu64.c | 1 +
82
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++
62
target/arm/tcg/sme_helper.c | 77 +++---
83
linux-headers/asm-arm/unistd-eabi.h | 5 +
63
tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++
84
linux-headers/asm-arm/unistd-oabi.h | 17 +
64
tests/tcg/aarch64/sme-smopa-1.c | 47 ++++
85
linux-headers/asm-arm/unistd.h | 419 +-------------
65
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++
86
linux-headers/asm-arm64/kvm.h | 13 +
66
hw/arm/Kconfig | 3 +-
87
linux-headers/asm-powerpc/kvm.h | 27 +
67
hw/gpio/Kconfig | 3 +
88
linux-headers/asm-powerpc/unistd.h | 1 +
68
hw/gpio/meson.build | 1 +
89
linux-headers/asm-x86/kvm_para.h | 13 +-
69
hw/gpio/trace-events | 6 +
90
linux-headers/linux/kvm.h | 24 +-
70
target/arm/meson.build | 3 +
91
linux-headers/linux/kvm_para.h | 2 +
71
target/arm/tcg/meson.build | 3 +
92
linux-headers/linux/userfaultfd.h | 67 ++-
72
target/arm/trace-events | 1 +
93
linux-headers/linux/vfio.h | 10 +
73
tests/qtest/meson.build | 3 +-
94
target/arm/cpu.h | 2 +
74
tests/tcg/aarch64/Makefile.target | 2 +-
95
hw/arm/armv7m.c | 379 ++++++++-----
75
31 files changed, 1962 insertions(+), 456 deletions(-)
96
hw/arm/bcm2835_peripherals.c | 43 +-
76
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
97
hw/arm/netduino2.c | 7 +-
77
create mode 100644 hw/gpio/stm32l4x5_gpio.c
98
hw/arm/stm32f205_soc.c | 28 +-
78
create mode 100644 target/arm/tcg/cpu-v7m.c
99
hw/core/qdev.c | 14 +
79
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
100
hw/gpio/bcm2835_gpio.c | 353 ++++++++++++
80
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
101
hw/intc/arm_gicv3_common.c | 38 ++
81
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
102
hw/intc/arm_gicv3_cpuif.c | 8 +
103
hw/intc/arm_gicv3_kvm.c | 629 ++++++++++++++++++++-
104
hw/intc/armv7m_nvic.c | 214 ++-----
105
hw/sd/core.c | 27 +
106
hw/timer/armv7m_systick.c | 240 ++++++++
107
default-configs/arm-softmmu.mak | 2 +
108
hw/timer/trace-events | 6 +
109
scripts/update-linux-headers.sh | 13 +-
110
46 files changed, 2479 insertions(+), 767 deletions(-)
111
create mode 100644 include/hw/arm/armv7m.h
112
create mode 100644 include/hw/arm/armv7m_nvic.h
113
create mode 100644 include/hw/gpio/bcm2835_gpio.h
114
create mode 100644 include/hw/timer/armv7m_systick.h
115
create mode 100644 linux-headers/asm-arm/unistd-common.h
116
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
117
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
118
create mode 100644 hw/gpio/bcm2835_gpio.c
119
create mode 100644 hw/timer/armv7m_systick.c
120
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/21] armv7m: Abstract out the "load kernel" code
Deleted patch
1
Abstract the "load kernel" code out of armv7m_init() into its own
2
function. This includes the registration of the CPU reset function,
3
to parallel how we handle this for A profile cores.
4
1
5
We make the function public so that boards which choose to
6
directly instantiate an ARMv7M device object can call it.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
13
---
14
include/hw/arm/arm.h | 12 ++++++++++++
15
hw/arm/armv7m.c | 23 ++++++++++++++++++-----
16
2 files changed, 30 insertions(+), 5 deletions(-)
17
18
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/arm.h
21
+++ b/include/hw/arm/arm.h
22
@@ -XXX,XX +XXX,XX @@ typedef enum {
23
/* armv7m.c */
24
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
25
const char *kernel_filename, const char *cpu_model);
26
+/**
27
+ * armv7m_load_kernel:
28
+ * @cpu: CPU
29
+ * @kernel_filename: file to load
30
+ * @mem_size: mem_size: maximum image size to load
31
+ *
32
+ * Load the guest image for an ARMv7M system. This must be called by
33
+ * any ARMv7M board, either directly or via armv7m_init(). (This is
34
+ * necessary to ensure that the CPU resets correctly on system reset,
35
+ * as well as for kernel loading.)
36
+ */
37
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
38
39
/*
40
* struct used as a parameter of the arm_load_kernel machine init
41
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/armv7m.c
44
+++ b/hw/arm/armv7m.c
45
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
46
ARMCPU *cpu;
47
CPUARMState *env;
48
DeviceState *nvic;
49
- int image_size;
50
- uint64_t entry;
51
- uint64_t lowaddr;
52
- int big_endian;
53
54
if (cpu_model == NULL) {
55
    cpu_model = "cortex-m3";
56
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
57
qdev_init_nofail(nvic);
58
sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
59
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
60
+ armv7m_load_kernel(cpu, kernel_filename, mem_size);
61
+ return nvic;
62
+}
63
+
64
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
65
+{
66
+ int image_size;
67
+ uint64_t entry;
68
+ uint64_t lowaddr;
69
+ int big_endian;
70
71
#ifdef TARGET_WORDS_BIGENDIAN
72
big_endian = 1;
73
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
74
}
75
}
76
77
+ /* CPU objects (unlike devices) are not automatically reset on system
78
+ * reset, so we must always register a handler to do so. Unlike
79
+ * A-profile CPUs, we don't need to do anything special in the
80
+ * handler to arrange that it starts correctly.
81
+ * This is arguably the wrong place to do this, but it matches the
82
+ * way A-profile does it. Note that this means that every M profile
83
+ * board must call this function!
84
+ */
85
qemu_register_reset(armv7m_reset, cpu);
86
- return nvic;
87
}
88
89
static Property bitband_properties[] = {
90
--
91
2.7.4
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/21] target-arm: Add GICv3CPUState in CPUARMState struct
[PULL 01/14] target/arm: Move some register related defines to internals.h
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
cpu.h has a lot of #defines relating to CPU register fields.
2
Most of these aren't actually used outside target/arm code,
3
so there's no point in cluttering up the cpu.h file with them.
4
Move some easy ones to internals.h.
2
5
3
Add gicv3state void pointer to CPUARMState struct
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to store GICv3CPUState.
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 128 -----------------------------------------
12
target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++
13
2 files changed, 128 insertions(+), 128 deletions(-)
5
14
6
In case of usecase like CPU reset, we need to reset
7
GICv3CPUState of the CPU. In such scenario, this pointer
8
becomes handy.
9
10
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 1487850673-26455-5-git-send-email-vijay.kilari@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/intc/gicv3_internal.h | 2 ++
17
target/arm/cpu.h | 2 ++
18
hw/intc/arm_gicv3_common.c | 2 ++
19
hw/intc/arm_gicv3_cpuif.c | 8 ++++++++
20
4 files changed, 14 insertions(+)
21
22
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/gicv3_internal.h
25
+++ b/hw/intc/gicv3_internal.h
26
@@ -XXX,XX +XXX,XX @@ static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
27
}
28
}
29
30
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
31
+
32
#endif /* QEMU_ARM_GICV3_INTERNAL_H */
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
17
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
@@ -XXX,XX +XXX,XX @@ typedef struct ARMGenericTimer {
38
20
uint64_t ctl; /* Timer Control register */
39
void *nvic;
21
} ARMGenericTimer;
40
const struct arm_boot_info *boot_info;
22
41
+ /* Store GICv3CPUState to access from this struct */
23
-#define VTCR_NSW (1u << 29)
42
+ void *gicv3state;
24
-#define VTCR_NSA (1u << 30)
43
} CPUARMState;
25
-#define VSTCR_SW VTCR_NSW
44
26
-#define VSTCR_SA VTCR_NSA
45
/**
27
-
46
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
28
/* Define a maximum sized vector register.
29
* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
30
* For 64-bit, this is a 2048-bit SVE register.
31
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
32
#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
33
#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
34
35
-/* Bit definitions for CPACR (AArch32 only) */
36
-FIELD(CPACR, CP10, 20, 2)
37
-FIELD(CPACR, CP11, 22, 2)
38
-FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
39
-FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
40
-FIELD(CPACR, ASEDIS, 31, 1)
41
-
42
-/* Bit definitions for CPACR_EL1 (AArch64 only) */
43
-FIELD(CPACR_EL1, ZEN, 16, 2)
44
-FIELD(CPACR_EL1, FPEN, 20, 2)
45
-FIELD(CPACR_EL1, SMEN, 24, 2)
46
-FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
47
-
48
-/* Bit definitions for HCPTR (AArch32 only) */
49
-FIELD(HCPTR, TCP10, 10, 1)
50
-FIELD(HCPTR, TCP11, 11, 1)
51
-FIELD(HCPTR, TASE, 15, 1)
52
-FIELD(HCPTR, TTA, 20, 1)
53
-FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
54
-FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
55
-
56
-/* Bit definitions for CPTR_EL2 (AArch64 only) */
57
-FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
58
-FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
59
-FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
60
-FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
61
-FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
62
-FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
63
-FIELD(CPTR_EL2, TTA, 28, 1)
64
-FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
65
-FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
66
-
67
-/* Bit definitions for CPTR_EL3 (AArch64 only) */
68
-FIELD(CPTR_EL3, EZ, 8, 1)
69
-FIELD(CPTR_EL3, TFP, 10, 1)
70
-FIELD(CPTR_EL3, ESM, 12, 1)
71
-FIELD(CPTR_EL3, TTA, 20, 1)
72
-FIELD(CPTR_EL3, TAM, 30, 1)
73
-FIELD(CPTR_EL3, TCPAC, 31, 1)
74
-
75
-#define MDCR_MTPME (1U << 28)
76
-#define MDCR_TDCC (1U << 27)
77
-#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
78
-#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
79
-#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
80
-#define MDCR_EPMAD (1U << 21)
81
-#define MDCR_EDAD (1U << 20)
82
-#define MDCR_TTRF (1U << 19)
83
-#define MDCR_STE (1U << 18) /* MDCR_EL3 */
84
-#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
85
-#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
86
-#define MDCR_SDD (1U << 16)
87
-#define MDCR_SPD (3U << 14)
88
-#define MDCR_TDRA (1U << 11)
89
-#define MDCR_TDOSA (1U << 10)
90
-#define MDCR_TDA (1U << 9)
91
-#define MDCR_TDE (1U << 8)
92
-#define MDCR_HPME (1U << 7)
93
-#define MDCR_TPM (1U << 6)
94
-#define MDCR_TPMCR (1U << 5)
95
-#define MDCR_HPMN (0x1fU)
96
-
97
-/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
98
-#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
99
- MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
100
- MDCR_STE | MDCR_SPME | MDCR_SPD)
101
-
102
#define CPSR_M (0x1fU)
103
#define CPSR_T (1U << 5)
104
#define CPSR_F (1U << 6)
105
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
106
#define XPSR_NZCV CPSR_NZCV
107
#define XPSR_IT CPSR_IT
108
109
-#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
110
-#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
111
-#define TTBCR_PD0 (1U << 4)
112
-#define TTBCR_PD1 (1U << 5)
113
-#define TTBCR_EPD0 (1U << 7)
114
-#define TTBCR_IRGN0 (3U << 8)
115
-#define TTBCR_ORGN0 (3U << 10)
116
-#define TTBCR_SH0 (3U << 12)
117
-#define TTBCR_T1SZ (3U << 16)
118
-#define TTBCR_A1 (1U << 22)
119
-#define TTBCR_EPD1 (1U << 23)
120
-#define TTBCR_IRGN1 (3U << 24)
121
-#define TTBCR_ORGN1 (3U << 26)
122
-#define TTBCR_SH1 (1U << 28)
123
-#define TTBCR_EAE (1U << 31)
124
-
125
-FIELD(VTCR, T0SZ, 0, 6)
126
-FIELD(VTCR, SL0, 6, 2)
127
-FIELD(VTCR, IRGN0, 8, 2)
128
-FIELD(VTCR, ORGN0, 10, 2)
129
-FIELD(VTCR, SH0, 12, 2)
130
-FIELD(VTCR, TG0, 14, 2)
131
-FIELD(VTCR, PS, 16, 3)
132
-FIELD(VTCR, VS, 19, 1)
133
-FIELD(VTCR, HA, 21, 1)
134
-FIELD(VTCR, HD, 22, 1)
135
-FIELD(VTCR, HWU59, 25, 1)
136
-FIELD(VTCR, HWU60, 26, 1)
137
-FIELD(VTCR, HWU61, 27, 1)
138
-FIELD(VTCR, HWU62, 28, 1)
139
-FIELD(VTCR, NSW, 29, 1)
140
-FIELD(VTCR, NSA, 30, 1)
141
-FIELD(VTCR, DS, 32, 1)
142
-FIELD(VTCR, SL2, 33, 1)
143
-
144
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
145
* Only these are valid when in AArch64 mode; in
146
* AArch32 mode SPSRs are basically CPSR-format.
147
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
148
#define HCR_TWEDEN (1ULL << 59)
149
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
150
151
-#define HCRX_ENAS0 (1ULL << 0)
152
-#define HCRX_ENALS (1ULL << 1)
153
-#define HCRX_ENASR (1ULL << 2)
154
-#define HCRX_FNXS (1ULL << 3)
155
-#define HCRX_FGTNXS (1ULL << 4)
156
-#define HCRX_SMPME (1ULL << 5)
157
-#define HCRX_TALLINT (1ULL << 6)
158
-#define HCRX_VINMI (1ULL << 7)
159
-#define HCRX_VFNMI (1ULL << 8)
160
-#define HCRX_CMOW (1ULL << 9)
161
-#define HCRX_MCE2 (1ULL << 10)
162
-#define HCRX_MSCEN (1ULL << 11)
163
-
164
-#define HPFAR_NS (1ULL << 63)
165
-
166
#define SCR_NS (1ULL << 0)
167
#define SCR_IRQ (1ULL << 1)
168
#define SCR_FIQ (1ULL << 2)
169
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
170
#define SCR_GPF (1ULL << 48)
171
#define SCR_NSE (1ULL << 62)
172
173
-#define HSTR_TTEE (1 << 16)
174
-#define HSTR_TJDBX (1 << 17)
175
-
176
-#define CNTHCTL_CNTVMASK (1 << 18)
177
-#define CNTHCTL_CNTPMASK (1 << 19)
178
-
179
/* Return the current FPSCR value. */
180
uint32_t vfp_get_fpscr(CPUARMState *env);
181
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
182
diff --git a/target/arm/internals.h b/target/arm/internals.h
47
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_common.c
184
--- a/target/arm/internals.h
49
+++ b/hw/intc/arm_gicv3_common.c
185
+++ b/target/arm/internals.h
50
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
186
@@ -XXX,XX +XXX,XX @@ FIELD(DBGWCR, WT, 20, 1)
51
187
FIELD(DBGWCR, MASK, 24, 5)
52
s->cpu[i].cpu = cpu;
188
FIELD(DBGWCR, SSCE, 29, 1)
53
s->cpu[i].gic = s;
189
54
+ /* Store GICv3CPUState in CPUARMState gicv3state pointer */
190
+#define VTCR_NSW (1u << 29)
55
+ gicv3_set_gicv3state(cpu, &s->cpu[i]);
191
+#define VTCR_NSA (1u << 30)
56
192
+#define VSTCR_SW VTCR_NSW
57
/* Pre-construct the GICR_TYPER:
193
+#define VSTCR_SA VTCR_NSA
58
* For our implementation:
194
+
59
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
195
+/* Bit definitions for CPACR (AArch32 only) */
60
index XXXXXXX..XXXXXXX 100644
196
+FIELD(CPACR, CP10, 20, 2)
61
--- a/hw/intc/arm_gicv3_cpuif.c
197
+FIELD(CPACR, CP11, 22, 2)
62
+++ b/hw/intc/arm_gicv3_cpuif.c
198
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
63
@@ -XXX,XX +XXX,XX @@
199
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
64
#include "gicv3_internal.h"
200
+FIELD(CPACR, ASEDIS, 31, 1)
65
#include "cpu.h"
201
+
66
202
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
203
+FIELD(CPACR_EL1, ZEN, 16, 2)
68
+{
204
+FIELD(CPACR_EL1, FPEN, 20, 2)
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
205
+FIELD(CPACR_EL1, SMEN, 24, 2)
70
+ CPUARMState *env = &arm_cpu->env;
206
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
71
+
207
+
72
+ env->gicv3state = (void *)s;
208
+/* Bit definitions for HCPTR (AArch32 only) */
73
+};
209
+FIELD(HCPTR, TCP10, 10, 1)
74
+
210
+FIELD(HCPTR, TCP11, 11, 1)
75
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
211
+FIELD(HCPTR, TASE, 15, 1)
76
{
212
+FIELD(HCPTR, TTA, 20, 1)
77
/* Given the CPU, find the right GICv3CPUState struct.
213
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
214
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
215
+
216
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
217
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
218
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
219
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
220
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
221
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
222
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
223
+FIELD(CPTR_EL2, TTA, 28, 1)
224
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
225
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
226
+
227
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
228
+FIELD(CPTR_EL3, EZ, 8, 1)
229
+FIELD(CPTR_EL3, TFP, 10, 1)
230
+FIELD(CPTR_EL3, ESM, 12, 1)
231
+FIELD(CPTR_EL3, TTA, 20, 1)
232
+FIELD(CPTR_EL3, TAM, 30, 1)
233
+FIELD(CPTR_EL3, TCPAC, 31, 1)
234
+
235
+#define MDCR_MTPME (1U << 28)
236
+#define MDCR_TDCC (1U << 27)
237
+#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
238
+#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
239
+#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
240
+#define MDCR_EPMAD (1U << 21)
241
+#define MDCR_EDAD (1U << 20)
242
+#define MDCR_TTRF (1U << 19)
243
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
244
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
245
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
246
+#define MDCR_SDD (1U << 16)
247
+#define MDCR_SPD (3U << 14)
248
+#define MDCR_TDRA (1U << 11)
249
+#define MDCR_TDOSA (1U << 10)
250
+#define MDCR_TDA (1U << 9)
251
+#define MDCR_TDE (1U << 8)
252
+#define MDCR_HPME (1U << 7)
253
+#define MDCR_TPM (1U << 6)
254
+#define MDCR_TPMCR (1U << 5)
255
+#define MDCR_HPMN (0x1fU)
256
+
257
+/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
258
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
259
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
260
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
261
+
262
+#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
263
+#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
264
+#define TTBCR_PD0 (1U << 4)
265
+#define TTBCR_PD1 (1U << 5)
266
+#define TTBCR_EPD0 (1U << 7)
267
+#define TTBCR_IRGN0 (3U << 8)
268
+#define TTBCR_ORGN0 (3U << 10)
269
+#define TTBCR_SH0 (3U << 12)
270
+#define TTBCR_T1SZ (3U << 16)
271
+#define TTBCR_A1 (1U << 22)
272
+#define TTBCR_EPD1 (1U << 23)
273
+#define TTBCR_IRGN1 (3U << 24)
274
+#define TTBCR_ORGN1 (3U << 26)
275
+#define TTBCR_SH1 (1U << 28)
276
+#define TTBCR_EAE (1U << 31)
277
+
278
+FIELD(VTCR, T0SZ, 0, 6)
279
+FIELD(VTCR, SL0, 6, 2)
280
+FIELD(VTCR, IRGN0, 8, 2)
281
+FIELD(VTCR, ORGN0, 10, 2)
282
+FIELD(VTCR, SH0, 12, 2)
283
+FIELD(VTCR, TG0, 14, 2)
284
+FIELD(VTCR, PS, 16, 3)
285
+FIELD(VTCR, VS, 19, 1)
286
+FIELD(VTCR, HA, 21, 1)
287
+FIELD(VTCR, HD, 22, 1)
288
+FIELD(VTCR, HWU59, 25, 1)
289
+FIELD(VTCR, HWU60, 26, 1)
290
+FIELD(VTCR, HWU61, 27, 1)
291
+FIELD(VTCR, HWU62, 28, 1)
292
+FIELD(VTCR, NSW, 29, 1)
293
+FIELD(VTCR, NSA, 30, 1)
294
+FIELD(VTCR, DS, 32, 1)
295
+FIELD(VTCR, SL2, 33, 1)
296
+
297
+#define HCRX_ENAS0 (1ULL << 0)
298
+#define HCRX_ENALS (1ULL << 1)
299
+#define HCRX_ENASR (1ULL << 2)
300
+#define HCRX_FNXS (1ULL << 3)
301
+#define HCRX_FGTNXS (1ULL << 4)
302
+#define HCRX_SMPME (1ULL << 5)
303
+#define HCRX_TALLINT (1ULL << 6)
304
+#define HCRX_VINMI (1ULL << 7)
305
+#define HCRX_VFNMI (1ULL << 8)
306
+#define HCRX_CMOW (1ULL << 9)
307
+#define HCRX_MCE2 (1ULL << 10)
308
+#define HCRX_MSCEN (1ULL << 11)
309
+
310
+#define HPFAR_NS (1ULL << 63)
311
+
312
+#define HSTR_TTEE (1 << 16)
313
+#define HSTR_TJDBX (1 << 17)
314
+
315
+#define CNTHCTL_CNTVMASK (1 << 18)
316
+#define CNTHCTL_CNTPMASK (1 << 19)
317
+
318
/* We use a few fake FSR values for internal purposes in M profile.
319
* M profile cores don't have A/R format FSRs, but currently our
320
* get_phys_addr() code assumes A/R profile and reports failures via
78
--
321
--
79
2.7.4
322
2.34.1
80
323
81
324
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/21] qdev: Have qdev_set_parent_bus() handle devices already on a bus
[PULL 02/14] target/arm: Timer _EL02 registers UNDEF for E2H == 0
1
Instead of qdev_set_parent_bus() silently doing the wrong
1
The timer _EL02 registers should UNDEF for invalid accesses from EL2
2
thing if it's handed a device that's already on a bus,
2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
3
have it remove the device from the old bus and add it to
3
delivering the exception to EL2 with the wrong syndrome.
4
the new one. This is useful for the raspi2 sdcard.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1488293711-14195-2-git-send-email-peter.maydell@linaro.org
7
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
9
---
8
---
10
hw/core/qdev.c | 14 ++++++++++++++
9
target/arm/helper.c | 2 +-
11
1 file changed, 14 insertions(+)
10
1 file changed, 1 insertion(+), 1 deletion(-)
12
11
13
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/core/qdev.c
14
--- a/target/arm/helper.c
16
+++ b/hw/core/qdev.c
15
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
16
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
18
17
return CP_ACCESS_OK;
19
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
18
}
20
{
19
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
21
+ bool replugging = dev->parent_bus != NULL;
20
- return CP_ACCESS_TRAP;
22
+
21
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
23
+ if (replugging) {
22
}
24
+ /* Keep a reference to the device while it's not plugged into
23
return CP_ACCESS_OK;
25
+ * any bus, to avoid it potentially evaporating when it is
26
+ * dereffed in bus_remove_child().
27
+ */
28
+ object_ref(OBJECT(dev));
29
+ bus_remove_child(dev->parent_bus, dev);
30
+ object_unref(OBJECT(dev->parent_bus));
31
+ }
32
dev->parent_bus = bus;
33
object_ref(OBJECT(bus));
34
bus_add_child(bus, dev);
35
+ if (replugging) {
36
+ object_unref(OBJECT(dev));
37
+ }
38
}
24
}
39
40
/* Create a new device. This only initializes the device state
41
--
25
--
42
2.7.4
26
2.34.1
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/21] armv7m: Make ARMv7M object take memory region link
[PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions
1
Make the ARMv7M object take a memory region link which it uses
1
We prefer the FIELD macro over ad-hoc #defines for register bits;
2
to wire up the bitband rather than having them always put
2
switch CNTHCTL to that style before we add any more bits.
3
themselves in the system address space.
4
3
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
8
---
8
---
9
include/hw/arm/armv7m.h | 10 ++++++++++
9
target/arm/internals.h | 27 +++++++++++++++++++++++++--
10
hw/arm/armv7m.c | 23 ++++++++++++++++++++++-
10
target/arm/helper.c | 9 ++++-----
11
2 files changed, 32 insertions(+), 1 deletion(-)
11
2 files changed, 29 insertions(+), 7 deletions(-)
12
12
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/armv7m.h
15
--- a/target/arm/internals.h
16
+++ b/include/hw/arm/armv7m.h
16
+++ b/target/arm/internals.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct {
17
@@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1)
18
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
18
#define HSTR_TTEE (1 << 16)
19
* + Property "cpu-model": CPU model to instantiate
19
#define HSTR_TJDBX (1 << 17)
20
* + Property "num-irq": number of external IRQ lines
20
21
+ * + Property "memory": MemoryRegion defining the physical address space
21
-#define CNTHCTL_CNTVMASK (1 << 18)
22
+ * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
22
-#define CNTHCTL_CNTPMASK (1 << 19)
23
+ * devices will be automatically layered on top of this view.)
23
+/*
24
*/
24
+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1
25
typedef struct ARMv7MState {
25
+ * have different bit definitions, and EL1PCTEN might be
26
/*< private >*/
26
+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
27
+ * disambiguate if necessary.
28
BitBandState bitband[ARMV7M_NUM_BITBANDS];
28
+ */
29
ARMCPU *cpu;
29
+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
30
30
+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)
31
+ /* MemoryRegion we pass to the CPU, with our devices layered on
31
+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
32
+ * top of the ones the board provides in board_memory.
32
+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)
33
+ */
33
+FIELD(CNTHCTL, EVNTEN, 2, 1)
34
+ MemoryRegion container;
34
+FIELD(CNTHCTL, EVNTDIR, 3, 1)
35
+
35
+FIELD(CNTHCTL, EVNTI, 4, 4)
36
/* Properties */
36
+FIELD(CNTHCTL, EL0VTEN, 8, 1)
37
char *cpu_model;
37
+FIELD(CNTHCTL, EL0PTEN, 9, 1)
38
+ /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
38
+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)
39
+ MemoryRegion *board_memory;
39
+FIELD(CNTHCTL, EL1PTEN, 11, 1)
40
} ARMv7MState;
40
+FIELD(CNTHCTL, ECV, 12, 1)
41
41
+FIELD(CNTHCTL, EL1TVT, 13, 1)
42
#endif
42
+FIELD(CNTHCTL, EL1TVCT, 14, 1)
43
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
43
+FIELD(CNTHCTL, EL1NVPCT, 15, 1)
44
+FIELD(CNTHCTL, EL1NVVCT, 16, 1)
45
+FIELD(CNTHCTL, EVNTIS, 17, 1)
46
+FIELD(CNTHCTL, CNTVMASK, 18, 1)
47
+FIELD(CNTHCTL, CNTPMASK, 19, 1)
48
49
/* We use a few fake FSR values for internal purposes in M profile.
50
* M profile cores don't have A/R format FSRs, but currently our
51
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/armv7m.c
53
--- a/target/arm/helper.c
46
+++ b/hw/arm/armv7m.c
54
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
48
#include "elf.h"
56
* It is RES0 in Secure and NonSecure state.
49
#include "sysemu/qtest.h"
57
*/
50
#include "qemu/error-report.h"
58
if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
51
+#include "exec/address-spaces.h"
59
- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
52
60
- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
53
/* Bitbanded IO. Each word corresponds to a single bit. */
61
+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
54
62
+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
55
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
63
irqstate = 0;
56
57
/* Can't init the cpu here, we don't yet know which model to use */
58
59
+ object_property_add_link(obj, "memory",
60
+ TYPE_MEMORY_REGION,
61
+ (Object **)&s->board_memory,
62
+ qdev_prop_allow_set_link_before_realize,
63
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
64
+ &error_abort);
65
+ memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
66
+
67
object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
68
qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
69
object_property_add_alias(obj, "num-irq",
70
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
71
const char *typename;
72
CPUClass *cc;
73
74
+ if (!s->board_memory) {
75
+ error_setg(errp, "memory property was not set");
76
+ return;
77
+ }
78
+
79
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
80
+
81
cpustr = g_strsplit(s->cpu_model, ",", 2);
82
83
oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
84
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
85
return;
86
}
64
}
87
65
88
+ object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
66
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
89
+ &error_abort);
67
{
90
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
68
ARMCPU *cpu = env_archcpu(env);
91
if (err != NULL) {
69
uint32_t oldval = env->cp15.cnthctl_el2;
92
error_propagate(errp, err);
70
-
93
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
71
raw_write(env, ri, value);
94
return;
72
95
}
73
- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
96
74
+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
97
- sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
75
gt_update_irq(cpu, GTIMER_VIRT);
98
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
76
- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
99
+ sysbus_mmio_get_region(sbd, 0));
77
+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
78
gt_update_irq(cpu, GTIMER_PHYS);
100
}
79
}
101
}
80
}
102
103
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
104
armv7m = qdev_create(NULL, "armv7m");
105
qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
106
qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
107
+ object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
108
+ "memory", &error_abort);
109
/* This will exit with an error if the user passed us a bad cpu_model */
110
qdev_init_nofail(armv7m);
111
112
--
81
--
113
2.7.4
82
2.34.1
114
83
115
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/21] armv7m: Make bitband device take the address space to access
[PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
1
Instead of the bitband device doing a cpu_physical_memory_read/write,
1
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
2
make it take a MemoryRegion which specifies where it should be
2
This is not strictly architecturally required, but it is how we've
3
accessing, and use address_space_read/write to access the
3
tended to implement registers more recently.
4
corresponding AddressSpace.
5
4
6
Since this entails pretty much a rewrite, convert away from
5
In particular, bits [19:18] are only present with FEAT_RME,
7
old_mmio in the process.
6
and bits [17:12] will only be present with FEAT_ECV.
8
7
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
10
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
12
---
11
---
13
include/hw/arm/armv7m.h | 2 +
12
target/arm/helper.c | 18 ++++++++++++++++++
14
hw/arm/armv7m.c | 166 +++++++++++++++++++++++-------------------------
13
1 file changed, 18 insertions(+)
15
2 files changed, 81 insertions(+), 87 deletions(-)
16
14
17
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/armv7m.h
17
--- a/target/arm/helper.c
20
+++ b/include/hw/arm/armv7m.h
18
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
22
SysBusDevice parent_obj;
23
/*< public >*/
24
25
+ AddressSpace *source_as;
26
MemoryRegion iomem;
27
uint32_t base;
28
+ MemoryRegion *source_memory;
29
} BitBandState;
30
31
#define TYPE_ARMV7M "armv7m"
32
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/armv7m.c
35
+++ b/hw/arm/armv7m.c
36
@@ -XXX,XX +XXX,XX @@
37
/* Bitbanded IO. Each word corresponds to a single bit. */
38
39
/* Get the byte address of the real memory for a bitband access. */
40
-static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
41
+static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
42
{
20
{
43
- uint32_t res;
21
ARMCPU *cpu = env_archcpu(env);
44
-
22
uint32_t oldval = env->cp15.cnthctl_el2;
45
- res = *(uint32_t *)opaque;
23
+ uint32_t valid_mask =
46
- res |= (addr & 0x1ffffff) >> 5;
24
+ R_CNTHCTL_EL0PCTEN_E2H1_MASK |
47
- return res;
25
+ R_CNTHCTL_EL0VCTEN_E2H1_MASK |
48
-
26
+ R_CNTHCTL_EVNTEN_MASK |
49
-}
27
+ R_CNTHCTL_EVNTDIR_MASK |
50
-
28
+ R_CNTHCTL_EVNTI_MASK |
51
-static uint32_t bitband_readb(void *opaque, hwaddr offset)
29
+ R_CNTHCTL_EL0VTEN_MASK |
52
-{
30
+ R_CNTHCTL_EL0PTEN_MASK |
53
- uint8_t v;
31
+ R_CNTHCTL_EL1PCTEN_E2H1_MASK |
54
- cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
32
+ R_CNTHCTL_EL1PTEN_MASK;
55
- return (v & (1 << ((offset >> 2) & 7))) != 0;
56
-}
57
-
58
-static void bitband_writeb(void *opaque, hwaddr offset,
59
- uint32_t value)
60
-{
61
- uint32_t addr;
62
- uint8_t mask;
63
- uint8_t v;
64
- addr = bitband_addr(opaque, offset);
65
- mask = (1 << ((offset >> 2) & 7));
66
- cpu_physical_memory_read(addr, &v, 1);
67
- if (value & 1)
68
- v |= mask;
69
- else
70
- v &= ~mask;
71
- cpu_physical_memory_write(addr, &v, 1);
72
-}
73
-
74
-static uint32_t bitband_readw(void *opaque, hwaddr offset)
75
-{
76
- uint32_t addr;
77
- uint16_t mask;
78
- uint16_t v;
79
- addr = bitband_addr(opaque, offset) & ~1;
80
- mask = (1 << ((offset >> 2) & 15));
81
- mask = tswap16(mask);
82
- cpu_physical_memory_read(addr, &v, 2);
83
- return (v & mask) != 0;
84
-}
85
-
86
-static void bitband_writew(void *opaque, hwaddr offset,
87
- uint32_t value)
88
-{
89
- uint32_t addr;
90
- uint16_t mask;
91
- uint16_t v;
92
- addr = bitband_addr(opaque, offset) & ~1;
93
- mask = (1 << ((offset >> 2) & 15));
94
- mask = tswap16(mask);
95
- cpu_physical_memory_read(addr, &v, 2);
96
- if (value & 1)
97
- v |= mask;
98
- else
99
- v &= ~mask;
100
- cpu_physical_memory_write(addr, &v, 2);
101
+ return s->base | (offset & 0x1ffffff) >> 5;
102
}
103
104
-static uint32_t bitband_readl(void *opaque, hwaddr offset)
105
+static MemTxResult bitband_read(void *opaque, hwaddr offset,
106
+ uint64_t *data, unsigned size, MemTxAttrs attrs)
107
{
108
- uint32_t addr;
109
- uint32_t mask;
110
- uint32_t v;
111
- addr = bitband_addr(opaque, offset) & ~3;
112
- mask = (1 << ((offset >> 2) & 31));
113
- mask = tswap32(mask);
114
- cpu_physical_memory_read(addr, &v, 4);
115
- return (v & mask) != 0;
116
+ BitBandState *s = opaque;
117
+ uint8_t buf[4];
118
+ MemTxResult res;
119
+ int bitpos, bit;
120
+ hwaddr addr;
121
+
33
+
122
+ assert(size <= 4);
34
+ if (cpu_isar_feature(aa64_rme, cpu)) {
123
+
35
+ valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
124
+ /* Find address in underlying memory and round down to multiple of size */
125
+ addr = bitband_addr(s, offset) & (-size);
126
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
127
+ if (res) {
128
+ return res;
129
+ }
130
+ /* Bit position in the N bytes read... */
131
+ bitpos = (offset >> 2) & ((size * 8) - 1);
132
+ /* ...converted to byte in buffer and bit in byte */
133
+ bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
134
+ *data = bit;
135
+ return MEMTX_OK;
136
}
137
138
-static void bitband_writel(void *opaque, hwaddr offset,
139
- uint32_t value)
140
+static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
141
+ unsigned size, MemTxAttrs attrs)
142
{
143
- uint32_t addr;
144
- uint32_t mask;
145
- uint32_t v;
146
- addr = bitband_addr(opaque, offset) & ~3;
147
- mask = (1 << ((offset >> 2) & 31));
148
- mask = tswap32(mask);
149
- cpu_physical_memory_read(addr, &v, 4);
150
- if (value & 1)
151
- v |= mask;
152
- else
153
- v &= ~mask;
154
- cpu_physical_memory_write(addr, &v, 4);
155
+ BitBandState *s = opaque;
156
+ uint8_t buf[4];
157
+ MemTxResult res;
158
+ int bitpos, bit;
159
+ hwaddr addr;
160
+
161
+ assert(size <= 4);
162
+
163
+ /* Find address in underlying memory and round down to multiple of size */
164
+ addr = bitband_addr(s, offset) & (-size);
165
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
166
+ if (res) {
167
+ return res;
168
+ }
169
+ /* Bit position in the N bytes read... */
170
+ bitpos = (offset >> 2) & ((size * 8) - 1);
171
+ /* ...converted to byte in buffer and bit in byte */
172
+ bit = 1 << (bitpos & 7);
173
+ if (value & 1) {
174
+ buf[bitpos >> 3] |= bit;
175
+ } else {
176
+ buf[bitpos >> 3] &= ~bit;
177
+ }
178
+ return address_space_write(s->source_as, addr, attrs, buf, size);
179
}
180
181
static const MemoryRegionOps bitband_ops = {
182
- .old_mmio = {
183
- .read = { bitband_readb, bitband_readw, bitband_readl, },
184
- .write = { bitband_writeb, bitband_writew, bitband_writel, },
185
- },
186
+ .read_with_attrs = bitband_read,
187
+ .write_with_attrs = bitband_write,
188
.endianness = DEVICE_NATIVE_ENDIAN,
189
+ .impl.min_access_size = 1,
190
+ .impl.max_access_size = 4,
191
+ .valid.min_access_size = 1,
192
+ .valid.max_access_size = 4,
193
};
194
195
static void bitband_init(Object *obj)
196
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
197
BitBandState *s = BITBAND(obj);
198
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
199
200
- memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
201
+ object_property_add_link(obj, "source-memory",
202
+ TYPE_MEMORY_REGION,
203
+ (Object **)&s->source_memory,
204
+ qdev_prop_allow_set_link_before_realize,
205
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
206
+ &error_abort);
207
+ memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
208
"bitband", 0x02000000);
209
sysbus_init_mmio(dev, &s->iomem);
210
}
211
212
+static void bitband_realize(DeviceState *dev, Error **errp)
213
+{
214
+ BitBandState *s = BITBAND(dev);
215
+
216
+ if (!s->source_memory) {
217
+ error_setg(errp, "source-memory property not set");
218
+ return;
219
+ }
36
+ }
220
+
37
+
221
+ s->source_as = address_space_init_shareable(s->source_memory,
38
+ /* Clear RES0 bits */
222
+ "bitband-source");
39
+ value &= valid_mask;
223
+}
224
+
40
+
225
/* Board init. */
41
raw_write(env, ri, value);
226
42
227
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
43
if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
228
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
229
error_propagate(errp, err);
230
return;
231
}
232
+ object_property_set_link(obj, OBJECT(s->board_memory),
233
+ "source-memory", &error_abort);
234
object_property_set_bool(obj, true, "realized", &err);
235
if (err != NULL) {
236
error_propagate(errp, err);
237
@@ -XXX,XX +XXX,XX @@ static void bitband_class_init(ObjectClass *klass, void *data)
238
{
239
DeviceClass *dc = DEVICE_CLASS(klass);
240
241
+ dc->realize = bitband_realize;
242
dc->props = bitband_properties;
243
}
244
245
--
44
--
246
2.7.4
45
2.34.1
247
248
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/21] armv7m: QOMify the armv7m container
[PULL 05/14] target/arm: Implement new FEAT_ECV trap bits
1
Create a proper QOM object for the armv7m container, which
1
The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:
2
holds the CPU, the NVIC and the bitband regions.
2
* four new trap bits for various counter and timer registers
3
* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control
4
scaling of the event stream. This is a no-op for us, because we don't
5
implement the event stream (our WFE is a NOP): all we need to do is
6
allow CNTHCTL_EL2.ENVTIS to be read and written.
7
* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and
8
TRFCR_EL2.TS: these are all no-ops for us, because we don't implement
9
FEAT_SPE or FEAT_TRF.
10
* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are
11
"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning
12
that no barriers are needed around their accesses. For us these
13
are just the same as the normal views, because all our sysregs are
14
inherently self-sychronizing.
15
16
In this commit we implement the trap handling and permit the new
17
CNTHCTL_EL2 bits to be written.
3
18
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
21
Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
7
---
22
---
8
include/hw/arm/armv7m.h | 51 ++++++++++++++++++
23
target/arm/cpu-features.h | 5 ++++
9
hw/arm/armv7m.c | 139 +++++++++++++++++++++++++++++++++++++++++++-----
24
target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++----
10
2 files changed, 178 insertions(+), 12 deletions(-)
25
2 files changed, 51 insertions(+), 5 deletions(-)
11
create mode 100644 include/hw/arm/armv7m.h
12
26
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
27
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
14
new file mode 100644
15
index XXXXXXX..XXXXXXX
16
--- /dev/null
17
+++ b/include/hw/arm/armv7m.h
18
@@ -XXX,XX +XXX,XX @@
19
+/*
20
+ * ARMv7M CPU object
21
+ *
22
+ * Copyright (c) 2017 Linaro Ltd
23
+ * Written by Peter Maydell <peter.maydell@linaro.org>
24
+ *
25
+ * This code is licensed under the GPL version 2 or later.
26
+ */
27
+
28
+#ifndef HW_ARM_ARMV7M_H
29
+#define HW_ARM_ARMV7M_H
30
+
31
+#include "hw/sysbus.h"
32
+#include "hw/arm/armv7m_nvic.h"
33
+
34
+#define TYPE_BITBAND "ARM,bitband-memory"
35
+#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
36
+
37
+typedef struct {
38
+ /*< private >*/
39
+ SysBusDevice parent_obj;
40
+ /*< public >*/
41
+
42
+ MemoryRegion iomem;
43
+ uint32_t base;
44
+} BitBandState;
45
+
46
+#define TYPE_ARMV7M "armv7m"
47
+#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
48
+
49
+#define ARMV7M_NUM_BITBANDS 2
50
+
51
+/* ARMv7M container object.
52
+ * + Unnamed GPIO input lines: external IRQ lines for the NVIC
53
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
54
+ * + Property "cpu-model": CPU model to instantiate
55
+ * + Property "num-irq": number of external IRQ lines
56
+ */
57
+typedef struct ARMv7MState {
58
+ /*< private >*/
59
+ SysBusDevice parent_obj;
60
+ /*< public >*/
61
+ NVICState nvic;
62
+ BitBandState bitband[ARMV7M_NUM_BITBANDS];
63
+ ARMCPU *cpu;
64
+
65
+ /* Properties */
66
+ char *cpu_model;
67
+} ARMv7MState;
68
+
69
+#endif
70
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
71
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/armv7m.c
29
--- a/target/arm/cpu-features.h
73
+++ b/hw/arm/armv7m.c
30
+++ b/target/arm/cpu-features.h
74
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
75
*/
32
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
76
33
}
77
#include "qemu/osdep.h"
34
78
+#include "hw/arm/armv7m.h"
35
+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
79
#include "qapi/error.h"
80
#include "qemu-common.h"
81
#include "cpu.h"
82
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bitband_ops = {
83
.endianness = DEVICE_NATIVE_ENDIAN,
84
};
85
86
-#define TYPE_BITBAND "ARM,bitband-memory"
87
-#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
88
-
89
-typedef struct {
90
- /*< private >*/
91
- SysBusDevice parent_obj;
92
- /*< public >*/
93
-
94
- MemoryRegion iomem;
95
- uint32_t base;
96
-} BitBandState;
97
-
98
static void bitband_init(Object *obj)
99
{
100
BitBandState *s = BITBAND(obj);
101
@@ -XXX,XX +XXX,XX @@ static void armv7m_bitband_init(void)
102
103
/* Board init. */
104
105
+static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
106
+ 0x20000000, 0x40000000
107
+};
108
+
109
+static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
110
+ 0x22000000, 0x42000000
111
+};
112
+
113
+static void armv7m_instance_init(Object *obj)
114
+{
36
+{
115
+ ARMv7MState *s = ARMV7M(obj);
37
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
116
+ int i;
117
+
118
+ /* Can't init the cpu here, we don't yet know which model to use */
119
+
120
+ object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
121
+ qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
122
+ object_property_add_alias(obj, "num-irq",
123
+ OBJECT(&s->nvic), "num-irq", &error_abort);
124
+
125
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
126
+ object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
127
+ qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
128
+ }
129
+}
38
+}
130
+
39
+
131
+static void armv7m_realize(DeviceState *dev, Error **errp)
40
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
41
{
42
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/helper.c
46
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
48
: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
49
return CP_ACCESS_TRAP_EL2;
50
}
51
+ if (has_el2 && timeridx == GTIMER_VIRT) {
52
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {
53
+ return CP_ACCESS_TRAP_EL2;
54
+ }
55
+ }
56
break;
57
}
58
return CP_ACCESS_OK;
59
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
60
}
61
}
62
}
63
+ if (has_el2 && timeridx == GTIMER_VIRT) {
64
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {
65
+ return CP_ACCESS_TRAP_EL2;
66
+ }
67
+ }
68
break;
69
}
70
return CP_ACCESS_OK;
71
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
if (cpu_isar_feature(aa64_rme, cpu)) {
73
valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
74
}
75
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
76
+ valid_mask |=
77
+ R_CNTHCTL_EL1TVT_MASK |
78
+ R_CNTHCTL_EL1TVCT_MASK |
79
+ R_CNTHCTL_EL1NVPCT_MASK |
80
+ R_CNTHCTL_EL1NVVCT_MASK |
81
+ R_CNTHCTL_EVNTIS_MASK;
82
+ }
83
84
/* Clear RES0 bits */
85
value &= valid_mask;
86
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
87
{
88
if (arm_current_el(env) == 1) {
89
/* This must be a FEAT_NV access */
90
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
91
return CP_ACCESS_OK;
92
}
93
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
94
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
95
return CP_ACCESS_OK;
96
}
97
98
+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
132
+{
100
+{
133
+ ARMv7MState *s = ARMV7M(dev);
101
+ if (arm_current_el(env) == 1) {
134
+ Error *err = NULL;
102
+ /* This must be a FEAT_NV access with NVx == 101 */
135
+ int i;
103
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {
136
+ char **cpustr;
104
+ return CP_ACCESS_TRAP_EL2;
137
+ ObjectClass *oc;
105
+ }
138
+ const char *typename;
139
+ CPUClass *cc;
140
+
141
+ cpustr = g_strsplit(s->cpu_model, ",", 2);
142
+
143
+ oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
144
+ if (!oc) {
145
+ error_setg(errp, "Unknown CPU model %s", cpustr[0]);
146
+ g_strfreev(cpustr);
147
+ return;
148
+ }
106
+ }
149
+
107
+ return e2h_access(env, ri, isread);
150
+ cc = CPU_CLASS(oc);
151
+ typename = object_class_get_name(oc);
152
+ cc->parse_features(typename, cpustr[1], &err);
153
+ g_strfreev(cpustr);
154
+ if (err) {
155
+ error_propagate(errp, err);
156
+ return;
157
+ }
158
+
159
+ s->cpu = ARM_CPU(object_new(typename));
160
+ if (!s->cpu) {
161
+ error_setg(errp, "Unknown CPU model %s", s->cpu_model);
162
+ return;
163
+ }
164
+
165
+ object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
166
+ if (err != NULL) {
167
+ error_propagate(errp, err);
168
+ return;
169
+ }
170
+
171
+ /* Note that we must realize the NVIC after the CPU */
172
+ object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
173
+ if (err != NULL) {
174
+ error_propagate(errp, err);
175
+ return;
176
+ }
177
+
178
+ /* Alias the NVIC's input and output GPIOs as our own so the board
179
+ * code can wire them up. (We do this in realize because the
180
+ * NVIC doesn't create the input GPIO array until realize.)
181
+ */
182
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
183
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
184
+
185
+ /* Wire the NVIC up to the CPU */
186
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
187
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
188
+ s->cpu->env.nvic = &s->nvic;
189
+
190
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
191
+ Object *obj = OBJECT(&s->bitband[i]);
192
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
193
+
194
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
195
+ if (err != NULL) {
196
+ error_propagate(errp, err);
197
+ return;
198
+ }
199
+ object_property_set_bool(obj, true, "realized", &err);
200
+ if (err != NULL) {
201
+ error_propagate(errp, err);
202
+ return;
203
+ }
204
+
205
+ sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
206
+ }
207
+}
108
+}
208
+
109
+
209
+static Property armv7m_properties[] = {
110
+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
210
+ DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
111
+ bool isread)
211
+ DEFINE_PROP_END_OF_LIST(),
212
+};
213
+
214
+static void armv7m_class_init(ObjectClass *klass, void *data)
215
+{
112
+{
216
+ DeviceClass *dc = DEVICE_CLASS(klass);
113
+ if (arm_current_el(env) == 1) {
217
+
114
+ /* This must be a FEAT_NV access with NVx == 101 */
218
+ dc->realize = armv7m_realize;
115
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {
219
+ dc->props = armv7m_properties;
116
+ return CP_ACCESS_TRAP_EL2;
117
+ }
118
+ }
119
+ return e2h_access(env, ri, isread);
220
+}
120
+}
221
+
121
+
222
+static const TypeInfo armv7m_info = {
122
/* Test if system register redirection is to occur in the current state. */
223
+ .name = TYPE_ARMV7M,
123
static bool redirect_for_e2h(CPUARMState *env)
224
+ .parent = TYPE_SYS_BUS_DEVICE,
225
+ .instance_size = sizeof(ARMv7MState),
226
+ .instance_init = armv7m_instance_init,
227
+ .class_init = armv7m_class_init,
228
+};
229
+
230
static void armv7m_reset(void *opaque)
231
{
124
{
232
ARMCPU *cpu = opaque;
125
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
233
@@ -XXX,XX +XXX,XX @@ static const TypeInfo bitband_info = {
126
{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
234
static void armv7m_register_types(void)
127
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
235
{
128
.type = ARM_CP_IO | ARM_CP_ALIAS,
236
type_register_static(&bitband_info);
129
- .access = PL2_RW, .accessfn = e2h_access,
237
+ type_register_static(&armv7m_info);
130
+ .access = PL2_RW, .accessfn = access_el1nvpct,
238
}
131
.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
239
132
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
240
type_init(armv7m_register_types)
133
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
134
{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
135
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
136
.type = ARM_CP_IO | ARM_CP_ALIAS,
137
- .access = PL2_RW, .accessfn = e2h_access,
138
+ .access = PL2_RW, .accessfn = access_el1nvvct,
139
.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
140
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
141
.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
143
.type = ARM_CP_IO | ARM_CP_ALIAS,
144
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
145
.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
146
- .access = PL2_RW, .accessfn = e2h_access,
147
+ .access = PL2_RW, .accessfn = access_el1nvpct,
148
.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
149
{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
150
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
151
.type = ARM_CP_IO | ARM_CP_ALIAS,
152
.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
153
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
154
- .access = PL2_RW, .accessfn = e2h_access,
155
+ .access = PL2_RW, .accessfn = access_el1nvvct,
156
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
157
#endif
158
};
241
--
159
--
242
2.7.4
160
2.34.1
243
244
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/21] update Linux headers to 4.11
[PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
2
defined, which are "self-synchronized" views of the physical and
3
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
4
(meaning that no barriers are needed around accesses to them to
5
ensure that reads of them do not occur speculatively and out-of-order
6
with other instructions).
2
7
3
virtio_mmio.h would be deleted; I am leaving it in though it was a
8
For QEMU, all our system registers are self-synchronized, so we can
4
mistake to add it.
9
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
10
to the new register encodings.
5
11
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12
This means we now implement all the functionality required for
13
ID_AA64MMFR0_EL1.ECV == 0b0001.
14
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
8
---
18
---
9
include/standard-headers/asm-x86/hyperv.h | 8 +
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
10
include/standard-headers/linux/input-event-codes.h | 2 +-
20
1 file changed, 43 insertions(+)
11
include/standard-headers/linux/pci_regs.h | 25 ++
12
include/standard-headers/linux/virtio_ids.h | 1 +
13
linux-headers/asm-arm/kvm.h | 15 +
14
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++++++++
15
linux-headers/asm-arm/unistd-eabi.h | 5 +
16
linux-headers/asm-arm/unistd-oabi.h | 17 +
17
linux-headers/asm-arm/unistd.h | 419 +--------------------
18
linux-headers/asm-arm64/kvm.h | 13 +
19
linux-headers/asm-powerpc/kvm.h | 27 ++
20
linux-headers/asm-powerpc/unistd.h | 1 +
21
linux-headers/asm-x86/kvm_para.h | 13 +-
22
linux-headers/linux/kvm.h | 24 +-
23
linux-headers/linux/kvm_para.h | 2 +
24
linux-headers/linux/userfaultfd.h | 67 +++-
25
linux-headers/linux/vfio.h | 10 +
26
17 files changed, 577 insertions(+), 429 deletions(-)
27
create mode 100644 linux-headers/asm-arm/unistd-common.h
28
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
29
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
30
21
31
diff --git a/include/standard-headers/asm-x86/hyperv.h b/include/standard-headers/asm-x86/hyperv.h
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
33
--- a/include/standard-headers/asm-x86/hyperv.h
24
--- a/target/arm/helper.c
34
+++ b/include/standard-headers/asm-x86/hyperv.h
25
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
36
*/
27
},
37
#define HV_X64_MSR_STAT_PAGES_AVAILABLE        (1 << 8)
28
};
38
39
+/* Crash MSR available */
40
+#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
41
+
42
/*
43
* Feature identification: EBX indicates which flags were specified at
44
* partition creation. The format is the same as the partition creation
45
@@ -XXX,XX +XXX,XX @@
46
*/
47
#define HV_X64_RELAXED_TIMING_RECOMMENDED    (1 << 5)
48
29
49
+/*
30
+/*
50
+ * Crash notification flag.
31
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
32
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
33
+ * so our implementations here are identical to the normal registers.
51
+ */
34
+ */
52
+#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
35
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
53
+
36
+ { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9,
54
/* MSR used to identify the guest OS. */
37
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
55
#define HV_X64_MSR_GUEST_OS_ID            0x40000000
38
+ .accessfn = gt_vct_access,
56
39
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
57
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
40
+ },
58
index XXXXXXX..XXXXXXX 100644
41
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
59
--- a/include/standard-headers/linux/input-event-codes.h
42
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
60
+++ b/include/standard-headers/linux/input-event-codes.h
43
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
61
@@ -XXX,XX +XXX,XX @@
44
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
62
* Control a data application associated with the currently viewed channel,
45
+ },
63
* e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
46
+ { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8,
64
*/
47
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
65
-#define KEY_DATA            0x275
48
+ .accessfn = gt_pct_access,
66
+#define KEY_DATA            0x277
49
+ .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
67
50
+ },
68
#define BTN_TRIGGER_HAPPY        0x2c0
51
+ { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64,
69
#define BTN_TRIGGER_HAPPY1        0x2c0
52
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
70
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
53
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
71
index XXXXXXX..XXXXXXX 100644
54
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
72
--- a/include/standard-headers/linux/pci_regs.h
55
+ },
73
+++ b/include/standard-headers/linux/pci_regs.h
74
@@ -XXX,XX +XXX,XX @@
75
#define LINUX_PCI_REGS_H
76
77
/*
78
+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
79
+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
80
+ * configuration space.
81
+ */
82
+#define PCI_CFG_SPACE_SIZE    256
83
+#define PCI_CFG_SPACE_EXP_SIZE    4096
84
+
85
+/*
86
* Under PCI, each device has 256 bytes of configuration address space,
87
* of which the first 64 bytes are standardized as follows:
88
*/
89
@@ -XXX,XX +XXX,XX @@
90
#define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
91
#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
92
#define PCI_EXT_CAP_ID_DPC    0x1D    /* Downstream Port Containment */
93
+#define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
94
#define PCI_EXT_CAP_ID_PTM    0x1F    /* Precision Time Measurement */
95
#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PTM
96
97
@@ -XXX,XX +XXX,XX @@
98
#define PCI_EXP_DPC_STATUS        8    /* DPC Status */
99
#define PCI_EXP_DPC_STATUS_TRIGGER    0x01    /* Trigger Status */
100
#define PCI_EXP_DPC_STATUS_INTERRUPT    0x08    /* Interrupt Status */
101
+#define PCI_EXP_DPC_RP_BUSY        0x10    /* Root Port Busy */
102
103
#define PCI_EXP_DPC_SOURCE_ID        10    /* DPC Source Identifier */
104
105
@@ -XXX,XX +XXX,XX @@
106
#define PCI_PTM_CTRL_ENABLE        0x00000001 /* PTM enable */
107
#define PCI_PTM_CTRL_ROOT        0x00000002 /* Root select */
108
109
+/* L1 PM Substates */
110
+#define PCI_L1SS_CAP         4    /* capability register */
111
+#define PCI_L1SS_CAP_PCIPM_L1_2     1    /* PCI PM L1.2 Support */
112
+#define PCI_L1SS_CAP_PCIPM_L1_1     2    /* PCI PM L1.1 Support */
113
+#define PCI_L1SS_CAP_ASPM_L1_2         4    /* ASPM L1.2 Support */
114
+#define PCI_L1SS_CAP_ASPM_L1_1         8    /* ASPM L1.1 Support */
115
+#define PCI_L1SS_CAP_L1_PM_SS        16    /* L1 PM Substates Support */
116
+#define PCI_L1SS_CTL1         8    /* Control Register 1 */
117
+#define PCI_L1SS_CTL1_PCIPM_L1_2    1    /* PCI PM L1.2 Enable */
118
+#define PCI_L1SS_CTL1_PCIPM_L1_1    2    /* PCI PM L1.1 Support */
119
+#define PCI_L1SS_CTL1_ASPM_L1_2    4    /* ASPM L1.2 Support */
120
+#define PCI_L1SS_CTL1_ASPM_L1_1    8    /* ASPM L1.1 Support */
121
+#define PCI_L1SS_CTL1_L1SS_MASK    0x0000000F
122
+#define PCI_L1SS_CTL2         0xC    /* Control Register 2 */
123
+
124
#endif /* LINUX_PCI_REGS_H */
125
diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h
126
index XXXXXXX..XXXXXXX 100644
127
--- a/include/standard-headers/linux/virtio_ids.h
128
+++ b/include/standard-headers/linux/virtio_ids.h
129
@@ -XXX,XX +XXX,XX @@
130
#define VIRTIO_ID_INPUT 18 /* virtio input */
131
#define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */
132
#define VIRTIO_ID_CRYPTO 20 /* virtio crypto */
133
+
134
#endif /* _LINUX_VIRTIO_IDS_H */
135
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-headers/asm-arm/kvm.h
138
+++ b/linux-headers/asm-arm/kvm.h
139
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
140
/* Supported VGICv3 address types */
141
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
142
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
143
+#define KVM_VGIC_ITS_ADDR_TYPE        4
144
145
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
146
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
147
+#define KVM_VGIC_V3_ITS_SIZE        (2 * SZ_64K)
148
149
#define KVM_ARM_VCPU_POWER_OFF        0 /* CPU is started in OFF state */
150
#define KVM_ARM_VCPU_PSCI_0_2        1 /* CPU uses PSCI v0.2 */
151
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
152
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
153
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
154
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
155
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
156
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
157
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
158
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
159
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
160
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
161
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
162
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
163
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
164
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
165
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
166
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
167
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
168
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
169
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
170
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
171
+
172
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
173
174
/* KVM_IRQ_LINE irq field index values */
175
diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h
176
new file mode 100644
177
index XXXXXXX..XXXXXXX
178
--- /dev/null
179
+++ b/linux-headers/asm-arm/unistd-common.h
180
@@ -XXX,XX +XXX,XX @@
181
+#ifndef _ASM_ARM_UNISTD_COMMON_H
182
+#define _ASM_ARM_UNISTD_COMMON_H 1
183
+
184
+#define __NR_restart_syscall (__NR_SYSCALL_BASE + 0)
185
+#define __NR_exit (__NR_SYSCALL_BASE + 1)
186
+#define __NR_fork (__NR_SYSCALL_BASE + 2)
187
+#define __NR_read (__NR_SYSCALL_BASE + 3)
188
+#define __NR_write (__NR_SYSCALL_BASE + 4)
189
+#define __NR_open (__NR_SYSCALL_BASE + 5)
190
+#define __NR_close (__NR_SYSCALL_BASE + 6)
191
+#define __NR_creat (__NR_SYSCALL_BASE + 8)
192
+#define __NR_link (__NR_SYSCALL_BASE + 9)
193
+#define __NR_unlink (__NR_SYSCALL_BASE + 10)
194
+#define __NR_execve (__NR_SYSCALL_BASE + 11)
195
+#define __NR_chdir (__NR_SYSCALL_BASE + 12)
196
+#define __NR_mknod (__NR_SYSCALL_BASE + 14)
197
+#define __NR_chmod (__NR_SYSCALL_BASE + 15)
198
+#define __NR_lchown (__NR_SYSCALL_BASE + 16)
199
+#define __NR_lseek (__NR_SYSCALL_BASE + 19)
200
+#define __NR_getpid (__NR_SYSCALL_BASE + 20)
201
+#define __NR_mount (__NR_SYSCALL_BASE + 21)
202
+#define __NR_setuid (__NR_SYSCALL_BASE + 23)
203
+#define __NR_getuid (__NR_SYSCALL_BASE + 24)
204
+#define __NR_ptrace (__NR_SYSCALL_BASE + 26)
205
+#define __NR_pause (__NR_SYSCALL_BASE + 29)
206
+#define __NR_access (__NR_SYSCALL_BASE + 33)
207
+#define __NR_nice (__NR_SYSCALL_BASE + 34)
208
+#define __NR_sync (__NR_SYSCALL_BASE + 36)
209
+#define __NR_kill (__NR_SYSCALL_BASE + 37)
210
+#define __NR_rename (__NR_SYSCALL_BASE + 38)
211
+#define __NR_mkdir (__NR_SYSCALL_BASE + 39)
212
+#define __NR_rmdir (__NR_SYSCALL_BASE + 40)
213
+#define __NR_dup (__NR_SYSCALL_BASE + 41)
214
+#define __NR_pipe (__NR_SYSCALL_BASE + 42)
215
+#define __NR_times (__NR_SYSCALL_BASE + 43)
216
+#define __NR_brk (__NR_SYSCALL_BASE + 45)
217
+#define __NR_setgid (__NR_SYSCALL_BASE + 46)
218
+#define __NR_getgid (__NR_SYSCALL_BASE + 47)
219
+#define __NR_geteuid (__NR_SYSCALL_BASE + 49)
220
+#define __NR_getegid (__NR_SYSCALL_BASE + 50)
221
+#define __NR_acct (__NR_SYSCALL_BASE + 51)
222
+#define __NR_umount2 (__NR_SYSCALL_BASE + 52)
223
+#define __NR_ioctl (__NR_SYSCALL_BASE + 54)
224
+#define __NR_fcntl (__NR_SYSCALL_BASE + 55)
225
+#define __NR_setpgid (__NR_SYSCALL_BASE + 57)
226
+#define __NR_umask (__NR_SYSCALL_BASE + 60)
227
+#define __NR_chroot (__NR_SYSCALL_BASE + 61)
228
+#define __NR_ustat (__NR_SYSCALL_BASE + 62)
229
+#define __NR_dup2 (__NR_SYSCALL_BASE + 63)
230
+#define __NR_getppid (__NR_SYSCALL_BASE + 64)
231
+#define __NR_getpgrp (__NR_SYSCALL_BASE + 65)
232
+#define __NR_setsid (__NR_SYSCALL_BASE + 66)
233
+#define __NR_sigaction (__NR_SYSCALL_BASE + 67)
234
+#define __NR_setreuid (__NR_SYSCALL_BASE + 70)
235
+#define __NR_setregid (__NR_SYSCALL_BASE + 71)
236
+#define __NR_sigsuspend (__NR_SYSCALL_BASE + 72)
237
+#define __NR_sigpending (__NR_SYSCALL_BASE + 73)
238
+#define __NR_sethostname (__NR_SYSCALL_BASE + 74)
239
+#define __NR_setrlimit (__NR_SYSCALL_BASE + 75)
240
+#define __NR_getrusage (__NR_SYSCALL_BASE + 77)
241
+#define __NR_gettimeofday (__NR_SYSCALL_BASE + 78)
242
+#define __NR_settimeofday (__NR_SYSCALL_BASE + 79)
243
+#define __NR_getgroups (__NR_SYSCALL_BASE + 80)
244
+#define __NR_setgroups (__NR_SYSCALL_BASE + 81)
245
+#define __NR_symlink (__NR_SYSCALL_BASE + 83)
246
+#define __NR_readlink (__NR_SYSCALL_BASE + 85)
247
+#define __NR_uselib (__NR_SYSCALL_BASE + 86)
248
+#define __NR_swapon (__NR_SYSCALL_BASE + 87)
249
+#define __NR_reboot (__NR_SYSCALL_BASE + 88)
250
+#define __NR_munmap (__NR_SYSCALL_BASE + 91)
251
+#define __NR_truncate (__NR_SYSCALL_BASE + 92)
252
+#define __NR_ftruncate (__NR_SYSCALL_BASE + 93)
253
+#define __NR_fchmod (__NR_SYSCALL_BASE + 94)
254
+#define __NR_fchown (__NR_SYSCALL_BASE + 95)
255
+#define __NR_getpriority (__NR_SYSCALL_BASE + 96)
256
+#define __NR_setpriority (__NR_SYSCALL_BASE + 97)
257
+#define __NR_statfs (__NR_SYSCALL_BASE + 99)
258
+#define __NR_fstatfs (__NR_SYSCALL_BASE + 100)
259
+#define __NR_syslog (__NR_SYSCALL_BASE + 103)
260
+#define __NR_setitimer (__NR_SYSCALL_BASE + 104)
261
+#define __NR_getitimer (__NR_SYSCALL_BASE + 105)
262
+#define __NR_stat (__NR_SYSCALL_BASE + 106)
263
+#define __NR_lstat (__NR_SYSCALL_BASE + 107)
264
+#define __NR_fstat (__NR_SYSCALL_BASE + 108)
265
+#define __NR_vhangup (__NR_SYSCALL_BASE + 111)
266
+#define __NR_wait4 (__NR_SYSCALL_BASE + 114)
267
+#define __NR_swapoff (__NR_SYSCALL_BASE + 115)
268
+#define __NR_sysinfo (__NR_SYSCALL_BASE + 116)
269
+#define __NR_fsync (__NR_SYSCALL_BASE + 118)
270
+#define __NR_sigreturn (__NR_SYSCALL_BASE + 119)
271
+#define __NR_clone (__NR_SYSCALL_BASE + 120)
272
+#define __NR_setdomainname (__NR_SYSCALL_BASE + 121)
273
+#define __NR_uname (__NR_SYSCALL_BASE + 122)
274
+#define __NR_adjtimex (__NR_SYSCALL_BASE + 124)
275
+#define __NR_mprotect (__NR_SYSCALL_BASE + 125)
276
+#define __NR_sigprocmask (__NR_SYSCALL_BASE + 126)
277
+#define __NR_init_module (__NR_SYSCALL_BASE + 128)
278
+#define __NR_delete_module (__NR_SYSCALL_BASE + 129)
279
+#define __NR_quotactl (__NR_SYSCALL_BASE + 131)
280
+#define __NR_getpgid (__NR_SYSCALL_BASE + 132)
281
+#define __NR_fchdir (__NR_SYSCALL_BASE + 133)
282
+#define __NR_bdflush (__NR_SYSCALL_BASE + 134)
283
+#define __NR_sysfs (__NR_SYSCALL_BASE + 135)
284
+#define __NR_personality (__NR_SYSCALL_BASE + 136)
285
+#define __NR_setfsuid (__NR_SYSCALL_BASE + 138)
286
+#define __NR_setfsgid (__NR_SYSCALL_BASE + 139)
287
+#define __NR__llseek (__NR_SYSCALL_BASE + 140)
288
+#define __NR_getdents (__NR_SYSCALL_BASE + 141)
289
+#define __NR__newselect (__NR_SYSCALL_BASE + 142)
290
+#define __NR_flock (__NR_SYSCALL_BASE + 143)
291
+#define __NR_msync (__NR_SYSCALL_BASE + 144)
292
+#define __NR_readv (__NR_SYSCALL_BASE + 145)
293
+#define __NR_writev (__NR_SYSCALL_BASE + 146)
294
+#define __NR_getsid (__NR_SYSCALL_BASE + 147)
295
+#define __NR_fdatasync (__NR_SYSCALL_BASE + 148)
296
+#define __NR__sysctl (__NR_SYSCALL_BASE + 149)
297
+#define __NR_mlock (__NR_SYSCALL_BASE + 150)
298
+#define __NR_munlock (__NR_SYSCALL_BASE + 151)
299
+#define __NR_mlockall (__NR_SYSCALL_BASE + 152)
300
+#define __NR_munlockall (__NR_SYSCALL_BASE + 153)
301
+#define __NR_sched_setparam (__NR_SYSCALL_BASE + 154)
302
+#define __NR_sched_getparam (__NR_SYSCALL_BASE + 155)
303
+#define __NR_sched_setscheduler (__NR_SYSCALL_BASE + 156)
304
+#define __NR_sched_getscheduler (__NR_SYSCALL_BASE + 157)
305
+#define __NR_sched_yield (__NR_SYSCALL_BASE + 158)
306
+#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE + 159)
307
+#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE + 160)
308
+#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE + 161)
309
+#define __NR_nanosleep (__NR_SYSCALL_BASE + 162)
310
+#define __NR_mremap (__NR_SYSCALL_BASE + 163)
311
+#define __NR_setresuid (__NR_SYSCALL_BASE + 164)
312
+#define __NR_getresuid (__NR_SYSCALL_BASE + 165)
313
+#define __NR_poll (__NR_SYSCALL_BASE + 168)
314
+#define __NR_nfsservctl (__NR_SYSCALL_BASE + 169)
315
+#define __NR_setresgid (__NR_SYSCALL_BASE + 170)
316
+#define __NR_getresgid (__NR_SYSCALL_BASE + 171)
317
+#define __NR_prctl (__NR_SYSCALL_BASE + 172)
318
+#define __NR_rt_sigreturn (__NR_SYSCALL_BASE + 173)
319
+#define __NR_rt_sigaction (__NR_SYSCALL_BASE + 174)
320
+#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE + 175)
321
+#define __NR_rt_sigpending (__NR_SYSCALL_BASE + 176)
322
+#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE + 177)
323
+#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE + 178)
324
+#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE + 179)
325
+#define __NR_pread64 (__NR_SYSCALL_BASE + 180)
326
+#define __NR_pwrite64 (__NR_SYSCALL_BASE + 181)
327
+#define __NR_chown (__NR_SYSCALL_BASE + 182)
328
+#define __NR_getcwd (__NR_SYSCALL_BASE + 183)
329
+#define __NR_capget (__NR_SYSCALL_BASE + 184)
330
+#define __NR_capset (__NR_SYSCALL_BASE + 185)
331
+#define __NR_sigaltstack (__NR_SYSCALL_BASE + 186)
332
+#define __NR_sendfile (__NR_SYSCALL_BASE + 187)
333
+#define __NR_vfork (__NR_SYSCALL_BASE + 190)
334
+#define __NR_ugetrlimit (__NR_SYSCALL_BASE + 191)
335
+#define __NR_mmap2 (__NR_SYSCALL_BASE + 192)
336
+#define __NR_truncate64 (__NR_SYSCALL_BASE + 193)
337
+#define __NR_ftruncate64 (__NR_SYSCALL_BASE + 194)
338
+#define __NR_stat64 (__NR_SYSCALL_BASE + 195)
339
+#define __NR_lstat64 (__NR_SYSCALL_BASE + 196)
340
+#define __NR_fstat64 (__NR_SYSCALL_BASE + 197)
341
+#define __NR_lchown32 (__NR_SYSCALL_BASE + 198)
342
+#define __NR_getuid32 (__NR_SYSCALL_BASE + 199)
343
+#define __NR_getgid32 (__NR_SYSCALL_BASE + 200)
344
+#define __NR_geteuid32 (__NR_SYSCALL_BASE + 201)
345
+#define __NR_getegid32 (__NR_SYSCALL_BASE + 202)
346
+#define __NR_setreuid32 (__NR_SYSCALL_BASE + 203)
347
+#define __NR_setregid32 (__NR_SYSCALL_BASE + 204)
348
+#define __NR_getgroups32 (__NR_SYSCALL_BASE + 205)
349
+#define __NR_setgroups32 (__NR_SYSCALL_BASE + 206)
350
+#define __NR_fchown32 (__NR_SYSCALL_BASE + 207)
351
+#define __NR_setresuid32 (__NR_SYSCALL_BASE + 208)
352
+#define __NR_getresuid32 (__NR_SYSCALL_BASE + 209)
353
+#define __NR_setresgid32 (__NR_SYSCALL_BASE + 210)
354
+#define __NR_getresgid32 (__NR_SYSCALL_BASE + 211)
355
+#define __NR_chown32 (__NR_SYSCALL_BASE + 212)
356
+#define __NR_setuid32 (__NR_SYSCALL_BASE + 213)
357
+#define __NR_setgid32 (__NR_SYSCALL_BASE + 214)
358
+#define __NR_setfsuid32 (__NR_SYSCALL_BASE + 215)
359
+#define __NR_setfsgid32 (__NR_SYSCALL_BASE + 216)
360
+#define __NR_getdents64 (__NR_SYSCALL_BASE + 217)
361
+#define __NR_pivot_root (__NR_SYSCALL_BASE + 218)
362
+#define __NR_mincore (__NR_SYSCALL_BASE + 219)
363
+#define __NR_madvise (__NR_SYSCALL_BASE + 220)
364
+#define __NR_fcntl64 (__NR_SYSCALL_BASE + 221)
365
+#define __NR_gettid (__NR_SYSCALL_BASE + 224)
366
+#define __NR_readahead (__NR_SYSCALL_BASE + 225)
367
+#define __NR_setxattr (__NR_SYSCALL_BASE + 226)
368
+#define __NR_lsetxattr (__NR_SYSCALL_BASE + 227)
369
+#define __NR_fsetxattr (__NR_SYSCALL_BASE + 228)
370
+#define __NR_getxattr (__NR_SYSCALL_BASE + 229)
371
+#define __NR_lgetxattr (__NR_SYSCALL_BASE + 230)
372
+#define __NR_fgetxattr (__NR_SYSCALL_BASE + 231)
373
+#define __NR_listxattr (__NR_SYSCALL_BASE + 232)
374
+#define __NR_llistxattr (__NR_SYSCALL_BASE + 233)
375
+#define __NR_flistxattr (__NR_SYSCALL_BASE + 234)
376
+#define __NR_removexattr (__NR_SYSCALL_BASE + 235)
377
+#define __NR_lremovexattr (__NR_SYSCALL_BASE + 236)
378
+#define __NR_fremovexattr (__NR_SYSCALL_BASE + 237)
379
+#define __NR_tkill (__NR_SYSCALL_BASE + 238)
380
+#define __NR_sendfile64 (__NR_SYSCALL_BASE + 239)
381
+#define __NR_futex (__NR_SYSCALL_BASE + 240)
382
+#define __NR_sched_setaffinity (__NR_SYSCALL_BASE + 241)
383
+#define __NR_sched_getaffinity (__NR_SYSCALL_BASE + 242)
384
+#define __NR_io_setup (__NR_SYSCALL_BASE + 243)
385
+#define __NR_io_destroy (__NR_SYSCALL_BASE + 244)
386
+#define __NR_io_getevents (__NR_SYSCALL_BASE + 245)
387
+#define __NR_io_submit (__NR_SYSCALL_BASE + 246)
388
+#define __NR_io_cancel (__NR_SYSCALL_BASE + 247)
389
+#define __NR_exit_group (__NR_SYSCALL_BASE + 248)
390
+#define __NR_lookup_dcookie (__NR_SYSCALL_BASE + 249)
391
+#define __NR_epoll_create (__NR_SYSCALL_BASE + 250)
392
+#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 251)
393
+#define __NR_epoll_wait (__NR_SYSCALL_BASE + 252)
394
+#define __NR_remap_file_pages (__NR_SYSCALL_BASE + 253)
395
+#define __NR_set_tid_address (__NR_SYSCALL_BASE + 256)
396
+#define __NR_timer_create (__NR_SYSCALL_BASE + 257)
397
+#define __NR_timer_settime (__NR_SYSCALL_BASE + 258)
398
+#define __NR_timer_gettime (__NR_SYSCALL_BASE + 259)
399
+#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 260)
400
+#define __NR_timer_delete (__NR_SYSCALL_BASE + 261)
401
+#define __NR_clock_settime (__NR_SYSCALL_BASE + 262)
402
+#define __NR_clock_gettime (__NR_SYSCALL_BASE + 263)
403
+#define __NR_clock_getres (__NR_SYSCALL_BASE + 264)
404
+#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 265)
405
+#define __NR_statfs64 (__NR_SYSCALL_BASE + 266)
406
+#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 267)
407
+#define __NR_tgkill (__NR_SYSCALL_BASE + 268)
408
+#define __NR_utimes (__NR_SYSCALL_BASE + 269)
409
+#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE + 270)
410
+#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE + 271)
411
+#define __NR_pciconfig_read (__NR_SYSCALL_BASE + 272)
412
+#define __NR_pciconfig_write (__NR_SYSCALL_BASE + 273)
413
+#define __NR_mq_open (__NR_SYSCALL_BASE + 274)
414
+#define __NR_mq_unlink (__NR_SYSCALL_BASE + 275)
415
+#define __NR_mq_timedsend (__NR_SYSCALL_BASE + 276)
416
+#define __NR_mq_timedreceive (__NR_SYSCALL_BASE + 277)
417
+#define __NR_mq_notify (__NR_SYSCALL_BASE + 278)
418
+#define __NR_mq_getsetattr (__NR_SYSCALL_BASE + 279)
419
+#define __NR_waitid (__NR_SYSCALL_BASE + 280)
420
+#define __NR_socket (__NR_SYSCALL_BASE + 281)
421
+#define __NR_bind (__NR_SYSCALL_BASE + 282)
422
+#define __NR_connect (__NR_SYSCALL_BASE + 283)
423
+#define __NR_listen (__NR_SYSCALL_BASE + 284)
424
+#define __NR_accept (__NR_SYSCALL_BASE + 285)
425
+#define __NR_getsockname (__NR_SYSCALL_BASE + 286)
426
+#define __NR_getpeername (__NR_SYSCALL_BASE + 287)
427
+#define __NR_socketpair (__NR_SYSCALL_BASE + 288)
428
+#define __NR_send (__NR_SYSCALL_BASE + 289)
429
+#define __NR_sendto (__NR_SYSCALL_BASE + 290)
430
+#define __NR_recv (__NR_SYSCALL_BASE + 291)
431
+#define __NR_recvfrom (__NR_SYSCALL_BASE + 292)
432
+#define __NR_shutdown (__NR_SYSCALL_BASE + 293)
433
+#define __NR_setsockopt (__NR_SYSCALL_BASE + 294)
434
+#define __NR_getsockopt (__NR_SYSCALL_BASE + 295)
435
+#define __NR_sendmsg (__NR_SYSCALL_BASE + 296)
436
+#define __NR_recvmsg (__NR_SYSCALL_BASE + 297)
437
+#define __NR_semop (__NR_SYSCALL_BASE + 298)
438
+#define __NR_semget (__NR_SYSCALL_BASE + 299)
439
+#define __NR_semctl (__NR_SYSCALL_BASE + 300)
440
+#define __NR_msgsnd (__NR_SYSCALL_BASE + 301)
441
+#define __NR_msgrcv (__NR_SYSCALL_BASE + 302)
442
+#define __NR_msgget (__NR_SYSCALL_BASE + 303)
443
+#define __NR_msgctl (__NR_SYSCALL_BASE + 304)
444
+#define __NR_shmat (__NR_SYSCALL_BASE + 305)
445
+#define __NR_shmdt (__NR_SYSCALL_BASE + 306)
446
+#define __NR_shmget (__NR_SYSCALL_BASE + 307)
447
+#define __NR_shmctl (__NR_SYSCALL_BASE + 308)
448
+#define __NR_add_key (__NR_SYSCALL_BASE + 309)
449
+#define __NR_request_key (__NR_SYSCALL_BASE + 310)
450
+#define __NR_keyctl (__NR_SYSCALL_BASE + 311)
451
+#define __NR_semtimedop (__NR_SYSCALL_BASE + 312)
452
+#define __NR_vserver (__NR_SYSCALL_BASE + 313)
453
+#define __NR_ioprio_set (__NR_SYSCALL_BASE + 314)
454
+#define __NR_ioprio_get (__NR_SYSCALL_BASE + 315)
455
+#define __NR_inotify_init (__NR_SYSCALL_BASE + 316)
456
+#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 317)
457
+#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 318)
458
+#define __NR_mbind (__NR_SYSCALL_BASE + 319)
459
+#define __NR_get_mempolicy (__NR_SYSCALL_BASE + 320)
460
+#define __NR_set_mempolicy (__NR_SYSCALL_BASE + 321)
461
+#define __NR_openat (__NR_SYSCALL_BASE + 322)
462
+#define __NR_mkdirat (__NR_SYSCALL_BASE + 323)
463
+#define __NR_mknodat (__NR_SYSCALL_BASE + 324)
464
+#define __NR_fchownat (__NR_SYSCALL_BASE + 325)
465
+#define __NR_futimesat (__NR_SYSCALL_BASE + 326)
466
+#define __NR_fstatat64 (__NR_SYSCALL_BASE + 327)
467
+#define __NR_unlinkat (__NR_SYSCALL_BASE + 328)
468
+#define __NR_renameat (__NR_SYSCALL_BASE + 329)
469
+#define __NR_linkat (__NR_SYSCALL_BASE + 330)
470
+#define __NR_symlinkat (__NR_SYSCALL_BASE + 331)
471
+#define __NR_readlinkat (__NR_SYSCALL_BASE + 332)
472
+#define __NR_fchmodat (__NR_SYSCALL_BASE + 333)
473
+#define __NR_faccessat (__NR_SYSCALL_BASE + 334)
474
+#define __NR_pselect6 (__NR_SYSCALL_BASE + 335)
475
+#define __NR_ppoll (__NR_SYSCALL_BASE + 336)
476
+#define __NR_unshare (__NR_SYSCALL_BASE + 337)
477
+#define __NR_set_robust_list (__NR_SYSCALL_BASE + 338)
478
+#define __NR_get_robust_list (__NR_SYSCALL_BASE + 339)
479
+#define __NR_splice (__NR_SYSCALL_BASE + 340)
480
+#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE + 341)
481
+#define __NR_tee (__NR_SYSCALL_BASE + 342)
482
+#define __NR_vmsplice (__NR_SYSCALL_BASE + 343)
483
+#define __NR_move_pages (__NR_SYSCALL_BASE + 344)
484
+#define __NR_getcpu (__NR_SYSCALL_BASE + 345)
485
+#define __NR_epoll_pwait (__NR_SYSCALL_BASE + 346)
486
+#define __NR_kexec_load (__NR_SYSCALL_BASE + 347)
487
+#define __NR_utimensat (__NR_SYSCALL_BASE + 348)
488
+#define __NR_signalfd (__NR_SYSCALL_BASE + 349)
489
+#define __NR_timerfd_create (__NR_SYSCALL_BASE + 350)
490
+#define __NR_eventfd (__NR_SYSCALL_BASE + 351)
491
+#define __NR_fallocate (__NR_SYSCALL_BASE + 352)
492
+#define __NR_timerfd_settime (__NR_SYSCALL_BASE + 353)
493
+#define __NR_timerfd_gettime (__NR_SYSCALL_BASE + 354)
494
+#define __NR_signalfd4 (__NR_SYSCALL_BASE + 355)
495
+#define __NR_eventfd2 (__NR_SYSCALL_BASE + 356)
496
+#define __NR_epoll_create1 (__NR_SYSCALL_BASE + 357)
497
+#define __NR_dup3 (__NR_SYSCALL_BASE + 358)
498
+#define __NR_pipe2 (__NR_SYSCALL_BASE + 359)
499
+#define __NR_inotify_init1 (__NR_SYSCALL_BASE + 360)
500
+#define __NR_preadv (__NR_SYSCALL_BASE + 361)
501
+#define __NR_pwritev (__NR_SYSCALL_BASE + 362)
502
+#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE + 363)
503
+#define __NR_perf_event_open (__NR_SYSCALL_BASE + 364)
504
+#define __NR_recvmmsg (__NR_SYSCALL_BASE + 365)
505
+#define __NR_accept4 (__NR_SYSCALL_BASE + 366)
506
+#define __NR_fanotify_init (__NR_SYSCALL_BASE + 367)
507
+#define __NR_fanotify_mark (__NR_SYSCALL_BASE + 368)
508
+#define __NR_prlimit64 (__NR_SYSCALL_BASE + 369)
509
+#define __NR_name_to_handle_at (__NR_SYSCALL_BASE + 370)
510
+#define __NR_open_by_handle_at (__NR_SYSCALL_BASE + 371)
511
+#define __NR_clock_adjtime (__NR_SYSCALL_BASE + 372)
512
+#define __NR_syncfs (__NR_SYSCALL_BASE + 373)
513
+#define __NR_sendmmsg (__NR_SYSCALL_BASE + 374)
514
+#define __NR_setns (__NR_SYSCALL_BASE + 375)
515
+#define __NR_process_vm_readv (__NR_SYSCALL_BASE + 376)
516
+#define __NR_process_vm_writev (__NR_SYSCALL_BASE + 377)
517
+#define __NR_kcmp (__NR_SYSCALL_BASE + 378)
518
+#define __NR_finit_module (__NR_SYSCALL_BASE + 379)
519
+#define __NR_sched_setattr (__NR_SYSCALL_BASE + 380)
520
+#define __NR_sched_getattr (__NR_SYSCALL_BASE + 381)
521
+#define __NR_renameat2 (__NR_SYSCALL_BASE + 382)
522
+#define __NR_seccomp (__NR_SYSCALL_BASE + 383)
523
+#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
524
+#define __NR_memfd_create (__NR_SYSCALL_BASE + 385)
525
+#define __NR_bpf (__NR_SYSCALL_BASE + 386)
526
+#define __NR_execveat (__NR_SYSCALL_BASE + 387)
527
+#define __NR_userfaultfd (__NR_SYSCALL_BASE + 388)
528
+#define __NR_membarrier (__NR_SYSCALL_BASE + 389)
529
+#define __NR_mlock2 (__NR_SYSCALL_BASE + 390)
530
+#define __NR_copy_file_range (__NR_SYSCALL_BASE + 391)
531
+#define __NR_preadv2 (__NR_SYSCALL_BASE + 392)
532
+#define __NR_pwritev2 (__NR_SYSCALL_BASE + 393)
533
+#define __NR_pkey_mprotect (__NR_SYSCALL_BASE + 394)
534
+#define __NR_pkey_alloc (__NR_SYSCALL_BASE + 395)
535
+#define __NR_pkey_free (__NR_SYSCALL_BASE + 396)
536
+
537
+#endif /* _ASM_ARM_UNISTD_COMMON_H */
538
diff --git a/linux-headers/asm-arm/unistd-eabi.h b/linux-headers/asm-arm/unistd-eabi.h
539
new file mode 100644
540
index XXXXXXX..XXXXXXX
541
--- /dev/null
542
+++ b/linux-headers/asm-arm/unistd-eabi.h
543
@@ -XXX,XX +XXX,XX @@
544
+#ifndef _ASM_ARM_UNISTD_EABI_H
545
+#define _ASM_ARM_UNISTD_EABI_H 1
546
+
547
+
548
+#endif /* _ASM_ARM_UNISTD_EABI_H */
549
diff --git a/linux-headers/asm-arm/unistd-oabi.h b/linux-headers/asm-arm/unistd-oabi.h
550
new file mode 100644
551
index XXXXXXX..XXXXXXX
552
--- /dev/null
553
+++ b/linux-headers/asm-arm/unistd-oabi.h
554
@@ -XXX,XX +XXX,XX @@
555
+#ifndef _ASM_ARM_UNISTD_OABI_H
556
+#define _ASM_ARM_UNISTD_OABI_H 1
557
+
558
+#define __NR_time (__NR_SYSCALL_BASE + 13)
559
+#define __NR_umount (__NR_SYSCALL_BASE + 22)
560
+#define __NR_stime (__NR_SYSCALL_BASE + 25)
561
+#define __NR_alarm (__NR_SYSCALL_BASE + 27)
562
+#define __NR_utime (__NR_SYSCALL_BASE + 30)
563
+#define __NR_getrlimit (__NR_SYSCALL_BASE + 76)
564
+#define __NR_select (__NR_SYSCALL_BASE + 82)
565
+#define __NR_readdir (__NR_SYSCALL_BASE + 89)
566
+#define __NR_mmap (__NR_SYSCALL_BASE + 90)
567
+#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
568
+#define __NR_syscall (__NR_SYSCALL_BASE + 113)
569
+#define __NR_ipc (__NR_SYSCALL_BASE + 117)
570
+
571
+#endif /* _ASM_ARM_UNISTD_OABI_H */
572
diff --git a/linux-headers/asm-arm/unistd.h b/linux-headers/asm-arm/unistd.h
573
index XXXXXXX..XXXXXXX 100644
574
--- a/linux-headers/asm-arm/unistd.h
575
+++ b/linux-headers/asm-arm/unistd.h
576
@@ -XXX,XX +XXX,XX @@
577
578
#if defined(__thumb__) || defined(__ARM_EABI__)
579
#define __NR_SYSCALL_BASE    0
580
+#include <asm/unistd-eabi.h>
581
#else
582
#define __NR_SYSCALL_BASE    __NR_OABI_SYSCALL_BASE
583
+#include <asm/unistd-oabi.h>
584
#endif
585
586
-/*
587
- * This file contains the system call numbers.
588
- */
589
-
590
-#define __NR_restart_syscall        (__NR_SYSCALL_BASE+ 0)
591
-#define __NR_exit            (__NR_SYSCALL_BASE+ 1)
592
-#define __NR_fork            (__NR_SYSCALL_BASE+ 2)
593
-#define __NR_read            (__NR_SYSCALL_BASE+ 3)
594
-#define __NR_write            (__NR_SYSCALL_BASE+ 4)
595
-#define __NR_open            (__NR_SYSCALL_BASE+ 5)
596
-#define __NR_close            (__NR_SYSCALL_BASE+ 6)
597
-                    /* 7 was sys_waitpid */
598
-#define __NR_creat            (__NR_SYSCALL_BASE+ 8)
599
-#define __NR_link            (__NR_SYSCALL_BASE+ 9)
600
-#define __NR_unlink            (__NR_SYSCALL_BASE+ 10)
601
-#define __NR_execve            (__NR_SYSCALL_BASE+ 11)
602
-#define __NR_chdir            (__NR_SYSCALL_BASE+ 12)
603
-#define __NR_time            (__NR_SYSCALL_BASE+ 13)
604
-#define __NR_mknod            (__NR_SYSCALL_BASE+ 14)
605
-#define __NR_chmod            (__NR_SYSCALL_BASE+ 15)
606
-#define __NR_lchown            (__NR_SYSCALL_BASE+ 16)
607
-                    /* 17 was sys_break */
608
-                    /* 18 was sys_stat */
609
-#define __NR_lseek            (__NR_SYSCALL_BASE+ 19)
610
-#define __NR_getpid            (__NR_SYSCALL_BASE+ 20)
611
-#define __NR_mount            (__NR_SYSCALL_BASE+ 21)
612
-#define __NR_umount            (__NR_SYSCALL_BASE+ 22)
613
-#define __NR_setuid            (__NR_SYSCALL_BASE+ 23)
614
-#define __NR_getuid            (__NR_SYSCALL_BASE+ 24)
615
-#define __NR_stime            (__NR_SYSCALL_BASE+ 25)
616
-#define __NR_ptrace            (__NR_SYSCALL_BASE+ 26)
617
-#define __NR_alarm            (__NR_SYSCALL_BASE+ 27)
618
-                    /* 28 was sys_fstat */
619
-#define __NR_pause            (__NR_SYSCALL_BASE+ 29)
620
-#define __NR_utime            (__NR_SYSCALL_BASE+ 30)
621
-                    /* 31 was sys_stty */
622
-                    /* 32 was sys_gtty */
623
-#define __NR_access            (__NR_SYSCALL_BASE+ 33)
624
-#define __NR_nice            (__NR_SYSCALL_BASE+ 34)
625
-                    /* 35 was sys_ftime */
626
-#define __NR_sync            (__NR_SYSCALL_BASE+ 36)
627
-#define __NR_kill            (__NR_SYSCALL_BASE+ 37)
628
-#define __NR_rename            (__NR_SYSCALL_BASE+ 38)
629
-#define __NR_mkdir            (__NR_SYSCALL_BASE+ 39)
630
-#define __NR_rmdir            (__NR_SYSCALL_BASE+ 40)
631
-#define __NR_dup            (__NR_SYSCALL_BASE+ 41)
632
-#define __NR_pipe            (__NR_SYSCALL_BASE+ 42)
633
-#define __NR_times            (__NR_SYSCALL_BASE+ 43)
634
-                    /* 44 was sys_prof */
635
-#define __NR_brk            (__NR_SYSCALL_BASE+ 45)
636
-#define __NR_setgid            (__NR_SYSCALL_BASE+ 46)
637
-#define __NR_getgid            (__NR_SYSCALL_BASE+ 47)
638
-                    /* 48 was sys_signal */
639
-#define __NR_geteuid            (__NR_SYSCALL_BASE+ 49)
640
-#define __NR_getegid            (__NR_SYSCALL_BASE+ 50)
641
-#define __NR_acct            (__NR_SYSCALL_BASE+ 51)
642
-#define __NR_umount2            (__NR_SYSCALL_BASE+ 52)
643
-                    /* 53 was sys_lock */
644
-#define __NR_ioctl            (__NR_SYSCALL_BASE+ 54)
645
-#define __NR_fcntl            (__NR_SYSCALL_BASE+ 55)
646
-                    /* 56 was sys_mpx */
647
-#define __NR_setpgid            (__NR_SYSCALL_BASE+ 57)
648
-                    /* 58 was sys_ulimit */
649
-                    /* 59 was sys_olduname */
650
-#define __NR_umask            (__NR_SYSCALL_BASE+ 60)
651
-#define __NR_chroot            (__NR_SYSCALL_BASE+ 61)
652
-#define __NR_ustat            (__NR_SYSCALL_BASE+ 62)
653
-#define __NR_dup2            (__NR_SYSCALL_BASE+ 63)
654
-#define __NR_getppid            (__NR_SYSCALL_BASE+ 64)
655
-#define __NR_getpgrp            (__NR_SYSCALL_BASE+ 65)
656
-#define __NR_setsid            (__NR_SYSCALL_BASE+ 66)
657
-#define __NR_sigaction            (__NR_SYSCALL_BASE+ 67)
658
-                    /* 68 was sys_sgetmask */
659
-                    /* 69 was sys_ssetmask */
660
-#define __NR_setreuid            (__NR_SYSCALL_BASE+ 70)
661
-#define __NR_setregid            (__NR_SYSCALL_BASE+ 71)
662
-#define __NR_sigsuspend            (__NR_SYSCALL_BASE+ 72)
663
-#define __NR_sigpending            (__NR_SYSCALL_BASE+ 73)
664
-#define __NR_sethostname        (__NR_SYSCALL_BASE+ 74)
665
-#define __NR_setrlimit            (__NR_SYSCALL_BASE+ 75)
666
-#define __NR_getrlimit            (__NR_SYSCALL_BASE+ 76)    /* Back compat 2GB limited rlimit */
667
-#define __NR_getrusage            (__NR_SYSCALL_BASE+ 77)
668
-#define __NR_gettimeofday        (__NR_SYSCALL_BASE+ 78)
669
-#define __NR_settimeofday        (__NR_SYSCALL_BASE+ 79)
670
-#define __NR_getgroups            (__NR_SYSCALL_BASE+ 80)
671
-#define __NR_setgroups            (__NR_SYSCALL_BASE+ 81)
672
-#define __NR_select            (__NR_SYSCALL_BASE+ 82)
673
-#define __NR_symlink            (__NR_SYSCALL_BASE+ 83)
674
-                    /* 84 was sys_lstat */
675
-#define __NR_readlink            (__NR_SYSCALL_BASE+ 85)
676
-#define __NR_uselib            (__NR_SYSCALL_BASE+ 86)
677
-#define __NR_swapon            (__NR_SYSCALL_BASE+ 87)
678
-#define __NR_reboot            (__NR_SYSCALL_BASE+ 88)
679
-#define __NR_readdir            (__NR_SYSCALL_BASE+ 89)
680
-#define __NR_mmap            (__NR_SYSCALL_BASE+ 90)
681
-#define __NR_munmap            (__NR_SYSCALL_BASE+ 91)
682
-#define __NR_truncate            (__NR_SYSCALL_BASE+ 92)
683
-#define __NR_ftruncate            (__NR_SYSCALL_BASE+ 93)
684
-#define __NR_fchmod            (__NR_SYSCALL_BASE+ 94)
685
-#define __NR_fchown            (__NR_SYSCALL_BASE+ 95)
686
-#define __NR_getpriority        (__NR_SYSCALL_BASE+ 96)
687
-#define __NR_setpriority        (__NR_SYSCALL_BASE+ 97)
688
-                    /* 98 was sys_profil */
689
-#define __NR_statfs            (__NR_SYSCALL_BASE+ 99)
690
-#define __NR_fstatfs            (__NR_SYSCALL_BASE+100)
691
-                    /* 101 was sys_ioperm */
692
-#define __NR_socketcall            (__NR_SYSCALL_BASE+102)
693
-#define __NR_syslog            (__NR_SYSCALL_BASE+103)
694
-#define __NR_setitimer            (__NR_SYSCALL_BASE+104)
695
-#define __NR_getitimer            (__NR_SYSCALL_BASE+105)
696
-#define __NR_stat            (__NR_SYSCALL_BASE+106)
697
-#define __NR_lstat            (__NR_SYSCALL_BASE+107)
698
-#define __NR_fstat            (__NR_SYSCALL_BASE+108)
699
-                    /* 109 was sys_uname */
700
-                    /* 110 was sys_iopl */
701
-#define __NR_vhangup            (__NR_SYSCALL_BASE+111)
702
-                    /* 112 was sys_idle */
703
-#define __NR_syscall            (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
704
-#define __NR_wait4            (__NR_SYSCALL_BASE+114)
705
-#define __NR_swapoff            (__NR_SYSCALL_BASE+115)
706
-#define __NR_sysinfo            (__NR_SYSCALL_BASE+116)
707
-#define __NR_ipc            (__NR_SYSCALL_BASE+117)
708
-#define __NR_fsync            (__NR_SYSCALL_BASE+118)
709
-#define __NR_sigreturn            (__NR_SYSCALL_BASE+119)
710
-#define __NR_clone            (__NR_SYSCALL_BASE+120)
711
-#define __NR_setdomainname        (__NR_SYSCALL_BASE+121)
712
-#define __NR_uname            (__NR_SYSCALL_BASE+122)
713
-                    /* 123 was sys_modify_ldt */
714
-#define __NR_adjtimex            (__NR_SYSCALL_BASE+124)
715
-#define __NR_mprotect            (__NR_SYSCALL_BASE+125)
716
-#define __NR_sigprocmask        (__NR_SYSCALL_BASE+126)
717
-                    /* 127 was sys_create_module */
718
-#define __NR_init_module        (__NR_SYSCALL_BASE+128)
719
-#define __NR_delete_module        (__NR_SYSCALL_BASE+129)
720
-                    /* 130 was sys_get_kernel_syms */
721
-#define __NR_quotactl            (__NR_SYSCALL_BASE+131)
722
-#define __NR_getpgid            (__NR_SYSCALL_BASE+132)
723
-#define __NR_fchdir            (__NR_SYSCALL_BASE+133)
724
-#define __NR_bdflush            (__NR_SYSCALL_BASE+134)
725
-#define __NR_sysfs            (__NR_SYSCALL_BASE+135)
726
-#define __NR_personality        (__NR_SYSCALL_BASE+136)
727
-                    /* 137 was sys_afs_syscall */
728
-#define __NR_setfsuid            (__NR_SYSCALL_BASE+138)
729
-#define __NR_setfsgid            (__NR_SYSCALL_BASE+139)
730
-#define __NR__llseek            (__NR_SYSCALL_BASE+140)
731
-#define __NR_getdents            (__NR_SYSCALL_BASE+141)
732
-#define __NR__newselect            (__NR_SYSCALL_BASE+142)
733
-#define __NR_flock            (__NR_SYSCALL_BASE+143)
734
-#define __NR_msync            (__NR_SYSCALL_BASE+144)
735
-#define __NR_readv            (__NR_SYSCALL_BASE+145)
736
-#define __NR_writev            (__NR_SYSCALL_BASE+146)
737
-#define __NR_getsid            (__NR_SYSCALL_BASE+147)
738
-#define __NR_fdatasync            (__NR_SYSCALL_BASE+148)
739
-#define __NR__sysctl            (__NR_SYSCALL_BASE+149)
740
-#define __NR_mlock            (__NR_SYSCALL_BASE+150)
741
-#define __NR_munlock            (__NR_SYSCALL_BASE+151)
742
-#define __NR_mlockall            (__NR_SYSCALL_BASE+152)
743
-#define __NR_munlockall            (__NR_SYSCALL_BASE+153)
744
-#define __NR_sched_setparam        (__NR_SYSCALL_BASE+154)
745
-#define __NR_sched_getparam        (__NR_SYSCALL_BASE+155)
746
-#define __NR_sched_setscheduler        (__NR_SYSCALL_BASE+156)
747
-#define __NR_sched_getscheduler        (__NR_SYSCALL_BASE+157)
748
-#define __NR_sched_yield        (__NR_SYSCALL_BASE+158)
749
-#define __NR_sched_get_priority_max    (__NR_SYSCALL_BASE+159)
750
-#define __NR_sched_get_priority_min    (__NR_SYSCALL_BASE+160)
751
-#define __NR_sched_rr_get_interval    (__NR_SYSCALL_BASE+161)
752
-#define __NR_nanosleep            (__NR_SYSCALL_BASE+162)
753
-#define __NR_mremap            (__NR_SYSCALL_BASE+163)
754
-#define __NR_setresuid            (__NR_SYSCALL_BASE+164)
755
-#define __NR_getresuid            (__NR_SYSCALL_BASE+165)
756
-                    /* 166 was sys_vm86 */
757
-                    /* 167 was sys_query_module */
758
-#define __NR_poll            (__NR_SYSCALL_BASE+168)
759
-#define __NR_nfsservctl            (__NR_SYSCALL_BASE+169)
760
-#define __NR_setresgid            (__NR_SYSCALL_BASE+170)
761
-#define __NR_getresgid            (__NR_SYSCALL_BASE+171)
762
-#define __NR_prctl            (__NR_SYSCALL_BASE+172)
763
-#define __NR_rt_sigreturn        (__NR_SYSCALL_BASE+173)
764
-#define __NR_rt_sigaction        (__NR_SYSCALL_BASE+174)
765
-#define __NR_rt_sigprocmask        (__NR_SYSCALL_BASE+175)
766
-#define __NR_rt_sigpending        (__NR_SYSCALL_BASE+176)
767
-#define __NR_rt_sigtimedwait        (__NR_SYSCALL_BASE+177)
768
-#define __NR_rt_sigqueueinfo        (__NR_SYSCALL_BASE+178)
769
-#define __NR_rt_sigsuspend        (__NR_SYSCALL_BASE+179)
770
-#define __NR_pread64            (__NR_SYSCALL_BASE+180)
771
-#define __NR_pwrite64            (__NR_SYSCALL_BASE+181)
772
-#define __NR_chown            (__NR_SYSCALL_BASE+182)
773
-#define __NR_getcwd            (__NR_SYSCALL_BASE+183)
774
-#define __NR_capget            (__NR_SYSCALL_BASE+184)
775
-#define __NR_capset            (__NR_SYSCALL_BASE+185)
776
-#define __NR_sigaltstack        (__NR_SYSCALL_BASE+186)
777
-#define __NR_sendfile            (__NR_SYSCALL_BASE+187)
778
-                    /* 188 reserved */
779
-                    /* 189 reserved */
780
-#define __NR_vfork            (__NR_SYSCALL_BASE+190)
781
-#define __NR_ugetrlimit            (__NR_SYSCALL_BASE+191)    /* SuS compliant getrlimit */
782
-#define __NR_mmap2            (__NR_SYSCALL_BASE+192)
783
-#define __NR_truncate64            (__NR_SYSCALL_BASE+193)
784
-#define __NR_ftruncate64        (__NR_SYSCALL_BASE+194)
785
-#define __NR_stat64            (__NR_SYSCALL_BASE+195)
786
-#define __NR_lstat64            (__NR_SYSCALL_BASE+196)
787
-#define __NR_fstat64            (__NR_SYSCALL_BASE+197)
788
-#define __NR_lchown32            (__NR_SYSCALL_BASE+198)
789
-#define __NR_getuid32            (__NR_SYSCALL_BASE+199)
790
-#define __NR_getgid32            (__NR_SYSCALL_BASE+200)
791
-#define __NR_geteuid32            (__NR_SYSCALL_BASE+201)
792
-#define __NR_getegid32            (__NR_SYSCALL_BASE+202)
793
-#define __NR_setreuid32            (__NR_SYSCALL_BASE+203)
794
-#define __NR_setregid32            (__NR_SYSCALL_BASE+204)
795
-#define __NR_getgroups32        (__NR_SYSCALL_BASE+205)
796
-#define __NR_setgroups32        (__NR_SYSCALL_BASE+206)
797
-#define __NR_fchown32            (__NR_SYSCALL_BASE+207)
798
-#define __NR_setresuid32        (__NR_SYSCALL_BASE+208)
799
-#define __NR_getresuid32        (__NR_SYSCALL_BASE+209)
800
-#define __NR_setresgid32        (__NR_SYSCALL_BASE+210)
801
-#define __NR_getresgid32        (__NR_SYSCALL_BASE+211)
802
-#define __NR_chown32            (__NR_SYSCALL_BASE+212)
803
-#define __NR_setuid32            (__NR_SYSCALL_BASE+213)
804
-#define __NR_setgid32            (__NR_SYSCALL_BASE+214)
805
-#define __NR_setfsuid32            (__NR_SYSCALL_BASE+215)
806
-#define __NR_setfsgid32            (__NR_SYSCALL_BASE+216)
807
-#define __NR_getdents64            (__NR_SYSCALL_BASE+217)
808
-#define __NR_pivot_root            (__NR_SYSCALL_BASE+218)
809
-#define __NR_mincore            (__NR_SYSCALL_BASE+219)
810
-#define __NR_madvise            (__NR_SYSCALL_BASE+220)
811
-#define __NR_fcntl64            (__NR_SYSCALL_BASE+221)
812
-                    /* 222 for tux */
813
-                    /* 223 is unused */
814
-#define __NR_gettid            (__NR_SYSCALL_BASE+224)
815
-#define __NR_readahead            (__NR_SYSCALL_BASE+225)
816
-#define __NR_setxattr            (__NR_SYSCALL_BASE+226)
817
-#define __NR_lsetxattr            (__NR_SYSCALL_BASE+227)
818
-#define __NR_fsetxattr            (__NR_SYSCALL_BASE+228)
819
-#define __NR_getxattr            (__NR_SYSCALL_BASE+229)
820
-#define __NR_lgetxattr            (__NR_SYSCALL_BASE+230)
821
-#define __NR_fgetxattr            (__NR_SYSCALL_BASE+231)
822
-#define __NR_listxattr            (__NR_SYSCALL_BASE+232)
823
-#define __NR_llistxattr            (__NR_SYSCALL_BASE+233)
824
-#define __NR_flistxattr            (__NR_SYSCALL_BASE+234)
825
-#define __NR_removexattr        (__NR_SYSCALL_BASE+235)
826
-#define __NR_lremovexattr        (__NR_SYSCALL_BASE+236)
827
-#define __NR_fremovexattr        (__NR_SYSCALL_BASE+237)
828
-#define __NR_tkill            (__NR_SYSCALL_BASE+238)
829
-#define __NR_sendfile64            (__NR_SYSCALL_BASE+239)
830
-#define __NR_futex            (__NR_SYSCALL_BASE+240)
831
-#define __NR_sched_setaffinity        (__NR_SYSCALL_BASE+241)
832
-#define __NR_sched_getaffinity        (__NR_SYSCALL_BASE+242)
833
-#define __NR_io_setup            (__NR_SYSCALL_BASE+243)
834
-#define __NR_io_destroy            (__NR_SYSCALL_BASE+244)
835
-#define __NR_io_getevents        (__NR_SYSCALL_BASE+245)
836
-#define __NR_io_submit            (__NR_SYSCALL_BASE+246)
837
-#define __NR_io_cancel            (__NR_SYSCALL_BASE+247)
838
-#define __NR_exit_group            (__NR_SYSCALL_BASE+248)
839
-#define __NR_lookup_dcookie        (__NR_SYSCALL_BASE+249)
840
-#define __NR_epoll_create        (__NR_SYSCALL_BASE+250)
841
-#define __NR_epoll_ctl            (__NR_SYSCALL_BASE+251)
842
-#define __NR_epoll_wait            (__NR_SYSCALL_BASE+252)
843
-#define __NR_remap_file_pages        (__NR_SYSCALL_BASE+253)
844
-                    /* 254 for set_thread_area */
845
-                    /* 255 for get_thread_area */
846
-#define __NR_set_tid_address        (__NR_SYSCALL_BASE+256)
847
-#define __NR_timer_create        (__NR_SYSCALL_BASE+257)
848
-#define __NR_timer_settime        (__NR_SYSCALL_BASE+258)
849
-#define __NR_timer_gettime        (__NR_SYSCALL_BASE+259)
850
-#define __NR_timer_getoverrun        (__NR_SYSCALL_BASE+260)
851
-#define __NR_timer_delete        (__NR_SYSCALL_BASE+261)
852
-#define __NR_clock_settime        (__NR_SYSCALL_BASE+262)
853
-#define __NR_clock_gettime        (__NR_SYSCALL_BASE+263)
854
-#define __NR_clock_getres        (__NR_SYSCALL_BASE+264)
855
-#define __NR_clock_nanosleep        (__NR_SYSCALL_BASE+265)
856
-#define __NR_statfs64            (__NR_SYSCALL_BASE+266)
857
-#define __NR_fstatfs64            (__NR_SYSCALL_BASE+267)
858
-#define __NR_tgkill            (__NR_SYSCALL_BASE+268)
859
-#define __NR_utimes            (__NR_SYSCALL_BASE+269)
860
-#define __NR_arm_fadvise64_64        (__NR_SYSCALL_BASE+270)
861
-#define __NR_pciconfig_iobase        (__NR_SYSCALL_BASE+271)
862
-#define __NR_pciconfig_read        (__NR_SYSCALL_BASE+272)
863
-#define __NR_pciconfig_write        (__NR_SYSCALL_BASE+273)
864
-#define __NR_mq_open            (__NR_SYSCALL_BASE+274)
865
-#define __NR_mq_unlink            (__NR_SYSCALL_BASE+275)
866
-#define __NR_mq_timedsend        (__NR_SYSCALL_BASE+276)
867
-#define __NR_mq_timedreceive        (__NR_SYSCALL_BASE+277)
868
-#define __NR_mq_notify            (__NR_SYSCALL_BASE+278)
869
-#define __NR_mq_getsetattr        (__NR_SYSCALL_BASE+279)
870
-#define __NR_waitid            (__NR_SYSCALL_BASE+280)
871
-#define __NR_socket            (__NR_SYSCALL_BASE+281)
872
-#define __NR_bind            (__NR_SYSCALL_BASE+282)
873
-#define __NR_connect            (__NR_SYSCALL_BASE+283)
874
-#define __NR_listen            (__NR_SYSCALL_BASE+284)
875
-#define __NR_accept            (__NR_SYSCALL_BASE+285)
876
-#define __NR_getsockname        (__NR_SYSCALL_BASE+286)
877
-#define __NR_getpeername        (__NR_SYSCALL_BASE+287)
878
-#define __NR_socketpair            (__NR_SYSCALL_BASE+288)
879
-#define __NR_send            (__NR_SYSCALL_BASE+289)
880
-#define __NR_sendto            (__NR_SYSCALL_BASE+290)
881
-#define __NR_recv            (__NR_SYSCALL_BASE+291)
882
-#define __NR_recvfrom            (__NR_SYSCALL_BASE+292)
883
-#define __NR_shutdown            (__NR_SYSCALL_BASE+293)
884
-#define __NR_setsockopt            (__NR_SYSCALL_BASE+294)
885
-#define __NR_getsockopt            (__NR_SYSCALL_BASE+295)
886
-#define __NR_sendmsg            (__NR_SYSCALL_BASE+296)
887
-#define __NR_recvmsg            (__NR_SYSCALL_BASE+297)
888
-#define __NR_semop            (__NR_SYSCALL_BASE+298)
889
-#define __NR_semget            (__NR_SYSCALL_BASE+299)
890
-#define __NR_semctl            (__NR_SYSCALL_BASE+300)
891
-#define __NR_msgsnd            (__NR_SYSCALL_BASE+301)
892
-#define __NR_msgrcv            (__NR_SYSCALL_BASE+302)
893
-#define __NR_msgget            (__NR_SYSCALL_BASE+303)
894
-#define __NR_msgctl            (__NR_SYSCALL_BASE+304)
895
-#define __NR_shmat            (__NR_SYSCALL_BASE+305)
896
-#define __NR_shmdt            (__NR_SYSCALL_BASE+306)
897
-#define __NR_shmget            (__NR_SYSCALL_BASE+307)
898
-#define __NR_shmctl            (__NR_SYSCALL_BASE+308)
899
-#define __NR_add_key            (__NR_SYSCALL_BASE+309)
900
-#define __NR_request_key        (__NR_SYSCALL_BASE+310)
901
-#define __NR_keyctl            (__NR_SYSCALL_BASE+311)
902
-#define __NR_semtimedop            (__NR_SYSCALL_BASE+312)
903
-#define __NR_vserver            (__NR_SYSCALL_BASE+313)
904
-#define __NR_ioprio_set            (__NR_SYSCALL_BASE+314)
905
-#define __NR_ioprio_get            (__NR_SYSCALL_BASE+315)
906
-#define __NR_inotify_init        (__NR_SYSCALL_BASE+316)
907
-#define __NR_inotify_add_watch        (__NR_SYSCALL_BASE+317)
908
-#define __NR_inotify_rm_watch        (__NR_SYSCALL_BASE+318)
909
-#define __NR_mbind            (__NR_SYSCALL_BASE+319)
910
-#define __NR_get_mempolicy        (__NR_SYSCALL_BASE+320)
911
-#define __NR_set_mempolicy        (__NR_SYSCALL_BASE+321)
912
-#define __NR_openat            (__NR_SYSCALL_BASE+322)
913
-#define __NR_mkdirat            (__NR_SYSCALL_BASE+323)
914
-#define __NR_mknodat            (__NR_SYSCALL_BASE+324)
915
-#define __NR_fchownat            (__NR_SYSCALL_BASE+325)
916
-#define __NR_futimesat            (__NR_SYSCALL_BASE+326)
917
-#define __NR_fstatat64            (__NR_SYSCALL_BASE+327)
918
-#define __NR_unlinkat            (__NR_SYSCALL_BASE+328)
919
-#define __NR_renameat            (__NR_SYSCALL_BASE+329)
920
-#define __NR_linkat            (__NR_SYSCALL_BASE+330)
921
-#define __NR_symlinkat            (__NR_SYSCALL_BASE+331)
922
-#define __NR_readlinkat            (__NR_SYSCALL_BASE+332)
923
-#define __NR_fchmodat            (__NR_SYSCALL_BASE+333)
924
-#define __NR_faccessat            (__NR_SYSCALL_BASE+334)
925
-#define __NR_pselect6            (__NR_SYSCALL_BASE+335)
926
-#define __NR_ppoll            (__NR_SYSCALL_BASE+336)
927
-#define __NR_unshare            (__NR_SYSCALL_BASE+337)
928
-#define __NR_set_robust_list        (__NR_SYSCALL_BASE+338)
929
-#define __NR_get_robust_list        (__NR_SYSCALL_BASE+339)
930
-#define __NR_splice            (__NR_SYSCALL_BASE+340)
931
-#define __NR_arm_sync_file_range    (__NR_SYSCALL_BASE+341)
932
+#include <asm/unistd-common.h>
933
#define __NR_sync_file_range2        __NR_arm_sync_file_range
934
-#define __NR_tee            (__NR_SYSCALL_BASE+342)
935
-#define __NR_vmsplice            (__NR_SYSCALL_BASE+343)
936
-#define __NR_move_pages            (__NR_SYSCALL_BASE+344)
937
-#define __NR_getcpu            (__NR_SYSCALL_BASE+345)
938
-#define __NR_epoll_pwait        (__NR_SYSCALL_BASE+346)
939
-#define __NR_kexec_load            (__NR_SYSCALL_BASE+347)
940
-#define __NR_utimensat            (__NR_SYSCALL_BASE+348)
941
-#define __NR_signalfd            (__NR_SYSCALL_BASE+349)
942
-#define __NR_timerfd_create        (__NR_SYSCALL_BASE+350)
943
-#define __NR_eventfd            (__NR_SYSCALL_BASE+351)
944
-#define __NR_fallocate            (__NR_SYSCALL_BASE+352)
945
-#define __NR_timerfd_settime        (__NR_SYSCALL_BASE+353)
946
-#define __NR_timerfd_gettime        (__NR_SYSCALL_BASE+354)
947
-#define __NR_signalfd4            (__NR_SYSCALL_BASE+355)
948
-#define __NR_eventfd2            (__NR_SYSCALL_BASE+356)
949
-#define __NR_epoll_create1        (__NR_SYSCALL_BASE+357)
950
-#define __NR_dup3            (__NR_SYSCALL_BASE+358)
951
-#define __NR_pipe2            (__NR_SYSCALL_BASE+359)
952
-#define __NR_inotify_init1        (__NR_SYSCALL_BASE+360)
953
-#define __NR_preadv            (__NR_SYSCALL_BASE+361)
954
-#define __NR_pwritev            (__NR_SYSCALL_BASE+362)
955
-#define __NR_rt_tgsigqueueinfo        (__NR_SYSCALL_BASE+363)
956
-#define __NR_perf_event_open        (__NR_SYSCALL_BASE+364)
957
-#define __NR_recvmmsg            (__NR_SYSCALL_BASE+365)
958
-#define __NR_accept4            (__NR_SYSCALL_BASE+366)
959
-#define __NR_fanotify_init        (__NR_SYSCALL_BASE+367)
960
-#define __NR_fanotify_mark        (__NR_SYSCALL_BASE+368)
961
-#define __NR_prlimit64            (__NR_SYSCALL_BASE+369)
962
-#define __NR_name_to_handle_at        (__NR_SYSCALL_BASE+370)
963
-#define __NR_open_by_handle_at        (__NR_SYSCALL_BASE+371)
964
-#define __NR_clock_adjtime        (__NR_SYSCALL_BASE+372)
965
-#define __NR_syncfs            (__NR_SYSCALL_BASE+373)
966
-#define __NR_sendmmsg            (__NR_SYSCALL_BASE+374)
967
-#define __NR_setns            (__NR_SYSCALL_BASE+375)
968
-#define __NR_process_vm_readv        (__NR_SYSCALL_BASE+376)
969
-#define __NR_process_vm_writev        (__NR_SYSCALL_BASE+377)
970
-#define __NR_kcmp            (__NR_SYSCALL_BASE+378)
971
-#define __NR_finit_module        (__NR_SYSCALL_BASE+379)
972
-#define __NR_sched_setattr        (__NR_SYSCALL_BASE+380)
973
-#define __NR_sched_getattr        (__NR_SYSCALL_BASE+381)
974
-#define __NR_renameat2            (__NR_SYSCALL_BASE+382)
975
-#define __NR_seccomp            (__NR_SYSCALL_BASE+383)
976
-#define __NR_getrandom            (__NR_SYSCALL_BASE+384)
977
-#define __NR_memfd_create        (__NR_SYSCALL_BASE+385)
978
-#define __NR_bpf            (__NR_SYSCALL_BASE+386)
979
-#define __NR_execveat            (__NR_SYSCALL_BASE+387)
980
-#define __NR_userfaultfd        (__NR_SYSCALL_BASE+388)
981
-#define __NR_membarrier            (__NR_SYSCALL_BASE+389)
982
-#define __NR_mlock2            (__NR_SYSCALL_BASE+390)
983
-#define __NR_copy_file_range        (__NR_SYSCALL_BASE+391)
984
-#define __NR_preadv2            (__NR_SYSCALL_BASE+392)
985
-#define __NR_pwritev2            (__NR_SYSCALL_BASE+393)
986
987
/*
988
* The following SWIs are ARM private.
989
@@ -XXX,XX +XXX,XX @@
990
#define __ARM_NR_usr32            (__ARM_NR_BASE+4)
991
#define __ARM_NR_set_tls        (__ARM_NR_BASE+5)
992
993
-/*
994
- * The following syscalls are obsolete and no longer available for EABI.
995
- */
996
-#if defined(__ARM_EABI__)
997
-#undef __NR_time
998
-#undef __NR_umount
999
-#undef __NR_stime
1000
-#undef __NR_alarm
1001
-#undef __NR_utime
1002
-#undef __NR_getrlimit
1003
-#undef __NR_select
1004
-#undef __NR_readdir
1005
-#undef __NR_mmap
1006
-#undef __NR_socketcall
1007
-#undef __NR_syscall
1008
-#undef __NR_ipc
1009
-#endif
1010
-
1011
#endif /* __ASM_ARM_UNISTD_H */
1012
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
1013
index XXXXXXX..XXXXXXX 100644
1014
--- a/linux-headers/asm-arm64/kvm.h
1015
+++ b/linux-headers/asm-arm64/kvm.h
1016
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
1017
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
1018
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
1019
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
1020
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
1021
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
1022
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
1023
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
1024
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
1025
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
1026
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
1027
#define KVM_DEV_ARM_VGIC_GRP_CTRL    4
1028
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
1029
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
1030
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
1031
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
1032
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
1033
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
1034
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK    0x3ff
1035
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
1036
+
1037
#define KVM_DEV_ARM_VGIC_CTRL_INIT    0
1038
1039
/* Device Control API on vcpu fd */
1040
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
1041
index XXXXXXX..XXXXXXX 100644
1042
--- a/linux-headers/asm-powerpc/kvm.h
1043
+++ b/linux-headers/asm-powerpc/kvm.h
1044
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1045
    __u16    n_invalid;
1046
};
1047
1048
+/* For KVM_PPC_CONFIGURE_V3_MMU */
1049
+struct kvm_ppc_mmuv3_cfg {
1050
+    __u64    flags;
1051
+    __u64    process_table;    /* second doubleword of partition table entry */
1052
+};
56
+};
1053
+
57
+
1054
+/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
58
#else
1055
+#define KVM_PPC_MMUV3_RADIX    1    /* 1 = radix mode, 0 = HPT */
59
1056
+#define KVM_PPC_MMUV3_GTSE    2    /* global translation shootdown enb. */
60
/*
1057
+
61
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1058
+/* For KVM_PPC_GET_RMMU_INFO */
62
},
1059
+struct kvm_ppc_rmmu_info {
63
};
1060
+    struct kvm_ppc_radix_geom {
64
1061
+        __u8    page_shift;
65
+/*
1062
+        __u8    level_bits[4];
66
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
1063
+        __u8    pad[3];
67
+ * is exposed to userspace by Linux.
1064
+    }    geometries[8];
68
+ */
1065
+    __u32    ap_encodings[8];
69
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
70
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
71
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
72
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
73
+ .readfn = gt_virt_cnt_read,
74
+ },
1066
+};
75
+};
1067
+
76
+
1068
/* Per-vcpu XICS interrupt controller state */
77
#endif
1069
#define KVM_REG_PPC_ICP_STATE    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
78
1070
79
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1071
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
80
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
1072
#define KVM_REG_PPC_SPRG9    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
81
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1073
#define KVM_REG_PPC_DBSR    (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
82
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1074
83
}
1075
+/* POWER9 registers */
84
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
1076
+#define KVM_REG_PPC_TIDR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
85
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
1077
+#define KVM_REG_PPC_PSSCR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
86
+ }
1078
+
87
if (arm_feature(env, ARM_FEATURE_VAPA)) {
1079
/* Transactional Memory checkpointed state:
88
ARMCPRegInfo vapa_cp_reginfo[] = {
1080
* This is all GPRs, all VSX regs and a subset of SPRs
89
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1081
*/
1082
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1083
#define KVM_REG_PPC_TM_VSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
1084
#define KVM_REG_PPC_TM_DSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
1085
#define KVM_REG_PPC_TM_TAR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
1086
+#define KVM_REG_PPC_TM_XER    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
1087
1088
/* PPC64 eXternal Interrupt Controller Specification */
1089
#define KVM_DEV_XICS_GRP_SOURCES    1    /* 64-bit source attributes */
1090
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1091
#define KVM_XICS_LEVEL_SENSITIVE    (1ULL << 40)
1092
#define KVM_XICS_MASKED        (1ULL << 41)
1093
#define KVM_XICS_PENDING        (1ULL << 42)
1094
+#define KVM_XICS_PRESENTED        (1ULL << 43)
1095
+#define KVM_XICS_QUEUED        (1ULL << 44)
1096
1097
#endif /* __LINUX_KVM_POWERPC_H */
1098
diff --git a/linux-headers/asm-powerpc/unistd.h b/linux-headers/asm-powerpc/unistd.h
1099
index XXXXXXX..XXXXXXX 100644
1100
--- a/linux-headers/asm-powerpc/unistd.h
1101
+++ b/linux-headers/asm-powerpc/unistd.h
1102
@@ -XXX,XX +XXX,XX @@
1103
#define __NR_copy_file_range    379
1104
#define __NR_preadv2        380
1105
#define __NR_pwritev2        381
1106
+#define __NR_kexec_file_load    382
1107
1108
#endif /* _ASM_POWERPC_UNISTD_H_ */
1109
diff --git a/linux-headers/asm-x86/kvm_para.h b/linux-headers/asm-x86/kvm_para.h
1110
index XXXXXXX..XXXXXXX 100644
1111
--- a/linux-headers/asm-x86/kvm_para.h
1112
+++ b/linux-headers/asm-x86/kvm_para.h
1113
@@ -XXX,XX +XXX,XX @@ struct kvm_steal_time {
1114
    __u64 steal;
1115
    __u32 version;
1116
    __u32 flags;
1117
-    __u32 pad[12];
1118
+    __u8 preempted;
1119
+    __u8 u8_pad[3];
1120
+    __u32 pad[11];
1121
+};
1122
+
1123
+#define KVM_CLOCK_PAIRING_WALLCLOCK 0
1124
+struct kvm_clock_pairing {
1125
+    __s64 sec;
1126
+    __s64 nsec;
1127
+    __u64 tsc;
1128
+    __u32 flags;
1129
+    __u32 pad[9];
1130
};
1131
1132
#define KVM_STEAL_ALIGNMENT_BITS 5
1133
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/linux-headers/linux/kvm.h
1136
+++ b/linux-headers/linux/kvm.h
1137
@@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit {
1138
struct kvm_run {
1139
    /* in */
1140
    __u8 request_interrupt_window;
1141
-    __u8 padding1[7];
1142
+    __u8 immediate_exit;
1143
+    __u8 padding1[6];
1144
1145
    /* out */
1146
    __u32 exit_reason;
1147
@@ -XXX,XX +XXX,XX @@ struct kvm_enable_cap {
1148
};
1149
1150
/* for KVM_PPC_GET_PVINFO */
1151
+
1152
+#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1153
+
1154
struct kvm_ppc_pvinfo {
1155
    /* out */
1156
    __u32 flags;
1157
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1158
    struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
1159
};
1160
1161
-#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1162
+/* for KVM_PPC_RESIZE_HPT_{PREPARE,COMMIT} */
1163
+struct kvm_ppc_resize_hpt {
1164
+    __u64 flags;
1165
+    __u32 shift;
1166
+    __u32 pad;
1167
+};
1168
1169
#define KVMIO 0xAE
1170
1171
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1172
#define KVM_CAP_S390_USER_INSTR0 130
1173
#define KVM_CAP_MSI_DEVID 131
1174
#define KVM_CAP_PPC_HTM 132
1175
+#define KVM_CAP_SPAPR_RESIZE_HPT 133
1176
+#define KVM_CAP_PPC_MMU_RADIX 134
1177
+#define KVM_CAP_PPC_MMU_HASH_V3 135
1178
+#define KVM_CAP_IMMEDIATE_EXIT 136
1179
1180
#ifdef KVM_CAP_IRQ_ROUTING
1181
1182
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
1183
#define KVM_ARM_SET_DEVICE_ADDR     _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
1184
/* Available with KVM_CAP_PPC_RTAS */
1185
#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
1186
+/* Available with KVM_CAP_SPAPR_RESIZE_HPT */
1187
+#define KVM_PPC_RESIZE_HPT_PREPARE _IOR(KVMIO, 0xad, struct kvm_ppc_resize_hpt)
1188
+#define KVM_PPC_RESIZE_HPT_COMMIT _IOR(KVMIO, 0xae, struct kvm_ppc_resize_hpt)
1189
+/* Available with KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3 */
1190
+#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
1191
+/* Available with KVM_CAP_PPC_RADIX_MMU */
1192
+#define KVM_PPC_GET_RMMU_INFO     _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
1193
1194
/* ioctl for vm fd */
1195
#define KVM_CREATE_DEVICE     _IOWR(KVMIO, 0xe0, struct kvm_create_device)
1196
diff --git a/linux-headers/linux/kvm_para.h b/linux-headers/linux/kvm_para.h
1197
index XXXXXXX..XXXXXXX 100644
1198
--- a/linux-headers/linux/kvm_para.h
1199
+++ b/linux-headers/linux/kvm_para.h
1200
@@ -XXX,XX +XXX,XX @@
1201
#define KVM_EFAULT        EFAULT
1202
#define KVM_E2BIG        E2BIG
1203
#define KVM_EPERM        EPERM
1204
+#define KVM_EOPNOTSUPP        95
1205
1206
#define KVM_HC_VAPIC_POLL_IRQ        1
1207
#define KVM_HC_MMU_OP            2
1208
@@ -XXX,XX +XXX,XX @@
1209
#define KVM_HC_MIPS_GET_CLOCK_FREQ    6
1210
#define KVM_HC_MIPS_EXIT_VM        7
1211
#define KVM_HC_MIPS_CONSOLE_OUTPUT    8
1212
+#define KVM_HC_CLOCK_PAIRING        9
1213
1214
/*
1215
* hypercalls use architecture specific
1216
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
1217
index XXXXXXX..XXXXXXX 100644
1218
--- a/linux-headers/linux/userfaultfd.h
1219
+++ b/linux-headers/linux/userfaultfd.h
1220
@@ -XXX,XX +XXX,XX @@
1221
1222
#include <linux/types.h>
1223
1224
-#define UFFD_API ((__u64)0xAA)
1225
/*
1226
- * After implementing the respective features it will become:
1227
- * #define UFFD_API_FEATURES (UFFD_FEATURE_PAGEFAULT_FLAG_WP | \
1228
- *             UFFD_FEATURE_EVENT_FORK)
1229
+ * If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and
1230
+ * UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In
1231
+ * userfaultfd.h we assumed the kernel was reading (instead _IOC_READ
1232
+ * means the userland is reading).
1233
*/
1234
-#define UFFD_API_FEATURES (0)
1235
+#define UFFD_API ((__u64)0xAA)
1236
+#define UFFD_API_FEATURES (UFFD_FEATURE_EVENT_FORK |        \
1237
+             UFFD_FEATURE_EVENT_REMAP |        \
1238
+             UFFD_FEATURE_EVENT_MADVDONTNEED |    \
1239
+             UFFD_FEATURE_MISSING_HUGETLBFS |    \
1240
+             UFFD_FEATURE_MISSING_SHMEM)
1241
#define UFFD_API_IOCTLS                \
1242
    ((__u64)1 << _UFFDIO_REGISTER |        \
1243
     (__u64)1 << _UFFDIO_UNREGISTER |    \
1244
@@ -XXX,XX +XXX,XX @@
1245
    ((__u64)1 << _UFFDIO_WAKE |        \
1246
     (__u64)1 << _UFFDIO_COPY |        \
1247
     (__u64)1 << _UFFDIO_ZEROPAGE)
1248
+#define UFFD_API_RANGE_IOCTLS_BASIC        \
1249
+    ((__u64)1 << _UFFDIO_WAKE |        \
1250
+     (__u64)1 << _UFFDIO_COPY)
1251
1252
/*
1253
* Valid ioctl command number range with this API is from 0x00 to
1254
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1255
        } pagefault;
1256
1257
        struct {
1258
+            __u32    ufd;
1259
+        } fork;
1260
+
1261
+        struct {
1262
+            __u64    from;
1263
+            __u64    to;
1264
+            __u64    len;
1265
+        } remap;
1266
+
1267
+        struct {
1268
+            __u64    start;
1269
+            __u64    end;
1270
+        } madv_dn;
1271
+
1272
+        struct {
1273
            /* unused reserved fields */
1274
            __u64    reserved1;
1275
            __u64    reserved2;
1276
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1277
* Start at 0x12 and not at 0 to be more strict against bugs.
1278
*/
1279
#define UFFD_EVENT_PAGEFAULT    0x12
1280
-#if 0 /* not available yet */
1281
#define UFFD_EVENT_FORK        0x13
1282
-#endif
1283
+#define UFFD_EVENT_REMAP    0x14
1284
+#define UFFD_EVENT_MADVDONTNEED    0x15
1285
1286
/* flags for UFFD_EVENT_PAGEFAULT */
1287
#define UFFD_PAGEFAULT_FLAG_WRITE    (1<<0)    /* If this was a write fault */
1288
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
1289
     * Note: UFFD_EVENT_PAGEFAULT and UFFD_PAGEFAULT_FLAG_WRITE
1290
     * are to be considered implicitly always enabled in all kernels as
1291
     * long as the uffdio_api.api requested matches UFFD_API.
1292
+     *
1293
+     * UFFD_FEATURE_MISSING_HUGETLBFS means an UFFDIO_REGISTER
1294
+     * with UFFDIO_REGISTER_MODE_MISSING mode will succeed on
1295
+     * hugetlbfs virtual memory ranges. Adding or not adding
1296
+     * UFFD_FEATURE_MISSING_HUGETLBFS to uffdio_api.features has
1297
+     * no real functional effect after UFFDIO_API returns, but
1298
+     * it's only useful for an initial feature set probe at
1299
+     * UFFDIO_API time. There are two ways to use it:
1300
+     *
1301
+     * 1) by adding UFFD_FEATURE_MISSING_HUGETLBFS to the
1302
+     * uffdio_api.features before calling UFFDIO_API, an error
1303
+     * will be returned by UFFDIO_API on a kernel without
1304
+     * hugetlbfs missing support
1305
+     *
1306
+     * 2) the UFFD_FEATURE_MISSING_HUGETLBFS can not be added in
1307
+     * uffdio_api.features and instead it will be set by the
1308
+     * kernel in the uffdio_api.features if the kernel supports
1309
+     * it, so userland can later check if the feature flag is
1310
+     * present in uffdio_api.features after UFFDIO_API
1311
+     * succeeded.
1312
+     *
1313
+     * UFFD_FEATURE_MISSING_SHMEM works the same as
1314
+     * UFFD_FEATURE_MISSING_HUGETLBFS, but it applies to shmem
1315
+     * (i.e. tmpfs and other shmem based APIs).
1316
     */
1317
-#if 0 /* not available yet */
1318
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
1319
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
1320
-#endif
1321
+#define UFFD_FEATURE_EVENT_REMAP        (1<<2)
1322
+#define UFFD_FEATURE_EVENT_MADVDONTNEED        (1<<3)
1323
+#define UFFD_FEATURE_MISSING_HUGETLBFS        (1<<4)
1324
+#define UFFD_FEATURE_MISSING_SHMEM        (1<<5)
1325
    __u64 features;
1326
1327
    __u64 ioctls;
1328
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
1329
index XXXXXXX..XXXXXXX 100644
1330
--- a/linux-headers/linux/vfio.h
1331
+++ b/linux-headers/linux/vfio.h
1332
@@ -XXX,XX +XXX,XX @@ struct vfio_device_info {
1333
};
1334
#define VFIO_DEVICE_GET_INFO        _IO(VFIO_TYPE, VFIO_BASE + 7)
1335
1336
+/*
1337
+ * Vendor driver using Mediated device framework should provide device_api
1338
+ * attribute in supported type attribute groups. Device API string should be one
1339
+ * of the following corresponding to device flags in vfio_device_info structure.
1340
+ */
1341
+
1342
+#define VFIO_DEVICE_API_PCI_STRING        "vfio-pci"
1343
+#define VFIO_DEVICE_API_PLATFORM_STRING        "vfio-platform"
1344
+#define VFIO_DEVICE_API_AMBA_STRING        "vfio-amba"
1345
+
1346
/**
1347
* VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8,
1348
*                 struct vfio_region_info)
1349
--
90
--
1350
2.7.4
91
2.34.1
1351
1352
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/21] hw/intc/arm_gicv3_kvm: Implement get/put functions
[PULL 07/14] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
2
implemented. This is similar to the existing CNTVOFF_EL2, except
3
that it controls a hypervisor-adjustable offset made to the physical
4
counter and timer.
2
5
3
This actually implements pre_save and post_load methods for in-kernel
6
Implement the handling for this register, which includes control/trap
4
vGICv3.
7
bits in SCR_EL3 and CNTHCTL_EL2.
5
8
6
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
11
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
10
Message-id: 1487850673-26455-4-git-send-email-vijay.kilari@gmail.com
11
[PMM:
12
* use decimal, not 0bnnn
13
* fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1
14
* completely rearranged the get and put functions to read and write
15
the state in a natural order, rather than mixing distributor and
16
redistributor state together]
17
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
18
[Vijay:
19
* Update macro KVM_VGIC_ATTR
20
* Use 32 bit access for gicd and gicr
21
* GICD_IROUTER, GICD_TYPER, GICR_PROPBASER and GICR_PENDBASER reg
22
access are changed from 64-bit to 32-bit access
23
* Add ICC_SRE_EL1 save and restore
24
* Dropped translate_fn mechanism and coded functions to handle
25
save and restore of edge_trigger and priority
26
* Number of APnR register saved/restored based on number of
27
priority bits supported]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
---
12
---
30
hw/intc/gicv3_internal.h | 1 +
13
target/arm/cpu-features.h | 5 +++
31
hw/intc/arm_gicv3_kvm.c | 573 +++++++++++++++++++++++++++++++++++++++++++++--
14
target/arm/cpu.h | 1 +
32
2 files changed, 558 insertions(+), 16 deletions(-)
15
target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--
16
target/arm/trace-events | 1 +
17
4 files changed, 73 insertions(+), 2 deletions(-)
33
18
34
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
19
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
35
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/intc/gicv3_internal.h
21
--- a/target/arm/cpu-features.h
37
+++ b/hw/intc/gicv3_internal.h
22
+++ b/target/arm/cpu-features.h
38
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
39
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
24
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
40
#define ICC_CTLR_EL1_PMHE (1U << 6)
41
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
42
+#define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
43
#define ICC_CTLR_EL1_IDBITS_SHIFT 11
44
#define ICC_CTLR_EL1_SEIS (1U << 14)
45
#define ICC_CTLR_EL1_A3V (1U << 15)
46
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_kvm.c
49
+++ b/hw/intc/arm_gicv3_kvm.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "qapi/error.h"
52
#include "hw/intc/arm_gicv3_common.h"
53
#include "hw/sysbus.h"
54
+#include "qemu/error-report.h"
55
#include "sysemu/kvm.h"
56
#include "kvm_arm.h"
57
+#include "gicv3_internal.h"
58
#include "vgic_common.h"
59
#include "migration/migration.h"
60
61
@@ -XXX,XX +XXX,XX @@
62
#define KVM_ARM_GICV3_GET_CLASS(obj) \
63
OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
64
65
+#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
66
+ (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
67
+ ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
68
+ ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
69
+ ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
70
+ ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
71
+
72
+#define ICC_PMR_EL1 \
73
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
74
+#define ICC_BPR0_EL1 \
75
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
76
+#define ICC_AP0R_EL1(n) \
77
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
78
+#define ICC_AP1R_EL1(n) \
79
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
80
+#define ICC_BPR1_EL1 \
81
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
82
+#define ICC_CTLR_EL1 \
83
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
84
+#define ICC_SRE_EL1 \
85
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
86
+#define ICC_IGRPEN0_EL1 \
87
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
88
+#define ICC_IGRPEN1_EL1 \
89
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
90
+
91
typedef struct KVMARMGICv3Class {
92
ARMGICv3CommonClass parent_class;
93
DeviceRealize parent_realize;
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
95
kvm_arm_gic_set_irq(s->num_irq, irq, level);
96
}
25
}
97
26
98
+#define KVM_VGIC_ATTR(reg, typer) \
27
+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
99
+ ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
100
+
101
+static inline void kvm_gicd_access(GICv3State *s, int offset,
102
+ uint32_t *val, bool write)
103
+{
28
+{
104
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
29
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
105
+ KVM_VGIC_ATTR(offset, 0),
106
+ val, write);
107
+}
30
+}
108
+
31
+
109
+static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
32
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
110
+ uint32_t *val, bool write)
33
{
34
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
35
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.h
38
+++ b/target/arm/cpu.h
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
40
uint64_t c14_cntkctl; /* Timer Control register */
41
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
42
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
43
+ uint64_t cntpoff_el2; /* Counter Physical Offset register */
44
ARMGenericTimer c14_timer[NUM_GTIMERS];
45
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
46
uint32_t c15_ticonfig; /* TI925T configuration byte. */
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
52
if (cpu_isar_feature(aa64_rme, cpu)) {
53
valid_mask |= SCR_NSE | SCR_GPF;
54
}
55
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
56
+ valid_mask |= SCR_ECVEN;
57
+ }
58
} else {
59
valid_mask &= ~(SCR_RW | SCR_ST);
60
if (cpu_isar_feature(aa32_ras, cpu)) {
61
@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)
62
gt_update_irq(cpu, GTIMER_PHYS);
63
}
64
65
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
111
+{
66
+{
112
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
67
+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&
113
+ KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
68
+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
114
+ val, write);
69
+ arm_is_el2_enabled(env) &&
70
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
71
+ return env->cp15.cntpoff_el2;
72
+ }
73
+ return 0;
115
+}
74
+}
116
+
75
+
117
+static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
76
+static uint64_t gt_phys_cnt_offset(CPUARMState *env)
118
+ uint64_t *val, bool write)
119
+{
77
+{
120
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
78
+ if (arm_current_el(env) >= 2) {
121
+ KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
79
+ return 0;
122
+ val, write);
80
+ }
81
+ return gt_phys_raw_cnt_offset(env);
123
+}
82
+}
124
+
83
+
125
+static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
84
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
126
+ uint32_t *val, bool write)
85
{
86
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
87
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
88
* reset timer to when ISTATUS next has to change
89
*/
90
uint64_t offset = timeridx == GTIMER_VIRT ?
91
- cpu->env.cp15.cntvoff_el2 : 0;
92
+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
93
uint64_t count = gt_get_countervalue(&cpu->env);
94
/* Note that this must be unsigned 64 bit arithmetic: */
95
int istatus = count - offset >= gt->cval;
96
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
97
98
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
99
{
100
- return gt_get_countervalue(env);
101
+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
102
}
103
104
static uint64_t gt_virt_cnt_offset(CPUARMState *env)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
106
case GTIMER_HYPVIRT:
107
offset = gt_virt_cnt_offset(env);
108
break;
109
+ case GTIMER_PHYS:
110
+ offset = gt_phys_cnt_offset(env);
111
+ break;
112
}
113
114
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
115
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
116
case GTIMER_HYPVIRT:
117
offset = gt_virt_cnt_offset(env);
118
break;
119
+ case GTIMER_PHYS:
120
+ offset = gt_phys_cnt_offset(env);
121
+ break;
122
}
123
124
trace_arm_gt_tval_write(timeridx, value);
125
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
126
R_CNTHCTL_EL1NVVCT_MASK |
127
R_CNTHCTL_EVNTIS_MASK;
128
}
129
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
130
+ valid_mask |= R_CNTHCTL_ECV_MASK;
131
+ }
132
133
/* Clear RES0 bits */
134
value &= valid_mask;
135
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
136
},
137
};
138
139
+static CPAccessResult gt_cntpoff_access(CPUARMState *env,
140
+ const ARMCPRegInfo *ri,
141
+ bool isread)
127
+{
142
+{
128
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
143
+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
129
+ KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
144
+ return CP_ACCESS_TRAP_EL3;
130
+ (VGIC_LEVEL_INFO_LINE_LEVEL <<
145
+ }
131
+ KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
146
+ return CP_ACCESS_OK;
132
+ val, write);
133
+}
147
+}
134
+
148
+
135
+/* Loop through each distributor IRQ related register; since bits
149
+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
136
+ * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
150
+ uint64_t value)
137
+ * is enabled, we skip those.
151
+{
138
+ */
152
+ ARMCPU *cpu = env_archcpu(env);
139
+#define for_each_dist_irq_reg(_irq, _max, _field_width) \
140
+ for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
141
+
153
+
142
+static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
154
+ trace_arm_gt_cntpoff_write(value);
143
+{
155
+ raw_write(env, ri, value);
144
+ uint32_t reg, *field;
156
+ gt_recalc_timer(cpu, GTIMER_PHYS);
145
+ int irq;
146
+
147
+ field = (uint32_t *)bmp;
148
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
149
+ kvm_gicd_access(s, offset, &reg, false);
150
+ *field = reg;
151
+ offset += 4;
152
+ field++;
153
+ }
154
+}
157
+}
155
+
158
+
156
+static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
159
+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {
157
+{
160
+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,
158
+ uint32_t reg, *field;
161
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
159
+ int irq;
162
+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
160
+
163
+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,
161
+ field = (uint32_t *)bmp;
164
+ .nv2_redirect_offset = 0x1a8,
162
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
165
+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),
163
+ reg = *field;
166
+};
164
+ kvm_gicd_access(s, offset, &reg, true);
167
#else
165
+ offset += 4;
168
166
+ field++;
169
/*
170
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
171
if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
172
define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
173
}
174
+#ifndef CONFIG_USER_ONLY
175
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
176
+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);
167
+ }
177
+ }
168
+}
178
+#endif
169
+
179
if (arm_feature(env, ARM_FEATURE_VAPA)) {
170
+static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
180
ARMCPRegInfo vapa_cp_reginfo[] = {
171
+ uint32_t *bmp)
181
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
172
+{
182
diff --git a/target/arm/trace-events b/target/arm/trace-events
173
+ uint32_t reg;
183
index XXXXXXX..XXXXXXX 100644
174
+ int irq;
184
--- a/target/arm/trace-events
175
+
185
+++ b/target/arm/trace-events
176
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
186
@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"
177
+ kvm_gicd_access(s, offset, &reg, false);
187
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
178
+ reg = half_unshuffle32(reg >> 1);
188
arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
179
+ if (irq % 32 != 0) {
189
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
180
+ reg = (reg << 16);
190
+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64
181
+ }
191
arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
182
+ *gic_bmp_ptr32(bmp, irq) |= reg;
192
183
+ offset += 4;
193
# kvm.c
184
+ }
185
+}
186
+
187
+static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
188
+ uint32_t *bmp)
189
+{
190
+ uint32_t reg;
191
+ int irq;
192
+
193
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
194
+ reg = *gic_bmp_ptr32(bmp, irq);
195
+ if (irq % 32 != 0) {
196
+ reg = (reg & 0xffff0000) >> 16;
197
+ } else {
198
+ reg = reg & 0xffff;
199
+ }
200
+ reg = half_shuffle32(reg) << 1;
201
+ kvm_gicd_access(s, offset, &reg, true);
202
+ offset += 4;
203
+ }
204
+}
205
+
206
+static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
207
+{
208
+ uint32_t reg;
209
+ int irq;
210
+
211
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
212
+ kvm_gic_line_level_access(s, irq, 0, &reg, false);
213
+ *gic_bmp_ptr32(bmp, irq) = reg;
214
+ }
215
+}
216
+
217
+static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
218
+{
219
+ uint32_t reg;
220
+ int irq;
221
+
222
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
223
+ reg = *gic_bmp_ptr32(bmp, irq);
224
+ kvm_gic_line_level_access(s, irq, 0, &reg, true);
225
+ }
226
+}
227
+
228
+/* Read a bitmap register group from the kernel VGIC. */
229
+static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
230
+{
231
+ uint32_t reg;
232
+ int irq;
233
+
234
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
235
+ kvm_gicd_access(s, offset, &reg, false);
236
+ *gic_bmp_ptr32(bmp, irq) = reg;
237
+ offset += 4;
238
+ }
239
+}
240
+
241
+static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
242
+ uint32_t clroffset, uint32_t *bmp)
243
+{
244
+ uint32_t reg;
245
+ int irq;
246
+
247
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
248
+ /* If this bitmap is a set/clear register pair, first write to the
249
+ * clear-reg to clear all bits before using the set-reg to write
250
+ * the 1 bits.
251
+ */
252
+ if (clroffset != 0) {
253
+ reg = 0;
254
+ kvm_gicd_access(s, clroffset, &reg, true);
255
+ }
256
+ reg = *gic_bmp_ptr32(bmp, irq);
257
+ kvm_gicd_access(s, offset, &reg, true);
258
+ offset += 4;
259
+ }
260
+}
261
+
262
+static void kvm_arm_gicv3_check(GICv3State *s)
263
+{
264
+ uint32_t reg;
265
+ uint32_t num_irq;
266
+
267
+ /* Sanity checking s->num_irq */
268
+ kvm_gicd_access(s, GICD_TYPER, &reg, false);
269
+ num_irq = ((reg & 0x1f) + 1) * 32;
270
+
271
+ if (num_irq < s->num_irq) {
272
+ error_report("Model requests %u IRQs, but kernel supports max %u",
273
+ s->num_irq, num_irq);
274
+ abort();
275
+ }
276
+}
277
+
278
static void kvm_arm_gicv3_put(GICv3State *s)
279
{
280
- /* TODO */
281
- DPRINTF("Cannot put kernel gic state, no kernel interface\n");
282
+ uint32_t regl, regh, reg;
283
+ uint64_t reg64, redist_typer;
284
+ int ncpu, i;
285
+
286
+ kvm_arm_gicv3_check(s);
287
+
288
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
289
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
290
+ redist_typer = ((uint64_t)regh << 32) | regl;
291
+
292
+ reg = s->gicd_ctlr;
293
+ kvm_gicd_access(s, GICD_CTLR, &reg, true);
294
+
295
+ if (redist_typer & GICR_TYPER_PLPIS) {
296
+ /* Set base addresses before LPIs are enabled by GICR_CTLR write */
297
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
298
+ GICv3CPUState *c = &s->cpu[ncpu];
299
+
300
+ reg64 = c->gicr_propbaser;
301
+ regl = (uint32_t)reg64;
302
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, true);
303
+ regh = (uint32_t)(reg64 >> 32);
304
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
305
+
306
+ reg64 = c->gicr_pendbaser;
307
+ if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
308
+ /* Setting PTZ is advised if LPIs are disabled, to reduce
309
+ * GIC initialization time.
310
+ */
311
+ reg64 |= GICR_PENDBASER_PTZ;
312
+ }
313
+ regl = (uint32_t)reg64;
314
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
315
+ regh = (uint32_t)(reg64 >> 32);
316
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, true);
317
+ }
318
+ }
319
+
320
+ /* Redistributor state (one per CPU) */
321
+
322
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
323
+ GICv3CPUState *c = &s->cpu[ncpu];
324
+
325
+ reg = c->gicr_ctlr;
326
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, true);
327
+
328
+ reg = c->gicr_statusr[GICV3_NS];
329
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, true);
330
+
331
+ reg = c->gicr_waker;
332
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, true);
333
+
334
+ reg = c->gicr_igroupr0;
335
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, true);
336
+
337
+ reg = ~0;
338
+ kvm_gicr_access(s, GICR_ICENABLER0, ncpu, &reg, true);
339
+ reg = c->gicr_ienabler0;
340
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, true);
341
+
342
+ /* Restore config before pending so we treat level/edge correctly */
343
+ reg = half_shuffle32(c->edge_trigger >> 16) << 1;
344
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, true);
345
+
346
+ reg = c->level;
347
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, true);
348
+
349
+ reg = ~0;
350
+ kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true);
351
+ reg = c->gicr_ipendr0;
352
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true);
353
+
354
+ reg = ~0;
355
+ kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, &reg, true);
356
+ reg = c->gicr_iactiver0;
357
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true);
358
+
359
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
360
+ reg = c->gicr_ipriorityr[i] |
361
+ (c->gicr_ipriorityr[i + 1] << 8) |
362
+ (c->gicr_ipriorityr[i + 2] << 16) |
363
+ (c->gicr_ipriorityr[i + 3] << 24);
364
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, true);
365
+ }
366
+ }
367
+
368
+ /* Distributor state (shared between all CPUs */
369
+ reg = s->gicd_statusr[GICV3_NS];
370
+ kvm_gicd_access(s, GICD_STATUSR, &reg, true);
371
+
372
+ /* s->enable bitmap -> GICD_ISENABLERn */
373
+ kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
374
+
375
+ /* s->group bitmap -> GICD_IGROUPRn */
376
+ kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
377
+
378
+ /* Restore targets before pending to ensure the pending state is set on
379
+ * the appropriate CPU interfaces in the kernel
380
+ */
381
+
382
+ /* s->gicd_irouter[irq] -> GICD_IROUTERn
383
+ * We can't use kvm_dist_put() here because the registers are 64-bit
384
+ */
385
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
386
+ uint32_t offset;
387
+
388
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
389
+ reg = (uint32_t)s->gicd_irouter[i];
390
+ kvm_gicd_access(s, offset, &reg, true);
391
+
392
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
393
+ reg = (uint32_t)(s->gicd_irouter[i] >> 32);
394
+ kvm_gicd_access(s, offset, &reg, true);
395
+ }
396
+
397
+ /* s->trigger bitmap -> GICD_ICFGRn
398
+ * (restore configuration registers before pending IRQs so we treat
399
+ * level/edge correctly)
400
+ */
401
+ kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
402
+
403
+ /* s->level bitmap -> line_level */
404
+ kvm_gic_put_line_level_bmp(s, s->level);
405
+
406
+ /* s->pending bitmap -> GICD_ISPENDRn */
407
+ kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
408
+
409
+ /* s->active bitmap -> GICD_ISACTIVERn */
410
+ kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
411
+
412
+ /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
413
+ kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
414
+
415
+ /* CPU Interface state (one per CPU) */
416
+
417
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
418
+ GICv3CPUState *c = &s->cpu[ncpu];
419
+ int num_pri_bits;
420
+
421
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
422
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
423
+ &c->icc_ctlr_el1[GICV3_NS], true);
424
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
425
+ &c->icc_igrpen[GICV3_G0], true);
426
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
427
+ &c->icc_igrpen[GICV3_G1NS], true);
428
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
429
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
430
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
431
+
432
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
433
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
434
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
435
+
436
+ switch (num_pri_bits) {
437
+ case 7:
438
+ reg64 = c->icc_apr[GICV3_G0][3];
439
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, true);
440
+ reg64 = c->icc_apr[GICV3_G0][2];
441
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, true);
442
+ case 6:
443
+ reg64 = c->icc_apr[GICV3_G0][1];
444
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, true);
445
+ default:
446
+ reg64 = c->icc_apr[GICV3_G0][0];
447
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, true);
448
+ }
449
+
450
+ switch (num_pri_bits) {
451
+ case 7:
452
+ reg64 = c->icc_apr[GICV3_G1NS][3];
453
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true);
454
+ reg64 = c->icc_apr[GICV3_G1NS][2];
455
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true);
456
+ case 6:
457
+ reg64 = c->icc_apr[GICV3_G1NS][1];
458
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true);
459
+ default:
460
+ reg64 = c->icc_apr[GICV3_G1NS][0];
461
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true);
462
+ }
463
+ }
464
}
465
466
static void kvm_arm_gicv3_get(GICv3State *s)
467
{
468
- /* TODO */
469
- DPRINTF("Cannot get kernel gic state, no kernel interface\n");
470
+ uint32_t regl, regh, reg;
471
+ uint64_t reg64, redist_typer;
472
+ int ncpu, i;
473
+
474
+ kvm_arm_gicv3_check(s);
475
+
476
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
477
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
478
+ redist_typer = ((uint64_t)regh << 32) | regl;
479
+
480
+ kvm_gicd_access(s, GICD_CTLR, &reg, false);
481
+ s->gicd_ctlr = reg;
482
+
483
+ /* Redistributor state (one per CPU) */
484
+
485
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
486
+ GICv3CPUState *c = &s->cpu[ncpu];
487
+
488
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, false);
489
+ c->gicr_ctlr = reg;
490
+
491
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, false);
492
+ c->gicr_statusr[GICV3_NS] = reg;
493
+
494
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, false);
495
+ c->gicr_waker = reg;
496
+
497
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, false);
498
+ c->gicr_igroupr0 = reg;
499
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, false);
500
+ c->gicr_ienabler0 = reg;
501
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, false);
502
+ c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
503
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, false);
504
+ c->level = reg;
505
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, false);
506
+ c->gicr_ipendr0 = reg;
507
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false);
508
+ c->gicr_iactiver0 = reg;
509
+
510
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
511
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false);
512
+ c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
513
+ c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
514
+ c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
515
+ c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
516
+ }
517
+ }
518
+
519
+ if (redist_typer & GICR_TYPER_PLPIS) {
520
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
521
+ GICv3CPUState *c = &s->cpu[ncpu];
522
+
523
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, false);
524
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, false);
525
+ c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
526
+
527
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, false);
528
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, false);
529
+ c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
530
+ }
531
+ }
532
+
533
+ /* Distributor state (shared between all CPUs */
534
+
535
+ kvm_gicd_access(s, GICD_STATUSR, &reg, false);
536
+ s->gicd_statusr[GICV3_NS] = reg;
537
+
538
+ /* GICD_IGROUPRn -> s->group bitmap */
539
+ kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
540
+
541
+ /* GICD_ISENABLERn -> s->enabled bitmap */
542
+ kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
543
+
544
+ /* Line level of irq */
545
+ kvm_gic_get_line_level_bmp(s, s->level);
546
+ /* GICD_ISPENDRn -> s->pending bitmap */
547
+ kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
548
+
549
+ /* GICD_ISACTIVERn -> s->active bitmap */
550
+ kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
551
+
552
+ /* GICD_ICFGRn -> s->trigger bitmap */
553
+ kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
554
+
555
+ /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
556
+ kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
557
+
558
+ /* GICD_IROUTERn -> s->gicd_irouter[irq] */
559
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
560
+ uint32_t offset;
561
+
562
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
563
+ kvm_gicd_access(s, offset, &regl, false);
564
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
565
+ kvm_gicd_access(s, offset, &regh, false);
566
+ s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
567
+ }
568
+
569
+ /*****************************************************************
570
+ * CPU Interface(s) State
571
+ */
572
+
573
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
574
+ GICv3CPUState *c = &s->cpu[ncpu];
575
+ int num_pri_bits;
576
+
577
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
578
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
579
+ &c->icc_ctlr_el1[GICV3_NS], false);
580
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
581
+ &c->icc_igrpen[GICV3_G0], false);
582
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
583
+ &c->icc_igrpen[GICV3_G1NS], false);
584
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
585
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
586
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
587
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
588
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
589
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
590
+
591
+ switch (num_pri_bits) {
592
+ case 7:
593
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, false);
594
+ c->icc_apr[GICV3_G0][3] = reg64;
595
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, false);
596
+ c->icc_apr[GICV3_G0][2] = reg64;
597
+ case 6:
598
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, false);
599
+ c->icc_apr[GICV3_G0][1] = reg64;
600
+ default:
601
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, false);
602
+ c->icc_apr[GICV3_G0][0] = reg64;
603
+ }
604
+
605
+ switch (num_pri_bits) {
606
+ case 7:
607
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false);
608
+ c->icc_apr[GICV3_G1NS][3] = reg64;
609
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false);
610
+ c->icc_apr[GICV3_G1NS][2] = reg64;
611
+ case 6:
612
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false);
613
+ c->icc_apr[GICV3_G1NS][1] = reg64;
614
+ default:
615
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);
616
+ c->icc_apr[GICV3_G1NS][0] = reg64;
617
+ }
618
+ }
619
}
620
621
static void kvm_arm_gicv3_reset(DeviceState *dev)
622
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
623
DPRINTF("Reset\n");
624
625
kgc->parent_reset(dev);
626
+
627
+ if (s->migration_blocker) {
628
+ DPRINTF("Cannot put kernel gic state, no kernel interface\n");
629
+ return;
630
+ }
631
+
632
kvm_arm_gicv3_put(s);
633
}
634
635
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
636
637
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
638
639
- /* Block migration of a KVM GICv3 device: the API for saving and restoring
640
- * the state in the kernel is not yet finalised in the kernel or
641
- * implemented in QEMU.
642
- */
643
- error_setg(&s->migration_blocker, "vGICv3 migration is not implemented");
644
- migrate_add_blocker(s->migration_blocker, &local_err);
645
- if (local_err) {
646
- error_propagate(errp, local_err);
647
- error_free(s->migration_blocker);
648
- return;
649
- }
650
-
651
/* Try to create the device via the device control API */
652
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
653
if (s->dev_fd < 0) {
654
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
655
656
kvm_irqchip_commit_routes(kvm_state);
657
}
658
+
659
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
660
+ GICD_CTLR)) {
661
+ error_setg(&s->migration_blocker, "This operating system kernel does "
662
+ "not support vGICv3 migration");
663
+ migrate_add_blocker(s->migration_blocker, &local_err);
664
+ if (local_err) {
665
+ error_propagate(errp, local_err);
666
+ error_free(s->migration_blocker);
667
+ return;
668
+ }
669
+ }
670
}
671
672
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
673
--
194
--
674
2.7.4
195
2.34.1
675
676
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/21] stm32f205: Rename 'nvic' local to 'armv7m'
[PULL 08/14] target/arm: Enable FEAT_ECV for 'max' CPU
1
The local variable 'nvic' in stm32f205_soc_realize() no longer
1
Enable all FEAT_ECV features on the 'max' CPU.
2
holds a direct pointer to the NVIC device; it is a pointer to
3
the ARMv7M container object. Rename it 'armv7m' accordingly.
4
2
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
9
Message-id: 1487604965-23220-12-git-send-email-peter.maydell@linaro.org
10
---
7
---
11
hw/arm/stm32f205_soc.c | 18 +++++++++---------
8
docs/system/arm/emulation.rst | 1 +
12
1 file changed, 9 insertions(+), 9 deletions(-)
9
target/arm/tcg/cpu64.c | 1 +
10
2 files changed, 2 insertions(+)
13
11
14
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/stm32f205_soc.c
14
--- a/docs/system/arm/emulation.rst
17
+++ b/hw/arm/stm32f205_soc.c
15
+++ b/docs/system/arm/emulation.rst
18
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
19
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
17
- FEAT_DotProd (Advanced SIMD dot product instructions)
20
{
18
- FEAT_DoubleFault (Double Fault Extension)
21
STM32F205State *s = STM32F205_SOC(dev_soc);
19
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
22
- DeviceState *dev, *nvic;
20
+- FEAT_ECV (Enhanced Counter Virtualization)
23
+ DeviceState *dev, *armv7m;
21
- FEAT_EPAC (Enhanced pointer authentication)
24
SysBusDevice *busdev;
22
- FEAT_ETS (Enhanced Translation Synchronization)
25
Error *err = NULL;
23
- FEAT_EVT (Enhanced Virtualization Traps)
26
int i;
24
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
27
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
25
index XXXXXXX..XXXXXXX 100644
28
vmstate_register_ram_global(sram);
26
--- a/target/arm/tcg/cpu64.c
29
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
27
+++ b/target/arm/tcg/cpu64.c
30
28
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
31
- nvic = DEVICE(&s->armv7m);
29
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
32
- qdev_prop_set_uint32(nvic, "num-irq", 96);
30
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
33
- qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
31
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
34
+ armv7m = DEVICE(&s->armv7m);
32
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
35
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
33
cpu->isar.id_aa64mmfr0 = t;
36
+ qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
34
37
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
35
t = cpu->isar.id_aa64mmfr1;
38
"memory", &error_abort);
39
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
40
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
41
}
42
busdev = SYS_BUS_DEVICE(dev);
43
sysbus_mmio_map(busdev, 0, 0x40013800);
44
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
45
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
46
47
/* Attach UART (uses USART registers) and USART controllers */
48
for (i = 0; i < STM_NUM_USARTS; i++) {
49
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
50
}
51
busdev = SYS_BUS_DEVICE(dev);
52
sysbus_mmio_map(busdev, 0, usart_addr[i]);
53
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
54
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
55
}
56
57
/* Timer 2 to 5 */
58
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
59
}
60
busdev = SYS_BUS_DEVICE(dev);
61
sysbus_mmio_map(busdev, 0, timer_addr[i]);
62
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
63
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
64
}
65
66
/* ADC 1 to 3 */
67
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
68
return;
69
}
70
qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
71
- qdev_get_gpio_in(nvic, ADC_IRQ));
72
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
73
74
for (i = 0; i < STM_NUM_ADCS; i++) {
75
dev = DEVICE(&(s->adc[i]));
76
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
77
}
78
busdev = SYS_BUS_DEVICE(dev);
79
sysbus_mmio_map(busdev, 0, spi_addr[i]);
80
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
81
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
82
}
83
}
84
85
--
36
--
86
2.7.4
37
2.34.1
87
38
88
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/21] bcm2835_gpio: add bcm2835 gpio controller
[PULL 09/14] hw/gpio: Implement STM32L4x5 GPIO
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
This adds the BCM2835 GPIO controller.
3
Features supported :
4
- the 8 STM32L4x5 GPIOs are initialized with their reset values
5
(except IDR, see below)
6
- input mode : setting a pin in input mode "externally" (using input
7
irqs) results in an out irq (transmitted to SYSCFG)
8
- output mode : setting a bit in ODR sets the corresponding out irq
9
(if this line is configured in output mode)
10
- pull-up, pull-down
11
- push-pull, open-drain
4
12
5
It currently implements:
13
Difference with the real GPIOs :
6
- The 54 GPIOs as outputs (qemu_irq)
14
- Alternate Function and Analog mode aren't implemented :
7
- The SD controller selection via alternate function of GPIOs 48-53
15
pins in AF/Analog behave like pins in input mode
16
- floating pins stay at their last value
17
- register IDR reset values differ from the real one :
18
values are coherent with the other registers reset values
19
and the fact that AF/Analog modes aren't implemented
20
- setting I/O output speed isn't supported
21
- locking port bits isn't supported
22
- ADC function isn't supported
23
- GPIOH has 16 pins instead of 2 pins
24
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
8
25
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org
29
Acked-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr
30
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
32
---
17
hw/gpio/Makefile.objs | 1 +
33
MAINTAINERS | 1 +
18
include/hw/gpio/bcm2835_gpio.h | 39 +++++
34
docs/system/arm/b-l475e-iot01a.rst | 2 +-
19
hw/gpio/bcm2835_gpio.c | 353 +++++++++++++++++++++++++++++++++++++++++
35
include/hw/gpio/stm32l4x5_gpio.h | 70 +++++
20
3 files changed, 393 insertions(+)
36
hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++
21
create mode 100644 include/hw/gpio/bcm2835_gpio.h
37
hw/gpio/Kconfig | 3 +
22
create mode 100644 hw/gpio/bcm2835_gpio.c
38
hw/gpio/meson.build | 1 +
39
hw/gpio/trace-events | 6 +
40
7 files changed, 559 insertions(+), 1 deletion(-)
41
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
42
create mode 100644 hw/gpio/stm32l4x5_gpio.c
23
43
24
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
44
diff --git a/MAINTAINERS b/MAINTAINERS
25
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/gpio/Makefile.objs
46
--- a/MAINTAINERS
27
+++ b/hw/gpio/Makefile.objs
47
+++ b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
48
@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c
29
49
F: hw/misc/stm32l4x5_exti.c
30
obj-$(CONFIG_OMAP) += omap_gpio.o
50
F: hw/misc/stm32l4x5_syscfg.c
31
obj-$(CONFIG_IMX) += imx_gpio.o
51
F: hw/misc/stm32l4x5_rcc.c
32
+obj-$(CONFIG_RASPI) += bcm2835_gpio.o
52
+F: hw/gpio/stm32l4x5_gpio.c
33
diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpio.h
53
F: include/hw/*/stm32l4x5_*.h
54
55
B-L475E-IOT01A IoT Node
56
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
57
index XXXXXXX..XXXXXXX 100644
58
--- a/docs/system/arm/b-l475e-iot01a.rst
59
+++ b/docs/system/arm/b-l475e-iot01a.rst
60
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
61
- STM32L4x5 EXTI (Extended interrupts and events controller)
62
- STM32L4x5 SYSCFG (System configuration controller)
63
- STM32L4x5 RCC (Reset and clock control)
64
+- STM32L4x5 GPIOs (General-purpose I/Os)
65
66
Missing devices
67
"""""""""""""""
68
@@ -XXX,XX +XXX,XX @@ Missing devices
69
The B-L475E-IOT01A does *not* support the following devices:
70
71
- Serial ports (UART)
72
-- General-purpose I/Os (GPIO)
73
- Analog to Digital Converter (ADC)
74
- SPI controller
75
- Timer controller (TIMER)
76
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
34
new file mode 100644
77
new file mode 100644
35
index XXXXXXX..XXXXXXX
78
index XXXXXXX..XXXXXXX
36
--- /dev/null
79
--- /dev/null
37
+++ b/include/hw/gpio/bcm2835_gpio.h
80
+++ b/include/hw/gpio/stm32l4x5_gpio.h
38
@@ -XXX,XX +XXX,XX @@
81
@@ -XXX,XX +XXX,XX @@
39
+/*
82
+/*
40
+ * Raspberry Pi (BCM2835) GPIO Controller
83
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
41
+ *
84
+ *
42
+ * Copyright (c) 2017 Antfield SAS
85
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
86
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
43
+ *
87
+ *
44
+ * Authors:
88
+ * SPDX-License-Identifier: GPL-2.0-or-later
45
+ * Clement Deschamps <clement.deschamps@antfield.fr>
46
+ * Luc Michel <luc.michel@antfield.fr>
47
+ *
89
+ *
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
90
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
49
+ * See the COPYING file in the top-level directory.
91
+ * See the COPYING file in the top-level directory.
50
+ */
92
+ */
51
+
93
+
52
+#ifndef BCM2835_GPIO_H
94
+/*
53
+#define BCM2835_GPIO_H
95
+ * The reference used is the STMicroElectronics RM0351 Reference manual
54
+
96
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
55
+#include "hw/sd/sd.h"
97
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
56
+
98
+ */
57
+typedef struct BCM2835GpioState {
99
+
100
+#ifndef HW_STM32L4X5_GPIO_H
101
+#define HW_STM32L4X5_GPIO_H
102
+
103
+#include "hw/sysbus.h"
104
+#include "qom/object.h"
105
+
106
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
107
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
108
+
109
+#define GPIO_NUM_PINS 16
110
+
111
+struct Stm32l4x5GpioState {
58
+ SysBusDevice parent_obj;
112
+ SysBusDevice parent_obj;
59
+
113
+
60
+ MemoryRegion iomem;
114
+ MemoryRegion mmio;
61
+
115
+
62
+ /* SDBus selector */
116
+ /* GPIO registers */
63
+ SDBus sdbus;
117
+ uint32_t moder;
64
+ SDBus *sdbus_sdhci;
118
+ uint32_t otyper;
65
+ SDBus *sdbus_sdhost;
119
+ uint32_t ospeedr;
66
+
120
+ uint32_t pupdr;
67
+ uint8_t fsel[54];
121
+ uint32_t idr;
68
+ uint32_t lev0, lev1;
122
+ uint32_t odr;
69
+ uint8_t sd_fsel;
123
+ uint32_t lckr;
70
+ qemu_irq out[54];
124
+ uint32_t afrl;
71
+} BCM2835GpioState;
125
+ uint32_t afrh;
72
+
126
+ uint32_t ascr;
73
+#define TYPE_BCM2835_GPIO "bcm2835_gpio"
127
+
74
+#define BCM2835_GPIO(obj) \
128
+ /* GPIO registers reset values */
75
+ OBJECT_CHECK(BCM2835GpioState, (obj), TYPE_BCM2835_GPIO)
129
+ uint32_t moder_reset;
130
+ uint32_t ospeedr_reset;
131
+ uint32_t pupdr_reset;
132
+
133
+ /*
134
+ * External driving of pins.
135
+ * The pins can be set externally through the device
136
+ * anonymous input GPIOs lines under certain conditions.
137
+ * The pin must not be in push-pull output mode,
138
+ * and can't be set high in open-drain mode.
139
+ * Pins driven externally and configured to
140
+ * output mode will in general be "disconnected"
141
+ * (see `get_gpio_pinmask_to_disconnect()`)
142
+ */
143
+ uint16_t disconnected_pins;
144
+ uint16_t pins_connected_high;
145
+
146
+ char *name;
147
+ Clock *clk;
148
+ qemu_irq pin[GPIO_NUM_PINS];
149
+};
76
+
150
+
77
+#endif
151
+#endif
78
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
152
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
79
new file mode 100644
153
new file mode 100644
80
index XXXXXXX..XXXXXXX
154
index XXXXXXX..XXXXXXX
81
--- /dev/null
155
--- /dev/null
82
+++ b/hw/gpio/bcm2835_gpio.c
156
+++ b/hw/gpio/stm32l4x5_gpio.c
83
@@ -XXX,XX +XXX,XX @@
157
@@ -XXX,XX +XXX,XX @@
84
+/*
158
+/*
85
+ * Raspberry Pi (BCM2835) GPIO Controller
159
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
86
+ *
160
+ *
87
+ * Copyright (c) 2017 Antfield SAS
161
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
162
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
88
+ *
163
+ *
89
+ * Authors:
164
+ * SPDX-License-Identifier: GPL-2.0-or-later
90
+ * Clement Deschamps <clement.deschamps@antfield.fr>
91
+ * Luc Michel <luc.michel@antfield.fr>
92
+ *
165
+ *
93
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
94
+ * See the COPYING file in the top-level directory.
167
+ * See the COPYING file in the top-level directory.
95
+ */
168
+ */
96
+
169
+
170
+/*
171
+ * The reference used is the STMicroElectronics RM0351 Reference manual
172
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
173
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
174
+ */
175
+
97
+#include "qemu/osdep.h"
176
+#include "qemu/osdep.h"
98
+#include "qemu/log.h"
177
+#include "qemu/log.h"
99
+#include "qemu/timer.h"
178
+#include "hw/gpio/stm32l4x5_gpio.h"
179
+#include "hw/irq.h"
180
+#include "hw/qdev-clock.h"
181
+#include "hw/qdev-properties.h"
182
+#include "qapi/visitor.h"
100
+#include "qapi/error.h"
183
+#include "qapi/error.h"
101
+#include "hw/sysbus.h"
184
+#include "migration/vmstate.h"
102
+#include "hw/sd/sd.h"
185
+#include "trace.h"
103
+#include "hw/gpio/bcm2835_gpio.h"
186
+
104
+
187
+#define GPIO_MODER 0x00
105
+#define GPFSEL0 0x00
188
+#define GPIO_OTYPER 0x04
106
+#define GPFSEL1 0x04
189
+#define GPIO_OSPEEDR 0x08
107
+#define GPFSEL2 0x08
190
+#define GPIO_PUPDR 0x0C
108
+#define GPFSEL3 0x0C
191
+#define GPIO_IDR 0x10
109
+#define GPFSEL4 0x10
192
+#define GPIO_ODR 0x14
110
+#define GPFSEL5 0x14
193
+#define GPIO_BSRR 0x18
111
+#define GPSET0 0x1C
194
+#define GPIO_LCKR 0x1C
112
+#define GPSET1 0x20
195
+#define GPIO_AFRL 0x20
113
+#define GPCLR0 0x28
196
+#define GPIO_AFRH 0x24
114
+#define GPCLR1 0x2C
197
+#define GPIO_BRR 0x28
115
+#define GPLEV0 0x34
198
+#define GPIO_ASCR 0x2C
116
+#define GPLEV1 0x38
199
+
117
+#define GPEDS0 0x40
200
+/* 0b11111111_11111111_00000000_00000000 */
118
+#define GPEDS1 0x44
201
+#define RESERVED_BITS_MASK 0xFFFF0000
119
+#define GPREN0 0x4C
202
+
120
+#define GPREN1 0x50
203
+static void update_gpio_idr(Stm32l4x5GpioState *s);
121
+#define GPFEN0 0x58
204
+
122
+#define GPFEN1 0x5C
205
+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
123
+#define GPHEN0 0x64
206
+{
124
+#define GPHEN1 0x68
207
+ return extract32(s->pupdr, 2 * pin, 2) == 1;
125
+#define GPLEN0 0x70
208
+}
126
+#define GPLEN1 0x74
209
+
127
+#define GPAREN0 0x7C
210
+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
128
+#define GPAREN1 0x80
211
+{
129
+#define GPAFEN0 0x88
212
+ return extract32(s->pupdr, 2 * pin, 2) == 2;
130
+#define GPAFEN1 0x8C
213
+}
131
+#define GPPUD 0x94
214
+
132
+#define GPPUDCLK0 0x98
215
+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
133
+#define GPPUDCLK1 0x9C
216
+{
134
+
217
+ return extract32(s->moder, 2 * pin, 2) == 1;
135
+static uint32_t gpfsel_get(BCM2835GpioState *s, uint8_t reg)
218
+}
136
+{
219
+
137
+ int i;
220
+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
138
+ uint32_t value = 0;
221
+{
139
+ for (i = 0; i < 10; i++) {
222
+ return extract32(s->otyper, pin, 1) == 1;
140
+ uint32_t index = 10 * reg + i;
223
+}
141
+ if (index < sizeof(s->fsel)) {
224
+
142
+ value |= (s->fsel[index] & 0x7) << (3 * i);
225
+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
226
+{
227
+ return extract32(s->otyper, pin, 1) == 0;
228
+}
229
+
230
+static void stm32l4x5_gpio_reset_hold(Object *obj)
231
+{
232
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
233
+
234
+ s->moder = s->moder_reset;
235
+ s->otyper = 0x00000000;
236
+ s->ospeedr = s->ospeedr_reset;
237
+ s->pupdr = s->pupdr_reset;
238
+ s->idr = 0x00000000;
239
+ s->odr = 0x00000000;
240
+ s->lckr = 0x00000000;
241
+ s->afrl = 0x00000000;
242
+ s->afrh = 0x00000000;
243
+ s->ascr = 0x00000000;
244
+
245
+ s->disconnected_pins = 0xFFFF;
246
+ s->pins_connected_high = 0x0000;
247
+ update_gpio_idr(s);
248
+}
249
+
250
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
251
+{
252
+ Stm32l4x5GpioState *s = opaque;
253
+ /*
254
+ * The pin isn't set if line is configured in output mode
255
+ * except if level is 0 and the output is open-drain.
256
+ * This way there will be no short-circuit prone situations.
257
+ */
258
+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
259
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
260
+ line);
261
+ return;
262
+ }
263
+
264
+ s->disconnected_pins &= ~(1 << line);
265
+ if (level) {
266
+ s->pins_connected_high |= (1 << line);
267
+ } else {
268
+ s->pins_connected_high &= ~(1 << line);
269
+ }
270
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
271
+ s->pins_connected_high);
272
+ update_gpio_idr(s);
273
+}
274
+
275
+
276
+static void update_gpio_idr(Stm32l4x5GpioState *s)
277
+{
278
+ uint32_t new_idr_mask = 0;
279
+ uint32_t new_idr = s->odr;
280
+ uint32_t old_idr = s->idr;
281
+ int new_pin_state, old_pin_state;
282
+
283
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
284
+ if (is_output(s, i)) {
285
+ if (is_push_pull(s, i)) {
286
+ new_idr_mask |= (1 << i);
287
+ } else if (!(s->odr & (1 << i))) {
288
+ /* open-drain ODR 0 */
289
+ new_idr_mask |= (1 << i);
290
+ /* open-drain ODR 1 */
291
+ } else if (!(s->disconnected_pins & (1 << i)) &&
292
+ !(s->pins_connected_high & (1 << i))) {
293
+ /* open-drain ODR 1 with pin connected low */
294
+ new_idr_mask |= (1 << i);
295
+ new_idr &= ~(1 << i);
296
+ /* open-drain ODR 1 with unactive pin */
297
+ } else if (is_pull_up(s, i)) {
298
+ new_idr_mask |= (1 << i);
299
+ } else if (is_pull_down(s, i)) {
300
+ new_idr_mask |= (1 << i);
301
+ new_idr &= ~(1 << i);
302
+ }
303
+ /*
304
+ * The only case left is for open-drain ODR 1
305
+ * with unactive pin without pull-up or pull-down :
306
+ * the value is floating.
307
+ */
308
+ /* input or analog mode with connected pin */
309
+ } else if (!(s->disconnected_pins & (1 << i))) {
310
+ if (s->pins_connected_high & (1 << i)) {
311
+ /* pin high */
312
+ new_idr_mask |= (1 << i);
313
+ new_idr |= (1 << i);
314
+ } else {
315
+ /* pin low */
316
+ new_idr_mask |= (1 << i);
317
+ new_idr &= ~(1 << i);
318
+ }
319
+ /* input or analog mode with disconnected pin */
320
+ } else {
321
+ if (is_pull_up(s, i)) {
322
+ /* pull-up */
323
+ new_idr_mask |= (1 << i);
324
+ new_idr |= (1 << i);
325
+ } else if (is_pull_down(s, i)) {
326
+ /* pull-down */
327
+ new_idr_mask |= (1 << i);
328
+ new_idr &= ~(1 << i);
329
+ }
330
+ /*
331
+ * The only case left is for a disconnected pin
332
+ * without pull-up or pull-down :
333
+ * the value is floating.
334
+ */
143
+ }
335
+ }
144
+ }
336
+ }
145
+ return value;
337
+
146
+}
338
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
147
+
339
+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
148
+static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value)
340
+
149
+{
341
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
150
+ int i;
342
+ if (new_idr_mask & (1 << i)) {
151
+ for (i = 0; i < 10; i++) {
343
+ new_pin_state = (new_idr & (1 << i)) > 0;
152
+ uint32_t index = 10 * reg + i;
344
+ old_pin_state = (old_idr & (1 << i)) > 0;
153
+ if (index < sizeof(s->fsel)) {
345
+ if (new_pin_state > old_pin_state) {
154
+ int fsel = (value >> (3 * i)) & 0x7;
346
+ qemu_irq_raise(s->pin[i]);
155
+ s->fsel[index] = fsel;
347
+ } else if (new_pin_state < old_pin_state) {
348
+ qemu_irq_lower(s->pin[i]);
349
+ }
156
+ }
350
+ }
157
+ }
351
+ }
158
+
352
+}
159
+ /* SD controller selection (48-53) */
353
+
160
+ if (s->sd_fsel != 0
354
+/*
161
+ && (s->fsel[48] == 0) /* SD_CLK_R */
355
+ * Return mask of pins that are both configured in output
162
+ && (s->fsel[49] == 0) /* SD_CMD_R */
356
+ * mode and externally driven (except pins in open-drain
163
+ && (s->fsel[50] == 0) /* SD_DATA0_R */
357
+ * mode externally set to 0).
164
+ && (s->fsel[51] == 0) /* SD_DATA1_R */
358
+ */
165
+ && (s->fsel[52] == 0) /* SD_DATA2_R */
359
+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
166
+ && (s->fsel[53] == 0) /* SD_DATA3_R */
360
+{
167
+ ) {
361
+ uint32_t pins_to_disconnect = 0;
168
+ /* SDHCI controller selected */
362
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
169
+ sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci);
363
+ /* for each connected pin in output mode */
170
+ s->sd_fsel = 0;
364
+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
171
+ } else if (s->sd_fsel != 4
365
+ /* if either push-pull or high level */
172
+ && (s->fsel[48] == 4) /* SD_CLK_R */
366
+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
173
+ && (s->fsel[49] == 4) /* SD_CMD_R */
367
+ pins_to_disconnect |= (1 << i);
174
+ && (s->fsel[50] == 4) /* SD_DATA0_R */
368
+ qemu_log_mask(LOG_GUEST_ERROR,
175
+ && (s->fsel[51] == 4) /* SD_DATA1_R */
369
+ "Line %d can't be driven externally\n",
176
+ && (s->fsel[52] == 4) /* SD_DATA2_R */
370
+ i);
177
+ && (s->fsel[53] == 4) /* SD_DATA3_R */
371
+ }
178
+ ) {
179
+ /* SDHost controller selected */
180
+ sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost);
181
+ s->sd_fsel = 4;
182
+ }
183
+}
184
+
185
+static int gpfsel_is_out(BCM2835GpioState *s, int index)
186
+{
187
+ if (index >= 0 && index < 54) {
188
+ return s->fsel[index] == 1;
189
+ }
190
+ return 0;
191
+}
192
+
193
+static void gpset(BCM2835GpioState *s,
194
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
195
+{
196
+ uint32_t changes = val & ~*lev;
197
+ uint32_t cur = 1;
198
+
199
+ int i;
200
+ for (i = 0; i < count; i++) {
201
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
202
+ qemu_set_irq(s->out[start + i], 1);
203
+ }
372
+ }
204
+ cur <<= 1;
373
+ }
205
+ }
374
+ return pins_to_disconnect;
206
+
375
+}
207
+ *lev |= val;
376
+
208
+}
377
+/*
209
+
378
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
210
+static void gpclr(BCM2835GpioState *s,
379
+ */
211
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
380
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
212
+{
381
+{
213
+ uint32_t changes = val & *lev;
382
+ s->disconnected_pins |= lines;
214
+ uint32_t cur = 1;
383
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
215
+
384
+ s->pins_connected_high);
216
+ int i;
385
+ update_gpio_idr(s);
217
+ for (i = 0; i < count; i++) {
386
+}
218
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
387
+
219
+ qemu_set_irq(s->out[start + i], 0);
388
+static void disconnected_pins_set(Object *obj, Visitor *v,
220
+ }
389
+ const char *name, void *opaque, Error **errp)
221
+ cur <<= 1;
390
+{
222
+ }
391
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
223
+
392
+ uint16_t value;
224
+ *lev &= ~val;
393
+ if (!visit_type_uint16(v, name, &value, errp)) {
225
+}
394
+ return;
226
+
395
+ }
227
+static uint64_t bcm2835_gpio_read(void *opaque, hwaddr offset,
396
+ disconnect_gpio_pins(s, value);
228
+ unsigned size)
397
+}
229
+{
398
+
230
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
399
+static void disconnected_pins_get(Object *obj, Visitor *v,
231
+
400
+ const char *name, void *opaque, Error **errp)
232
+ switch (offset) {
401
+{
233
+ case GPFSEL0:
402
+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);
234
+ case GPFSEL1:
403
+}
235
+ case GPFSEL2:
404
+
236
+ case GPFSEL3:
405
+static void clock_freq_get(Object *obj, Visitor *v,
237
+ case GPFSEL4:
406
+ const char *name, void *opaque, Error **errp)
238
+ case GPFSEL5:
407
+{
239
+ return gpfsel_get(s, offset / 4);
408
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
240
+ case GPSET0:
409
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
241
+ case GPSET1:
410
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
242
+ /* Write Only */
411
+}
412
+
413
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
414
+ uint64_t val64, unsigned int size)
415
+{
416
+ Stm32l4x5GpioState *s = opaque;
417
+
418
+ uint32_t value = val64;
419
+ trace_stm32l4x5_gpio_write(s->name, addr, val64);
420
+
421
+ switch (addr) {
422
+ case GPIO_MODER:
423
+ s->moder = value;
424
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
425
+ qemu_log_mask(LOG_UNIMP,
426
+ "%s: Analog and AF modes aren't supported\n\
427
+ Analog and AF mode behave like input mode\n",
428
+ __func__);
429
+ return;
430
+ case GPIO_OTYPER:
431
+ s->otyper = value & ~RESERVED_BITS_MASK;
432
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
433
+ return;
434
+ case GPIO_OSPEEDR:
435
+ qemu_log_mask(LOG_UNIMP,
436
+ "%s: Changing I/O output speed isn't supported\n\
437
+ I/O speed is already maximal\n",
438
+ __func__);
439
+ s->ospeedr = value;
440
+ return;
441
+ case GPIO_PUPDR:
442
+ s->pupdr = value;
443
+ update_gpio_idr(s);
444
+ return;
445
+ case GPIO_IDR:
446
+ qemu_log_mask(LOG_UNIMP,
447
+ "%s: GPIO->IDR is read-only\n",
448
+ __func__);
449
+ return;
450
+ case GPIO_ODR:
451
+ s->odr = value & ~RESERVED_BITS_MASK;
452
+ update_gpio_idr(s);
453
+ return;
454
+ case GPIO_BSRR: {
455
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
456
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
457
+ /* If both BSx and BRx are set, BSx has priority.*/
458
+ s->odr &= ~bits_to_reset;
459
+ s->odr |= bits_to_set;
460
+ update_gpio_idr(s);
461
+ return;
462
+ }
463
+ case GPIO_LCKR:
464
+ qemu_log_mask(LOG_UNIMP,
465
+ "%s: Locking port bits configuration isn't supported\n",
466
+ __func__);
467
+ s->lckr = value & ~RESERVED_BITS_MASK;
468
+ return;
469
+ case GPIO_AFRL:
470
+ qemu_log_mask(LOG_UNIMP,
471
+ "%s: Alternate functions aren't supported\n",
472
+ __func__);
473
+ s->afrl = value;
474
+ return;
475
+ case GPIO_AFRH:
476
+ qemu_log_mask(LOG_UNIMP,
477
+ "%s: Alternate functions aren't supported\n",
478
+ __func__);
479
+ s->afrh = value;
480
+ return;
481
+ case GPIO_BRR: {
482
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
483
+ s->odr &= ~bits_to_reset;
484
+ update_gpio_idr(s);
485
+ return;
486
+ }
487
+ case GPIO_ASCR:
488
+ qemu_log_mask(LOG_UNIMP,
489
+ "%s: ADC function isn't supported\n",
490
+ __func__);
491
+ s->ascr = value & ~RESERVED_BITS_MASK;
492
+ return;
493
+ default:
494
+ qemu_log_mask(LOG_GUEST_ERROR,
495
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
496
+ }
497
+}
498
+
499
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
500
+ unsigned int size)
501
+{
502
+ Stm32l4x5GpioState *s = opaque;
503
+
504
+ trace_stm32l4x5_gpio_read(s->name, addr);
505
+
506
+ switch (addr) {
507
+ case GPIO_MODER:
508
+ return s->moder;
509
+ case GPIO_OTYPER:
510
+ return s->otyper;
511
+ case GPIO_OSPEEDR:
512
+ return s->ospeedr;
513
+ case GPIO_PUPDR:
514
+ return s->pupdr;
515
+ case GPIO_IDR:
516
+ return s->idr;
517
+ case GPIO_ODR:
518
+ return s->odr;
519
+ case GPIO_BSRR:
243
+ return 0;
520
+ return 0;
244
+ case GPCLR0:
521
+ case GPIO_LCKR:
245
+ case GPCLR1:
522
+ return s->lckr;
246
+ /* Write Only */
523
+ case GPIO_AFRL:
524
+ return s->afrl;
525
+ case GPIO_AFRH:
526
+ return s->afrh;
527
+ case GPIO_BRR:
247
+ return 0;
528
+ return 0;
248
+ case GPLEV0:
529
+ case GPIO_ASCR:
249
+ return s->lev0;
530
+ return s->ascr;
250
+ case GPLEV1:
531
+ default:
251
+ return s->lev1;
532
+ qemu_log_mask(LOG_GUEST_ERROR,
252
+ case GPEDS0:
533
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
253
+ case GPEDS1:
254
+ case GPREN0:
255
+ case GPREN1:
256
+ case GPFEN0:
257
+ case GPFEN1:
258
+ case GPHEN0:
259
+ case GPHEN1:
260
+ case GPLEN0:
261
+ case GPLEN1:
262
+ case GPAREN0:
263
+ case GPAREN1:
264
+ case GPAFEN0:
265
+ case GPAFEN1:
266
+ case GPPUD:
267
+ case GPPUDCLK0:
268
+ case GPPUDCLK1:
269
+ /* Not implemented */
270
+ return 0;
534
+ return 0;
271
+ default:
535
+ }
272
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
536
+}
273
+ __func__, offset);
537
+
274
+ break;
538
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
275
+ }
539
+ .read = stm32l4x5_gpio_read,
276
+
540
+ .write = stm32l4x5_gpio_write,
277
+ return 0;
278
+}
279
+
280
+static void bcm2835_gpio_write(void *opaque, hwaddr offset,
281
+ uint64_t value, unsigned size)
282
+{
283
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
284
+
285
+ switch (offset) {
286
+ case GPFSEL0:
287
+ case GPFSEL1:
288
+ case GPFSEL2:
289
+ case GPFSEL3:
290
+ case GPFSEL4:
291
+ case GPFSEL5:
292
+ gpfsel_set(s, offset / 4, value);
293
+ break;
294
+ case GPSET0:
295
+ gpset(s, value, 0, 32, &s->lev0);
296
+ break;
297
+ case GPSET1:
298
+ gpset(s, value, 32, 22, &s->lev1);
299
+ break;
300
+ case GPCLR0:
301
+ gpclr(s, value, 0, 32, &s->lev0);
302
+ break;
303
+ case GPCLR1:
304
+ gpclr(s, value, 32, 22, &s->lev1);
305
+ break;
306
+ case GPLEV0:
307
+ case GPLEV1:
308
+ /* Read Only */
309
+ break;
310
+ case GPEDS0:
311
+ case GPEDS1:
312
+ case GPREN0:
313
+ case GPREN1:
314
+ case GPFEN0:
315
+ case GPFEN1:
316
+ case GPHEN0:
317
+ case GPHEN1:
318
+ case GPLEN0:
319
+ case GPLEN1:
320
+ case GPAREN0:
321
+ case GPAREN1:
322
+ case GPAFEN0:
323
+ case GPAFEN1:
324
+ case GPPUD:
325
+ case GPPUDCLK0:
326
+ case GPPUDCLK1:
327
+ /* Not implemented */
328
+ break;
329
+ default:
330
+ goto err_out;
331
+ }
332
+ return;
333
+
334
+err_out:
335
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
336
+ __func__, offset);
337
+}
338
+
339
+static void bcm2835_gpio_reset(DeviceState *dev)
340
+{
341
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
342
+
343
+ int i;
344
+ for (i = 0; i < 6; i++) {
345
+ gpfsel_set(s, i, 0);
346
+ }
347
+
348
+ s->sd_fsel = 0;
349
+
350
+ /* SDHCI is selected by default */
351
+ sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci);
352
+
353
+ s->lev0 = 0;
354
+ s->lev1 = 0;
355
+}
356
+
357
+static const MemoryRegionOps bcm2835_gpio_ops = {
358
+ .read = bcm2835_gpio_read,
359
+ .write = bcm2835_gpio_write,
360
+ .endianness = DEVICE_NATIVE_ENDIAN,
541
+ .endianness = DEVICE_NATIVE_ENDIAN,
542
+ .impl = {
543
+ .min_access_size = 4,
544
+ .max_access_size = 4,
545
+ .unaligned = false,
546
+ },
547
+ .valid = {
548
+ .min_access_size = 4,
549
+ .max_access_size = 4,
550
+ .unaligned = false,
551
+ },
361
+};
552
+};
362
+
553
+
363
+static const VMStateDescription vmstate_bcm2835_gpio = {
554
+static void stm32l4x5_gpio_init(Object *obj)
364
+ .name = "bcm2835_gpio",
555
+{
556
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
557
+
558
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
559
+ TYPE_STM32L4X5_GPIO, 0x400);
560
+
561
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
562
+
563
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
564
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
565
+
566
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
567
+
568
+ object_property_add(obj, "disconnected-pins", "uint16",
569
+ disconnected_pins_get, disconnected_pins_set,
570
+ NULL, &s->disconnected_pins);
571
+ object_property_add(obj, "clock-freq-hz", "uint32",
572
+ clock_freq_get, NULL, NULL, NULL);
573
+}
574
+
575
+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
576
+{
577
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
578
+ if (!clock_has_source(s->clk)) {
579
+ error_setg(errp, "GPIO: clk input must be connected");
580
+ return;
581
+ }
582
+}
583
+
584
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
585
+ .name = TYPE_STM32L4X5_GPIO,
365
+ .version_id = 1,
586
+ .version_id = 1,
366
+ .minimum_version_id = 1,
587
+ .minimum_version_id = 1,
367
+ .fields = (VMStateField[]) {
588
+ .fields = (VMStateField[]){
368
+ VMSTATE_UINT8_ARRAY(fsel, BCM2835GpioState, 54),
589
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
369
+ VMSTATE_UINT32(lev0, BCM2835GpioState),
590
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
370
+ VMSTATE_UINT32(lev1, BCM2835GpioState),
591
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
371
+ VMSTATE_UINT8(sd_fsel, BCM2835GpioState),
592
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
593
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
594
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
595
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
596
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
597
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
598
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
599
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
600
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
372
+ VMSTATE_END_OF_LIST()
601
+ VMSTATE_END_OF_LIST()
373
+ }
602
+ }
374
+};
603
+};
375
+
604
+
376
+static void bcm2835_gpio_init(Object *obj)
605
+static Property stm32l4x5_gpio_properties[] = {
377
+{
606
+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
378
+ BCM2835GpioState *s = BCM2835_GPIO(obj);
607
+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
379
+ DeviceState *dev = DEVICE(obj);
608
+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
380
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
609
+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
381
+
610
+ DEFINE_PROP_END_OF_LIST(),
382
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
611
+};
383
+ TYPE_SD_BUS, DEVICE(s), "sd-bus");
612
+
384
+
613
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
385
+ memory_region_init_io(&s->iomem, obj,
386
+ &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
387
+ sysbus_init_mmio(sbd, &s->iomem);
388
+ qdev_init_gpio_out(dev, s->out, 54);
389
+}
390
+
391
+static void bcm2835_gpio_realize(DeviceState *dev, Error **errp)
392
+{
393
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
394
+ Object *obj;
395
+ Error *err = NULL;
396
+
397
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhci", &err);
398
+ if (obj == NULL) {
399
+ error_setg(errp, "%s: required sdhci link not found: %s",
400
+ __func__, error_get_pretty(err));
401
+ return;
402
+ }
403
+ s->sdbus_sdhci = SD_BUS(obj);
404
+
405
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhost", &err);
406
+ if (obj == NULL) {
407
+ error_setg(errp, "%s: required sdhost link not found: %s",
408
+ __func__, error_get_pretty(err));
409
+ return;
410
+ }
411
+ s->sdbus_sdhost = SD_BUS(obj);
412
+}
413
+
414
+static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
415
+{
614
+{
416
+ DeviceClass *dc = DEVICE_CLASS(klass);
615
+ DeviceClass *dc = DEVICE_CLASS(klass);
417
+
616
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
418
+ dc->vmsd = &vmstate_bcm2835_gpio;
617
+
419
+ dc->realize = &bcm2835_gpio_realize;
618
+ device_class_set_props(dc, stm32l4x5_gpio_properties);
420
+ dc->reset = &bcm2835_gpio_reset;
619
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
421
+}
620
+ dc->realize = stm32l4x5_gpio_realize;
422
+
621
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
423
+static const TypeInfo bcm2835_gpio_info = {
622
+}
424
+ .name = TYPE_BCM2835_GPIO,
623
+
425
+ .parent = TYPE_SYS_BUS_DEVICE,
624
+static const TypeInfo stm32l4x5_gpio_types[] = {
426
+ .instance_size = sizeof(BCM2835GpioState),
625
+ {
427
+ .instance_init = bcm2835_gpio_init,
626
+ .name = TYPE_STM32L4X5_GPIO,
428
+ .class_init = bcm2835_gpio_class_init,
627
+ .parent = TYPE_SYS_BUS_DEVICE,
628
+ .instance_size = sizeof(Stm32l4x5GpioState),
629
+ .instance_init = stm32l4x5_gpio_init,
630
+ .class_init = stm32l4x5_gpio_class_init,
631
+ },
429
+};
632
+};
430
+
633
+
431
+static void bcm2835_gpio_register_types(void)
634
+DEFINE_TYPES(stm32l4x5_gpio_types)
432
+{
635
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
433
+ type_register_static(&bcm2835_gpio_info);
636
index XXXXXXX..XXXXXXX 100644
434
+}
637
--- a/hw/gpio/Kconfig
435
+
638
+++ b/hw/gpio/Kconfig
436
+type_init(bcm2835_gpio_register_types)
639
@@ -XXX,XX +XXX,XX @@ config GPIO_PWR
640
641
config SIFIVE_GPIO
642
bool
643
+
644
+config STM32L4X5_GPIO
645
+ bool
646
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
647
index XXXXXXX..XXXXXXX 100644
648
--- a/hw/gpio/meson.build
649
+++ b/hw/gpio/meson.build
650
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
651
'bcm2835_gpio.c',
652
'bcm2838_gpio.c'
653
))
654
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
655
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
656
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
657
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
658
index XXXXXXX..XXXXXXX 100644
659
--- a/hw/gpio/trace-events
660
+++ b/hw/gpio/trace-events
661
@@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
662
# aspeed_gpio.c
663
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
664
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
665
+
666
+# stm32l4x5_gpio.c
667
+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
668
+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
669
+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
670
+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
437
--
671
--
438
2.7.4
672
2.34.1
439
673
440
674
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/21] bcm2835: add sdhost and gpio controllers
[PULL 10/14] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform.
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
For supporting the SD controller selection (alternate function of GPIOs
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
48-53), the bcm2835_gpio now exposes an sdbus.
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
It also has a link to both the sdbus of sdhci and sdhost controllers,
7
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
8
and the card is reparented from one bus to another when the alternate
9
function of GPIOs 48-53 is modified.
10
11
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org
15
Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
9
---
19
include/hw/arm/bcm2835_peripherals.h | 4 ++++
10
include/hw/arm/stm32l4x5_soc.h | 2 +
20
hw/arm/bcm2835_peripherals.c | 43 ++++++++++++++++++++++++++++++++++--
11
include/hw/gpio/stm32l4x5_gpio.h | 1 +
21
2 files changed, 45 insertions(+), 2 deletions(-)
12
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
22
13
hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++-------
23
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
14
hw/misc/stm32l4x5_syscfg.c | 1 +
24
index XXXXXXX..XXXXXXX 100644
15
hw/arm/Kconfig | 3 +-
25
--- a/include/hw/arm/bcm2835_peripherals.h
16
6 files changed, 63 insertions(+), 18 deletions(-)
26
+++ b/include/hw/arm/bcm2835_peripherals.h
17
27
@@ -XXX,XX +XXX,XX @@
18
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
28
#include "hw/misc/bcm2835_rng.h"
19
index XXXXXXX..XXXXXXX 100644
29
#include "hw/misc/bcm2835_mbox.h"
20
--- a/include/hw/arm/stm32l4x5_soc.h
30
#include "hw/sd/sdhci.h"
21
+++ b/include/hw/arm/stm32l4x5_soc.h
31
+#include "hw/sd/bcm2835_sdhost.h"
22
@@ -XXX,XX +XXX,XX @@
32
+#include "hw/gpio/bcm2835_gpio.h"
23
#include "hw/misc/stm32l4x5_syscfg.h"
33
24
#include "hw/misc/stm32l4x5_exti.h"
34
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
25
#include "hw/misc/stm32l4x5_rcc.h"
35
#define BCM2835_PERIPHERALS(obj) \
26
+#include "hw/gpio/stm32l4x5_gpio.h"
36
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
27
#include "qom/object.h"
37
BCM2835RngState rng;
28
38
BCM2835MboxState mboxes;
29
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
39
SDHCIState sdhci;
30
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {
40
+ BCM2835SDHostState sdhost;
31
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
41
+ BCM2835GpioState gpio;
32
Stm32l4x5SyscfgState syscfg;
42
} BCM2835PeripheralState;
33
Stm32l4x5RccState rcc;
43
34
+ Stm32l4x5GpioState gpio[NUM_GPIOS];
44
#endif /* BCM2835_PERIPHERALS_H */
35
45
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
36
MemoryRegion sram1;
46
index XXXXXXX..XXXXXXX 100644
37
MemoryRegion sram2;
47
--- a/hw/arm/bcm2835_peripherals.c
38
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
48
+++ b/hw/arm/bcm2835_peripherals.c
39
index XXXXXXX..XXXXXXX 100644
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
40
--- a/include/hw/gpio/stm32l4x5_gpio.h
50
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
41
+++ b/include/hw/gpio/stm32l4x5_gpio.h
51
qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
42
@@ -XXX,XX +XXX,XX @@
52
43
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
53
+ /* SDHOST */
44
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
54
+ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
45
55
+ object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
46
+#define NUM_GPIOS 8
56
+ qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
47
#define GPIO_NUM_PINS 16
57
+
48
58
/* DMA Channels */
49
struct Stm32l4x5GpioState {
59
object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
50
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
60
object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
51
index XXXXXXX..XXXXXXX 100644
61
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
52
--- a/include/hw/misc/stm32l4x5_syscfg.h
62
53
+++ b/include/hw/misc/stm32l4x5_syscfg.h
63
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
54
@@ -XXX,XX +XXX,XX @@
64
OBJECT(&s->gpu_bus_mr), &error_abort);
55
65
+
56
#include "hw/sysbus.h"
66
+ /* GPIO */
57
#include "qom/object.h"
67
+ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
58
+#include "hw/gpio/stm32l4x5_gpio.h"
68
+ object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
59
69
+ qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
60
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
70
+
61
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
71
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
62
72
+ OBJECT(&s->sdhci.sdbus), &error_abort);
63
-#define NUM_GPIOS 8
73
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
64
-#define GPIO_NUM_PINS 16
74
+ OBJECT(&s->sdhost.sdbus), &error_abort);
65
#define SYSCFG_NUM_EXTICR 4
75
}
66
76
67
struct Stm32l4x5SyscfgState {
77
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
68
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
78
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
69
index XXXXXXX..XXXXXXX 100644
79
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
70
--- a/hw/arm/stm32l4x5_soc.c
80
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
71
+++ b/hw/arm/stm32l4x5_soc.c
81
INTERRUPT_ARASANSDIO));
72
@@ -XXX,XX +XXX,XX @@
82
- object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "sd-bus",
73
#include "sysemu/sysemu.h"
83
- &err);
74
#include "hw/or-irq.h"
84
+
75
#include "hw/arm/stm32l4x5_soc.h"
85
+ /* SDHOST */
76
+#include "hw/gpio/stm32l4x5_gpio.h"
86
+ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
77
#include "hw/qdev-clock.h"
87
if (err) {
78
#include "hw/misc/unimp.h"
88
error_propagate(errp, err);
79
89
return;
80
@@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {
90
}
81
16, 35, 36, 37, 38,
91
82
};
92
+ memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
83
93
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
84
+static const struct {
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
85
+ uint32_t addr;
95
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
86
+ uint32_t moder_reset;
96
+ INTERRUPT_SDIO));
87
+ uint32_t ospeedr_reset;
97
+
88
+ uint32_t pupdr_reset;
98
/* DMA Channels */
89
+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
99
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
90
+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
100
if (err) {
91
+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
101
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
92
+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
102
BCM2835_IC_GPU_IRQ,
93
+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
103
INTERRUPT_DMA0 + n));
94
+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
104
}
95
+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
105
+
96
+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
106
+ /* GPIO */
97
+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
107
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
98
+};
108
+ if (err) {
99
+
109
+ error_propagate(errp, err);
100
static void stm32l4x5_soc_initfn(Object *obj)
110
+ return;
101
{
111
+ }
102
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
112
+
103
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)
113
+ memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
104
}
114
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
105
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
115
+
106
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
116
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
107
+
117
+ &err);
108
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
118
+ if (err) {
109
+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
119
+ error_propagate(errp, err);
110
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
120
+ return;
121
+ }
111
+ }
122
}
112
}
123
113
124
static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
114
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
115
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
116
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
117
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
118
MemoryRegion *system_memory = get_system_memory();
119
- DeviceState *armv7m;
120
+ DeviceState *armv7m, *dev;
121
SysBusDevice *busdev;
122
+ uint32_t pin_index;
123
124
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
125
sc->flash_size, errp)) {
126
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
127
return;
128
}
129
130
+ /* GPIOs */
131
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
132
+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);
133
+ dev = DEVICE(&s->gpio[i]);
134
+ qdev_prop_set_string(dev, "name", name);
135
+ qdev_prop_set_uint32(dev, "mode-reset",
136
+ stm32l4x5_gpio_cfg[i].moder_reset);
137
+ qdev_prop_set_uint32(dev, "ospeed-reset",
138
+ stm32l4x5_gpio_cfg[i].ospeedr_reset);
139
+ qdev_prop_set_uint32(dev, "pupd-reset",
140
+ stm32l4x5_gpio_cfg[i].pupdr_reset);
141
+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);
142
+ g_free(name);
143
+ name = g_strdup_printf("gpio%c-out", 'a' + i);
144
+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
145
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
146
+ if (!sysbus_realize(busdev, errp)) {
147
+ return;
148
+ }
149
+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
150
+ }
151
+
152
/* System configuration controller */
153
busdev = SYS_BUS_DEVICE(&s->syscfg);
154
if (!sysbus_realize(busdev, errp)) {
155
return;
156
}
157
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
158
- /*
159
- * TODO: when the GPIO device is implemented, connect it
160
- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
161
- * GPIO_NUM_PINS.
162
- */
163
+
164
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
165
+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
166
+ pin_index = GPIO_NUM_PINS * i + j;
167
+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
168
+ qdev_get_gpio_in(DEVICE(&s->syscfg),
169
+ pin_index));
170
+ }
171
+ }
172
173
/* EXTI device */
174
busdev = SYS_BUS_DEVICE(&s->exti);
175
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
176
}
177
}
178
179
- for (unsigned i = 0; i < 16; i++) {
180
+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
181
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
182
qdev_get_gpio_in(DEVICE(&s->exti), i));
183
}
184
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
185
/* RESERVED: 0x40024400, 0x7FDBC00 */
186
187
/* AHB2 BUS */
188
- create_unimplemented_device("GPIOA", 0x48000000, 0x400);
189
- create_unimplemented_device("GPIOB", 0x48000400, 0x400);
190
- create_unimplemented_device("GPIOC", 0x48000800, 0x400);
191
- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
192
- create_unimplemented_device("GPIOE", 0x48001000, 0x400);
193
- create_unimplemented_device("GPIOF", 0x48001400, 0x400);
194
- create_unimplemented_device("GPIOG", 0x48001800, 0x400);
195
- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
196
/* RESERVED: 0x48002000, 0x7FDBC00 */
197
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
198
create_unimplemented_device("ADC", 0x50040000, 0x400);
199
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/misc/stm32l4x5_syscfg.c
202
+++ b/hw/misc/stm32l4x5_syscfg.c
203
@@ -XXX,XX +XXX,XX @@
204
#include "hw/irq.h"
205
#include "migration/vmstate.h"
206
#include "hw/misc/stm32l4x5_syscfg.h"
207
+#include "hw/gpio/stm32l4x5_gpio.h"
208
209
#define SYSCFG_MEMRMP 0x00
210
#define SYSCFG_CFGR1 0x04
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
212
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/arm/Kconfig
214
+++ b/hw/arm/Kconfig
215
@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC
216
bool
217
select ARM_V7M
218
select OR_IRQ
219
- select STM32L4X5_SYSCFG
220
select STM32L4X5_EXTI
221
+ select STM32L4X5_SYSCFG
222
select STM32L4X5_RCC
223
+ select STM32L4X5_GPIO
224
225
config XLNX_ZYNQMP_ARM
226
bool
125
--
227
--
126
2.7.4
228
2.34.1
127
229
128
230
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/21] armv7m: Move NVICState struct definition into header
[PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase
1
Move the NVICState struct definition into a header, so we can
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
embed it into other QOM objects like SoCs.
3
2
3
The testcase contains :
4
- `test_idr_reset_value()` :
5
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
6
- `test_gpio_output_mode()` :
7
Checks that writing a bit in register ODR results in the corresponding
8
pin rising or lowering, if this pin is configured in output mode.
9
- `test_gpio_input_mode()` :
10
Checks that a input pin set high or low externally results
11
in the pin rising and lowering.
12
- `test_pull_up_pull_down()` :
13
Checks that a floating pin in pull-up/down mode is actually high/down.
14
- `test_push_pull()` :
15
Checks that a pin set externally is disconnected when configured in
16
push-pull output mode, and can't be set externally while in this mode.
17
- `test_open_drain()` :
18
Checks that a pin set externally high is disconnected when configured
19
in open-drain output mode, and can't be set high while in this mode.
20
- `test_bsrr_brr()` :
21
Checks that writing to BSRR and BRR has the desired result in ODR.
22
- `test_clock_enable()` :
23
Checks that GPIO clock is at the right frequency after enabling it.
24
25
Acked-by: Thomas Huth <thuth@redhat.com>
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
28
Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
8
---
30
---
9
include/hw/arm/armv7m_nvic.h | 66 ++++++++++++++++++++++++++++++++++++++++++++
31
tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++
10
hw/intc/armv7m_nvic.c | 49 +-------------------------------
32
tests/qtest/meson.build | 3 +-
11
2 files changed, 67 insertions(+), 48 deletions(-)
33
2 files changed, 553 insertions(+), 1 deletion(-)
12
create mode 100644 include/hw/arm/armv7m_nvic.h
34
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
13
35
14
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
36
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
15
new file mode 100644
37
new file mode 100644
16
index XXXXXXX..XXXXXXX
38
index XXXXXXX..XXXXXXX
17
--- /dev/null
39
--- /dev/null
18
+++ b/include/hw/arm/armv7m_nvic.h
40
+++ b/tests/qtest/stm32l4x5_gpio-test.c
19
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
20
+/*
42
+/*
21
+ * ARMv7M NVIC object
43
+ * QTest testcase for STM32L4x5_GPIO
22
+ *
44
+ *
23
+ * Copyright (c) 2017 Linaro Ltd
45
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
24
+ * Written by Peter Maydell <peter.maydell@linaro.org>
46
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
25
+ *
47
+ *
26
+ * This code is licensed under the GPL version 2 or later.
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
49
+ * See the COPYING file in the top-level directory.
27
+ */
50
+ */
28
+
51
+
29
+#ifndef HW_ARM_ARMV7M_NVIC_H
52
+#include "qemu/osdep.h"
30
+#define HW_ARM_ARMV7M_NVIC_H
53
+#include "libqtest-single.h"
31
+
54
+
32
+#include "target/arm/cpu.h"
55
+#define GPIO_BASE_ADDR 0x48000000
33
+#include "hw/sysbus.h"
56
+#define GPIO_SIZE 0x400
34
+
57
+#define NUM_GPIOS 8
35
+#define TYPE_NVIC "armv7m_nvic"
58
+#define NUM_GPIO_PINS 16
36
+
59
+
37
+#define NVIC(obj) \
60
+#define GPIO_A 0x48000000
38
+ OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
61
+#define GPIO_B 0x48000400
39
+
62
+#define GPIO_C 0x48000800
40
+/* Highest permitted number of exceptions (architectural limit) */
63
+#define GPIO_D 0x48000C00
41
+#define NVIC_MAX_VECTORS 512
64
+#define GPIO_E 0x48001000
42
+
65
+#define GPIO_F 0x48001400
43
+typedef struct VecInfo {
66
+#define GPIO_G 0x48001800
44
+ /* Exception priorities can range from -3 to 255; only the unmodifiable
67
+#define GPIO_H 0x48001C00
45
+ * priority values for RESET, NMI and HardFault can be negative.
68
+
46
+ */
69
+#define MODER 0x00
47
+ int16_t prio;
70
+#define OTYPER 0x04
48
+ uint8_t enabled;
71
+#define PUPDR 0x0C
49
+ uint8_t pending;
72
+#define IDR 0x10
50
+ uint8_t active;
73
+#define ODR 0x14
51
+ uint8_t level; /* exceptions <=15 never set level */
74
+#define BSRR 0x18
52
+} VecInfo;
75
+#define BRR 0x28
53
+
76
+
54
+typedef struct NVICState {
77
+#define MODER_INPUT 0
55
+ /*< private >*/
78
+#define MODER_OUTPUT 1
56
+ SysBusDevice parent_obj;
79
+
57
+ /*< public >*/
80
+#define PUPDR_NONE 0
58
+
81
+#define PUPDR_PULLUP 1
59
+ ARMCPU *cpu;
82
+#define PUPDR_PULLDOWN 2
60
+
83
+
61
+ VecInfo vectors[NVIC_MAX_VECTORS];
84
+#define OTYPER_PUSH_PULL 0
62
+ uint32_t prigroup;
85
+#define OTYPER_OPEN_DRAIN 1
63
+
86
+
64
+ /* vectpending and exception_prio are both cached state that can
87
+const uint32_t moder_reset[NUM_GPIOS] = {
65
+ * be recalculated from the vectors[] array and the prigroup field.
88
+ 0xABFFFFFF,
66
+ */
89
+ 0xFFFFFEBF,
67
+ unsigned int vectpending; /* highest prio pending enabled exception */
90
+ 0xFFFFFFFF,
68
+ int exception_prio; /* group prio of the highest prio active exception */
91
+ 0xFFFFFFFF,
69
+
92
+ 0xFFFFFFFF,
70
+ struct {
93
+ 0xFFFFFFFF,
71
+ uint32_t control;
94
+ 0xFFFFFFFF,
72
+ uint32_t reload;
95
+ 0x0000000F
73
+ int64_t tick;
96
+};
74
+ QEMUTimer *timer;
97
+
75
+ } systick;
98
+const uint32_t pupdr_reset[NUM_GPIOS] = {
76
+
99
+ 0x64000000,
77
+ MemoryRegion sysregmem;
100
+ 0x00000100,
78
+ MemoryRegion container;
101
+ 0x00000000,
79
+
102
+ 0x00000000,
80
+ uint32_t num_irq;
103
+ 0x00000000,
81
+ qemu_irq excpout;
104
+ 0x00000000,
82
+ qemu_irq sysresetreq;
105
+ 0x00000000,
83
+} NVICState;
106
+ 0x00000000
84
+
107
+};
85
+#endif
108
+
86
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
109
+const uint32_t idr_reset[NUM_GPIOS] = {
110
+ 0x0000A000,
111
+ 0x00000010,
112
+ 0x00000000,
113
+ 0x00000000,
114
+ 0x00000000,
115
+ 0x00000000,
116
+ 0x00000000,
117
+ 0x00000000
118
+};
119
+
120
+static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
121
+{
122
+ return readl(gpio + offset);
123
+}
124
+
125
+static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
126
+{
127
+ writel(gpio + offset, value);
128
+}
129
+
130
+static void gpio_set_bit(unsigned int gpio, unsigned int reg,
131
+ unsigned int pin, uint32_t value)
132
+{
133
+ uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
134
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
135
+}
136
+
137
+static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
138
+ unsigned int pin, uint32_t value)
139
+{
140
+ uint32_t offset = 2 * pin;
141
+ uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
142
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
143
+}
144
+
145
+static unsigned int get_gpio_id(uint32_t gpio_addr)
146
+{
147
+ return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
148
+}
149
+
150
+static void gpio_set_irq(unsigned int gpio, int num, int level)
151
+{
152
+ g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
153
+ get_gpio_id(gpio) + 'a');
154
+ qtest_set_irq_in(global_qtest, name, NULL, num, level);
155
+}
156
+
157
+static void disconnect_all_pins(unsigned int gpio)
158
+{
159
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
160
+ get_gpio_id(gpio) + 'a');
161
+ QDict *r;
162
+
163
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
164
+ "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
165
+ path, 0xFFFF);
166
+ g_assert_false(qdict_haskey(r, "error"));
167
+ qobject_unref(r);
168
+}
169
+
170
+static uint32_t get_disconnected_pins(unsigned int gpio)
171
+{
172
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
173
+ get_gpio_id(gpio) + 'a');
174
+ uint32_t disconnected_pins = 0;
175
+ QDict *r;
176
+
177
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
178
+ " { 'path': %s, 'property': 'disconnected-pins'} }", path);
179
+ g_assert_false(qdict_haskey(r, "error"));
180
+ disconnected_pins = qdict_get_int(r, "return");
181
+ qobject_unref(r);
182
+ return disconnected_pins;
183
+}
184
+
185
+static uint32_t reset(uint32_t gpio, unsigned int offset)
186
+{
187
+ switch (offset) {
188
+ case MODER:
189
+ return moder_reset[get_gpio_id(gpio)];
190
+ case PUPDR:
191
+ return pupdr_reset[get_gpio_id(gpio)];
192
+ case IDR:
193
+ return idr_reset[get_gpio_id(gpio)];
194
+ }
195
+ return 0x0;
196
+}
197
+
198
+static void system_reset(void)
199
+{
200
+ QDict *r;
201
+ r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
202
+ g_assert_false(qdict_haskey(r, "error"));
203
+ qobject_unref(r);
204
+}
205
+
206
+static void test_idr_reset_value(void)
207
+{
208
+ /*
209
+ * Checks that the values in MODER, OTYPER, PUPDR and ODR
210
+ * after reset are correct, and that the value in IDR is
211
+ * coherent.
212
+ * Since AF and analog modes aren't implemented, IDR reset
213
+ * values aren't the same as with a real board.
214
+ *
215
+ * Register IDR contains the actual values of all GPIO pins.
216
+ * Its value depends on the pins' configuration
217
+ * (intput/output/analog : register MODER, push-pull/open-drain :
218
+ * register OTYPER, pull-up/pull-down/none : register PUPDR)
219
+ * and on the values stored in register ODR
220
+ * (in case the pin is in output mode).
221
+ */
222
+
223
+ gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
224
+ gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
225
+ gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
226
+ gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
227
+
228
+ gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
229
+ gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
230
+ gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
231
+ gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
232
+
233
+ gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
234
+ gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
235
+ gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
236
+ gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
237
+
238
+ gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
239
+ gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
240
+ gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
241
+ gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
242
+
243
+ system_reset();
244
+
245
+ uint32_t moder = gpio_readl(GPIO_A, MODER);
246
+ uint32_t odr = gpio_readl(GPIO_A, ODR);
247
+ uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
248
+ uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
249
+ uint32_t idr = gpio_readl(GPIO_A, IDR);
250
+ /* 15: AF, 14: AF, 13: AF, 12: Analog ... */
251
+ /* here AF is the same as Analog and Input mode */
252
+ g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
253
+ g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
254
+ g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
255
+ /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
256
+ g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
257
+ /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
258
+ g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
259
+
260
+ moder = gpio_readl(GPIO_B, MODER);
261
+ odr = gpio_readl(GPIO_B, ODR);
262
+ otyper = gpio_readl(GPIO_B, OTYPER);
263
+ pupdr = gpio_readl(GPIO_B, PUPDR);
264
+ idr = gpio_readl(GPIO_B, IDR);
265
+ /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
266
+ /* here AF is the same as Analog and Input mode */
267
+ g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
268
+ g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
269
+ g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
270
+ /* ... 5: neither, 4: pull-up, 3: neither ... */
271
+ g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
272
+ /* ... 5 : reset value, 4 : 1, 3 : reset value ... */
273
+ g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
274
+
275
+ moder = gpio_readl(GPIO_C, MODER);
276
+ odr = gpio_readl(GPIO_C, ODR);
277
+ otyper = gpio_readl(GPIO_C, OTYPER);
278
+ pupdr = gpio_readl(GPIO_C, PUPDR);
279
+ idr = gpio_readl(GPIO_C, IDR);
280
+ /* Analog, same as Input mode*/
281
+ g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
282
+ g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
283
+ g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
284
+ /* no pull-up or pull-down */
285
+ g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
286
+ /* reset value */
287
+ g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
288
+
289
+ moder = gpio_readl(GPIO_H, MODER);
290
+ odr = gpio_readl(GPIO_H, ODR);
291
+ otyper = gpio_readl(GPIO_H, OTYPER);
292
+ pupdr = gpio_readl(GPIO_H, PUPDR);
293
+ idr = gpio_readl(GPIO_H, IDR);
294
+ /* Analog, same as Input mode */
295
+ g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
296
+ g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
297
+ g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
298
+ /* no pull-up or pull-down */
299
+ g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
300
+ /* reset value */
301
+ g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
302
+}
303
+
304
+static void test_gpio_output_mode(const void *data)
305
+{
306
+ /*
307
+ * Checks that setting a bit in ODR sets the corresponding
308
+ * GPIO line high : it should set the right bit in IDR
309
+ * and send an irq to syscfg.
310
+ * Additionally, it checks that values written to ODR
311
+ * when not in output mode are stored and not discarded.
312
+ */
313
+ unsigned int pin = ((uint64_t)data) & 0xF;
314
+ uint32_t gpio = ((uint64_t)data) >> 32;
315
+ unsigned int gpio_id = get_gpio_id(gpio);
316
+
317
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
318
+
319
+ /* Set a bit in ODR and check nothing happens */
320
+ gpio_set_bit(gpio, ODR, pin, 1);
321
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
322
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
323
+
324
+ /* Configure the relevant line as output and check the pin is high */
325
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
326
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
327
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
328
+
329
+ /* Reset the bit in ODR and check the pin is low */
330
+ gpio_set_bit(gpio, ODR, pin, 0);
331
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
332
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
333
+
334
+ /* Clean the test */
335
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
336
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
337
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
338
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
339
+}
340
+
341
+static void test_gpio_input_mode(const void *data)
342
+{
343
+ /*
344
+ * Test that setting a line high/low externally sets the
345
+ * corresponding GPIO line high/low : it should set the
346
+ * right bit in IDR and send an irq to syscfg.
347
+ */
348
+ unsigned int pin = ((uint64_t)data) & 0xF;
349
+ uint32_t gpio = ((uint64_t)data) >> 32;
350
+ unsigned int gpio_id = get_gpio_id(gpio);
351
+
352
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
353
+
354
+ /* Configure a line as input, raise it, and check that the pin is high */
355
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
356
+ gpio_set_irq(gpio, pin, 1);
357
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
358
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
359
+
360
+ /* Lower the line and check that the pin is low */
361
+ gpio_set_irq(gpio, pin, 0);
362
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
363
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
364
+
365
+ /* Clean the test */
366
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
367
+ disconnect_all_pins(gpio);
368
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
369
+}
370
+
371
+static void test_pull_up_pull_down(const void *data)
372
+{
373
+ /*
374
+ * Test that a floating pin with pull-up sets the pin
375
+ * high and vice-versa.
376
+ */
377
+ unsigned int pin = ((uint64_t)data) & 0xF;
378
+ uint32_t gpio = ((uint64_t)data) >> 32;
379
+ unsigned int gpio_id = get_gpio_id(gpio);
380
+
381
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
382
+
383
+ /* Configure a line as input with pull-up, check the line is set high */
384
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
385
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
386
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
387
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
388
+
389
+ /* Configure the line with pull-down, check the line is low */
390
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
391
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
392
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
393
+
394
+ /* Clean the test */
395
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
396
+ gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
397
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
398
+}
399
+
400
+static void test_push_pull(const void *data)
401
+{
402
+ /*
403
+ * Test that configuring a line in push-pull output mode
404
+ * disconnects the pin, that the pin can't be set or reset
405
+ * externally afterwards.
406
+ */
407
+ unsigned int pin = ((uint64_t)data) & 0xF;
408
+ uint32_t gpio = ((uint64_t)data) >> 32;
409
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
410
+
411
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
412
+
413
+ /* Setting a line high externally, configuring it in push-pull output */
414
+ /* And checking the pin was disconnected */
415
+ gpio_set_irq(gpio, pin, 1);
416
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
417
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
418
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
419
+
420
+ /* Setting a line low externally, configuring it in push-pull output */
421
+ /* And checking the pin was disconnected */
422
+ gpio_set_irq(gpio2, pin, 0);
423
+ gpio_set_bit(gpio2, ODR, pin, 1);
424
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
425
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
426
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
427
+
428
+ /* Trying to set a push-pull output pin, checking it doesn't work */
429
+ gpio_set_irq(gpio, pin, 1);
430
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
431
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
432
+
433
+ /* Trying to reset a push-pull output pin, checking it doesn't work */
434
+ gpio_set_irq(gpio2, pin, 0);
435
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
436
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
437
+
438
+ /* Clean the test */
439
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
440
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
441
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
442
+}
443
+
444
+static void test_open_drain(const void *data)
445
+{
446
+ /*
447
+ * Test that configuring a line in open-drain output mode
448
+ * disconnects a pin set high externally and that the pin
449
+ * can't be set high externally while configured in open-drain.
450
+ *
451
+ * However a pin set low externally shouldn't be disconnected,
452
+ * and it can be set low externally when in open-drain mode.
453
+ */
454
+ unsigned int pin = ((uint64_t)data) & 0xF;
455
+ uint32_t gpio = ((uint64_t)data) >> 32;
456
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
457
+
458
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
459
+
460
+ /* Setting a line high externally, configuring it in open-drain output */
461
+ /* And checking the pin was disconnected */
462
+ gpio_set_irq(gpio, pin, 1);
463
+ gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
464
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
465
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
466
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
467
+
468
+ /* Setting a line low externally, configuring it in open-drain output */
469
+ /* And checking the pin wasn't disconnected */
470
+ gpio_set_irq(gpio2, pin, 0);
471
+ gpio_set_bit(gpio2, ODR, pin, 1);
472
+ gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
473
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
474
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
475
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
476
+ reset(gpio2, IDR) & ~(1 << pin));
477
+
478
+ /* Trying to set a open-drain output pin, checking it doesn't work */
479
+ gpio_set_irq(gpio, pin, 1);
480
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
481
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
482
+
483
+ /* Trying to reset a open-drain output pin, checking it works */
484
+ gpio_set_bit(gpio, ODR, pin, 1);
485
+ gpio_set_irq(gpio, pin, 0);
486
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
487
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
488
+ reset(gpio2, IDR) & ~(1 << pin));
489
+
490
+ /* Clean the test */
491
+ disconnect_all_pins(gpio2);
492
+ gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
493
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
494
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
495
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
496
+ disconnect_all_pins(gpio);
497
+ gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
498
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
499
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
500
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
501
+}
502
+
503
+static void test_bsrr_brr(const void *data)
504
+{
505
+ /*
506
+ * Test that writing a '1' in BSS and BSRR
507
+ * has the desired effect on ODR.
508
+ * In BSRR, BSx has priority over BRx.
509
+ */
510
+ unsigned int pin = ((uint64_t)data) & 0xF;
511
+ uint32_t gpio = ((uint64_t)data) >> 32;
512
+
513
+ gpio_writel(gpio, BSRR, (1 << pin));
514
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
515
+
516
+ gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
517
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
518
+
519
+ gpio_writel(gpio, BSRR, (1 << pin));
520
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
521
+
522
+ gpio_writel(gpio, BRR, (1 << pin));
523
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
524
+
525
+ /* BSx should have priority over BRx */
526
+ gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
527
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
528
+
529
+ gpio_writel(gpio, BRR, (1 << pin));
530
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
531
+
532
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
533
+}
534
+
535
+int main(int argc, char **argv)
536
+{
537
+ int ret;
538
+
539
+ g_test_init(&argc, &argv, NULL);
540
+ g_test_set_nonfatal_assertions();
541
+ qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
542
+ test_idr_reset_value);
543
+ /*
544
+ * The inputs for the tests (gpio and pin) can be changed,
545
+ * but the tests don't work for pins that are high at reset
546
+ * (GPIOA15, GPIO13 and GPIOB5).
547
+ * Specifically, rising the pin then checking `get_irq()`
548
+ * is problematic since the pin was already high.
549
+ */
550
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
551
+ (void *)((uint64_t)GPIO_C << 32 | 5),
552
+ test_gpio_output_mode);
553
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
554
+ (void *)((uint64_t)GPIO_H << 32 | 3),
555
+ test_gpio_output_mode);
556
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
557
+ (void *)((uint64_t)GPIO_D << 32 | 6),
558
+ test_gpio_input_mode);
559
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
560
+ (void *)((uint64_t)GPIO_C << 32 | 10),
561
+ test_gpio_input_mode);
562
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
563
+ (void *)((uint64_t)GPIO_B << 32 | 5),
564
+ test_pull_up_pull_down);
565
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
566
+ (void *)((uint64_t)GPIO_F << 32 | 1),
567
+ test_pull_up_pull_down);
568
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
569
+ (void *)((uint64_t)GPIO_G << 32 | 6),
570
+ test_push_pull);
571
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
572
+ (void *)((uint64_t)GPIO_H << 32 | 3),
573
+ test_push_pull);
574
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
575
+ (void *)((uint64_t)GPIO_C << 32 | 4),
576
+ test_open_drain);
577
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
578
+ (void *)((uint64_t)GPIO_E << 32 | 11),
579
+ test_open_drain);
580
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
581
+ (void *)((uint64_t)GPIO_A << 32 | 12),
582
+ test_bsrr_brr);
583
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
584
+ (void *)((uint64_t)GPIO_D << 32 | 0),
585
+ test_bsrr_brr);
586
+
587
+ qtest_start("-machine b-l475e-iot01a");
588
+ ret = g_test_run();
589
+ qtest_end();
590
+
591
+ return ret;
592
+}
593
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
87
index XXXXXXX..XXXXXXX 100644
594
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/intc/armv7m_nvic.c
595
--- a/tests/qtest/meson.build
89
+++ b/hw/intc/armv7m_nvic.c
596
+++ b/tests/qtest/meson.build
90
@@ -XXX,XX +XXX,XX @@
597
@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
91
#include "hw/sysbus.h"
598
qtests_stm32l4x5 = \
92
#include "qemu/timer.h"
599
['stm32l4x5_exti-test',
93
#include "hw/arm/arm.h"
600
'stm32l4x5_syscfg-test',
94
+#include "hw/arm/armv7m_nvic.h"
601
- 'stm32l4x5_rcc-test']
95
#include "target/arm/cpu.h"
602
+ 'stm32l4x5_rcc-test',
96
#include "exec/address-spaces.h"
603
+ 'stm32l4x5_gpio-test']
97
#include "qemu/log.h"
604
98
@@ -XXX,XX +XXX,XX @@
605
qtests_arm = \
99
* "exception" more or less interchangeably.
606
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
100
*/
101
#define NVIC_FIRST_IRQ 16
102
-#define NVIC_MAX_VECTORS 512
103
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
104
105
/* Effective running priority of the CPU when no exception is active
106
@@ -XXX,XX +XXX,XX @@
107
*/
108
#define NVIC_NOEXC_PRIO 0x100
109
110
-typedef struct VecInfo {
111
- /* Exception priorities can range from -3 to 255; only the unmodifiable
112
- * priority values for RESET, NMI and HardFault can be negative.
113
- */
114
- int16_t prio;
115
- uint8_t enabled;
116
- uint8_t pending;
117
- uint8_t active;
118
- uint8_t level; /* exceptions <=15 never set level */
119
-} VecInfo;
120
-
121
-typedef struct NVICState {
122
- /*< private >*/
123
- SysBusDevice parent_obj;
124
- /*< public >*/
125
-
126
- ARMCPU *cpu;
127
-
128
- VecInfo vectors[NVIC_MAX_VECTORS];
129
- uint32_t prigroup;
130
-
131
- /* vectpending and exception_prio are both cached state that can
132
- * be recalculated from the vectors[] array and the prigroup field.
133
- */
134
- unsigned int vectpending; /* highest prio pending enabled exception */
135
- int exception_prio; /* group prio of the highest prio active exception */
136
-
137
- struct {
138
- uint32_t control;
139
- uint32_t reload;
140
- int64_t tick;
141
- QEMUTimer *timer;
142
- } systick;
143
-
144
- MemoryRegion sysregmem;
145
- MemoryRegion container;
146
-
147
- uint32_t num_irq;
148
- qemu_irq excpout;
149
- qemu_irq sysresetreq;
150
-} NVICState;
151
-
152
-#define TYPE_NVIC "armv7m_nvic"
153
-
154
-#define NVIC(obj) \
155
- OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
156
-
157
static const uint8_t nvic_id[] = {
158
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
159
};
160
--
607
--
161
2.7.4
608
2.34.1
162
609
163
610
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/21] armv7m: Use QOMified armv7m object in armv7m_init()
Deleted patch
1
Make the legacy armv7m_init() function use the newly QOMified
2
armv7m object rather than doing everything by hand.
3
1
4
We can return the armv7m object rather than the NVIC from
5
armv7m_init() because its interface to the rest of the
6
board (GPIOs, etc) is identical.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487604965-23220-5-git-send-email-peter.maydell@linaro.org
12
---
13
hw/arm/armv7m.c | 49 ++++++++++++-------------------------------------
14
1 file changed, 12 insertions(+), 37 deletions(-)
15
16
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/armv7m.c
19
+++ b/hw/arm/armv7m.c
20
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
21
sysbus_init_mmio(dev, &s->iomem);
22
}
23
24
-static void armv7m_bitband_init(void)
25
-{
26
- DeviceState *dev;
27
-
28
- dev = qdev_create(NULL, TYPE_BITBAND);
29
- qdev_prop_set_uint32(dev, "base", 0x20000000);
30
- qdev_init_nofail(dev);
31
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
32
-
33
- dev = qdev_create(NULL, TYPE_BITBAND);
34
- qdev_prop_set_uint32(dev, "base", 0x40000000);
35
- qdev_init_nofail(dev);
36
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
37
-}
38
-
39
/* Board init. */
40
41
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
43
44
/* Init CPU and memory for a v7-M based board.
45
mem_size is in bytes.
46
- Returns the NVIC array. */
47
+ Returns the ARMv7M device. */
48
49
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
50
const char *kernel_filename, const char *cpu_model)
51
{
52
- ARMCPU *cpu;
53
- CPUARMState *env;
54
- DeviceState *nvic;
55
+ DeviceState *armv7m;
56
57
if (cpu_model == NULL) {
58
-    cpu_model = "cortex-m3";
59
+ cpu_model = "cortex-m3";
60
}
61
- cpu = cpu_arm_init(cpu_model);
62
- if (cpu == NULL) {
63
- fprintf(stderr, "Unable to find CPU definition\n");
64
- exit(1);
65
- }
66
- env = &cpu->env;
67
-
68
- armv7m_bitband_init();
69
-
70
- nvic = qdev_create(NULL, "armv7m_nvic");
71
- qdev_prop_set_uint32(nvic, "num-irq", num_irq);
72
- env->nvic = nvic;
73
- qdev_init_nofail(nvic);
74
- sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
75
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
76
- armv7m_load_kernel(cpu, kernel_filename, mem_size);
77
- return nvic;
78
+
79
+ armv7m = qdev_create(NULL, "armv7m");
80
+ qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
81
+ qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
82
+ /* This will exit with an error if the user passed us a bad cpu_model */
83
+ qdev_init_nofail(armv7m);
84
+
85
+ armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
86
+ return armv7m;
87
}
88
89
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
90
--
91
2.7.4
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/21] armv7m: Make NVIC expose a memory region rather than mapping itself
Deleted patch
1
Make the NVIC device expose a memory region for its users
2
to map, rather than mapping itself into the system memory
3
space on realize, and get the one user (the ARMv7M object)
4
to do this.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 1487604965-23220-7-git-send-email-peter.maydell@linaro.org
9
---
10
hw/arm/armv7m.c | 7 ++++++-
11
hw/intc/armv7m_nvic.c | 7 ++-----
12
2 files changed, 8 insertions(+), 6 deletions(-)
13
14
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/armv7m.c
17
+++ b/hw/arm/armv7m.c
18
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
19
static void armv7m_realize(DeviceState *dev, Error **errp)
20
{
21
ARMv7MState *s = ARMV7M(dev);
22
+ SysBusDevice *sbd;
23
Error *err = NULL;
24
int i;
25
char **cpustr;
26
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
27
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
28
29
/* Wire the NVIC up to the CPU */
30
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
31
+ sbd = SYS_BUS_DEVICE(&s->nvic);
32
+ sysbus_connect_irq(sbd, 0,
33
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
34
s->cpu->env.nvic = &s->nvic;
35
36
+ memory_region_add_subregion(&s->container, 0xe000e000,
37
+ sysbus_mmio_get_region(sbd, 0));
38
+
39
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
40
Object *obj = OBJECT(&s->bitband[i]);
41
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
42
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/intc/armv7m_nvic.c
45
+++ b/hw/intc/armv7m_nvic.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/arm/arm.h"
48
#include "hw/arm/armv7m_nvic.h"
49
#include "target/arm/cpu.h"
50
-#include "exec/address-spaces.h"
51
#include "qemu/log.h"
52
#include "trace.h"
53
54
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
55
"nvic_sysregs", 0x1000);
56
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
57
58
- /* Map the whole thing into system memory at the location required
59
- * by the v7M architecture.
60
- */
61
- memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
62
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
63
+
64
s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
65
}
66
67
--
68
2.7.4
69
70
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/21] armv7m: Don't put core v7M devices under CONFIG_STELLARIS
Deleted patch
1
The NVIC is a core v7M device that exists for all v7M CPUs;
2
put it under a CONFIG_ARM_V7M rather than hiding it under
3
CONFIG_STELLARIS.
4
1
5
(We'll use CONFIG_ARM_V7M for the SysTick device too
6
when we split it out of the NVIC.)
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
12
---
13
hw/intc/Makefile.objs | 2 +-
14
default-configs/arm-softmmu.mak | 2 ++
15
2 files changed, 3 insertions(+), 1 deletion(-)
16
17
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/Makefile.objs
20
+++ b/hw/intc/Makefile.objs
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_APIC) += apic.o apic_common.o
22
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
23
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
24
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
25
-obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
26
+obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o
27
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
28
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
29
obj-$(CONFIG_IOAPIC) += ioapic.o
30
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
31
index XXXXXXX..XXXXXXX 100644
32
--- a/default-configs/arm-softmmu.mak
33
+++ b/default-configs/arm-softmmu.mak
34
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM11MPCORE=y
35
CONFIG_A9MPCORE=y
36
CONFIG_A15MPCORE=y
37
38
+CONFIG_ARM_V7M=y
39
+
40
CONFIG_ARM_GIC=y
41
CONFIG_ARM_GIC_KVM=$(CONFIG_KVM)
42
CONFIG_ARM_TIMER=y
43
--
44
2.7.4
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
[PULL 12/14] target/arm: Fix 32-bit SMOPA
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reset CPU interface registers of GICv3 when CPU is reset.
3
While the 8-bit input elements are sequential in the input vector,
4
For this, ARMCPRegInfo struct is registered with one ICC
4
the 32-bit output elements are not sequential in the output matrix.
5
register whose resetfn is called when cpu is reset.
5
Do not attempt to compute 2 32-bit outputs at the same time.
6
6
7
All the ICC registers are reset under one single register
7
Cc: qemu-stable@nongnu.org
8
reset function instead of calling resetfn for each ICC
8
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
9
register.
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
10
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1487850673-26455-6-git-send-email-vijay.kilari@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
14
---
17
hw/intc/arm_gicv3_kvm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
15
target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++-------------
18
1 file changed, 60 insertions(+)
16
tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++
19
17
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++
20
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
18
tests/tcg/aarch64/Makefile.target | 2 +-
19
4 files changed, 147 insertions(+), 33 deletions(-)
20
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
21
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
22
23
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
21
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_kvm.c
25
--- a/target/arm/tcg/sme_helper.c
23
+++ b/hw/intc/arm_gicv3_kvm.c
26
+++ b/target/arm/tcg/sme_helper.c
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
25
}
28
}
26
}
29
}
27
30
28
+static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
31
-typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
32
+typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool);
33
+static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm,
34
+ uint8_t *pn, uint8_t *pm,
35
+ uint32_t desc, IMOPFn32 *fn)
29
+{
36
+{
30
+ ARMCPU *cpu;
37
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
31
+ GICv3State *s;
38
+ bool neg = simd_data(desc);
32
+ GICv3CPUState *c;
39
33
+
40
-static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
34
+ c = (GICv3CPUState *)env->gicv3state;
41
- uint8_t *pn, uint8_t *pm,
35
+ s = c->gic;
42
- uint32_t desc, IMOPFn *fn)
36
+ cpu = ARM_CPU(c->cpu);
43
+ for (row = 0; row < oprsz; ++row) {
37
+
44
+ uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf;
38
+ /* Initialize to actual HW supported configuration */
45
+ uint32_t *za_row = &za[tile_vslice_index(row)];
39
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
46
+ uint32_t n = zn[H4(row)];
40
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
47
+
41
+ &c->icc_ctlr_el1[GICV3_NS], false);
48
+ for (col = 0; col < oprsz; ++col) {
42
+
49
+ uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4);
43
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
50
+ uint32_t *a = &za_row[H4(col)];
44
+ c->icc_pmr_el1 = 0;
51
+
45
+ c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
52
+ *a = fn(n, zm[H4(col)], *a, pa & pb, neg);
46
+ c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
53
+ }
47
+ c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
54
+ }
48
+
49
+ c->icc_sre_el1 = 0x7;
50
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
51
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
52
+}
55
+}
53
+
56
+
54
static void kvm_arm_gicv3_reset(DeviceState *dev)
57
+typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool);
58
+static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm,
59
+ uint8_t *pn, uint8_t *pm,
60
+ uint32_t desc, IMOPFn64 *fn)
55
{
61
{
56
GICv3State *s = ARM_GICV3_COMMON(dev);
62
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
57
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
63
bool neg = simd_data(desc);
58
kvm_arm_gicv3_put(s);
64
@@ -XXX,XX +XXX,XX @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
59
}
65
}
60
66
61
+/*
67
#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
62
+ * CPU interface registers of GIC needs to be reset on CPU reset.
68
-static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
63
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
69
+static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \
64
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
70
{ \
65
+ * register reset, we define only one register of CPU interface instead
71
- uint32_t sum0 = 0, sum1 = 0; \
66
+ * of defining all the registers.
72
+ uint32_t sum = 0; \
67
+ */
73
/* Apply P to N as a mask, making the inactive elements 0. */ \
68
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
74
n &= expand_pred_b(p); \
69
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
75
- sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
70
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
76
- sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
71
+ /*
77
- sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
72
+ * If ARM_CP_NOP is used, resetfn is not called,
78
- sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
73
+ * So ARM_CP_NO_RAW is appropriate type.
79
- sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
74
+ */
80
- sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
75
+ .type = ARM_CP_NO_RAW,
81
- sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
76
+ .access = PL1_RW,
82
- sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
77
+ .readfn = arm_cp_read_zero,
83
- if (neg) { \
78
+ .writefn = arm_cp_write_ignore,
84
- sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
79
+ /*
85
- } else { \
80
+ * We hang the whole cpu interface reset routine off here
86
- sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
81
+ * rather than parcelling it out into one little function
87
- } \
82
+ * per register
88
- return ((uint64_t)sum1 << 32) | sum0; \
83
+ */
89
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
84
+ .resetfn = arm_gicv3_icc_reset,
90
+ sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
85
+ },
91
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
86
+ REGINFO_SENTINEL
92
+ sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
87
+};
93
+ return neg ? a - sum : a + sum; \
88
+
94
}
89
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
95
90
{
96
#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
91
GICv3State *s = KVM_ARM_GICV3(dev);
97
@@ -XXX,XX +XXX,XX @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
92
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
98
DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
93
99
DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
94
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
100
95
101
-#define DEF_IMOPH(NAME) \
96
+ for (i = 0; i < s->num_cpu; i++) {
102
- void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
97
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
103
- void *vpm, uint32_t desc) \
98
+
104
- { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
99
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
105
+#define DEF_IMOPH(NAME, S) \
100
+ }
106
+ void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \
101
+
107
+ void *vpn, void *vpm, uint32_t desc) \
102
/* Try to create the device via the device control API */
108
+ { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); }
103
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
109
104
if (s->dev_fd < 0) {
110
-DEF_IMOPH(smopa_s)
111
-DEF_IMOPH(umopa_s)
112
-DEF_IMOPH(sumopa_s)
113
-DEF_IMOPH(usmopa_s)
114
-DEF_IMOPH(smopa_d)
115
-DEF_IMOPH(umopa_d)
116
-DEF_IMOPH(sumopa_d)
117
-DEF_IMOPH(usmopa_d)
118
+DEF_IMOPH(smopa, s)
119
+DEF_IMOPH(umopa, s)
120
+DEF_IMOPH(sumopa, s)
121
+DEF_IMOPH(usmopa, s)
122
+
123
+DEF_IMOPH(smopa, d)
124
+DEF_IMOPH(umopa, d)
125
+DEF_IMOPH(sumopa, d)
126
+DEF_IMOPH(usmopa, d)
127
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
128
new file mode 100644
129
index XXXXXXX..XXXXXXX
130
--- /dev/null
131
+++ b/tests/tcg/aarch64/sme-smopa-1.c
132
@@ -XXX,XX +XXX,XX @@
133
+#include <stdio.h>
134
+#include <string.h>
135
+
136
+int main()
137
+{
138
+ static const int cmp[4][4] = {
139
+ { 110, 134, 158, 182 },
140
+ { 390, 478, 566, 654 },
141
+ { 670, 822, 974, 1126 },
142
+ { 950, 1166, 1382, 1598 }
143
+ };
144
+ int dst[4][4];
145
+ int *tmp = &dst[0][0];
146
+
147
+ asm volatile(
148
+ ".arch armv8-r+sme\n\t"
149
+ "smstart\n\t"
150
+ "index z0.b, #0, #1\n\t"
151
+ "movprfx z1, z0\n\t"
152
+ "add z1.b, z1.b, #16\n\t"
153
+ "ptrue p0.b\n\t"
154
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
155
+ "ptrue p0.s, vl4\n\t"
156
+ "mov w12, #0\n\t"
157
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
158
+ "add %0, %0, #16\n\t"
159
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
160
+ "add %0, %0, #16\n\t"
161
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
162
+ "add %0, %0, #16\n\t"
163
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
164
+ "smstop"
165
+ : "+r"(tmp) : : "memory");
166
+
167
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
168
+ return 0;
169
+ }
170
+
171
+ /* See above for correct results. */
172
+ for (int i = 0; i < 4; ++i) {
173
+ for (int j = 0; j < 4; ++j) {
174
+ printf("%6d", dst[i][j]);
175
+ }
176
+ printf("\n");
177
+ }
178
+ return 1;
179
+}
180
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
181
new file mode 100644
182
index XXXXXXX..XXXXXXX
183
--- /dev/null
184
+++ b/tests/tcg/aarch64/sme-smopa-2.c
185
@@ -XXX,XX +XXX,XX @@
186
+#include <stdio.h>
187
+#include <string.h>
188
+
189
+int main()
190
+{
191
+ static const long cmp[4][4] = {
192
+ { 110, 134, 158, 182 },
193
+ { 390, 478, 566, 654 },
194
+ { 670, 822, 974, 1126 },
195
+ { 950, 1166, 1382, 1598 }
196
+ };
197
+ long dst[4][4];
198
+ long *tmp = &dst[0][0];
199
+ long svl;
200
+
201
+ /* Validate that we have a wide enough vector for 4 elements. */
202
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
203
+ if (svl < 32) {
204
+ return 0;
205
+ }
206
+
207
+ asm volatile(
208
+ "smstart\n\t"
209
+ "index z0.h, #0, #1\n\t"
210
+ "movprfx z1, z0\n\t"
211
+ "add z1.h, z1.h, #16\n\t"
212
+ "ptrue p0.b\n\t"
213
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
214
+ "ptrue p0.d, vl4\n\t"
215
+ "mov w12, #0\n\t"
216
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
217
+ "add %0, %0, #32\n\t"
218
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
219
+ "mov w12, #2\n\t"
220
+ "add %0, %0, #32\n\t"
221
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
222
+ "add %0, %0, #32\n\t"
223
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
224
+ "smstop"
225
+ : "+r"(tmp) : : "memory");
226
+
227
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
228
+ return 0;
229
+ }
230
+
231
+ /* See above for correct results. */
232
+ for (int i = 0; i < 4; ++i) {
233
+ for (int j = 0; j < 4; ++j) {
234
+ printf("%6ld", dst[i][j]);
235
+ }
236
+ printf("\n");
237
+ }
238
+ return 1;
239
+}
240
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
241
index XXXXXXX..XXXXXXX 100644
242
--- a/tests/tcg/aarch64/Makefile.target
243
+++ b/tests/tcg/aarch64/Makefile.target
244
@@ -XXX,XX +XXX,XX @@ endif
245
246
# SME Tests
247
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
248
-AARCH64_TESTS += sme-outprod1
249
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
250
endif
251
252
# System Registers Tests
105
--
253
--
106
2.7.4
254
2.34.1
107
255
108
256
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/21] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
[PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
2
was unfortunately added with a license of GPL-v3-or-later, which is
3
not compatible with other QEMU code which has a GPL-v2-only license.
2
4
3
To Save and Restore ICC_SRE_EL1 register introduce vmstate
5
Relicense the code in the .c and the .h file to GPL-v2-or-later,
4
subsection and load only if non-zero.
6
to make it compatible with the rest of QEMU.
5
Also initialize icc_sre_el1 with to 0x7 in pre_load
6
function.
7
7
8
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
8
Cc: qemu-stable@nongnu.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com>
11
Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com
11
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
12
Signed-off-by: Markus Armbruster <armbru@redhat.com>
13
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
16
Acked-by: Alex Bennée <alex.bennee@linaro.org>
17
Message-id: 20240223161300.938542-1-peter.maydell@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
19
---
14
include/hw/intc/arm_gicv3_common.h | 1 +
20
include/hw/rtc/sun4v-rtc.h | 2 +-
15
hw/intc/arm_gicv3_common.c | 36 ++++++++++++++++++++++++++++++++++++
21
hw/rtc/sun4v-rtc.c | 2 +-
16
2 files changed, 37 insertions(+)
22
2 files changed, 2 insertions(+), 2 deletions(-)
17
23
18
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
24
diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/arm_gicv3_common.h
26
--- a/include/hw/rtc/sun4v-rtc.h
21
+++ b/include/hw/intc/arm_gicv3_common.h
27
+++ b/include/hw/rtc/sun4v-rtc.h
22
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
28
@@ -XXX,XX +XXX,XX @@
23
uint8_t gicr_ipriorityr[GIC_INTERNAL];
29
*
24
30
* Copyright (c) 2016 Artyom Tarasenko
25
/* CPU interface */
31
*
26
+ uint64_t icc_sre_el1;
32
- * This code is licensed under the GNU GPL v3 or (at your option) any later
27
uint64_t icc_ctlr_el1[2];
33
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
28
uint64_t icc_pmr_el1;
34
* version.
29
uint64_t icc_bpr[3];
35
*/
30
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
36
37
diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c
31
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_common.c
39
--- a/hw/rtc/sun4v-rtc.c
33
+++ b/hw/intc/arm_gicv3_common.c
40
+++ b/hw/rtc/sun4v-rtc.c
34
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu_virt = {
41
@@ -XXX,XX +XXX,XX @@
35
}
42
*
36
};
43
* Copyright (c) 2016 Artyom Tarasenko
37
44
*
38
+static int icc_sre_el1_reg_pre_load(void *opaque)
45
- * This code is licensed under the GNU GPL v3 or (at your option) any later
39
+{
46
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
40
+ GICv3CPUState *cs = opaque;
47
* version.
41
+
48
*/
42
+ /*
43
+ * If the sre_el1 subsection is not transferred this
44
+ * means SRE_EL1 is 0x7 (which might not be the same as
45
+ * our reset value).
46
+ */
47
+ cs->icc_sre_el1 = 0x7;
48
+ return 0;
49
+}
50
+
51
+static bool icc_sre_el1_reg_needed(void *opaque)
52
+{
53
+ GICv3CPUState *cs = opaque;
54
+
55
+ return cs->icc_sre_el1 != 7;
56
+}
57
+
58
+const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
59
+ .name = "arm_gicv3_cpu/sre_el1",
60
+ .version_id = 1,
61
+ .minimum_version_id = 1,
62
+ .pre_load = icc_sre_el1_reg_pre_load,
63
+ .needed = icc_sre_el1_reg_needed,
64
+ .fields = (VMStateField[]) {
65
+ VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
66
+ VMSTATE_END_OF_LIST()
67
+ }
68
+};
69
+
70
static const VMStateDescription vmstate_gicv3_cpu = {
71
.name = "arm_gicv3_cpu",
72
.version_id = 1,
73
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
74
.subsections = (const VMStateDescription * []) {
75
&vmstate_gicv3_cpu_virt,
76
NULL
77
+ },
78
+ .subsections = (const VMStateDescription * []) {
79
+ &vmstate_gicv3_cpu_sre_el1,
80
+ NULL
81
}
82
};
83
49
84
--
50
--
85
2.7.4
51
2.34.1
86
52
87
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/21] armv7m: Split systick out from NVIC
[PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file
1
The SysTick timer isn't really part of the NVIC proper;
1
From: Thomas Huth <thuth@redhat.com>
2
we just modelled it that way back when we couldn't
3
easily have devices that only occupied a small chunk
4
of a memory region. Split it out into its own device.
5
2
3
Move the code to a separate file so that we do not have to compile
4
it anymore if CONFIG_ARM_V7M is not set.
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Message-id: 20240308141051.536599-2-thuth@redhat.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
---
10
---
10
hw/timer/Makefile.objs | 1 +
11
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++
11
include/hw/arm/armv7m_nvic.h | 10 +-
12
target/arm/tcg/cpu32.c | 261 ---------------------------------
12
include/hw/timer/armv7m_systick.h | 34 ++++++
13
target/arm/meson.build | 3 +
13
hw/intc/armv7m_nvic.c | 160 ++++++-------------------
14
target/arm/tcg/meson.build | 3 +
14
hw/timer/armv7m_systick.c | 240 ++++++++++++++++++++++++++++++++++++++
15
4 files changed, 296 insertions(+), 261 deletions(-)
15
hw/timer/trace-events | 6 +
16
create mode 100644 target/arm/tcg/cpu-v7m.c
16
6 files changed, 318 insertions(+), 133 deletions(-)
17
create mode 100644 include/hw/timer/armv7m_systick.h
18
create mode 100644 hw/timer/armv7m_systick.c
19
17
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
18
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
23
+++ b/hw/timer/Makefile.objs
24
@@ -XXX,XX +XXX,XX @@
25
common-obj-$(CONFIG_ARM_TIMER) += arm_timer.o
26
common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
27
+common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o
28
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
29
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
30
common-obj-$(CONFIG_DS1338) += ds1338.o
31
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armv7m_nvic.h
34
+++ b/include/hw/arm/armv7m_nvic.h
35
@@ -XXX,XX +XXX,XX @@
36
37
#include "target/arm/cpu.h"
38
#include "hw/sysbus.h"
39
+#include "hw/timer/armv7m_systick.h"
40
41
#define TYPE_NVIC "armv7m_nvic"
42
43
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
44
unsigned int vectpending; /* highest prio pending enabled exception */
45
int exception_prio; /* group prio of the highest prio active exception */
46
47
- struct {
48
- uint32_t control;
49
- uint32_t reload;
50
- int64_t tick;
51
- QEMUTimer *timer;
52
- } systick;
53
-
54
MemoryRegion sysregmem;
55
MemoryRegion container;
56
57
uint32_t num_irq;
58
qemu_irq excpout;
59
qemu_irq sysresetreq;
60
+
61
+ SysTickState systick;
62
} NVICState;
63
64
#endif
65
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
66
new file mode 100644
19
new file mode 100644
67
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
68
--- /dev/null
21
--- /dev/null
69
+++ b/include/hw/timer/armv7m_systick.h
22
+++ b/target/arm/tcg/cpu-v7m.c
70
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
71
+/*
24
+/*
72
+ * ARMv7M SysTick timer
25
+ * QEMU ARMv7-M TCG-only CPUs.
73
+ *
26
+ *
74
+ * Copyright (c) 2006-2007 CodeSourcery.
27
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
75
+ * Written by Paul Brook
76
+ * Copyright (c) 2017 Linaro Ltd
77
+ * Written by Peter Maydell
78
+ *
28
+ *
79
+ * This code is licensed under the GPL (version 2 or later).
29
+ * This code is licensed under the GNU GPL v2 or later.
30
+ *
31
+ * SPDX-License-Identifier: GPL-2.0-or-later
80
+ */
32
+ */
81
+
33
+
82
+#ifndef HW_TIMER_ARMV7M_SYSTICK_H
34
+#include "qemu/osdep.h"
83
+#define HW_TIMER_ARMV7M_SYSTICK_H
35
+#include "cpu.h"
84
+
36
+#include "hw/core/tcg-cpu-ops.h"
85
+#include "hw/sysbus.h"
37
+#include "internals.h"
86
+
38
+
87
+#define TYPE_SYSTICK "armv7m_systick"
39
+#if !defined(CONFIG_USER_ONLY)
88
+
40
+
89
+#define SYSTICK(obj) OBJECT_CHECK(SysTickState, (obj), TYPE_SYSTICK)
41
+#include "hw/intc/armv7m_nvic.h"
90
+
42
+
91
+typedef struct SysTickState {
43
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
92
+ /*< private >*/
44
+{
93
+ SysBusDevice parent_obj;
45
+ CPUClass *cc = CPU_GET_CLASS(cs);
94
+ /*< public >*/
46
+ ARMCPU *cpu = ARM_CPU(cs);
95
+
47
+ CPUARMState *env = &cpu->env;
96
+ uint32_t control;
48
+ bool ret = false;
97
+ uint32_t reload;
49
+
98
+ int64_t tick;
50
+ /*
99
+ QEMUTimer *timer;
51
+ * ARMv7-M interrupt masking works differently than -A or -R.
100
+ MemoryRegion iomem;
52
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
101
+ qemu_irq irq;
53
+ * masking FIQ and IRQ interrupts, an exception is taken only
102
+} SysTickState;
54
+ * if it is higher priority than the current execution priority
103
+
55
+ * (which depends on state like BASEPRI, FAULTMASK and the
104
+#endif
56
+ * currently active exception).
105
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
57
+ */
58
+ if (interrupt_request & CPU_INTERRUPT_HARD
59
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
60
+ cs->exception_index = EXCP_IRQ;
61
+ cc->tcg_ops->do_interrupt(cs);
62
+ ret = true;
63
+ }
64
+ return ret;
65
+}
66
+
67
+#endif /* !CONFIG_USER_ONLY */
68
+
69
+static void cortex_m0_initfn(Object *obj)
70
+{
71
+ ARMCPU *cpu = ARM_CPU(obj);
72
+ set_feature(&cpu->env, ARM_FEATURE_V6);
73
+ set_feature(&cpu->env, ARM_FEATURE_M);
74
+
75
+ cpu->midr = 0x410cc200;
76
+
77
+ /*
78
+ * These ID register values are not guest visible, because
79
+ * we do not implement the Main Extension. They must be set
80
+ * to values corresponding to the Cortex-M0's implemented
81
+ * features, because QEMU generally controls its emulation
82
+ * by looking at ID register fields. We use the same values as
83
+ * for the M3.
84
+ */
85
+ cpu->isar.id_pfr0 = 0x00000030;
86
+ cpu->isar.id_pfr1 = 0x00000200;
87
+ cpu->isar.id_dfr0 = 0x00100000;
88
+ cpu->id_afr0 = 0x00000000;
89
+ cpu->isar.id_mmfr0 = 0x00000030;
90
+ cpu->isar.id_mmfr1 = 0x00000000;
91
+ cpu->isar.id_mmfr2 = 0x00000000;
92
+ cpu->isar.id_mmfr3 = 0x00000000;
93
+ cpu->isar.id_isar0 = 0x01141110;
94
+ cpu->isar.id_isar1 = 0x02111000;
95
+ cpu->isar.id_isar2 = 0x21112231;
96
+ cpu->isar.id_isar3 = 0x01111110;
97
+ cpu->isar.id_isar4 = 0x01310102;
98
+ cpu->isar.id_isar5 = 0x00000000;
99
+ cpu->isar.id_isar6 = 0x00000000;
100
+}
101
+
102
+static void cortex_m3_initfn(Object *obj)
103
+{
104
+ ARMCPU *cpu = ARM_CPU(obj);
105
+ set_feature(&cpu->env, ARM_FEATURE_V7);
106
+ set_feature(&cpu->env, ARM_FEATURE_M);
107
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
108
+ cpu->midr = 0x410fc231;
109
+ cpu->pmsav7_dregion = 8;
110
+ cpu->isar.id_pfr0 = 0x00000030;
111
+ cpu->isar.id_pfr1 = 0x00000200;
112
+ cpu->isar.id_dfr0 = 0x00100000;
113
+ cpu->id_afr0 = 0x00000000;
114
+ cpu->isar.id_mmfr0 = 0x00000030;
115
+ cpu->isar.id_mmfr1 = 0x00000000;
116
+ cpu->isar.id_mmfr2 = 0x00000000;
117
+ cpu->isar.id_mmfr3 = 0x00000000;
118
+ cpu->isar.id_isar0 = 0x01141110;
119
+ cpu->isar.id_isar1 = 0x02111000;
120
+ cpu->isar.id_isar2 = 0x21112231;
121
+ cpu->isar.id_isar3 = 0x01111110;
122
+ cpu->isar.id_isar4 = 0x01310102;
123
+ cpu->isar.id_isar5 = 0x00000000;
124
+ cpu->isar.id_isar6 = 0x00000000;
125
+}
126
+
127
+static void cortex_m4_initfn(Object *obj)
128
+{
129
+ ARMCPU *cpu = ARM_CPU(obj);
130
+
131
+ set_feature(&cpu->env, ARM_FEATURE_V7);
132
+ set_feature(&cpu->env, ARM_FEATURE_M);
133
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
134
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
135
+ cpu->midr = 0x410fc240; /* r0p0 */
136
+ cpu->pmsav7_dregion = 8;
137
+ cpu->isar.mvfr0 = 0x10110021;
138
+ cpu->isar.mvfr1 = 0x11000011;
139
+ cpu->isar.mvfr2 = 0x00000000;
140
+ cpu->isar.id_pfr0 = 0x00000030;
141
+ cpu->isar.id_pfr1 = 0x00000200;
142
+ cpu->isar.id_dfr0 = 0x00100000;
143
+ cpu->id_afr0 = 0x00000000;
144
+ cpu->isar.id_mmfr0 = 0x00000030;
145
+ cpu->isar.id_mmfr1 = 0x00000000;
146
+ cpu->isar.id_mmfr2 = 0x00000000;
147
+ cpu->isar.id_mmfr3 = 0x00000000;
148
+ cpu->isar.id_isar0 = 0x01141110;
149
+ cpu->isar.id_isar1 = 0x02111000;
150
+ cpu->isar.id_isar2 = 0x21112231;
151
+ cpu->isar.id_isar3 = 0x01111110;
152
+ cpu->isar.id_isar4 = 0x01310102;
153
+ cpu->isar.id_isar5 = 0x00000000;
154
+ cpu->isar.id_isar6 = 0x00000000;
155
+}
156
+
157
+static void cortex_m7_initfn(Object *obj)
158
+{
159
+ ARMCPU *cpu = ARM_CPU(obj);
160
+
161
+ set_feature(&cpu->env, ARM_FEATURE_V7);
162
+ set_feature(&cpu->env, ARM_FEATURE_M);
163
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
164
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
165
+ cpu->midr = 0x411fc272; /* r1p2 */
166
+ cpu->pmsav7_dregion = 8;
167
+ cpu->isar.mvfr0 = 0x10110221;
168
+ cpu->isar.mvfr1 = 0x12000011;
169
+ cpu->isar.mvfr2 = 0x00000040;
170
+ cpu->isar.id_pfr0 = 0x00000030;
171
+ cpu->isar.id_pfr1 = 0x00000200;
172
+ cpu->isar.id_dfr0 = 0x00100000;
173
+ cpu->id_afr0 = 0x00000000;
174
+ cpu->isar.id_mmfr0 = 0x00100030;
175
+ cpu->isar.id_mmfr1 = 0x00000000;
176
+ cpu->isar.id_mmfr2 = 0x01000000;
177
+ cpu->isar.id_mmfr3 = 0x00000000;
178
+ cpu->isar.id_isar0 = 0x01101110;
179
+ cpu->isar.id_isar1 = 0x02112000;
180
+ cpu->isar.id_isar2 = 0x20232231;
181
+ cpu->isar.id_isar3 = 0x01111131;
182
+ cpu->isar.id_isar4 = 0x01310132;
183
+ cpu->isar.id_isar5 = 0x00000000;
184
+ cpu->isar.id_isar6 = 0x00000000;
185
+}
186
+
187
+static void cortex_m33_initfn(Object *obj)
188
+{
189
+ ARMCPU *cpu = ARM_CPU(obj);
190
+
191
+ set_feature(&cpu->env, ARM_FEATURE_V8);
192
+ set_feature(&cpu->env, ARM_FEATURE_M);
193
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
194
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
195
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
196
+ cpu->midr = 0x410fd213; /* r0p3 */
197
+ cpu->pmsav7_dregion = 16;
198
+ cpu->sau_sregion = 8;
199
+ cpu->isar.mvfr0 = 0x10110021;
200
+ cpu->isar.mvfr1 = 0x11000011;
201
+ cpu->isar.mvfr2 = 0x00000040;
202
+ cpu->isar.id_pfr0 = 0x00000030;
203
+ cpu->isar.id_pfr1 = 0x00000210;
204
+ cpu->isar.id_dfr0 = 0x00200000;
205
+ cpu->id_afr0 = 0x00000000;
206
+ cpu->isar.id_mmfr0 = 0x00101F40;
207
+ cpu->isar.id_mmfr1 = 0x00000000;
208
+ cpu->isar.id_mmfr2 = 0x01000000;
209
+ cpu->isar.id_mmfr3 = 0x00000000;
210
+ cpu->isar.id_isar0 = 0x01101110;
211
+ cpu->isar.id_isar1 = 0x02212000;
212
+ cpu->isar.id_isar2 = 0x20232232;
213
+ cpu->isar.id_isar3 = 0x01111131;
214
+ cpu->isar.id_isar4 = 0x01310132;
215
+ cpu->isar.id_isar5 = 0x00000000;
216
+ cpu->isar.id_isar6 = 0x00000000;
217
+ cpu->clidr = 0x00000000;
218
+ cpu->ctr = 0x8000c000;
219
+}
220
+
221
+static void cortex_m55_initfn(Object *obj)
222
+{
223
+ ARMCPU *cpu = ARM_CPU(obj);
224
+
225
+ set_feature(&cpu->env, ARM_FEATURE_V8);
226
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
227
+ set_feature(&cpu->env, ARM_FEATURE_M);
228
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
229
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
230
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
231
+ cpu->midr = 0x410fd221; /* r0p1 */
232
+ cpu->revidr = 0;
233
+ cpu->pmsav7_dregion = 16;
234
+ cpu->sau_sregion = 8;
235
+ /* These are the MVFR* values for the FPU + full MVE configuration */
236
+ cpu->isar.mvfr0 = 0x10110221;
237
+ cpu->isar.mvfr1 = 0x12100211;
238
+ cpu->isar.mvfr2 = 0x00000040;
239
+ cpu->isar.id_pfr0 = 0x20000030;
240
+ cpu->isar.id_pfr1 = 0x00000230;
241
+ cpu->isar.id_dfr0 = 0x10200000;
242
+ cpu->id_afr0 = 0x00000000;
243
+ cpu->isar.id_mmfr0 = 0x00111040;
244
+ cpu->isar.id_mmfr1 = 0x00000000;
245
+ cpu->isar.id_mmfr2 = 0x01000000;
246
+ cpu->isar.id_mmfr3 = 0x00000011;
247
+ cpu->isar.id_isar0 = 0x01103110;
248
+ cpu->isar.id_isar1 = 0x02212000;
249
+ cpu->isar.id_isar2 = 0x20232232;
250
+ cpu->isar.id_isar3 = 0x01111131;
251
+ cpu->isar.id_isar4 = 0x01310132;
252
+ cpu->isar.id_isar5 = 0x00000000;
253
+ cpu->isar.id_isar6 = 0x00000000;
254
+ cpu->clidr = 0x00000000; /* caches not implemented */
255
+ cpu->ctr = 0x8303c003;
256
+}
257
+
258
+static const TCGCPUOps arm_v7m_tcg_ops = {
259
+ .initialize = arm_translate_init,
260
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
261
+ .debug_excp_handler = arm_debug_excp_handler,
262
+ .restore_state_to_opc = arm_restore_state_to_opc,
263
+
264
+#ifdef CONFIG_USER_ONLY
265
+ .record_sigsegv = arm_cpu_record_sigsegv,
266
+ .record_sigbus = arm_cpu_record_sigbus,
267
+#else
268
+ .tlb_fill = arm_cpu_tlb_fill,
269
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
270
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
271
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
272
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
273
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
274
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
275
+ .debug_check_breakpoint = arm_debug_check_breakpoint,
276
+#endif /* !CONFIG_USER_ONLY */
277
+};
278
+
279
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
280
+{
281
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
282
+ CPUClass *cc = CPU_CLASS(oc);
283
+
284
+ acc->info = data;
285
+ cc->tcg_ops = &arm_v7m_tcg_ops;
286
+ cc->gdb_core_xml_file = "arm-m-profile.xml";
287
+}
288
+
289
+static const ARMCPUInfo arm_v7m_cpus[] = {
290
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
291
+ .class_init = arm_v7m_class_init },
292
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
293
+ .class_init = arm_v7m_class_init },
294
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
295
+ .class_init = arm_v7m_class_init },
296
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
297
+ .class_init = arm_v7m_class_init },
298
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
299
+ .class_init = arm_v7m_class_init },
300
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
301
+ .class_init = arm_v7m_class_init },
302
+};
303
+
304
+static void arm_v7m_cpu_register_types(void)
305
+{
306
+ size_t i;
307
+
308
+ for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
309
+ arm_cpu_register(&arm_v7m_cpus[i]);
310
+ }
311
+}
312
+
313
+type_init(arm_v7m_cpu_register_types)
314
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
106
index XXXXXXX..XXXXXXX 100644
315
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/intc/armv7m_nvic.c
316
--- a/target/arm/tcg/cpu32.c
108
+++ b/hw/intc/armv7m_nvic.c
317
+++ b/target/arm/tcg/cpu32.c
109
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
318
@@ -XXX,XX +XXX,XX @@
110
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
319
#include "hw/boards.h"
111
};
320
#endif
112
321
#include "cpregs.h"
113
-/* qemu timers run at 1GHz. We want something closer to 1MHz. */
322
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
114
-#define SYSTICK_SCALE 1000ULL
323
-#include "hw/intc/armv7m_nvic.h"
115
-
324
-#endif
116
-#define SYSTICK_ENABLE (1 << 0)
325
117
-#define SYSTICK_TICKINT (1 << 1)
326
118
-#define SYSTICK_CLKSOURCE (1 << 2)
327
/* Share AArch32 -cpu max features with AArch64. */
119
-#define SYSTICK_COUNTFLAG (1 << 16)
328
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
120
-
329
/* CPU models. These are not needed for the AArch64 linux-user build. */
121
-int system_clock_scale;
330
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
122
-
331
123
-/* Conversion factor from qemu timer to SysTick frequencies. */
332
-#if !defined(CONFIG_USER_ONLY)
124
-static inline int64_t systick_scale(NVICState *s)
333
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
125
-{
334
-{
126
- if (s->systick.control & SYSTICK_CLKSOURCE)
335
- CPUClass *cc = CPU_GET_CLASS(cs);
127
- return system_clock_scale;
336
- ARMCPU *cpu = ARM_CPU(cs);
128
- else
337
- CPUARMState *env = &cpu->env;
129
- return 1000;
338
- bool ret = false;
130
-}
339
-
131
-
340
- /*
132
-static void systick_reload(NVICState *s, int reset)
341
- * ARMv7-M interrupt masking works differently than -A or -R.
133
-{
342
- * There is no FIQ/IRQ distinction. Instead of I and F bits
134
- /* The Cortex-M3 Devices Generic User Guide says that "When the
343
- * masking FIQ and IRQ interrupts, an exception is taken only
135
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
344
- * if it is higher priority than the current execution priority
136
- * SYST RVR register and then counts down". So, we need to check the
345
- * (which depends on state like BASEPRI, FAULTMASK and the
137
- * ENABLE bit before reloading the value.
346
- * currently active exception).
138
- */
347
- */
139
- if ((s->systick.control & SYSTICK_ENABLE) == 0) {
348
- if (interrupt_request & CPU_INTERRUPT_HARD
140
- return;
349
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
350
- cs->exception_index = EXCP_IRQ;
351
- cc->tcg_ops->do_interrupt(cs);
352
- ret = true;
141
- }
353
- }
142
-
354
- return ret;
143
- if (reset)
355
-}
144
- s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
356
-#endif /* !CONFIG_USER_ONLY */
145
- s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
357
-
146
- timer_mod(s->systick.timer, s->systick.tick);
358
static void arm926_initfn(Object *obj)
147
-}
148
-
149
-static void systick_timer_tick(void * opaque)
150
-{
151
- NVICState *s = (NVICState *)opaque;
152
- s->systick.control |= SYSTICK_COUNTFLAG;
153
- if (s->systick.control & SYSTICK_TICKINT) {
154
- /* Trigger the interrupt. */
155
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
156
- }
157
- if (s->systick.reload == 0) {
158
- s->systick.control &= ~SYSTICK_ENABLE;
159
- } else {
160
- systick_reload(s, 0);
161
- }
162
-}
163
-
164
-static void systick_reset(NVICState *s)
165
-{
166
- s->systick.control = 0;
167
- s->systick.reload = 0;
168
- s->systick.tick = 0;
169
- timer_del(s->systick.timer);
170
-}
171
-
172
static int nvic_pending_prio(NVICState *s)
173
{
359
{
174
/* return the priority of the current pending interrupt,
360
ARMCPU *cpu = ARM_CPU(obj);
175
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
361
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
176
switch (offset) {
362
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
177
case 4: /* Interrupt Control Type. */
178
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
179
- case 0x10: /* SysTick Control and Status. */
180
- val = s->systick.control;
181
- s->systick.control &= ~SYSTICK_COUNTFLAG;
182
- return val;
183
- case 0x14: /* SysTick Reload Value. */
184
- return s->systick.reload;
185
- case 0x18: /* SysTick Current Value. */
186
- {
187
- int64_t t;
188
- if ((s->systick.control & SYSTICK_ENABLE) == 0)
189
- return 0;
190
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
191
- if (t >= s->systick.tick)
192
- return 0;
193
- val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
194
- /* The interrupt in triggered when the timer reaches zero.
195
- However the counter is not reloaded until the next clock
196
- tick. This is a hack to return zero during the first tick. */
197
- if (val > s->systick.reload)
198
- val = 0;
199
- return val;
200
- }
201
- case 0x1c: /* SysTick Calibration Value. */
202
- return 10000;
203
case 0xd00: /* CPUID Base. */
204
return cpu->midr;
205
case 0xd04: /* Interrupt Control State. */
206
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
207
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
208
{
209
ARMCPU *cpu = s->cpu;
210
- uint32_t oldval;
211
+
212
switch (offset) {
213
- case 0x10: /* SysTick Control and Status. */
214
- oldval = s->systick.control;
215
- s->systick.control &= 0xfffffff8;
216
- s->systick.control |= value & 7;
217
- if ((oldval ^ value) & SYSTICK_ENABLE) {
218
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
219
- if (value & SYSTICK_ENABLE) {
220
- if (s->systick.tick) {
221
- s->systick.tick += now;
222
- timer_mod(s->systick.timer, s->systick.tick);
223
- } else {
224
- systick_reload(s, 1);
225
- }
226
- } else {
227
- timer_del(s->systick.timer);
228
- s->systick.tick -= now;
229
- if (s->systick.tick < 0)
230
- s->systick.tick = 0;
231
- }
232
- } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
233
- /* This is a hack. Force the timer to be reloaded
234
- when the reference clock is changed. */
235
- systick_reload(s, 1);
236
- }
237
- break;
238
- case 0x14: /* SysTick Reload Value. */
239
- s->systick.reload = value;
240
- break;
241
- case 0x18: /* SysTick Current Value. Writes reload the timer. */
242
- systick_reload(s, 1);
243
- s->systick.control &= ~SYSTICK_COUNTFLAG;
244
- break;
245
case 0xd04: /* Interrupt Control State. */
246
if (value & (1 << 31)) {
247
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
248
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
249
250
static const VMStateDescription vmstate_nvic = {
251
.name = "armv7m_nvic",
252
- .version_id = 3,
253
- .minimum_version_id = 3,
254
+ .version_id = 4,
255
+ .minimum_version_id = 4,
256
.post_load = &nvic_post_load,
257
.fields = (VMStateField[]) {
258
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
259
vmstate_VecInfo, VecInfo),
260
- VMSTATE_UINT32(systick.control, NVICState),
261
- VMSTATE_UINT32(systick.reload, NVICState),
262
- VMSTATE_INT64(systick.tick, NVICState),
263
- VMSTATE_TIMER_PTR(systick.timer, NVICState),
264
VMSTATE_UINT32(prigroup, NVICState),
265
VMSTATE_END_OF_LIST()
266
}
267
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
268
269
s->exception_prio = NVIC_NOEXC_PRIO;
270
s->vectpending = 0;
271
+}
272
273
- systick_reset(s);
274
+static void nvic_systick_trigger(void *opaque, int n, int level)
275
+{
276
+ NVICState *s = opaque;
277
+
278
+ if (level) {
279
+ /* SysTick just asked us to pend its exception.
280
+ * (This is different from an external interrupt line's
281
+ * behaviour.)
282
+ */
283
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
284
+ }
285
}
363
}
286
364
287
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
365
-static void cortex_m0_initfn(Object *obj)
288
{
366
-{
289
NVICState *s = NVIC(dev);
367
- ARMCPU *cpu = ARM_CPU(obj);
290
+ SysBusDevice *systick_sbd;
368
- set_feature(&cpu->env, ARM_FEATURE_V6);
291
+ Error *err = NULL;
369
- set_feature(&cpu->env, ARM_FEATURE_M);
292
370
-
293
s->cpu = ARM_CPU(qemu_get_cpu(0));
371
- cpu->midr = 0x410cc200;
294
assert(s->cpu);
372
-
295
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
373
- /*
296
/* include space for internal exception vectors */
374
- * These ID register values are not guest visible, because
297
s->num_irq += NVIC_FIRST_IRQ;
375
- * we do not implement the Main Extension. They must be set
298
376
- * to values corresponding to the Cortex-M0's implemented
299
+ object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
377
- * features, because QEMU generally controls its emulation
300
+ if (err != NULL) {
378
- * by looking at ID register fields. We use the same values as
301
+ error_propagate(errp, err);
379
- * for the M3.
302
+ return;
380
- */
303
+ }
381
- cpu->isar.id_pfr0 = 0x00000030;
304
+ systick_sbd = SYS_BUS_DEVICE(&s->systick);
382
- cpu->isar.id_pfr1 = 0x00000200;
305
+ sysbus_connect_irq(systick_sbd, 0,
383
- cpu->isar.id_dfr0 = 0x00100000;
306
+ qdev_get_gpio_in_named(dev, "systick-trigger", 0));
384
- cpu->id_afr0 = 0x00000000;
307
+
385
- cpu->isar.id_mmfr0 = 0x00000030;
308
/* The NVIC and System Control Space (SCS) starts at 0xe000e000
386
- cpu->isar.id_mmfr1 = 0x00000000;
309
* and looks like this:
387
- cpu->isar.id_mmfr2 = 0x00000000;
310
* 0x004 - ICTR
388
- cpu->isar.id_mmfr3 = 0x00000000;
311
- * 0x010 - 0x1c - systick
389
- cpu->isar.id_isar0 = 0x01141110;
312
+ * 0x010 - 0xff - systick
390
- cpu->isar.id_isar1 = 0x02111000;
313
* 0x100..0x7ec - NVIC
391
- cpu->isar.id_isar2 = 0x21112231;
314
* 0x7f0..0xcff - Reserved
392
- cpu->isar.id_isar3 = 0x01111110;
315
* 0xd00..0xd3c - SCS registers
393
- cpu->isar.id_isar4 = 0x01310102;
316
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
394
- cpu->isar.id_isar5 = 0x00000000;
317
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
395
- cpu->isar.id_isar6 = 0x00000000;
318
"nvic_sysregs", 0x1000);
396
-}
319
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
397
-
320
+ memory_region_add_subregion_overlap(&s->container, 0x10,
398
-static void cortex_m3_initfn(Object *obj)
321
+ sysbus_mmio_get_region(systick_sbd, 0),
399
-{
322
+ 1);
400
- ARMCPU *cpu = ARM_CPU(obj);
323
401
- set_feature(&cpu->env, ARM_FEATURE_V7);
324
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
402
- set_feature(&cpu->env, ARM_FEATURE_M);
325
-
403
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
326
- s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
404
- cpu->midr = 0x410fc231;
405
- cpu->pmsav7_dregion = 8;
406
- cpu->isar.id_pfr0 = 0x00000030;
407
- cpu->isar.id_pfr1 = 0x00000200;
408
- cpu->isar.id_dfr0 = 0x00100000;
409
- cpu->id_afr0 = 0x00000000;
410
- cpu->isar.id_mmfr0 = 0x00000030;
411
- cpu->isar.id_mmfr1 = 0x00000000;
412
- cpu->isar.id_mmfr2 = 0x00000000;
413
- cpu->isar.id_mmfr3 = 0x00000000;
414
- cpu->isar.id_isar0 = 0x01141110;
415
- cpu->isar.id_isar1 = 0x02111000;
416
- cpu->isar.id_isar2 = 0x21112231;
417
- cpu->isar.id_isar3 = 0x01111110;
418
- cpu->isar.id_isar4 = 0x01310102;
419
- cpu->isar.id_isar5 = 0x00000000;
420
- cpu->isar.id_isar6 = 0x00000000;
421
-}
422
-
423
-static void cortex_m4_initfn(Object *obj)
424
-{
425
- ARMCPU *cpu = ARM_CPU(obj);
426
-
427
- set_feature(&cpu->env, ARM_FEATURE_V7);
428
- set_feature(&cpu->env, ARM_FEATURE_M);
429
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
430
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
431
- cpu->midr = 0x410fc240; /* r0p0 */
432
- cpu->pmsav7_dregion = 8;
433
- cpu->isar.mvfr0 = 0x10110021;
434
- cpu->isar.mvfr1 = 0x11000011;
435
- cpu->isar.mvfr2 = 0x00000000;
436
- cpu->isar.id_pfr0 = 0x00000030;
437
- cpu->isar.id_pfr1 = 0x00000200;
438
- cpu->isar.id_dfr0 = 0x00100000;
439
- cpu->id_afr0 = 0x00000000;
440
- cpu->isar.id_mmfr0 = 0x00000030;
441
- cpu->isar.id_mmfr1 = 0x00000000;
442
- cpu->isar.id_mmfr2 = 0x00000000;
443
- cpu->isar.id_mmfr3 = 0x00000000;
444
- cpu->isar.id_isar0 = 0x01141110;
445
- cpu->isar.id_isar1 = 0x02111000;
446
- cpu->isar.id_isar2 = 0x21112231;
447
- cpu->isar.id_isar3 = 0x01111110;
448
- cpu->isar.id_isar4 = 0x01310102;
449
- cpu->isar.id_isar5 = 0x00000000;
450
- cpu->isar.id_isar6 = 0x00000000;
451
-}
452
-
453
-static void cortex_m7_initfn(Object *obj)
454
-{
455
- ARMCPU *cpu = ARM_CPU(obj);
456
-
457
- set_feature(&cpu->env, ARM_FEATURE_V7);
458
- set_feature(&cpu->env, ARM_FEATURE_M);
459
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
460
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
461
- cpu->midr = 0x411fc272; /* r1p2 */
462
- cpu->pmsav7_dregion = 8;
463
- cpu->isar.mvfr0 = 0x10110221;
464
- cpu->isar.mvfr1 = 0x12000011;
465
- cpu->isar.mvfr2 = 0x00000040;
466
- cpu->isar.id_pfr0 = 0x00000030;
467
- cpu->isar.id_pfr1 = 0x00000200;
468
- cpu->isar.id_dfr0 = 0x00100000;
469
- cpu->id_afr0 = 0x00000000;
470
- cpu->isar.id_mmfr0 = 0x00100030;
471
- cpu->isar.id_mmfr1 = 0x00000000;
472
- cpu->isar.id_mmfr2 = 0x01000000;
473
- cpu->isar.id_mmfr3 = 0x00000000;
474
- cpu->isar.id_isar0 = 0x01101110;
475
- cpu->isar.id_isar1 = 0x02112000;
476
- cpu->isar.id_isar2 = 0x20232231;
477
- cpu->isar.id_isar3 = 0x01111131;
478
- cpu->isar.id_isar4 = 0x01310132;
479
- cpu->isar.id_isar5 = 0x00000000;
480
- cpu->isar.id_isar6 = 0x00000000;
481
-}
482
-
483
-static void cortex_m33_initfn(Object *obj)
484
-{
485
- ARMCPU *cpu = ARM_CPU(obj);
486
-
487
- set_feature(&cpu->env, ARM_FEATURE_V8);
488
- set_feature(&cpu->env, ARM_FEATURE_M);
489
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
490
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
491
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
492
- cpu->midr = 0x410fd213; /* r0p3 */
493
- cpu->pmsav7_dregion = 16;
494
- cpu->sau_sregion = 8;
495
- cpu->isar.mvfr0 = 0x10110021;
496
- cpu->isar.mvfr1 = 0x11000011;
497
- cpu->isar.mvfr2 = 0x00000040;
498
- cpu->isar.id_pfr0 = 0x00000030;
499
- cpu->isar.id_pfr1 = 0x00000210;
500
- cpu->isar.id_dfr0 = 0x00200000;
501
- cpu->id_afr0 = 0x00000000;
502
- cpu->isar.id_mmfr0 = 0x00101F40;
503
- cpu->isar.id_mmfr1 = 0x00000000;
504
- cpu->isar.id_mmfr2 = 0x01000000;
505
- cpu->isar.id_mmfr3 = 0x00000000;
506
- cpu->isar.id_isar0 = 0x01101110;
507
- cpu->isar.id_isar1 = 0x02212000;
508
- cpu->isar.id_isar2 = 0x20232232;
509
- cpu->isar.id_isar3 = 0x01111131;
510
- cpu->isar.id_isar4 = 0x01310132;
511
- cpu->isar.id_isar5 = 0x00000000;
512
- cpu->isar.id_isar6 = 0x00000000;
513
- cpu->clidr = 0x00000000;
514
- cpu->ctr = 0x8000c000;
515
-}
516
-
517
-static void cortex_m55_initfn(Object *obj)
518
-{
519
- ARMCPU *cpu = ARM_CPU(obj);
520
-
521
- set_feature(&cpu->env, ARM_FEATURE_V8);
522
- set_feature(&cpu->env, ARM_FEATURE_V8_1M);
523
- set_feature(&cpu->env, ARM_FEATURE_M);
524
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
525
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
526
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
527
- cpu->midr = 0x410fd221; /* r0p1 */
528
- cpu->revidr = 0;
529
- cpu->pmsav7_dregion = 16;
530
- cpu->sau_sregion = 8;
531
- /* These are the MVFR* values for the FPU + full MVE configuration */
532
- cpu->isar.mvfr0 = 0x10110221;
533
- cpu->isar.mvfr1 = 0x12100211;
534
- cpu->isar.mvfr2 = 0x00000040;
535
- cpu->isar.id_pfr0 = 0x20000030;
536
- cpu->isar.id_pfr1 = 0x00000230;
537
- cpu->isar.id_dfr0 = 0x10200000;
538
- cpu->id_afr0 = 0x00000000;
539
- cpu->isar.id_mmfr0 = 0x00111040;
540
- cpu->isar.id_mmfr1 = 0x00000000;
541
- cpu->isar.id_mmfr2 = 0x01000000;
542
- cpu->isar.id_mmfr3 = 0x00000011;
543
- cpu->isar.id_isar0 = 0x01103110;
544
- cpu->isar.id_isar1 = 0x02212000;
545
- cpu->isar.id_isar2 = 0x20232232;
546
- cpu->isar.id_isar3 = 0x01111131;
547
- cpu->isar.id_isar4 = 0x01310132;
548
- cpu->isar.id_isar5 = 0x00000000;
549
- cpu->isar.id_isar6 = 0x00000000;
550
- cpu->clidr = 0x00000000; /* caches not implemented */
551
- cpu->ctr = 0x8303c003;
552
-}
553
-
554
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
555
/* Dummy the TCM region regs for the moment */
556
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
557
@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)
558
cpu->reset_sctlr = 0x00000078;
327
}
559
}
328
560
329
static void armv7m_nvic_instance_init(Object *obj)
561
-static const TCGCPUOps arm_v7m_tcg_ops = {
330
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_instance_init(Object *obj)
562
- .initialize = arm_translate_init,
331
NVICState *nvic = NVIC(obj);
563
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
332
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
564
- .debug_excp_handler = arm_debug_excp_handler,
333
565
- .restore_state_to_opc = arm_restore_state_to_opc,
334
+ object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
566
-
335
+ qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
567
-#ifdef CONFIG_USER_ONLY
336
+
568
- .record_sigsegv = arm_cpu_record_sigsegv,
337
sysbus_init_irq(sbd, &nvic->excpout);
569
- .record_sigbus = arm_cpu_record_sigbus,
338
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
570
-#else
339
+ qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
571
- .tlb_fill = arm_cpu_tlb_fill,
340
}
572
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
341
573
- .do_interrupt = arm_v7m_cpu_do_interrupt,
342
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
574
- .do_transaction_failed = arm_cpu_do_transaction_failed,
343
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
575
- .do_unaligned_access = arm_cpu_do_unaligned_access,
344
new file mode 100644
576
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
345
index XXXXXXX..XXXXXXX
577
- .debug_check_watchpoint = arm_debug_check_watchpoint,
346
--- /dev/null
578
- .debug_check_breakpoint = arm_debug_check_breakpoint,
347
+++ b/hw/timer/armv7m_systick.c
579
-#endif /* !CONFIG_USER_ONLY */
348
@@ -XXX,XX +XXX,XX @@
580
-};
349
+/*
581
-
350
+ * ARMv7M SysTick timer
582
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
351
+ *
583
-{
352
+ * Copyright (c) 2006-2007 CodeSourcery.
584
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
353
+ * Written by Paul Brook
585
- CPUClass *cc = CPU_CLASS(oc);
354
+ * Copyright (c) 2017 Linaro Ltd
586
-
355
+ * Written by Peter Maydell
587
- acc->info = data;
356
+ *
588
- cc->tcg_ops = &arm_v7m_tcg_ops;
357
+ * This code is licensed under the GPL (version 2 or later).
589
- cc->gdb_core_xml_file = "arm-m-profile.xml";
358
+ */
590
-}
359
+
591
-
360
+#include "qemu/osdep.h"
592
#ifndef TARGET_AARCH64
361
+#include "hw/timer/armv7m_systick.h"
593
/*
362
+#include "qemu-common.h"
594
* -cpu max: a CPU with as many features enabled as our emulation supports.
363
+#include "hw/sysbus.h"
595
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
364
+#include "qemu/timer.h"
596
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
365
+#include "qemu/log.h"
597
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
366
+#include "trace.h"
598
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
367
+
599
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
368
+/* qemu timers run at 1GHz. We want something closer to 1MHz. */
600
- .class_init = arm_v7m_class_init },
369
+#define SYSTICK_SCALE 1000ULL
601
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
370
+
602
- .class_init = arm_v7m_class_init },
371
+#define SYSTICK_ENABLE (1 << 0)
603
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
372
+#define SYSTICK_TICKINT (1 << 1)
604
- .class_init = arm_v7m_class_init },
373
+#define SYSTICK_CLKSOURCE (1 << 2)
605
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
374
+#define SYSTICK_COUNTFLAG (1 << 16)
606
- .class_init = arm_v7m_class_init },
375
+
607
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
376
+int system_clock_scale;
608
- .class_init = arm_v7m_class_init },
377
+
609
- { .name = "cortex-m55", .initfn = cortex_m55_initfn,
378
+/* Conversion factor from qemu timer to SysTick frequencies. */
610
- .class_init = arm_v7m_class_init },
379
+static inline int64_t systick_scale(SysTickState *s)
611
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
380
+{
612
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
381
+ if (s->control & SYSTICK_CLKSOURCE) {
613
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
382
+ return system_clock_scale;
614
diff --git a/target/arm/meson.build b/target/arm/meson.build
383
+ } else {
384
+ return 1000;
385
+ }
386
+}
387
+
388
+static void systick_reload(SysTickState *s, int reset)
389
+{
390
+ /* The Cortex-M3 Devices Generic User Guide says that "When the
391
+ * ENABLE bit is set to 1, the counter loads the RELOAD value from the
392
+ * SYST RVR register and then counts down". So, we need to check the
393
+ * ENABLE bit before reloading the value.
394
+ */
395
+ trace_systick_reload();
396
+
397
+ if ((s->control & SYSTICK_ENABLE) == 0) {
398
+ return;
399
+ }
400
+
401
+ if (reset) {
402
+ s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
403
+ }
404
+ s->tick += (s->reload + 1) * systick_scale(s);
405
+ timer_mod(s->timer, s->tick);
406
+}
407
+
408
+static void systick_timer_tick(void *opaque)
409
+{
410
+ SysTickState *s = (SysTickState *)opaque;
411
+
412
+ trace_systick_timer_tick();
413
+
414
+ s->control |= SYSTICK_COUNTFLAG;
415
+ if (s->control & SYSTICK_TICKINT) {
416
+ /* Tell the NVIC to pend the SysTick exception */
417
+ qemu_irq_pulse(s->irq);
418
+ }
419
+ if (s->reload == 0) {
420
+ s->control &= ~SYSTICK_ENABLE;
421
+ } else {
422
+ systick_reload(s, 0);
423
+ }
424
+}
425
+
426
+static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
427
+{
428
+ SysTickState *s = opaque;
429
+ uint32_t val;
430
+
431
+ switch (addr) {
432
+ case 0x0: /* SysTick Control and Status. */
433
+ val = s->control;
434
+ s->control &= ~SYSTICK_COUNTFLAG;
435
+ break;
436
+ case 0x4: /* SysTick Reload Value. */
437
+ val = s->reload;
438
+ break;
439
+ case 0x8: /* SysTick Current Value. */
440
+ {
441
+ int64_t t;
442
+
443
+ if ((s->control & SYSTICK_ENABLE) == 0) {
444
+ val = 0;
445
+ break;
446
+ }
447
+ t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
448
+ if (t >= s->tick) {
449
+ val = 0;
450
+ break;
451
+ }
452
+ val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
453
+ /* The interrupt in triggered when the timer reaches zero.
454
+ However the counter is not reloaded until the next clock
455
+ tick. This is a hack to return zero during the first tick. */
456
+ if (val > s->reload) {
457
+ val = 0;
458
+ }
459
+ break;
460
+ }
461
+ case 0xc: /* SysTick Calibration Value. */
462
+ val = 10000;
463
+ break;
464
+ default:
465
+ val = 0;
466
+ qemu_log_mask(LOG_GUEST_ERROR,
467
+ "SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
468
+ break;
469
+ }
470
+
471
+ trace_systick_read(addr, val, size);
472
+ return val;
473
+}
474
+
475
+static void systick_write(void *opaque, hwaddr addr,
476
+ uint64_t value, unsigned size)
477
+{
478
+ SysTickState *s = opaque;
479
+
480
+ trace_systick_write(addr, value, size);
481
+
482
+ switch (addr) {
483
+ case 0x0: /* SysTick Control and Status. */
484
+ {
485
+ uint32_t oldval = s->control;
486
+
487
+ s->control &= 0xfffffff8;
488
+ s->control |= value & 7;
489
+ if ((oldval ^ value) & SYSTICK_ENABLE) {
490
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
491
+ if (value & SYSTICK_ENABLE) {
492
+ if (s->tick) {
493
+ s->tick += now;
494
+ timer_mod(s->timer, s->tick);
495
+ } else {
496
+ systick_reload(s, 1);
497
+ }
498
+ } else {
499
+ timer_del(s->timer);
500
+ s->tick -= now;
501
+ if (s->tick < 0) {
502
+ s->tick = 0;
503
+ }
504
+ }
505
+ } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
506
+ /* This is a hack. Force the timer to be reloaded
507
+ when the reference clock is changed. */
508
+ systick_reload(s, 1);
509
+ }
510
+ break;
511
+ }
512
+ case 0x4: /* SysTick Reload Value. */
513
+ s->reload = value;
514
+ break;
515
+ case 0x8: /* SysTick Current Value. Writes reload the timer. */
516
+ systick_reload(s, 1);
517
+ s->control &= ~SYSTICK_COUNTFLAG;
518
+ break;
519
+ default:
520
+ qemu_log_mask(LOG_GUEST_ERROR,
521
+ "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
522
+ }
523
+}
524
+
525
+static const MemoryRegionOps systick_ops = {
526
+ .read = systick_read,
527
+ .write = systick_write,
528
+ .endianness = DEVICE_NATIVE_ENDIAN,
529
+ .valid.min_access_size = 4,
530
+ .valid.max_access_size = 4,
531
+};
532
+
533
+static void systick_reset(DeviceState *dev)
534
+{
535
+ SysTickState *s = SYSTICK(dev);
536
+
537
+ s->control = 0;
538
+ s->reload = 0;
539
+ s->tick = 0;
540
+ timer_del(s->timer);
541
+}
542
+
543
+static void systick_instance_init(Object *obj)
544
+{
545
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
546
+ SysTickState *s = SYSTICK(obj);
547
+
548
+ memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
549
+ sysbus_init_mmio(sbd, &s->iomem);
550
+ sysbus_init_irq(sbd, &s->irq);
551
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
552
+}
553
+
554
+static const VMStateDescription vmstate_systick = {
555
+ .name = "armv7m_systick",
556
+ .version_id = 1,
557
+ .minimum_version_id = 1,
558
+ .fields = (VMStateField[]) {
559
+ VMSTATE_UINT32(control, SysTickState),
560
+ VMSTATE_UINT32(reload, SysTickState),
561
+ VMSTATE_INT64(tick, SysTickState),
562
+ VMSTATE_TIMER_PTR(timer, SysTickState),
563
+ VMSTATE_END_OF_LIST()
564
+ }
565
+};
566
+
567
+static void systick_class_init(ObjectClass *klass, void *data)
568
+{
569
+ DeviceClass *dc = DEVICE_CLASS(klass);
570
+
571
+ dc->vmsd = &vmstate_systick;
572
+ dc->reset = systick_reset;
573
+}
574
+
575
+static const TypeInfo armv7m_systick_info = {
576
+ .name = TYPE_SYSTICK,
577
+ .parent = TYPE_SYS_BUS_DEVICE,
578
+ .instance_init = systick_instance_init,
579
+ .instance_size = sizeof(SysTickState),
580
+ .class_init = systick_class_init,
581
+};
582
+
583
+static void armv7m_systick_register_types(void)
584
+{
585
+ type_register_static(&armv7m_systick_info);
586
+}
587
+
588
+type_init(armv7m_systick_register_types)
589
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
590
index XXXXXXX..XXXXXXX 100644
615
index XXXXXXX..XXXXXXX 100644
591
--- a/hw/timer/trace-events
616
--- a/target/arm/meson.build
592
+++ b/hw/timer/trace-events
617
+++ b/target/arm/meson.build
593
@@ -XXX,XX +XXX,XX @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
618
@@ -XXX,XX +XXX,XX @@ arm_system_ss.add(files(
594
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
619
'ptw.c',
595
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
620
))
596
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
621
597
+
622
+arm_user_ss = ss.source_set()
598
+# hw/timer/armv7m_systick.c
623
+
599
+systick_reload(void) "systick reload"
624
subdir('hvf')
600
+systick_timer_tick(void) "systick reload"
625
601
+systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
626
if 'CONFIG_TCG' in config_all_accel
602
+systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
627
@@ -XXX,XX +XXX,XX @@ endif
628
629
target_arch += {'arm': arm_ss}
630
target_system_arch += {'arm': arm_system_ss}
631
+target_user_arch += {'arm': arm_user_ss}
632
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
633
index XXXXXXX..XXXXXXX 100644
634
--- a/target/arm/tcg/meson.build
635
+++ b/target/arm/tcg/meson.build
636
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
637
arm_system_ss.add(files(
638
'psci.c',
639
))
640
+
641
+arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
642
+arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
603
--
643
--
604
2.7.4
644
2.34.1
605
606
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/21] stm32f205: Create armv7m object without using armv7m_init()
Deleted patch
1
Switch the stm32f205 SoC to create the armv7m object directly
2
rather than via the armv7m_init() wrapper. This fits better
3
with the SoC model's very QOMified design.
4
1
5
In particular this means we can push loading the guest image
6
out to the top level board code where it belongs, rather
7
than the SoC object having a QOM property for the filename
8
to load.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
15
---
16
include/hw/arm/stm32f205_soc.h | 4 +++-
17
hw/arm/netduino2.c | 7 ++++---
18
hw/arm/stm32f205_soc.c | 16 +++++++++++++---
19
3 files changed, 20 insertions(+), 7 deletions(-)
20
21
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/stm32f205_soc.h
24
+++ b/include/hw/arm/stm32f205_soc.h
25
@@ -XXX,XX +XXX,XX @@
26
#include "hw/adc/stm32f2xx_adc.h"
27
#include "hw/or-irq.h"
28
#include "hw/ssi/stm32f2xx_spi.h"
29
+#include "hw/arm/armv7m.h"
30
31
#define TYPE_STM32F205_SOC "stm32f205-soc"
32
#define STM32F205_SOC(obj) \
33
@@ -XXX,XX +XXX,XX @@ typedef struct STM32F205State {
34
SysBusDevice parent_obj;
35
/*< public >*/
36
37
- char *kernel_filename;
38
char *cpu_model;
39
40
+ ARMv7MState armv7m;
41
+
42
STM32F2XXSyscfgState syscfg;
43
STM32F2XXUsartState usart[STM_NUM_USARTS];
44
STM32F2XXTimerState timer[STM_NUM_TIMERS];
45
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/netduino2.c
48
+++ b/hw/arm/netduino2.c
49
@@ -XXX,XX +XXX,XX @@
50
#include "hw/boards.h"
51
#include "qemu/error-report.h"
52
#include "hw/arm/stm32f205_soc.h"
53
+#include "hw/arm/arm.h"
54
55
static void netduino2_init(MachineState *machine)
56
{
57
DeviceState *dev;
58
59
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
60
- if (machine->kernel_filename) {
61
- qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
62
- }
63
qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
64
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
65
+
66
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
67
+ FLASH_SIZE);
68
}
69
70
static void netduino2_machine_init(MachineClass *mc)
71
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/arm/stm32f205_soc.c
74
+++ b/hw/arm/stm32f205_soc.c
75
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
76
STM32F205State *s = STM32F205_SOC(obj);
77
int i;
78
79
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
80
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
81
+
82
object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
83
qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
84
85
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
86
vmstate_register_ram_global(sram);
87
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
88
89
- nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
90
- s->kernel_filename, s->cpu_model);
91
+ nvic = DEVICE(&s->armv7m);
92
+ qdev_prop_set_uint32(nvic, "num-irq", 96);
93
+ qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
94
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
95
+ "memory", &error_abort);
96
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
97
+ if (err != NULL) {
98
+ error_propagate(errp, err);
99
+ return;
100
+ }
101
102
/* System configuration controller */
103
dev = DEVICE(&s->syscfg);
104
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
105
}
106
107
static Property stm32f205_soc_properties[] = {
108
- DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
109
DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
110
DEFINE_PROP_END_OF_LIST(),
111
};
112
--
113
2.7.4
114
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/21] update-linux-headers: update for 4.11
Deleted patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
1
3
The linux-headers/asm-arm/unistd.h file has been split in three
4
sub-files, copy them along. However, building them requires
5
setting ARCH rather than SRCARCH.
6
7
SRCARCH defaults to $(ARCH) anyway; to avoid future occurrence of
8
the same problem use ARCH for all architectures where SRCARCH=ARCH.
9
Currently these are all except x86, sparc, sh and tile.
10
11
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12
Message-id: 20170221122920.16245-2-pbonzini@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
scripts/update-linux-headers.sh | 13 ++++++++++++-
16
1 file changed, 12 insertions(+), 1 deletion(-)
17
18
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
19
index XXXXXXX..XXXXXXX 100755
20
--- a/scripts/update-linux-headers.sh
21
+++ b/scripts/update-linux-headers.sh
22
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
23
continue
24
fi
25
26
- make -C "$linux" INSTALL_HDR_PATH="$tmpdir" SRCARCH=$arch headers_install
27
+ if [ "$arch" = x86 ]; then
28
+ arch_var=SRCARCH
29
+ else
30
+ arch_var=ARCH
31
+ fi
32
+
33
+ make -C "$linux" INSTALL_HDR_PATH="$tmpdir" $arch_var=$arch headers_install
34
35
rm -rf "$output/linux-headers/asm-$arch"
36
mkdir -p "$output/linux-headers/asm-$arch"
37
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
38
cp_portable "$tmpdir/include/asm/kvm_virtio.h" "$output/include/standard-headers/asm-s390/"
39
cp_portable "$tmpdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/"
40
fi
41
+ if [ $arch = arm ]; then
42
+ cp "$tmpdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/"
43
+ cp "$tmpdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/"
44
+ cp "$tmpdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/"
45
+ fi
46
if [ $arch = x86 ]; then
47
cp_portable "$tmpdir/include/asm/hyperv.h" "$output/include/standard-headers/asm-x86/"
48
cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/"
49
--
50
2.7.4
51
52
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/21] hw/sd: add card-reparenting function
Deleted patch
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
2
1
3
Provide a new function sdbus_reparent_card() in sd core for reparenting
4
a card from a SDBus to another one.
5
6
This function is required by the raspi platform, where the two SD
7
controllers can be dynamically switched.
8
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org
13
Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a doc comment to the header file; changed to
16
use new behaviour of qdev_set_parent_bus()]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/sd/sd.h | 11 +++++++++++
20
hw/sd/core.c | 27 +++++++++++++++++++++++++++
21
2 files changed, 38 insertions(+)
22
23
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/sd/sd.h
26
+++ b/include/hw/sd/sd.h
27
@@ -XXX,XX +XXX,XX @@ uint8_t sdbus_read_data(SDBus *sd);
28
bool sdbus_data_ready(SDBus *sd);
29
bool sdbus_get_inserted(SDBus *sd);
30
bool sdbus_get_readonly(SDBus *sd);
31
+/**
32
+ * sdbus_reparent_card: Reparent an SD card from one controller to another
33
+ * @from: controller bus to remove card from
34
+ * @to: controller bus to move card to
35
+ *
36
+ * Reparent an SD card, effectively unplugging it from one controller
37
+ * and inserting it into another. This is useful for SoCs like the
38
+ * bcm2835 which have two SD controllers and connect a single SD card
39
+ * to them, selected by the guest reprogramming GPIO line routing.
40
+ */
41
+void sdbus_reparent_card(SDBus *from, SDBus *to);
42
43
/* Functions to be used by SD devices to report back to qdevified controllers */
44
void sdbus_set_inserted(SDBus *sd, bool inserted);
45
diff --git a/hw/sd/core.c b/hw/sd/core.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/sd/core.c
48
+++ b/hw/sd/core.c
49
@@ -XXX,XX +XXX,XX @@ void sdbus_set_readonly(SDBus *sdbus, bool readonly)
50
}
51
}
52
53
+void sdbus_reparent_card(SDBus *from, SDBus *to)
54
+{
55
+ SDState *card = get_card(from);
56
+ SDCardClass *sc;
57
+ bool readonly;
58
+
59
+ /* We directly reparent the card object rather than implementing this
60
+ * as a hotpluggable connection because we don't want to expose SD cards
61
+ * to users as being hotpluggable, and we can get away with it in this
62
+ * limited use case. This could perhaps be implemented more cleanly in
63
+ * future by adding support to the hotplug infrastructure for "device
64
+ * can be hotplugged only via code, not by user".
65
+ */
66
+
67
+ if (!card) {
68
+ return;
69
+ }
70
+
71
+ sc = SD_CARD_GET_CLASS(card);
72
+ readonly = sc->get_readonly(card);
73
+
74
+ sdbus_set_inserted(from, false);
75
+ qdev_set_parent_bus(DEVICE(card), &to->qbus);
76
+ sdbus_set_inserted(to, true);
77
+ sdbus_set_readonly(to, readonly);
78
+}
79
+
80
static const TypeInfo sd_bus_info = {
81
.name = TYPE_SD_BUS,
82
.parent = TYPE_BUS,
83
--
84
2.7.4
85
86
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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