[Qemu-devel] [PULL 00/21] target-arm queue
[PULL 00/24] target-arm queue
1
Second lot of ARM changes to sneak in before freeze:
1
The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
2
* fixed version of the raspi2 sd controller patches
3
* GICv3 save/restore
4
* v7M QOMify
5
2
6
I've also included the Linux header update patches stolen
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
7
from Paolo's pullreq since it hasn't quite hit master yet.
8
4
9
thanks
5
are available in the Git repository at:
10
-- PMM
11
6
12
The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
13
8
14
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging (2017-02-28 14:50:17 +0000)
9
for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
15
10
16
are available in the git repository at:
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
17
18
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228-1
19
20
for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:
21
22
bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +0000)
23
12
24
----------------------------------------------------------------
13
----------------------------------------------------------------
25
target-arm queue:
14
target-arm queue:
26
* raspi2: add gpio controller and sdhost controller, with
15
* more MVE instructions
27
the wiring so the guest can switch which controller the
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
28
SD card is attached to
17
* target/arm: Check NaN mode before silencing NaN
29
(this is sufficient to get raspbian kernels to boot)
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
30
* GICv3: support state save/restore from KVM
19
* hw/arm: Add basic power management to raspi.
31
* update Linux headers to 4.11
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
32
* refactor and QOMify the ARMv7M container object
33
21
34
----------------------------------------------------------------
22
----------------------------------------------------------------
35
Clement Deschamps (3):
23
Joe Komlodi (1):
36
hw/sd: add card-reparenting function
24
target/arm: Check NaN mode before silencing NaN
37
bcm2835_gpio: add bcm2835 gpio controller
38
bcm2835: add sdhost and gpio controllers
39
25
40
Paolo Bonzini (2):
26
Maxim Uvarov (1):
41
update-linux-headers: update for 4.11
27
hw/gpio/gpio_pwr: use shutdown function for reboot
42
update Linux headers to 4.11
43
28
44
Peter Maydell (12):
29
Nolan Leake (1):
45
armv7m: Abstract out the "load kernel" code
30
hw/arm: Add basic power management to raspi.
46
armv7m: Move NVICState struct definition into header
47
armv7m: QOMify the armv7m container
48
armv7m: Use QOMified armv7m object in armv7m_init()
49
armv7m: Make ARMv7M object take memory region link
50
armv7m: Make NVIC expose a memory region rather than mapping itself
51
armv7m: Make bitband device take the address space to access
52
armv7m: Don't put core v7M devices under CONFIG_STELLARIS
53
armv7m: Split systick out from NVIC
54
stm32f205: Create armv7m object without using armv7m_init()
55
stm32f205: Rename 'nvic' local to 'armv7m'
56
qdev: Have qdev_set_parent_bus() handle devices already on a bus
57
31
58
Vijaya Kumar K (4):
32
Patrick Venture (2):
59
hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
33
docs/system/arm: Add quanta-q7l1-bmc reference
60
hw/intc/arm_gicv3_kvm: Implement get/put functions
34
docs/system/arm: Add quanta-gbs-bmc reference
61
target-arm: Add GICv3CPUState in CPUARMState struct
62
hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
63
35
64
hw/gpio/Makefile.objs | 1 +
36
Peter Maydell (18):
65
hw/intc/Makefile.objs | 2 +-
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
66
hw/timer/Makefile.objs | 1 +
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
67
hw/intc/gicv3_internal.h | 3 +
39
target/arm: Make asimd_imm_const() public
68
include/hw/arm/arm.h | 12 +
40
target/arm: Use asimd_imm_const for A64 decode
69
include/hw/arm/armv7m.h | 63 +++
41
target/arm: Use dup_const() instead of bitfield_replicate()
70
include/hw/arm/armv7m_nvic.h | 62 ++
42
target/arm: Implement MVE logical immediate insns
71
include/hw/arm/bcm2835_peripherals.h | 4 +
43
target/arm: Implement MVE vector shift left by immediate insns
72
include/hw/arm/stm32f205_soc.h | 4 +-
44
target/arm: Implement MVE vector shift right by immediate insns
73
include/hw/gpio/bcm2835_gpio.h | 39 ++
45
target/arm: Implement MVE VSHLL
74
include/hw/intc/arm_gicv3_common.h | 1 +
46
target/arm: Implement MVE VSRI, VSLI
75
include/hw/sd/sd.h | 11 +
47
target/arm: Implement MVE VSHRN, VRSHRN
76
include/hw/timer/armv7m_systick.h | 34 ++
48
target/arm: Implement MVE saturating narrowing shifts
77
include/standard-headers/asm-x86/hyperv.h | 8 +
49
target/arm: Implement MVE VSHLC
78
include/standard-headers/linux/input-event-codes.h | 2 +-
50
target/arm: Implement MVE VADDLV
79
include/standard-headers/linux/pci_regs.h | 25 +
51
target/arm: Implement MVE long shifts by immediate
80
include/standard-headers/linux/virtio_ids.h | 1 +
52
target/arm: Implement MVE long shifts by register
81
linux-headers/asm-arm/kvm.h | 15 +
53
target/arm: Implement MVE shifts by immediate
82
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++
54
target/arm: Implement MVE shifts by register
83
linux-headers/asm-arm/unistd-eabi.h | 5 +
84
linux-headers/asm-arm/unistd-oabi.h | 17 +
85
linux-headers/asm-arm/unistd.h | 419 +-------------
86
linux-headers/asm-arm64/kvm.h | 13 +
87
linux-headers/asm-powerpc/kvm.h | 27 +
88
linux-headers/asm-powerpc/unistd.h | 1 +
89
linux-headers/asm-x86/kvm_para.h | 13 +-
90
linux-headers/linux/kvm.h | 24 +-
91
linux-headers/linux/kvm_para.h | 2 +
92
linux-headers/linux/userfaultfd.h | 67 ++-
93
linux-headers/linux/vfio.h | 10 +
94
target/arm/cpu.h | 2 +
95
hw/arm/armv7m.c | 379 ++++++++-----
96
hw/arm/bcm2835_peripherals.c | 43 +-
97
hw/arm/netduino2.c | 7 +-
98
hw/arm/stm32f205_soc.c | 28 +-
99
hw/core/qdev.c | 14 +
100
hw/gpio/bcm2835_gpio.c | 353 ++++++++++++
101
hw/intc/arm_gicv3_common.c | 38 ++
102
hw/intc/arm_gicv3_cpuif.c | 8 +
103
hw/intc/arm_gicv3_kvm.c | 629 ++++++++++++++++++++-
104
hw/intc/armv7m_nvic.c | 214 ++-----
105
hw/sd/core.c | 27 +
106
hw/timer/armv7m_systick.c | 240 ++++++++
107
default-configs/arm-softmmu.mak | 2 +
108
hw/timer/trace-events | 6 +
109
scripts/update-linux-headers.sh | 13 +-
110
46 files changed, 2479 insertions(+), 767 deletions(-)
111
create mode 100644 include/hw/arm/armv7m.h
112
create mode 100644 include/hw/arm/armv7m_nvic.h
113
create mode 100644 include/hw/gpio/bcm2835_gpio.h
114
create mode 100644 include/hw/timer/armv7m_systick.h
115
create mode 100644 linux-headers/asm-arm/unistd-common.h
116
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
117
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
118
create mode 100644 hw/gpio/bcm2835_gpio.c
119
create mode 100644 hw/timer/armv7m_systick.c
120
55
56
Philippe Mathieu-Daudé (1):
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
58
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/21] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
To Save and Restore ICC_SRE_EL1 register introduce vmstate
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
subsection and load only if non-zero.
4
entry.
5
Also initialize icc_sre_el1 with to 0x7 in pre_load
6
function.
7
5
8
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20210615192848.1065297-2-venture@google.com
11
Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
include/hw/intc/arm_gicv3_common.h | 1 +
11
docs/system/arm/aspeed.rst | 1 +
15
hw/intc/arm_gicv3_common.c | 36 ++++++++++++++++++++++++++++++++++++
12
1 file changed, 1 insertion(+)
16
2 files changed, 37 insertions(+)
17
13
18
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/arm_gicv3_common.h
16
--- a/docs/system/arm/aspeed.rst
21
+++ b/include/hw/intc/arm_gicv3_common.h
17
+++ b/docs/system/arm/aspeed.rst
22
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
18
@@ -XXX,XX +XXX,XX @@ etc.
23
uint8_t gicr_ipriorityr[GIC_INTERNAL];
19
AST2400 SoC based machines :
24
20
25
/* CPU interface */
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
26
+ uint64_t icc_sre_el1;
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
27
uint64_t icc_ctlr_el1[2];
23
28
uint64_t icc_pmr_el1;
24
AST2500 SoC based machines :
29
uint64_t icc_bpr[3];
30
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_common.c
33
+++ b/hw/intc/arm_gicv3_common.c
34
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu_virt = {
35
}
36
};
37
38
+static int icc_sre_el1_reg_pre_load(void *opaque)
39
+{
40
+ GICv3CPUState *cs = opaque;
41
+
42
+ /*
43
+ * If the sre_el1 subsection is not transferred this
44
+ * means SRE_EL1 is 0x7 (which might not be the same as
45
+ * our reset value).
46
+ */
47
+ cs->icc_sre_el1 = 0x7;
48
+ return 0;
49
+}
50
+
51
+static bool icc_sre_el1_reg_needed(void *opaque)
52
+{
53
+ GICv3CPUState *cs = opaque;
54
+
55
+ return cs->icc_sre_el1 != 7;
56
+}
57
+
58
+const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
59
+ .name = "arm_gicv3_cpu/sre_el1",
60
+ .version_id = 1,
61
+ .minimum_version_id = 1,
62
+ .pre_load = icc_sre_el1_reg_pre_load,
63
+ .needed = icc_sre_el1_reg_needed,
64
+ .fields = (VMStateField[]) {
65
+ VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
66
+ VMSTATE_END_OF_LIST()
67
+ }
68
+};
69
+
70
static const VMStateDescription vmstate_gicv3_cpu = {
71
.name = "arm_gicv3_cpu",
72
.version_id = 1,
73
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
74
.subsections = (const VMStateDescription * []) {
75
&vmstate_gicv3_cpu_virt,
76
NULL
77
+ },
78
+ .subsections = (const VMStateDescription * []) {
79
+ &vmstate_gicv3_cpu_sre_el1,
80
+ NULL
81
}
82
};
83
25
84
--
26
--
85
2.7.4
27
2.20.1
86
28
87
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/21] update Linux headers to 4.11
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
virtio_mmio.h would be deleted; I am leaving it in though it was a
3
Add line item reference to quanta-gbs-bmc machine.
4
mistake to add it.
5
4
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
5
Signed-off-by: Patrick Venture <venture@google.com>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 20210615192848.1065297-3-venture@google.com
8
[PMM: fixed underline Sphinx warning]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
include/standard-headers/asm-x86/hyperv.h | 8 +
11
docs/system/arm/nuvoton.rst | 5 +++--
10
include/standard-headers/linux/input-event-codes.h | 2 +-
12
1 file changed, 3 insertions(+), 2 deletions(-)
11
include/standard-headers/linux/pci_regs.h | 25 ++
12
include/standard-headers/linux/virtio_ids.h | 1 +
13
linux-headers/asm-arm/kvm.h | 15 +
14
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++++++++
15
linux-headers/asm-arm/unistd-eabi.h | 5 +
16
linux-headers/asm-arm/unistd-oabi.h | 17 +
17
linux-headers/asm-arm/unistd.h | 419 +--------------------
18
linux-headers/asm-arm64/kvm.h | 13 +
19
linux-headers/asm-powerpc/kvm.h | 27 ++
20
linux-headers/asm-powerpc/unistd.h | 1 +
21
linux-headers/asm-x86/kvm_para.h | 13 +-
22
linux-headers/linux/kvm.h | 24 +-
23
linux-headers/linux/kvm_para.h | 2 +
24
linux-headers/linux/userfaultfd.h | 67 +++-
25
linux-headers/linux/vfio.h | 10 +
26
17 files changed, 577 insertions(+), 429 deletions(-)
27
create mode 100644 linux-headers/asm-arm/unistd-common.h
28
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
29
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
30
13
31
diff --git a/include/standard-headers/asm-x86/hyperv.h b/include/standard-headers/asm-x86/hyperv.h
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
32
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
33
--- a/include/standard-headers/asm-x86/hyperv.h
16
--- a/docs/system/arm/nuvoton.rst
34
+++ b/include/standard-headers/asm-x86/hyperv.h
17
+++ b/docs/system/arm/nuvoton.rst
35
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@
36
*/
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
37
#define HV_X64_MSR_STAT_PAGES_AVAILABLE        (1 << 8)
20
-=====================================================
38
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
39
+/* Crash MSR available */
22
+================================================================
40
+#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
23
41
+
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
42
/*
25
designed to be used as Baseboard Management Controllers (BMCs) in various
43
* Feature identification: EBX indicates which flags were specified at
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
44
* partition creation. The format is the same as the partition creation
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
45
@@ -XXX,XX +XXX,XX @@
28
Hyperscale applications. The following machines are based on this chip :
46
*/
29
47
#define HV_X64_RELAXED_TIMING_RECOMMENDED    (1 << 5)
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
48
31
- ``quanta-gsj`` Quanta GSJ server BMC
49
+/*
32
50
+ * Crash notification flag.
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
51
+ */
52
+#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
53
+
54
/* MSR used to identify the guest OS. */
55
#define HV_X64_MSR_GUEST_OS_ID            0x40000000
56
57
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/standard-headers/linux/input-event-codes.h
60
+++ b/include/standard-headers/linux/input-event-codes.h
61
@@ -XXX,XX +XXX,XX @@
62
* Control a data application associated with the currently viewed channel,
63
* e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
64
*/
65
-#define KEY_DATA            0x275
66
+#define KEY_DATA            0x277
67
68
#define BTN_TRIGGER_HAPPY        0x2c0
69
#define BTN_TRIGGER_HAPPY1        0x2c0
70
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/standard-headers/linux/pci_regs.h
73
+++ b/include/standard-headers/linux/pci_regs.h
74
@@ -XXX,XX +XXX,XX @@
75
#define LINUX_PCI_REGS_H
76
77
/*
78
+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
79
+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
80
+ * configuration space.
81
+ */
82
+#define PCI_CFG_SPACE_SIZE    256
83
+#define PCI_CFG_SPACE_EXP_SIZE    4096
84
+
85
+/*
86
* Under PCI, each device has 256 bytes of configuration address space,
87
* of which the first 64 bytes are standardized as follows:
88
*/
89
@@ -XXX,XX +XXX,XX @@
90
#define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
91
#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
92
#define PCI_EXT_CAP_ID_DPC    0x1D    /* Downstream Port Containment */
93
+#define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
94
#define PCI_EXT_CAP_ID_PTM    0x1F    /* Precision Time Measurement */
95
#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PTM
96
97
@@ -XXX,XX +XXX,XX @@
98
#define PCI_EXP_DPC_STATUS        8    /* DPC Status */
99
#define PCI_EXP_DPC_STATUS_TRIGGER    0x01    /* Trigger Status */
100
#define PCI_EXP_DPC_STATUS_INTERRUPT    0x08    /* Interrupt Status */
101
+#define PCI_EXP_DPC_RP_BUSY        0x10    /* Root Port Busy */
102
103
#define PCI_EXP_DPC_SOURCE_ID        10    /* DPC Source Identifier */
104
105
@@ -XXX,XX +XXX,XX @@
106
#define PCI_PTM_CTRL_ENABLE        0x00000001 /* PTM enable */
107
#define PCI_PTM_CTRL_ROOT        0x00000002 /* Root select */
108
109
+/* L1 PM Substates */
110
+#define PCI_L1SS_CAP         4    /* capability register */
111
+#define PCI_L1SS_CAP_PCIPM_L1_2     1    /* PCI PM L1.2 Support */
112
+#define PCI_L1SS_CAP_PCIPM_L1_1     2    /* PCI PM L1.1 Support */
113
+#define PCI_L1SS_CAP_ASPM_L1_2         4    /* ASPM L1.2 Support */
114
+#define PCI_L1SS_CAP_ASPM_L1_1         8    /* ASPM L1.1 Support */
115
+#define PCI_L1SS_CAP_L1_PM_SS        16    /* L1 PM Substates Support */
116
+#define PCI_L1SS_CTL1         8    /* Control Register 1 */
117
+#define PCI_L1SS_CTL1_PCIPM_L1_2    1    /* PCI PM L1.2 Enable */
118
+#define PCI_L1SS_CTL1_PCIPM_L1_1    2    /* PCI PM L1.1 Support */
119
+#define PCI_L1SS_CTL1_ASPM_L1_2    4    /* ASPM L1.2 Support */
120
+#define PCI_L1SS_CTL1_ASPM_L1_1    8    /* ASPM L1.1 Support */
121
+#define PCI_L1SS_CTL1_L1SS_MASK    0x0000000F
122
+#define PCI_L1SS_CTL2         0xC    /* Control Register 2 */
123
+
124
#endif /* LINUX_PCI_REGS_H */
125
diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h
126
index XXXXXXX..XXXXXXX 100644
127
--- a/include/standard-headers/linux/virtio_ids.h
128
+++ b/include/standard-headers/linux/virtio_ids.h
129
@@ -XXX,XX +XXX,XX @@
130
#define VIRTIO_ID_INPUT 18 /* virtio input */
131
#define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */
132
#define VIRTIO_ID_CRYPTO 20 /* virtio crypto */
133
+
134
#endif /* _LINUX_VIRTIO_IDS_H */
135
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-headers/asm-arm/kvm.h
138
+++ b/linux-headers/asm-arm/kvm.h
139
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
140
/* Supported VGICv3 address types */
141
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
142
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
143
+#define KVM_VGIC_ITS_ADDR_TYPE        4
144
145
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
146
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
147
+#define KVM_VGIC_V3_ITS_SIZE        (2 * SZ_64K)
148
149
#define KVM_ARM_VCPU_POWER_OFF        0 /* CPU is started in OFF state */
150
#define KVM_ARM_VCPU_PSCI_0_2        1 /* CPU uses PSCI v0.2 */
151
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
152
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
153
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
154
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
155
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
156
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
157
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
158
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
159
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
160
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
161
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
162
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
163
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
164
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
165
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
166
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
167
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
168
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
169
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
170
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
171
+
172
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
173
174
/* KVM_IRQ_LINE irq field index values */
175
diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h
176
new file mode 100644
177
index XXXXXXX..XXXXXXX
178
--- /dev/null
179
+++ b/linux-headers/asm-arm/unistd-common.h
180
@@ -XXX,XX +XXX,XX @@
181
+#ifndef _ASM_ARM_UNISTD_COMMON_H
182
+#define _ASM_ARM_UNISTD_COMMON_H 1
183
+
184
+#define __NR_restart_syscall (__NR_SYSCALL_BASE + 0)
185
+#define __NR_exit (__NR_SYSCALL_BASE + 1)
186
+#define __NR_fork (__NR_SYSCALL_BASE + 2)
187
+#define __NR_read (__NR_SYSCALL_BASE + 3)
188
+#define __NR_write (__NR_SYSCALL_BASE + 4)
189
+#define __NR_open (__NR_SYSCALL_BASE + 5)
190
+#define __NR_close (__NR_SYSCALL_BASE + 6)
191
+#define __NR_creat (__NR_SYSCALL_BASE + 8)
192
+#define __NR_link (__NR_SYSCALL_BASE + 9)
193
+#define __NR_unlink (__NR_SYSCALL_BASE + 10)
194
+#define __NR_execve (__NR_SYSCALL_BASE + 11)
195
+#define __NR_chdir (__NR_SYSCALL_BASE + 12)
196
+#define __NR_mknod (__NR_SYSCALL_BASE + 14)
197
+#define __NR_chmod (__NR_SYSCALL_BASE + 15)
198
+#define __NR_lchown (__NR_SYSCALL_BASE + 16)
199
+#define __NR_lseek (__NR_SYSCALL_BASE + 19)
200
+#define __NR_getpid (__NR_SYSCALL_BASE + 20)
201
+#define __NR_mount (__NR_SYSCALL_BASE + 21)
202
+#define __NR_setuid (__NR_SYSCALL_BASE + 23)
203
+#define __NR_getuid (__NR_SYSCALL_BASE + 24)
204
+#define __NR_ptrace (__NR_SYSCALL_BASE + 26)
205
+#define __NR_pause (__NR_SYSCALL_BASE + 29)
206
+#define __NR_access (__NR_SYSCALL_BASE + 33)
207
+#define __NR_nice (__NR_SYSCALL_BASE + 34)
208
+#define __NR_sync (__NR_SYSCALL_BASE + 36)
209
+#define __NR_kill (__NR_SYSCALL_BASE + 37)
210
+#define __NR_rename (__NR_SYSCALL_BASE + 38)
211
+#define __NR_mkdir (__NR_SYSCALL_BASE + 39)
212
+#define __NR_rmdir (__NR_SYSCALL_BASE + 40)
213
+#define __NR_dup (__NR_SYSCALL_BASE + 41)
214
+#define __NR_pipe (__NR_SYSCALL_BASE + 42)
215
+#define __NR_times (__NR_SYSCALL_BASE + 43)
216
+#define __NR_brk (__NR_SYSCALL_BASE + 45)
217
+#define __NR_setgid (__NR_SYSCALL_BASE + 46)
218
+#define __NR_getgid (__NR_SYSCALL_BASE + 47)
219
+#define __NR_geteuid (__NR_SYSCALL_BASE + 49)
220
+#define __NR_getegid (__NR_SYSCALL_BASE + 50)
221
+#define __NR_acct (__NR_SYSCALL_BASE + 51)
222
+#define __NR_umount2 (__NR_SYSCALL_BASE + 52)
223
+#define __NR_ioctl (__NR_SYSCALL_BASE + 54)
224
+#define __NR_fcntl (__NR_SYSCALL_BASE + 55)
225
+#define __NR_setpgid (__NR_SYSCALL_BASE + 57)
226
+#define __NR_umask (__NR_SYSCALL_BASE + 60)
227
+#define __NR_chroot (__NR_SYSCALL_BASE + 61)
228
+#define __NR_ustat (__NR_SYSCALL_BASE + 62)
229
+#define __NR_dup2 (__NR_SYSCALL_BASE + 63)
230
+#define __NR_getppid (__NR_SYSCALL_BASE + 64)
231
+#define __NR_getpgrp (__NR_SYSCALL_BASE + 65)
232
+#define __NR_setsid (__NR_SYSCALL_BASE + 66)
233
+#define __NR_sigaction (__NR_SYSCALL_BASE + 67)
234
+#define __NR_setreuid (__NR_SYSCALL_BASE + 70)
235
+#define __NR_setregid (__NR_SYSCALL_BASE + 71)
236
+#define __NR_sigsuspend (__NR_SYSCALL_BASE + 72)
237
+#define __NR_sigpending (__NR_SYSCALL_BASE + 73)
238
+#define __NR_sethostname (__NR_SYSCALL_BASE + 74)
239
+#define __NR_setrlimit (__NR_SYSCALL_BASE + 75)
240
+#define __NR_getrusage (__NR_SYSCALL_BASE + 77)
241
+#define __NR_gettimeofday (__NR_SYSCALL_BASE + 78)
242
+#define __NR_settimeofday (__NR_SYSCALL_BASE + 79)
243
+#define __NR_getgroups (__NR_SYSCALL_BASE + 80)
244
+#define __NR_setgroups (__NR_SYSCALL_BASE + 81)
245
+#define __NR_symlink (__NR_SYSCALL_BASE + 83)
246
+#define __NR_readlink (__NR_SYSCALL_BASE + 85)
247
+#define __NR_uselib (__NR_SYSCALL_BASE + 86)
248
+#define __NR_swapon (__NR_SYSCALL_BASE + 87)
249
+#define __NR_reboot (__NR_SYSCALL_BASE + 88)
250
+#define __NR_munmap (__NR_SYSCALL_BASE + 91)
251
+#define __NR_truncate (__NR_SYSCALL_BASE + 92)
252
+#define __NR_ftruncate (__NR_SYSCALL_BASE + 93)
253
+#define __NR_fchmod (__NR_SYSCALL_BASE + 94)
254
+#define __NR_fchown (__NR_SYSCALL_BASE + 95)
255
+#define __NR_getpriority (__NR_SYSCALL_BASE + 96)
256
+#define __NR_setpriority (__NR_SYSCALL_BASE + 97)
257
+#define __NR_statfs (__NR_SYSCALL_BASE + 99)
258
+#define __NR_fstatfs (__NR_SYSCALL_BASE + 100)
259
+#define __NR_syslog (__NR_SYSCALL_BASE + 103)
260
+#define __NR_setitimer (__NR_SYSCALL_BASE + 104)
261
+#define __NR_getitimer (__NR_SYSCALL_BASE + 105)
262
+#define __NR_stat (__NR_SYSCALL_BASE + 106)
263
+#define __NR_lstat (__NR_SYSCALL_BASE + 107)
264
+#define __NR_fstat (__NR_SYSCALL_BASE + 108)
265
+#define __NR_vhangup (__NR_SYSCALL_BASE + 111)
266
+#define __NR_wait4 (__NR_SYSCALL_BASE + 114)
267
+#define __NR_swapoff (__NR_SYSCALL_BASE + 115)
268
+#define __NR_sysinfo (__NR_SYSCALL_BASE + 116)
269
+#define __NR_fsync (__NR_SYSCALL_BASE + 118)
270
+#define __NR_sigreturn (__NR_SYSCALL_BASE + 119)
271
+#define __NR_clone (__NR_SYSCALL_BASE + 120)
272
+#define __NR_setdomainname (__NR_SYSCALL_BASE + 121)
273
+#define __NR_uname (__NR_SYSCALL_BASE + 122)
274
+#define __NR_adjtimex (__NR_SYSCALL_BASE + 124)
275
+#define __NR_mprotect (__NR_SYSCALL_BASE + 125)
276
+#define __NR_sigprocmask (__NR_SYSCALL_BASE + 126)
277
+#define __NR_init_module (__NR_SYSCALL_BASE + 128)
278
+#define __NR_delete_module (__NR_SYSCALL_BASE + 129)
279
+#define __NR_quotactl (__NR_SYSCALL_BASE + 131)
280
+#define __NR_getpgid (__NR_SYSCALL_BASE + 132)
281
+#define __NR_fchdir (__NR_SYSCALL_BASE + 133)
282
+#define __NR_bdflush (__NR_SYSCALL_BASE + 134)
283
+#define __NR_sysfs (__NR_SYSCALL_BASE + 135)
284
+#define __NR_personality (__NR_SYSCALL_BASE + 136)
285
+#define __NR_setfsuid (__NR_SYSCALL_BASE + 138)
286
+#define __NR_setfsgid (__NR_SYSCALL_BASE + 139)
287
+#define __NR__llseek (__NR_SYSCALL_BASE + 140)
288
+#define __NR_getdents (__NR_SYSCALL_BASE + 141)
289
+#define __NR__newselect (__NR_SYSCALL_BASE + 142)
290
+#define __NR_flock (__NR_SYSCALL_BASE + 143)
291
+#define __NR_msync (__NR_SYSCALL_BASE + 144)
292
+#define __NR_readv (__NR_SYSCALL_BASE + 145)
293
+#define __NR_writev (__NR_SYSCALL_BASE + 146)
294
+#define __NR_getsid (__NR_SYSCALL_BASE + 147)
295
+#define __NR_fdatasync (__NR_SYSCALL_BASE + 148)
296
+#define __NR__sysctl (__NR_SYSCALL_BASE + 149)
297
+#define __NR_mlock (__NR_SYSCALL_BASE + 150)
298
+#define __NR_munlock (__NR_SYSCALL_BASE + 151)
299
+#define __NR_mlockall (__NR_SYSCALL_BASE + 152)
300
+#define __NR_munlockall (__NR_SYSCALL_BASE + 153)
301
+#define __NR_sched_setparam (__NR_SYSCALL_BASE + 154)
302
+#define __NR_sched_getparam (__NR_SYSCALL_BASE + 155)
303
+#define __NR_sched_setscheduler (__NR_SYSCALL_BASE + 156)
304
+#define __NR_sched_getscheduler (__NR_SYSCALL_BASE + 157)
305
+#define __NR_sched_yield (__NR_SYSCALL_BASE + 158)
306
+#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE + 159)
307
+#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE + 160)
308
+#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE + 161)
309
+#define __NR_nanosleep (__NR_SYSCALL_BASE + 162)
310
+#define __NR_mremap (__NR_SYSCALL_BASE + 163)
311
+#define __NR_setresuid (__NR_SYSCALL_BASE + 164)
312
+#define __NR_getresuid (__NR_SYSCALL_BASE + 165)
313
+#define __NR_poll (__NR_SYSCALL_BASE + 168)
314
+#define __NR_nfsservctl (__NR_SYSCALL_BASE + 169)
315
+#define __NR_setresgid (__NR_SYSCALL_BASE + 170)
316
+#define __NR_getresgid (__NR_SYSCALL_BASE + 171)
317
+#define __NR_prctl (__NR_SYSCALL_BASE + 172)
318
+#define __NR_rt_sigreturn (__NR_SYSCALL_BASE + 173)
319
+#define __NR_rt_sigaction (__NR_SYSCALL_BASE + 174)
320
+#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE + 175)
321
+#define __NR_rt_sigpending (__NR_SYSCALL_BASE + 176)
322
+#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE + 177)
323
+#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE + 178)
324
+#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE + 179)
325
+#define __NR_pread64 (__NR_SYSCALL_BASE + 180)
326
+#define __NR_pwrite64 (__NR_SYSCALL_BASE + 181)
327
+#define __NR_chown (__NR_SYSCALL_BASE + 182)
328
+#define __NR_getcwd (__NR_SYSCALL_BASE + 183)
329
+#define __NR_capget (__NR_SYSCALL_BASE + 184)
330
+#define __NR_capset (__NR_SYSCALL_BASE + 185)
331
+#define __NR_sigaltstack (__NR_SYSCALL_BASE + 186)
332
+#define __NR_sendfile (__NR_SYSCALL_BASE + 187)
333
+#define __NR_vfork (__NR_SYSCALL_BASE + 190)
334
+#define __NR_ugetrlimit (__NR_SYSCALL_BASE + 191)
335
+#define __NR_mmap2 (__NR_SYSCALL_BASE + 192)
336
+#define __NR_truncate64 (__NR_SYSCALL_BASE + 193)
337
+#define __NR_ftruncate64 (__NR_SYSCALL_BASE + 194)
338
+#define __NR_stat64 (__NR_SYSCALL_BASE + 195)
339
+#define __NR_lstat64 (__NR_SYSCALL_BASE + 196)
340
+#define __NR_fstat64 (__NR_SYSCALL_BASE + 197)
341
+#define __NR_lchown32 (__NR_SYSCALL_BASE + 198)
342
+#define __NR_getuid32 (__NR_SYSCALL_BASE + 199)
343
+#define __NR_getgid32 (__NR_SYSCALL_BASE + 200)
344
+#define __NR_geteuid32 (__NR_SYSCALL_BASE + 201)
345
+#define __NR_getegid32 (__NR_SYSCALL_BASE + 202)
346
+#define __NR_setreuid32 (__NR_SYSCALL_BASE + 203)
347
+#define __NR_setregid32 (__NR_SYSCALL_BASE + 204)
348
+#define __NR_getgroups32 (__NR_SYSCALL_BASE + 205)
349
+#define __NR_setgroups32 (__NR_SYSCALL_BASE + 206)
350
+#define __NR_fchown32 (__NR_SYSCALL_BASE + 207)
351
+#define __NR_setresuid32 (__NR_SYSCALL_BASE + 208)
352
+#define __NR_getresuid32 (__NR_SYSCALL_BASE + 209)
353
+#define __NR_setresgid32 (__NR_SYSCALL_BASE + 210)
354
+#define __NR_getresgid32 (__NR_SYSCALL_BASE + 211)
355
+#define __NR_chown32 (__NR_SYSCALL_BASE + 212)
356
+#define __NR_setuid32 (__NR_SYSCALL_BASE + 213)
357
+#define __NR_setgid32 (__NR_SYSCALL_BASE + 214)
358
+#define __NR_setfsuid32 (__NR_SYSCALL_BASE + 215)
359
+#define __NR_setfsgid32 (__NR_SYSCALL_BASE + 216)
360
+#define __NR_getdents64 (__NR_SYSCALL_BASE + 217)
361
+#define __NR_pivot_root (__NR_SYSCALL_BASE + 218)
362
+#define __NR_mincore (__NR_SYSCALL_BASE + 219)
363
+#define __NR_madvise (__NR_SYSCALL_BASE + 220)
364
+#define __NR_fcntl64 (__NR_SYSCALL_BASE + 221)
365
+#define __NR_gettid (__NR_SYSCALL_BASE + 224)
366
+#define __NR_readahead (__NR_SYSCALL_BASE + 225)
367
+#define __NR_setxattr (__NR_SYSCALL_BASE + 226)
368
+#define __NR_lsetxattr (__NR_SYSCALL_BASE + 227)
369
+#define __NR_fsetxattr (__NR_SYSCALL_BASE + 228)
370
+#define __NR_getxattr (__NR_SYSCALL_BASE + 229)
371
+#define __NR_lgetxattr (__NR_SYSCALL_BASE + 230)
372
+#define __NR_fgetxattr (__NR_SYSCALL_BASE + 231)
373
+#define __NR_listxattr (__NR_SYSCALL_BASE + 232)
374
+#define __NR_llistxattr (__NR_SYSCALL_BASE + 233)
375
+#define __NR_flistxattr (__NR_SYSCALL_BASE + 234)
376
+#define __NR_removexattr (__NR_SYSCALL_BASE + 235)
377
+#define __NR_lremovexattr (__NR_SYSCALL_BASE + 236)
378
+#define __NR_fremovexattr (__NR_SYSCALL_BASE + 237)
379
+#define __NR_tkill (__NR_SYSCALL_BASE + 238)
380
+#define __NR_sendfile64 (__NR_SYSCALL_BASE + 239)
381
+#define __NR_futex (__NR_SYSCALL_BASE + 240)
382
+#define __NR_sched_setaffinity (__NR_SYSCALL_BASE + 241)
383
+#define __NR_sched_getaffinity (__NR_SYSCALL_BASE + 242)
384
+#define __NR_io_setup (__NR_SYSCALL_BASE + 243)
385
+#define __NR_io_destroy (__NR_SYSCALL_BASE + 244)
386
+#define __NR_io_getevents (__NR_SYSCALL_BASE + 245)
387
+#define __NR_io_submit (__NR_SYSCALL_BASE + 246)
388
+#define __NR_io_cancel (__NR_SYSCALL_BASE + 247)
389
+#define __NR_exit_group (__NR_SYSCALL_BASE + 248)
390
+#define __NR_lookup_dcookie (__NR_SYSCALL_BASE + 249)
391
+#define __NR_epoll_create (__NR_SYSCALL_BASE + 250)
392
+#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 251)
393
+#define __NR_epoll_wait (__NR_SYSCALL_BASE + 252)
394
+#define __NR_remap_file_pages (__NR_SYSCALL_BASE + 253)
395
+#define __NR_set_tid_address (__NR_SYSCALL_BASE + 256)
396
+#define __NR_timer_create (__NR_SYSCALL_BASE + 257)
397
+#define __NR_timer_settime (__NR_SYSCALL_BASE + 258)
398
+#define __NR_timer_gettime (__NR_SYSCALL_BASE + 259)
399
+#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 260)
400
+#define __NR_timer_delete (__NR_SYSCALL_BASE + 261)
401
+#define __NR_clock_settime (__NR_SYSCALL_BASE + 262)
402
+#define __NR_clock_gettime (__NR_SYSCALL_BASE + 263)
403
+#define __NR_clock_getres (__NR_SYSCALL_BASE + 264)
404
+#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 265)
405
+#define __NR_statfs64 (__NR_SYSCALL_BASE + 266)
406
+#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 267)
407
+#define __NR_tgkill (__NR_SYSCALL_BASE + 268)
408
+#define __NR_utimes (__NR_SYSCALL_BASE + 269)
409
+#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE + 270)
410
+#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE + 271)
411
+#define __NR_pciconfig_read (__NR_SYSCALL_BASE + 272)
412
+#define __NR_pciconfig_write (__NR_SYSCALL_BASE + 273)
413
+#define __NR_mq_open (__NR_SYSCALL_BASE + 274)
414
+#define __NR_mq_unlink (__NR_SYSCALL_BASE + 275)
415
+#define __NR_mq_timedsend (__NR_SYSCALL_BASE + 276)
416
+#define __NR_mq_timedreceive (__NR_SYSCALL_BASE + 277)
417
+#define __NR_mq_notify (__NR_SYSCALL_BASE + 278)
418
+#define __NR_mq_getsetattr (__NR_SYSCALL_BASE + 279)
419
+#define __NR_waitid (__NR_SYSCALL_BASE + 280)
420
+#define __NR_socket (__NR_SYSCALL_BASE + 281)
421
+#define __NR_bind (__NR_SYSCALL_BASE + 282)
422
+#define __NR_connect (__NR_SYSCALL_BASE + 283)
423
+#define __NR_listen (__NR_SYSCALL_BASE + 284)
424
+#define __NR_accept (__NR_SYSCALL_BASE + 285)
425
+#define __NR_getsockname (__NR_SYSCALL_BASE + 286)
426
+#define __NR_getpeername (__NR_SYSCALL_BASE + 287)
427
+#define __NR_socketpair (__NR_SYSCALL_BASE + 288)
428
+#define __NR_send (__NR_SYSCALL_BASE + 289)
429
+#define __NR_sendto (__NR_SYSCALL_BASE + 290)
430
+#define __NR_recv (__NR_SYSCALL_BASE + 291)
431
+#define __NR_recvfrom (__NR_SYSCALL_BASE + 292)
432
+#define __NR_shutdown (__NR_SYSCALL_BASE + 293)
433
+#define __NR_setsockopt (__NR_SYSCALL_BASE + 294)
434
+#define __NR_getsockopt (__NR_SYSCALL_BASE + 295)
435
+#define __NR_sendmsg (__NR_SYSCALL_BASE + 296)
436
+#define __NR_recvmsg (__NR_SYSCALL_BASE + 297)
437
+#define __NR_semop (__NR_SYSCALL_BASE + 298)
438
+#define __NR_semget (__NR_SYSCALL_BASE + 299)
439
+#define __NR_semctl (__NR_SYSCALL_BASE + 300)
440
+#define __NR_msgsnd (__NR_SYSCALL_BASE + 301)
441
+#define __NR_msgrcv (__NR_SYSCALL_BASE + 302)
442
+#define __NR_msgget (__NR_SYSCALL_BASE + 303)
443
+#define __NR_msgctl (__NR_SYSCALL_BASE + 304)
444
+#define __NR_shmat (__NR_SYSCALL_BASE + 305)
445
+#define __NR_shmdt (__NR_SYSCALL_BASE + 306)
446
+#define __NR_shmget (__NR_SYSCALL_BASE + 307)
447
+#define __NR_shmctl (__NR_SYSCALL_BASE + 308)
448
+#define __NR_add_key (__NR_SYSCALL_BASE + 309)
449
+#define __NR_request_key (__NR_SYSCALL_BASE + 310)
450
+#define __NR_keyctl (__NR_SYSCALL_BASE + 311)
451
+#define __NR_semtimedop (__NR_SYSCALL_BASE + 312)
452
+#define __NR_vserver (__NR_SYSCALL_BASE + 313)
453
+#define __NR_ioprio_set (__NR_SYSCALL_BASE + 314)
454
+#define __NR_ioprio_get (__NR_SYSCALL_BASE + 315)
455
+#define __NR_inotify_init (__NR_SYSCALL_BASE + 316)
456
+#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 317)
457
+#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 318)
458
+#define __NR_mbind (__NR_SYSCALL_BASE + 319)
459
+#define __NR_get_mempolicy (__NR_SYSCALL_BASE + 320)
460
+#define __NR_set_mempolicy (__NR_SYSCALL_BASE + 321)
461
+#define __NR_openat (__NR_SYSCALL_BASE + 322)
462
+#define __NR_mkdirat (__NR_SYSCALL_BASE + 323)
463
+#define __NR_mknodat (__NR_SYSCALL_BASE + 324)
464
+#define __NR_fchownat (__NR_SYSCALL_BASE + 325)
465
+#define __NR_futimesat (__NR_SYSCALL_BASE + 326)
466
+#define __NR_fstatat64 (__NR_SYSCALL_BASE + 327)
467
+#define __NR_unlinkat (__NR_SYSCALL_BASE + 328)
468
+#define __NR_renameat (__NR_SYSCALL_BASE + 329)
469
+#define __NR_linkat (__NR_SYSCALL_BASE + 330)
470
+#define __NR_symlinkat (__NR_SYSCALL_BASE + 331)
471
+#define __NR_readlinkat (__NR_SYSCALL_BASE + 332)
472
+#define __NR_fchmodat (__NR_SYSCALL_BASE + 333)
473
+#define __NR_faccessat (__NR_SYSCALL_BASE + 334)
474
+#define __NR_pselect6 (__NR_SYSCALL_BASE + 335)
475
+#define __NR_ppoll (__NR_SYSCALL_BASE + 336)
476
+#define __NR_unshare (__NR_SYSCALL_BASE + 337)
477
+#define __NR_set_robust_list (__NR_SYSCALL_BASE + 338)
478
+#define __NR_get_robust_list (__NR_SYSCALL_BASE + 339)
479
+#define __NR_splice (__NR_SYSCALL_BASE + 340)
480
+#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE + 341)
481
+#define __NR_tee (__NR_SYSCALL_BASE + 342)
482
+#define __NR_vmsplice (__NR_SYSCALL_BASE + 343)
483
+#define __NR_move_pages (__NR_SYSCALL_BASE + 344)
484
+#define __NR_getcpu (__NR_SYSCALL_BASE + 345)
485
+#define __NR_epoll_pwait (__NR_SYSCALL_BASE + 346)
486
+#define __NR_kexec_load (__NR_SYSCALL_BASE + 347)
487
+#define __NR_utimensat (__NR_SYSCALL_BASE + 348)
488
+#define __NR_signalfd (__NR_SYSCALL_BASE + 349)
489
+#define __NR_timerfd_create (__NR_SYSCALL_BASE + 350)
490
+#define __NR_eventfd (__NR_SYSCALL_BASE + 351)
491
+#define __NR_fallocate (__NR_SYSCALL_BASE + 352)
492
+#define __NR_timerfd_settime (__NR_SYSCALL_BASE + 353)
493
+#define __NR_timerfd_gettime (__NR_SYSCALL_BASE + 354)
494
+#define __NR_signalfd4 (__NR_SYSCALL_BASE + 355)
495
+#define __NR_eventfd2 (__NR_SYSCALL_BASE + 356)
496
+#define __NR_epoll_create1 (__NR_SYSCALL_BASE + 357)
497
+#define __NR_dup3 (__NR_SYSCALL_BASE + 358)
498
+#define __NR_pipe2 (__NR_SYSCALL_BASE + 359)
499
+#define __NR_inotify_init1 (__NR_SYSCALL_BASE + 360)
500
+#define __NR_preadv (__NR_SYSCALL_BASE + 361)
501
+#define __NR_pwritev (__NR_SYSCALL_BASE + 362)
502
+#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE + 363)
503
+#define __NR_perf_event_open (__NR_SYSCALL_BASE + 364)
504
+#define __NR_recvmmsg (__NR_SYSCALL_BASE + 365)
505
+#define __NR_accept4 (__NR_SYSCALL_BASE + 366)
506
+#define __NR_fanotify_init (__NR_SYSCALL_BASE + 367)
507
+#define __NR_fanotify_mark (__NR_SYSCALL_BASE + 368)
508
+#define __NR_prlimit64 (__NR_SYSCALL_BASE + 369)
509
+#define __NR_name_to_handle_at (__NR_SYSCALL_BASE + 370)
510
+#define __NR_open_by_handle_at (__NR_SYSCALL_BASE + 371)
511
+#define __NR_clock_adjtime (__NR_SYSCALL_BASE + 372)
512
+#define __NR_syncfs (__NR_SYSCALL_BASE + 373)
513
+#define __NR_sendmmsg (__NR_SYSCALL_BASE + 374)
514
+#define __NR_setns (__NR_SYSCALL_BASE + 375)
515
+#define __NR_process_vm_readv (__NR_SYSCALL_BASE + 376)
516
+#define __NR_process_vm_writev (__NR_SYSCALL_BASE + 377)
517
+#define __NR_kcmp (__NR_SYSCALL_BASE + 378)
518
+#define __NR_finit_module (__NR_SYSCALL_BASE + 379)
519
+#define __NR_sched_setattr (__NR_SYSCALL_BASE + 380)
520
+#define __NR_sched_getattr (__NR_SYSCALL_BASE + 381)
521
+#define __NR_renameat2 (__NR_SYSCALL_BASE + 382)
522
+#define __NR_seccomp (__NR_SYSCALL_BASE + 383)
523
+#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
524
+#define __NR_memfd_create (__NR_SYSCALL_BASE + 385)
525
+#define __NR_bpf (__NR_SYSCALL_BASE + 386)
526
+#define __NR_execveat (__NR_SYSCALL_BASE + 387)
527
+#define __NR_userfaultfd (__NR_SYSCALL_BASE + 388)
528
+#define __NR_membarrier (__NR_SYSCALL_BASE + 389)
529
+#define __NR_mlock2 (__NR_SYSCALL_BASE + 390)
530
+#define __NR_copy_file_range (__NR_SYSCALL_BASE + 391)
531
+#define __NR_preadv2 (__NR_SYSCALL_BASE + 392)
532
+#define __NR_pwritev2 (__NR_SYSCALL_BASE + 393)
533
+#define __NR_pkey_mprotect (__NR_SYSCALL_BASE + 394)
534
+#define __NR_pkey_alloc (__NR_SYSCALL_BASE + 395)
535
+#define __NR_pkey_free (__NR_SYSCALL_BASE + 396)
536
+
537
+#endif /* _ASM_ARM_UNISTD_COMMON_H */
538
diff --git a/linux-headers/asm-arm/unistd-eabi.h b/linux-headers/asm-arm/unistd-eabi.h
539
new file mode 100644
540
index XXXXXXX..XXXXXXX
541
--- /dev/null
542
+++ b/linux-headers/asm-arm/unistd-eabi.h
543
@@ -XXX,XX +XXX,XX @@
544
+#ifndef _ASM_ARM_UNISTD_EABI_H
545
+#define _ASM_ARM_UNISTD_EABI_H 1
546
+
547
+
548
+#endif /* _ASM_ARM_UNISTD_EABI_H */
549
diff --git a/linux-headers/asm-arm/unistd-oabi.h b/linux-headers/asm-arm/unistd-oabi.h
550
new file mode 100644
551
index XXXXXXX..XXXXXXX
552
--- /dev/null
553
+++ b/linux-headers/asm-arm/unistd-oabi.h
554
@@ -XXX,XX +XXX,XX @@
555
+#ifndef _ASM_ARM_UNISTD_OABI_H
556
+#define _ASM_ARM_UNISTD_OABI_H 1
557
+
558
+#define __NR_time (__NR_SYSCALL_BASE + 13)
559
+#define __NR_umount (__NR_SYSCALL_BASE + 22)
560
+#define __NR_stime (__NR_SYSCALL_BASE + 25)
561
+#define __NR_alarm (__NR_SYSCALL_BASE + 27)
562
+#define __NR_utime (__NR_SYSCALL_BASE + 30)
563
+#define __NR_getrlimit (__NR_SYSCALL_BASE + 76)
564
+#define __NR_select (__NR_SYSCALL_BASE + 82)
565
+#define __NR_readdir (__NR_SYSCALL_BASE + 89)
566
+#define __NR_mmap (__NR_SYSCALL_BASE + 90)
567
+#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
568
+#define __NR_syscall (__NR_SYSCALL_BASE + 113)
569
+#define __NR_ipc (__NR_SYSCALL_BASE + 117)
570
+
571
+#endif /* _ASM_ARM_UNISTD_OABI_H */
572
diff --git a/linux-headers/asm-arm/unistd.h b/linux-headers/asm-arm/unistd.h
573
index XXXXXXX..XXXXXXX 100644
574
--- a/linux-headers/asm-arm/unistd.h
575
+++ b/linux-headers/asm-arm/unistd.h
576
@@ -XXX,XX +XXX,XX @@
577
578
#if defined(__thumb__) || defined(__ARM_EABI__)
579
#define __NR_SYSCALL_BASE    0
580
+#include <asm/unistd-eabi.h>
581
#else
582
#define __NR_SYSCALL_BASE    __NR_OABI_SYSCALL_BASE
583
+#include <asm/unistd-oabi.h>
584
#endif
585
586
-/*
587
- * This file contains the system call numbers.
588
- */
589
-
590
-#define __NR_restart_syscall        (__NR_SYSCALL_BASE+ 0)
591
-#define __NR_exit            (__NR_SYSCALL_BASE+ 1)
592
-#define __NR_fork            (__NR_SYSCALL_BASE+ 2)
593
-#define __NR_read            (__NR_SYSCALL_BASE+ 3)
594
-#define __NR_write            (__NR_SYSCALL_BASE+ 4)
595
-#define __NR_open            (__NR_SYSCALL_BASE+ 5)
596
-#define __NR_close            (__NR_SYSCALL_BASE+ 6)
597
-                    /* 7 was sys_waitpid */
598
-#define __NR_creat            (__NR_SYSCALL_BASE+ 8)
599
-#define __NR_link            (__NR_SYSCALL_BASE+ 9)
600
-#define __NR_unlink            (__NR_SYSCALL_BASE+ 10)
601
-#define __NR_execve            (__NR_SYSCALL_BASE+ 11)
602
-#define __NR_chdir            (__NR_SYSCALL_BASE+ 12)
603
-#define __NR_time            (__NR_SYSCALL_BASE+ 13)
604
-#define __NR_mknod            (__NR_SYSCALL_BASE+ 14)
605
-#define __NR_chmod            (__NR_SYSCALL_BASE+ 15)
606
-#define __NR_lchown            (__NR_SYSCALL_BASE+ 16)
607
-                    /* 17 was sys_break */
608
-                    /* 18 was sys_stat */
609
-#define __NR_lseek            (__NR_SYSCALL_BASE+ 19)
610
-#define __NR_getpid            (__NR_SYSCALL_BASE+ 20)
611
-#define __NR_mount            (__NR_SYSCALL_BASE+ 21)
612
-#define __NR_umount            (__NR_SYSCALL_BASE+ 22)
613
-#define __NR_setuid            (__NR_SYSCALL_BASE+ 23)
614
-#define __NR_getuid            (__NR_SYSCALL_BASE+ 24)
615
-#define __NR_stime            (__NR_SYSCALL_BASE+ 25)
616
-#define __NR_ptrace            (__NR_SYSCALL_BASE+ 26)
617
-#define __NR_alarm            (__NR_SYSCALL_BASE+ 27)
618
-                    /* 28 was sys_fstat */
619
-#define __NR_pause            (__NR_SYSCALL_BASE+ 29)
620
-#define __NR_utime            (__NR_SYSCALL_BASE+ 30)
621
-                    /* 31 was sys_stty */
622
-                    /* 32 was sys_gtty */
623
-#define __NR_access            (__NR_SYSCALL_BASE+ 33)
624
-#define __NR_nice            (__NR_SYSCALL_BASE+ 34)
625
-                    /* 35 was sys_ftime */
626
-#define __NR_sync            (__NR_SYSCALL_BASE+ 36)
627
-#define __NR_kill            (__NR_SYSCALL_BASE+ 37)
628
-#define __NR_rename            (__NR_SYSCALL_BASE+ 38)
629
-#define __NR_mkdir            (__NR_SYSCALL_BASE+ 39)
630
-#define __NR_rmdir            (__NR_SYSCALL_BASE+ 40)
631
-#define __NR_dup            (__NR_SYSCALL_BASE+ 41)
632
-#define __NR_pipe            (__NR_SYSCALL_BASE+ 42)
633
-#define __NR_times            (__NR_SYSCALL_BASE+ 43)
634
-                    /* 44 was sys_prof */
635
-#define __NR_brk            (__NR_SYSCALL_BASE+ 45)
636
-#define __NR_setgid            (__NR_SYSCALL_BASE+ 46)
637
-#define __NR_getgid            (__NR_SYSCALL_BASE+ 47)
638
-                    /* 48 was sys_signal */
639
-#define __NR_geteuid            (__NR_SYSCALL_BASE+ 49)
640
-#define __NR_getegid            (__NR_SYSCALL_BASE+ 50)
641
-#define __NR_acct            (__NR_SYSCALL_BASE+ 51)
642
-#define __NR_umount2            (__NR_SYSCALL_BASE+ 52)
643
-                    /* 53 was sys_lock */
644
-#define __NR_ioctl            (__NR_SYSCALL_BASE+ 54)
645
-#define __NR_fcntl            (__NR_SYSCALL_BASE+ 55)
646
-                    /* 56 was sys_mpx */
647
-#define __NR_setpgid            (__NR_SYSCALL_BASE+ 57)
648
-                    /* 58 was sys_ulimit */
649
-                    /* 59 was sys_olduname */
650
-#define __NR_umask            (__NR_SYSCALL_BASE+ 60)
651
-#define __NR_chroot            (__NR_SYSCALL_BASE+ 61)
652
-#define __NR_ustat            (__NR_SYSCALL_BASE+ 62)
653
-#define __NR_dup2            (__NR_SYSCALL_BASE+ 63)
654
-#define __NR_getppid            (__NR_SYSCALL_BASE+ 64)
655
-#define __NR_getpgrp            (__NR_SYSCALL_BASE+ 65)
656
-#define __NR_setsid            (__NR_SYSCALL_BASE+ 66)
657
-#define __NR_sigaction            (__NR_SYSCALL_BASE+ 67)
658
-                    /* 68 was sys_sgetmask */
659
-                    /* 69 was sys_ssetmask */
660
-#define __NR_setreuid            (__NR_SYSCALL_BASE+ 70)
661
-#define __NR_setregid            (__NR_SYSCALL_BASE+ 71)
662
-#define __NR_sigsuspend            (__NR_SYSCALL_BASE+ 72)
663
-#define __NR_sigpending            (__NR_SYSCALL_BASE+ 73)
664
-#define __NR_sethostname        (__NR_SYSCALL_BASE+ 74)
665
-#define __NR_setrlimit            (__NR_SYSCALL_BASE+ 75)
666
-#define __NR_getrlimit            (__NR_SYSCALL_BASE+ 76)    /* Back compat 2GB limited rlimit */
667
-#define __NR_getrusage            (__NR_SYSCALL_BASE+ 77)
668
-#define __NR_gettimeofday        (__NR_SYSCALL_BASE+ 78)
669
-#define __NR_settimeofday        (__NR_SYSCALL_BASE+ 79)
670
-#define __NR_getgroups            (__NR_SYSCALL_BASE+ 80)
671
-#define __NR_setgroups            (__NR_SYSCALL_BASE+ 81)
672
-#define __NR_select            (__NR_SYSCALL_BASE+ 82)
673
-#define __NR_symlink            (__NR_SYSCALL_BASE+ 83)
674
-                    /* 84 was sys_lstat */
675
-#define __NR_readlink            (__NR_SYSCALL_BASE+ 85)
676
-#define __NR_uselib            (__NR_SYSCALL_BASE+ 86)
677
-#define __NR_swapon            (__NR_SYSCALL_BASE+ 87)
678
-#define __NR_reboot            (__NR_SYSCALL_BASE+ 88)
679
-#define __NR_readdir            (__NR_SYSCALL_BASE+ 89)
680
-#define __NR_mmap            (__NR_SYSCALL_BASE+ 90)
681
-#define __NR_munmap            (__NR_SYSCALL_BASE+ 91)
682
-#define __NR_truncate            (__NR_SYSCALL_BASE+ 92)
683
-#define __NR_ftruncate            (__NR_SYSCALL_BASE+ 93)
684
-#define __NR_fchmod            (__NR_SYSCALL_BASE+ 94)
685
-#define __NR_fchown            (__NR_SYSCALL_BASE+ 95)
686
-#define __NR_getpriority        (__NR_SYSCALL_BASE+ 96)
687
-#define __NR_setpriority        (__NR_SYSCALL_BASE+ 97)
688
-                    /* 98 was sys_profil */
689
-#define __NR_statfs            (__NR_SYSCALL_BASE+ 99)
690
-#define __NR_fstatfs            (__NR_SYSCALL_BASE+100)
691
-                    /* 101 was sys_ioperm */
692
-#define __NR_socketcall            (__NR_SYSCALL_BASE+102)
693
-#define __NR_syslog            (__NR_SYSCALL_BASE+103)
694
-#define __NR_setitimer            (__NR_SYSCALL_BASE+104)
695
-#define __NR_getitimer            (__NR_SYSCALL_BASE+105)
696
-#define __NR_stat            (__NR_SYSCALL_BASE+106)
697
-#define __NR_lstat            (__NR_SYSCALL_BASE+107)
698
-#define __NR_fstat            (__NR_SYSCALL_BASE+108)
699
-                    /* 109 was sys_uname */
700
-                    /* 110 was sys_iopl */
701
-#define __NR_vhangup            (__NR_SYSCALL_BASE+111)
702
-                    /* 112 was sys_idle */
703
-#define __NR_syscall            (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
704
-#define __NR_wait4            (__NR_SYSCALL_BASE+114)
705
-#define __NR_swapoff            (__NR_SYSCALL_BASE+115)
706
-#define __NR_sysinfo            (__NR_SYSCALL_BASE+116)
707
-#define __NR_ipc            (__NR_SYSCALL_BASE+117)
708
-#define __NR_fsync            (__NR_SYSCALL_BASE+118)
709
-#define __NR_sigreturn            (__NR_SYSCALL_BASE+119)
710
-#define __NR_clone            (__NR_SYSCALL_BASE+120)
711
-#define __NR_setdomainname        (__NR_SYSCALL_BASE+121)
712
-#define __NR_uname            (__NR_SYSCALL_BASE+122)
713
-                    /* 123 was sys_modify_ldt */
714
-#define __NR_adjtimex            (__NR_SYSCALL_BASE+124)
715
-#define __NR_mprotect            (__NR_SYSCALL_BASE+125)
716
-#define __NR_sigprocmask        (__NR_SYSCALL_BASE+126)
717
-                    /* 127 was sys_create_module */
718
-#define __NR_init_module        (__NR_SYSCALL_BASE+128)
719
-#define __NR_delete_module        (__NR_SYSCALL_BASE+129)
720
-                    /* 130 was sys_get_kernel_syms */
721
-#define __NR_quotactl            (__NR_SYSCALL_BASE+131)
722
-#define __NR_getpgid            (__NR_SYSCALL_BASE+132)
723
-#define __NR_fchdir            (__NR_SYSCALL_BASE+133)
724
-#define __NR_bdflush            (__NR_SYSCALL_BASE+134)
725
-#define __NR_sysfs            (__NR_SYSCALL_BASE+135)
726
-#define __NR_personality        (__NR_SYSCALL_BASE+136)
727
-                    /* 137 was sys_afs_syscall */
728
-#define __NR_setfsuid            (__NR_SYSCALL_BASE+138)
729
-#define __NR_setfsgid            (__NR_SYSCALL_BASE+139)
730
-#define __NR__llseek            (__NR_SYSCALL_BASE+140)
731
-#define __NR_getdents            (__NR_SYSCALL_BASE+141)
732
-#define __NR__newselect            (__NR_SYSCALL_BASE+142)
733
-#define __NR_flock            (__NR_SYSCALL_BASE+143)
734
-#define __NR_msync            (__NR_SYSCALL_BASE+144)
735
-#define __NR_readv            (__NR_SYSCALL_BASE+145)
736
-#define __NR_writev            (__NR_SYSCALL_BASE+146)
737
-#define __NR_getsid            (__NR_SYSCALL_BASE+147)
738
-#define __NR_fdatasync            (__NR_SYSCALL_BASE+148)
739
-#define __NR__sysctl            (__NR_SYSCALL_BASE+149)
740
-#define __NR_mlock            (__NR_SYSCALL_BASE+150)
741
-#define __NR_munlock            (__NR_SYSCALL_BASE+151)
742
-#define __NR_mlockall            (__NR_SYSCALL_BASE+152)
743
-#define __NR_munlockall            (__NR_SYSCALL_BASE+153)
744
-#define __NR_sched_setparam        (__NR_SYSCALL_BASE+154)
745
-#define __NR_sched_getparam        (__NR_SYSCALL_BASE+155)
746
-#define __NR_sched_setscheduler        (__NR_SYSCALL_BASE+156)
747
-#define __NR_sched_getscheduler        (__NR_SYSCALL_BASE+157)
748
-#define __NR_sched_yield        (__NR_SYSCALL_BASE+158)
749
-#define __NR_sched_get_priority_max    (__NR_SYSCALL_BASE+159)
750
-#define __NR_sched_get_priority_min    (__NR_SYSCALL_BASE+160)
751
-#define __NR_sched_rr_get_interval    (__NR_SYSCALL_BASE+161)
752
-#define __NR_nanosleep            (__NR_SYSCALL_BASE+162)
753
-#define __NR_mremap            (__NR_SYSCALL_BASE+163)
754
-#define __NR_setresuid            (__NR_SYSCALL_BASE+164)
755
-#define __NR_getresuid            (__NR_SYSCALL_BASE+165)
756
-                    /* 166 was sys_vm86 */
757
-                    /* 167 was sys_query_module */
758
-#define __NR_poll            (__NR_SYSCALL_BASE+168)
759
-#define __NR_nfsservctl            (__NR_SYSCALL_BASE+169)
760
-#define __NR_setresgid            (__NR_SYSCALL_BASE+170)
761
-#define __NR_getresgid            (__NR_SYSCALL_BASE+171)
762
-#define __NR_prctl            (__NR_SYSCALL_BASE+172)
763
-#define __NR_rt_sigreturn        (__NR_SYSCALL_BASE+173)
764
-#define __NR_rt_sigaction        (__NR_SYSCALL_BASE+174)
765
-#define __NR_rt_sigprocmask        (__NR_SYSCALL_BASE+175)
766
-#define __NR_rt_sigpending        (__NR_SYSCALL_BASE+176)
767
-#define __NR_rt_sigtimedwait        (__NR_SYSCALL_BASE+177)
768
-#define __NR_rt_sigqueueinfo        (__NR_SYSCALL_BASE+178)
769
-#define __NR_rt_sigsuspend        (__NR_SYSCALL_BASE+179)
770
-#define __NR_pread64            (__NR_SYSCALL_BASE+180)
771
-#define __NR_pwrite64            (__NR_SYSCALL_BASE+181)
772
-#define __NR_chown            (__NR_SYSCALL_BASE+182)
773
-#define __NR_getcwd            (__NR_SYSCALL_BASE+183)
774
-#define __NR_capget            (__NR_SYSCALL_BASE+184)
775
-#define __NR_capset            (__NR_SYSCALL_BASE+185)
776
-#define __NR_sigaltstack        (__NR_SYSCALL_BASE+186)
777
-#define __NR_sendfile            (__NR_SYSCALL_BASE+187)
778
-                    /* 188 reserved */
779
-                    /* 189 reserved */
780
-#define __NR_vfork            (__NR_SYSCALL_BASE+190)
781
-#define __NR_ugetrlimit            (__NR_SYSCALL_BASE+191)    /* SuS compliant getrlimit */
782
-#define __NR_mmap2            (__NR_SYSCALL_BASE+192)
783
-#define __NR_truncate64            (__NR_SYSCALL_BASE+193)
784
-#define __NR_ftruncate64        (__NR_SYSCALL_BASE+194)
785
-#define __NR_stat64            (__NR_SYSCALL_BASE+195)
786
-#define __NR_lstat64            (__NR_SYSCALL_BASE+196)
787
-#define __NR_fstat64            (__NR_SYSCALL_BASE+197)
788
-#define __NR_lchown32            (__NR_SYSCALL_BASE+198)
789
-#define __NR_getuid32            (__NR_SYSCALL_BASE+199)
790
-#define __NR_getgid32            (__NR_SYSCALL_BASE+200)
791
-#define __NR_geteuid32            (__NR_SYSCALL_BASE+201)
792
-#define __NR_getegid32            (__NR_SYSCALL_BASE+202)
793
-#define __NR_setreuid32            (__NR_SYSCALL_BASE+203)
794
-#define __NR_setregid32            (__NR_SYSCALL_BASE+204)
795
-#define __NR_getgroups32        (__NR_SYSCALL_BASE+205)
796
-#define __NR_setgroups32        (__NR_SYSCALL_BASE+206)
797
-#define __NR_fchown32            (__NR_SYSCALL_BASE+207)
798
-#define __NR_setresuid32        (__NR_SYSCALL_BASE+208)
799
-#define __NR_getresuid32        (__NR_SYSCALL_BASE+209)
800
-#define __NR_setresgid32        (__NR_SYSCALL_BASE+210)
801
-#define __NR_getresgid32        (__NR_SYSCALL_BASE+211)
802
-#define __NR_chown32            (__NR_SYSCALL_BASE+212)
803
-#define __NR_setuid32            (__NR_SYSCALL_BASE+213)
804
-#define __NR_setgid32            (__NR_SYSCALL_BASE+214)
805
-#define __NR_setfsuid32            (__NR_SYSCALL_BASE+215)
806
-#define __NR_setfsgid32            (__NR_SYSCALL_BASE+216)
807
-#define __NR_getdents64            (__NR_SYSCALL_BASE+217)
808
-#define __NR_pivot_root            (__NR_SYSCALL_BASE+218)
809
-#define __NR_mincore            (__NR_SYSCALL_BASE+219)
810
-#define __NR_madvise            (__NR_SYSCALL_BASE+220)
811
-#define __NR_fcntl64            (__NR_SYSCALL_BASE+221)
812
-                    /* 222 for tux */
813
-                    /* 223 is unused */
814
-#define __NR_gettid            (__NR_SYSCALL_BASE+224)
815
-#define __NR_readahead            (__NR_SYSCALL_BASE+225)
816
-#define __NR_setxattr            (__NR_SYSCALL_BASE+226)
817
-#define __NR_lsetxattr            (__NR_SYSCALL_BASE+227)
818
-#define __NR_fsetxattr            (__NR_SYSCALL_BASE+228)
819
-#define __NR_getxattr            (__NR_SYSCALL_BASE+229)
820
-#define __NR_lgetxattr            (__NR_SYSCALL_BASE+230)
821
-#define __NR_fgetxattr            (__NR_SYSCALL_BASE+231)
822
-#define __NR_listxattr            (__NR_SYSCALL_BASE+232)
823
-#define __NR_llistxattr            (__NR_SYSCALL_BASE+233)
824
-#define __NR_flistxattr            (__NR_SYSCALL_BASE+234)
825
-#define __NR_removexattr        (__NR_SYSCALL_BASE+235)
826
-#define __NR_lremovexattr        (__NR_SYSCALL_BASE+236)
827
-#define __NR_fremovexattr        (__NR_SYSCALL_BASE+237)
828
-#define __NR_tkill            (__NR_SYSCALL_BASE+238)
829
-#define __NR_sendfile64            (__NR_SYSCALL_BASE+239)
830
-#define __NR_futex            (__NR_SYSCALL_BASE+240)
831
-#define __NR_sched_setaffinity        (__NR_SYSCALL_BASE+241)
832
-#define __NR_sched_getaffinity        (__NR_SYSCALL_BASE+242)
833
-#define __NR_io_setup            (__NR_SYSCALL_BASE+243)
834
-#define __NR_io_destroy            (__NR_SYSCALL_BASE+244)
835
-#define __NR_io_getevents        (__NR_SYSCALL_BASE+245)
836
-#define __NR_io_submit            (__NR_SYSCALL_BASE+246)
837
-#define __NR_io_cancel            (__NR_SYSCALL_BASE+247)
838
-#define __NR_exit_group            (__NR_SYSCALL_BASE+248)
839
-#define __NR_lookup_dcookie        (__NR_SYSCALL_BASE+249)
840
-#define __NR_epoll_create        (__NR_SYSCALL_BASE+250)
841
-#define __NR_epoll_ctl            (__NR_SYSCALL_BASE+251)
842
-#define __NR_epoll_wait            (__NR_SYSCALL_BASE+252)
843
-#define __NR_remap_file_pages        (__NR_SYSCALL_BASE+253)
844
-                    /* 254 for set_thread_area */
845
-                    /* 255 for get_thread_area */
846
-#define __NR_set_tid_address        (__NR_SYSCALL_BASE+256)
847
-#define __NR_timer_create        (__NR_SYSCALL_BASE+257)
848
-#define __NR_timer_settime        (__NR_SYSCALL_BASE+258)
849
-#define __NR_timer_gettime        (__NR_SYSCALL_BASE+259)
850
-#define __NR_timer_getoverrun        (__NR_SYSCALL_BASE+260)
851
-#define __NR_timer_delete        (__NR_SYSCALL_BASE+261)
852
-#define __NR_clock_settime        (__NR_SYSCALL_BASE+262)
853
-#define __NR_clock_gettime        (__NR_SYSCALL_BASE+263)
854
-#define __NR_clock_getres        (__NR_SYSCALL_BASE+264)
855
-#define __NR_clock_nanosleep        (__NR_SYSCALL_BASE+265)
856
-#define __NR_statfs64            (__NR_SYSCALL_BASE+266)
857
-#define __NR_fstatfs64            (__NR_SYSCALL_BASE+267)
858
-#define __NR_tgkill            (__NR_SYSCALL_BASE+268)
859
-#define __NR_utimes            (__NR_SYSCALL_BASE+269)
860
-#define __NR_arm_fadvise64_64        (__NR_SYSCALL_BASE+270)
861
-#define __NR_pciconfig_iobase        (__NR_SYSCALL_BASE+271)
862
-#define __NR_pciconfig_read        (__NR_SYSCALL_BASE+272)
863
-#define __NR_pciconfig_write        (__NR_SYSCALL_BASE+273)
864
-#define __NR_mq_open            (__NR_SYSCALL_BASE+274)
865
-#define __NR_mq_unlink            (__NR_SYSCALL_BASE+275)
866
-#define __NR_mq_timedsend        (__NR_SYSCALL_BASE+276)
867
-#define __NR_mq_timedreceive        (__NR_SYSCALL_BASE+277)
868
-#define __NR_mq_notify            (__NR_SYSCALL_BASE+278)
869
-#define __NR_mq_getsetattr        (__NR_SYSCALL_BASE+279)
870
-#define __NR_waitid            (__NR_SYSCALL_BASE+280)
871
-#define __NR_socket            (__NR_SYSCALL_BASE+281)
872
-#define __NR_bind            (__NR_SYSCALL_BASE+282)
873
-#define __NR_connect            (__NR_SYSCALL_BASE+283)
874
-#define __NR_listen            (__NR_SYSCALL_BASE+284)
875
-#define __NR_accept            (__NR_SYSCALL_BASE+285)
876
-#define __NR_getsockname        (__NR_SYSCALL_BASE+286)
877
-#define __NR_getpeername        (__NR_SYSCALL_BASE+287)
878
-#define __NR_socketpair            (__NR_SYSCALL_BASE+288)
879
-#define __NR_send            (__NR_SYSCALL_BASE+289)
880
-#define __NR_sendto            (__NR_SYSCALL_BASE+290)
881
-#define __NR_recv            (__NR_SYSCALL_BASE+291)
882
-#define __NR_recvfrom            (__NR_SYSCALL_BASE+292)
883
-#define __NR_shutdown            (__NR_SYSCALL_BASE+293)
884
-#define __NR_setsockopt            (__NR_SYSCALL_BASE+294)
885
-#define __NR_getsockopt            (__NR_SYSCALL_BASE+295)
886
-#define __NR_sendmsg            (__NR_SYSCALL_BASE+296)
887
-#define __NR_recvmsg            (__NR_SYSCALL_BASE+297)
888
-#define __NR_semop            (__NR_SYSCALL_BASE+298)
889
-#define __NR_semget            (__NR_SYSCALL_BASE+299)
890
-#define __NR_semctl            (__NR_SYSCALL_BASE+300)
891
-#define __NR_msgsnd            (__NR_SYSCALL_BASE+301)
892
-#define __NR_msgrcv            (__NR_SYSCALL_BASE+302)
893
-#define __NR_msgget            (__NR_SYSCALL_BASE+303)
894
-#define __NR_msgctl            (__NR_SYSCALL_BASE+304)
895
-#define __NR_shmat            (__NR_SYSCALL_BASE+305)
896
-#define __NR_shmdt            (__NR_SYSCALL_BASE+306)
897
-#define __NR_shmget            (__NR_SYSCALL_BASE+307)
898
-#define __NR_shmctl            (__NR_SYSCALL_BASE+308)
899
-#define __NR_add_key            (__NR_SYSCALL_BASE+309)
900
-#define __NR_request_key        (__NR_SYSCALL_BASE+310)
901
-#define __NR_keyctl            (__NR_SYSCALL_BASE+311)
902
-#define __NR_semtimedop            (__NR_SYSCALL_BASE+312)
903
-#define __NR_vserver            (__NR_SYSCALL_BASE+313)
904
-#define __NR_ioprio_set            (__NR_SYSCALL_BASE+314)
905
-#define __NR_ioprio_get            (__NR_SYSCALL_BASE+315)
906
-#define __NR_inotify_init        (__NR_SYSCALL_BASE+316)
907
-#define __NR_inotify_add_watch        (__NR_SYSCALL_BASE+317)
908
-#define __NR_inotify_rm_watch        (__NR_SYSCALL_BASE+318)
909
-#define __NR_mbind            (__NR_SYSCALL_BASE+319)
910
-#define __NR_get_mempolicy        (__NR_SYSCALL_BASE+320)
911
-#define __NR_set_mempolicy        (__NR_SYSCALL_BASE+321)
912
-#define __NR_openat            (__NR_SYSCALL_BASE+322)
913
-#define __NR_mkdirat            (__NR_SYSCALL_BASE+323)
914
-#define __NR_mknodat            (__NR_SYSCALL_BASE+324)
915
-#define __NR_fchownat            (__NR_SYSCALL_BASE+325)
916
-#define __NR_futimesat            (__NR_SYSCALL_BASE+326)
917
-#define __NR_fstatat64            (__NR_SYSCALL_BASE+327)
918
-#define __NR_unlinkat            (__NR_SYSCALL_BASE+328)
919
-#define __NR_renameat            (__NR_SYSCALL_BASE+329)
920
-#define __NR_linkat            (__NR_SYSCALL_BASE+330)
921
-#define __NR_symlinkat            (__NR_SYSCALL_BASE+331)
922
-#define __NR_readlinkat            (__NR_SYSCALL_BASE+332)
923
-#define __NR_fchmodat            (__NR_SYSCALL_BASE+333)
924
-#define __NR_faccessat            (__NR_SYSCALL_BASE+334)
925
-#define __NR_pselect6            (__NR_SYSCALL_BASE+335)
926
-#define __NR_ppoll            (__NR_SYSCALL_BASE+336)
927
-#define __NR_unshare            (__NR_SYSCALL_BASE+337)
928
-#define __NR_set_robust_list        (__NR_SYSCALL_BASE+338)
929
-#define __NR_get_robust_list        (__NR_SYSCALL_BASE+339)
930
-#define __NR_splice            (__NR_SYSCALL_BASE+340)
931
-#define __NR_arm_sync_file_range    (__NR_SYSCALL_BASE+341)
932
+#include <asm/unistd-common.h>
933
#define __NR_sync_file_range2        __NR_arm_sync_file_range
934
-#define __NR_tee            (__NR_SYSCALL_BASE+342)
935
-#define __NR_vmsplice            (__NR_SYSCALL_BASE+343)
936
-#define __NR_move_pages            (__NR_SYSCALL_BASE+344)
937
-#define __NR_getcpu            (__NR_SYSCALL_BASE+345)
938
-#define __NR_epoll_pwait        (__NR_SYSCALL_BASE+346)
939
-#define __NR_kexec_load            (__NR_SYSCALL_BASE+347)
940
-#define __NR_utimensat            (__NR_SYSCALL_BASE+348)
941
-#define __NR_signalfd            (__NR_SYSCALL_BASE+349)
942
-#define __NR_timerfd_create        (__NR_SYSCALL_BASE+350)
943
-#define __NR_eventfd            (__NR_SYSCALL_BASE+351)
944
-#define __NR_fallocate            (__NR_SYSCALL_BASE+352)
945
-#define __NR_timerfd_settime        (__NR_SYSCALL_BASE+353)
946
-#define __NR_timerfd_gettime        (__NR_SYSCALL_BASE+354)
947
-#define __NR_signalfd4            (__NR_SYSCALL_BASE+355)
948
-#define __NR_eventfd2            (__NR_SYSCALL_BASE+356)
949
-#define __NR_epoll_create1        (__NR_SYSCALL_BASE+357)
950
-#define __NR_dup3            (__NR_SYSCALL_BASE+358)
951
-#define __NR_pipe2            (__NR_SYSCALL_BASE+359)
952
-#define __NR_inotify_init1        (__NR_SYSCALL_BASE+360)
953
-#define __NR_preadv            (__NR_SYSCALL_BASE+361)
954
-#define __NR_pwritev            (__NR_SYSCALL_BASE+362)
955
-#define __NR_rt_tgsigqueueinfo        (__NR_SYSCALL_BASE+363)
956
-#define __NR_perf_event_open        (__NR_SYSCALL_BASE+364)
957
-#define __NR_recvmmsg            (__NR_SYSCALL_BASE+365)
958
-#define __NR_accept4            (__NR_SYSCALL_BASE+366)
959
-#define __NR_fanotify_init        (__NR_SYSCALL_BASE+367)
960
-#define __NR_fanotify_mark        (__NR_SYSCALL_BASE+368)
961
-#define __NR_prlimit64            (__NR_SYSCALL_BASE+369)
962
-#define __NR_name_to_handle_at        (__NR_SYSCALL_BASE+370)
963
-#define __NR_open_by_handle_at        (__NR_SYSCALL_BASE+371)
964
-#define __NR_clock_adjtime        (__NR_SYSCALL_BASE+372)
965
-#define __NR_syncfs            (__NR_SYSCALL_BASE+373)
966
-#define __NR_sendmmsg            (__NR_SYSCALL_BASE+374)
967
-#define __NR_setns            (__NR_SYSCALL_BASE+375)
968
-#define __NR_process_vm_readv        (__NR_SYSCALL_BASE+376)
969
-#define __NR_process_vm_writev        (__NR_SYSCALL_BASE+377)
970
-#define __NR_kcmp            (__NR_SYSCALL_BASE+378)
971
-#define __NR_finit_module        (__NR_SYSCALL_BASE+379)
972
-#define __NR_sched_setattr        (__NR_SYSCALL_BASE+380)
973
-#define __NR_sched_getattr        (__NR_SYSCALL_BASE+381)
974
-#define __NR_renameat2            (__NR_SYSCALL_BASE+382)
975
-#define __NR_seccomp            (__NR_SYSCALL_BASE+383)
976
-#define __NR_getrandom            (__NR_SYSCALL_BASE+384)
977
-#define __NR_memfd_create        (__NR_SYSCALL_BASE+385)
978
-#define __NR_bpf            (__NR_SYSCALL_BASE+386)
979
-#define __NR_execveat            (__NR_SYSCALL_BASE+387)
980
-#define __NR_userfaultfd        (__NR_SYSCALL_BASE+388)
981
-#define __NR_membarrier            (__NR_SYSCALL_BASE+389)
982
-#define __NR_mlock2            (__NR_SYSCALL_BASE+390)
983
-#define __NR_copy_file_range        (__NR_SYSCALL_BASE+391)
984
-#define __NR_preadv2            (__NR_SYSCALL_BASE+392)
985
-#define __NR_pwritev2            (__NR_SYSCALL_BASE+393)
986
987
/*
988
* The following SWIs are ARM private.
989
@@ -XXX,XX +XXX,XX @@
990
#define __ARM_NR_usr32            (__ARM_NR_BASE+4)
991
#define __ARM_NR_set_tls        (__ARM_NR_BASE+5)
992
993
-/*
994
- * The following syscalls are obsolete and no longer available for EABI.
995
- */
996
-#if defined(__ARM_EABI__)
997
-#undef __NR_time
998
-#undef __NR_umount
999
-#undef __NR_stime
1000
-#undef __NR_alarm
1001
-#undef __NR_utime
1002
-#undef __NR_getrlimit
1003
-#undef __NR_select
1004
-#undef __NR_readdir
1005
-#undef __NR_mmap
1006
-#undef __NR_socketcall
1007
-#undef __NR_syscall
1008
-#undef __NR_ipc
1009
-#endif
1010
-
1011
#endif /* __ASM_ARM_UNISTD_H */
1012
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
1013
index XXXXXXX..XXXXXXX 100644
1014
--- a/linux-headers/asm-arm64/kvm.h
1015
+++ b/linux-headers/asm-arm64/kvm.h
1016
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
1017
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
1018
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
1019
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
1020
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
1021
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
1022
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
1023
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
1024
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
1025
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
1026
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
1027
#define KVM_DEV_ARM_VGIC_GRP_CTRL    4
1028
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
1029
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
1030
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
1031
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
1032
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
1033
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
1034
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK    0x3ff
1035
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
1036
+
1037
#define KVM_DEV_ARM_VGIC_CTRL_INIT    0
1038
1039
/* Device Control API on vcpu fd */
1040
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
1041
index XXXXXXX..XXXXXXX 100644
1042
--- a/linux-headers/asm-powerpc/kvm.h
1043
+++ b/linux-headers/asm-powerpc/kvm.h
1044
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1045
    __u16    n_invalid;
1046
};
1047
1048
+/* For KVM_PPC_CONFIGURE_V3_MMU */
1049
+struct kvm_ppc_mmuv3_cfg {
1050
+    __u64    flags;
1051
+    __u64    process_table;    /* second doubleword of partition table entry */
1052
+};
1053
+
1054
+/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
1055
+#define KVM_PPC_MMUV3_RADIX    1    /* 1 = radix mode, 0 = HPT */
1056
+#define KVM_PPC_MMUV3_GTSE    2    /* global translation shootdown enb. */
1057
+
1058
+/* For KVM_PPC_GET_RMMU_INFO */
1059
+struct kvm_ppc_rmmu_info {
1060
+    struct kvm_ppc_radix_geom {
1061
+        __u8    page_shift;
1062
+        __u8    level_bits[4];
1063
+        __u8    pad[3];
1064
+    }    geometries[8];
1065
+    __u32    ap_encodings[8];
1066
+};
1067
+
1068
/* Per-vcpu XICS interrupt controller state */
1069
#define KVM_REG_PPC_ICP_STATE    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
1070
1071
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1072
#define KVM_REG_PPC_SPRG9    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
1073
#define KVM_REG_PPC_DBSR    (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
1074
1075
+/* POWER9 registers */
1076
+#define KVM_REG_PPC_TIDR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
1077
+#define KVM_REG_PPC_PSSCR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
1078
+
1079
/* Transactional Memory checkpointed state:
1080
* This is all GPRs, all VSX regs and a subset of SPRs
1081
*/
1082
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1083
#define KVM_REG_PPC_TM_VSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
1084
#define KVM_REG_PPC_TM_DSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
1085
#define KVM_REG_PPC_TM_TAR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
1086
+#define KVM_REG_PPC_TM_XER    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
1087
1088
/* PPC64 eXternal Interrupt Controller Specification */
1089
#define KVM_DEV_XICS_GRP_SOURCES    1    /* 64-bit source attributes */
1090
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1091
#define KVM_XICS_LEVEL_SENSITIVE    (1ULL << 40)
1092
#define KVM_XICS_MASKED        (1ULL << 41)
1093
#define KVM_XICS_PENDING        (1ULL << 42)
1094
+#define KVM_XICS_PRESENTED        (1ULL << 43)
1095
+#define KVM_XICS_QUEUED        (1ULL << 44)
1096
1097
#endif /* __LINUX_KVM_POWERPC_H */
1098
diff --git a/linux-headers/asm-powerpc/unistd.h b/linux-headers/asm-powerpc/unistd.h
1099
index XXXXXXX..XXXXXXX 100644
1100
--- a/linux-headers/asm-powerpc/unistd.h
1101
+++ b/linux-headers/asm-powerpc/unistd.h
1102
@@ -XXX,XX +XXX,XX @@
1103
#define __NR_copy_file_range    379
1104
#define __NR_preadv2        380
1105
#define __NR_pwritev2        381
1106
+#define __NR_kexec_file_load    382
1107
1108
#endif /* _ASM_POWERPC_UNISTD_H_ */
1109
diff --git a/linux-headers/asm-x86/kvm_para.h b/linux-headers/asm-x86/kvm_para.h
1110
index XXXXXXX..XXXXXXX 100644
1111
--- a/linux-headers/asm-x86/kvm_para.h
1112
+++ b/linux-headers/asm-x86/kvm_para.h
1113
@@ -XXX,XX +XXX,XX @@ struct kvm_steal_time {
1114
    __u64 steal;
1115
    __u32 version;
1116
    __u32 flags;
1117
-    __u32 pad[12];
1118
+    __u8 preempted;
1119
+    __u8 u8_pad[3];
1120
+    __u32 pad[11];
1121
+};
1122
+
1123
+#define KVM_CLOCK_PAIRING_WALLCLOCK 0
1124
+struct kvm_clock_pairing {
1125
+    __s64 sec;
1126
+    __s64 nsec;
1127
+    __u64 tsc;
1128
+    __u32 flags;
1129
+    __u32 pad[9];
1130
};
1131
1132
#define KVM_STEAL_ALIGNMENT_BITS 5
1133
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/linux-headers/linux/kvm.h
1136
+++ b/linux-headers/linux/kvm.h
1137
@@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit {
1138
struct kvm_run {
1139
    /* in */
1140
    __u8 request_interrupt_window;
1141
-    __u8 padding1[7];
1142
+    __u8 immediate_exit;
1143
+    __u8 padding1[6];
1144
1145
    /* out */
1146
    __u32 exit_reason;
1147
@@ -XXX,XX +XXX,XX @@ struct kvm_enable_cap {
1148
};
1149
1150
/* for KVM_PPC_GET_PVINFO */
1151
+
1152
+#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1153
+
1154
struct kvm_ppc_pvinfo {
1155
    /* out */
1156
    __u32 flags;
1157
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1158
    struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
1159
};
1160
1161
-#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1162
+/* for KVM_PPC_RESIZE_HPT_{PREPARE,COMMIT} */
1163
+struct kvm_ppc_resize_hpt {
1164
+    __u64 flags;
1165
+    __u32 shift;
1166
+    __u32 pad;
1167
+};
1168
1169
#define KVMIO 0xAE
1170
1171
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1172
#define KVM_CAP_S390_USER_INSTR0 130
1173
#define KVM_CAP_MSI_DEVID 131
1174
#define KVM_CAP_PPC_HTM 132
1175
+#define KVM_CAP_SPAPR_RESIZE_HPT 133
1176
+#define KVM_CAP_PPC_MMU_RADIX 134
1177
+#define KVM_CAP_PPC_MMU_HASH_V3 135
1178
+#define KVM_CAP_IMMEDIATE_EXIT 136
1179
1180
#ifdef KVM_CAP_IRQ_ROUTING
1181
1182
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
1183
#define KVM_ARM_SET_DEVICE_ADDR     _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
1184
/* Available with KVM_CAP_PPC_RTAS */
1185
#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
1186
+/* Available with KVM_CAP_SPAPR_RESIZE_HPT */
1187
+#define KVM_PPC_RESIZE_HPT_PREPARE _IOR(KVMIO, 0xad, struct kvm_ppc_resize_hpt)
1188
+#define KVM_PPC_RESIZE_HPT_COMMIT _IOR(KVMIO, 0xae, struct kvm_ppc_resize_hpt)
1189
+/* Available with KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3 */
1190
+#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
1191
+/* Available with KVM_CAP_PPC_RADIX_MMU */
1192
+#define KVM_PPC_GET_RMMU_INFO     _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
1193
1194
/* ioctl for vm fd */
1195
#define KVM_CREATE_DEVICE     _IOWR(KVMIO, 0xe0, struct kvm_create_device)
1196
diff --git a/linux-headers/linux/kvm_para.h b/linux-headers/linux/kvm_para.h
1197
index XXXXXXX..XXXXXXX 100644
1198
--- a/linux-headers/linux/kvm_para.h
1199
+++ b/linux-headers/linux/kvm_para.h
1200
@@ -XXX,XX +XXX,XX @@
1201
#define KVM_EFAULT        EFAULT
1202
#define KVM_E2BIG        E2BIG
1203
#define KVM_EPERM        EPERM
1204
+#define KVM_EOPNOTSUPP        95
1205
1206
#define KVM_HC_VAPIC_POLL_IRQ        1
1207
#define KVM_HC_MMU_OP            2
1208
@@ -XXX,XX +XXX,XX @@
1209
#define KVM_HC_MIPS_GET_CLOCK_FREQ    6
1210
#define KVM_HC_MIPS_EXIT_VM        7
1211
#define KVM_HC_MIPS_CONSOLE_OUTPUT    8
1212
+#define KVM_HC_CLOCK_PAIRING        9
1213
1214
/*
1215
* hypercalls use architecture specific
1216
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
1217
index XXXXXXX..XXXXXXX 100644
1218
--- a/linux-headers/linux/userfaultfd.h
1219
+++ b/linux-headers/linux/userfaultfd.h
1220
@@ -XXX,XX +XXX,XX @@
1221
1222
#include <linux/types.h>
1223
1224
-#define UFFD_API ((__u64)0xAA)
1225
/*
1226
- * After implementing the respective features it will become:
1227
- * #define UFFD_API_FEATURES (UFFD_FEATURE_PAGEFAULT_FLAG_WP | \
1228
- *             UFFD_FEATURE_EVENT_FORK)
1229
+ * If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and
1230
+ * UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In
1231
+ * userfaultfd.h we assumed the kernel was reading (instead _IOC_READ
1232
+ * means the userland is reading).
1233
*/
1234
-#define UFFD_API_FEATURES (0)
1235
+#define UFFD_API ((__u64)0xAA)
1236
+#define UFFD_API_FEATURES (UFFD_FEATURE_EVENT_FORK |        \
1237
+             UFFD_FEATURE_EVENT_REMAP |        \
1238
+             UFFD_FEATURE_EVENT_MADVDONTNEED |    \
1239
+             UFFD_FEATURE_MISSING_HUGETLBFS |    \
1240
+             UFFD_FEATURE_MISSING_SHMEM)
1241
#define UFFD_API_IOCTLS                \
1242
    ((__u64)1 << _UFFDIO_REGISTER |        \
1243
     (__u64)1 << _UFFDIO_UNREGISTER |    \
1244
@@ -XXX,XX +XXX,XX @@
1245
    ((__u64)1 << _UFFDIO_WAKE |        \
1246
     (__u64)1 << _UFFDIO_COPY |        \
1247
     (__u64)1 << _UFFDIO_ZEROPAGE)
1248
+#define UFFD_API_RANGE_IOCTLS_BASIC        \
1249
+    ((__u64)1 << _UFFDIO_WAKE |        \
1250
+     (__u64)1 << _UFFDIO_COPY)
1251
1252
/*
1253
* Valid ioctl command number range with this API is from 0x00 to
1254
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1255
        } pagefault;
1256
1257
        struct {
1258
+            __u32    ufd;
1259
+        } fork;
1260
+
1261
+        struct {
1262
+            __u64    from;
1263
+            __u64    to;
1264
+            __u64    len;
1265
+        } remap;
1266
+
1267
+        struct {
1268
+            __u64    start;
1269
+            __u64    end;
1270
+        } madv_dn;
1271
+
1272
+        struct {
1273
            /* unused reserved fields */
1274
            __u64    reserved1;
1275
            __u64    reserved2;
1276
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1277
* Start at 0x12 and not at 0 to be more strict against bugs.
1278
*/
1279
#define UFFD_EVENT_PAGEFAULT    0x12
1280
-#if 0 /* not available yet */
1281
#define UFFD_EVENT_FORK        0x13
1282
-#endif
1283
+#define UFFD_EVENT_REMAP    0x14
1284
+#define UFFD_EVENT_MADVDONTNEED    0x15
1285
1286
/* flags for UFFD_EVENT_PAGEFAULT */
1287
#define UFFD_PAGEFAULT_FLAG_WRITE    (1<<0)    /* If this was a write fault */
1288
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
1289
     * Note: UFFD_EVENT_PAGEFAULT and UFFD_PAGEFAULT_FLAG_WRITE
1290
     * are to be considered implicitly always enabled in all kernels as
1291
     * long as the uffdio_api.api requested matches UFFD_API.
1292
+     *
1293
+     * UFFD_FEATURE_MISSING_HUGETLBFS means an UFFDIO_REGISTER
1294
+     * with UFFDIO_REGISTER_MODE_MISSING mode will succeed on
1295
+     * hugetlbfs virtual memory ranges. Adding or not adding
1296
+     * UFFD_FEATURE_MISSING_HUGETLBFS to uffdio_api.features has
1297
+     * no real functional effect after UFFDIO_API returns, but
1298
+     * it's only useful for an initial feature set probe at
1299
+     * UFFDIO_API time. There are two ways to use it:
1300
+     *
1301
+     * 1) by adding UFFD_FEATURE_MISSING_HUGETLBFS to the
1302
+     * uffdio_api.features before calling UFFDIO_API, an error
1303
+     * will be returned by UFFDIO_API on a kernel without
1304
+     * hugetlbfs missing support
1305
+     *
1306
+     * 2) the UFFD_FEATURE_MISSING_HUGETLBFS can not be added in
1307
+     * uffdio_api.features and instead it will be set by the
1308
+     * kernel in the uffdio_api.features if the kernel supports
1309
+     * it, so userland can later check if the feature flag is
1310
+     * present in uffdio_api.features after UFFDIO_API
1311
+     * succeeded.
1312
+     *
1313
+     * UFFD_FEATURE_MISSING_SHMEM works the same as
1314
+     * UFFD_FEATURE_MISSING_HUGETLBFS, but it applies to shmem
1315
+     * (i.e. tmpfs and other shmem based APIs).
1316
     */
1317
-#if 0 /* not available yet */
1318
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
1319
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
1320
-#endif
1321
+#define UFFD_FEATURE_EVENT_REMAP        (1<<2)
1322
+#define UFFD_FEATURE_EVENT_MADVDONTNEED        (1<<3)
1323
+#define UFFD_FEATURE_MISSING_HUGETLBFS        (1<<4)
1324
+#define UFFD_FEATURE_MISSING_SHMEM        (1<<5)
1325
    __u64 features;
1326
1327
    __u64 ioctls;
1328
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
1329
index XXXXXXX..XXXXXXX 100644
1330
--- a/linux-headers/linux/vfio.h
1331
+++ b/linux-headers/linux/vfio.h
1332
@@ -XXX,XX +XXX,XX @@ struct vfio_device_info {
1333
};
1334
#define VFIO_DEVICE_GET_INFO        _IO(VFIO_TYPE, VFIO_BASE + 7)
1335
1336
+/*
1337
+ * Vendor driver using Mediated device framework should provide device_api
1338
+ * attribute in supported type attribute groups. Device API string should be one
1339
+ * of the following corresponding to device flags in vfio_device_info structure.
1340
+ */
1341
+
1342
+#define VFIO_DEVICE_API_PCI_STRING        "vfio-pci"
1343
+#define VFIO_DEVICE_API_PLATFORM_STRING        "vfio-platform"
1344
+#define VFIO_DEVICE_API_AMBA_STRING        "vfio-amba"
1345
+
1346
/**
1347
* VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8,
1348
*                 struct vfio_region_info)
1349
--
34
--
1350
2.7.4
35
2.20.1
1351
36
1352
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/21] bcm2835_gpio: add bcm2835 gpio controller
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
This adds the BCM2835 GPIO controller.
3
This is just enough to make reboot and poweroff work. Works for
4
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
It currently implements:
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
- The 54 GPIOs as outputs (qemu_irq)
6
do what linux does for reset.
7
- The SD controller selection via alternate function of GPIOs 48-53
7
8
8
The watchdog timer functionality is not yet implemented.
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
18
---
17
hw/gpio/Makefile.objs | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
18
include/hw/gpio/bcm2835_gpio.h | 39 +++++
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
19
hw/gpio/bcm2835_gpio.c | 353 +++++++++++++++++++++++++++++++++++++++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
20
3 files changed, 393 insertions(+)
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
21
create mode 100644 include/hw/gpio/bcm2835_gpio.h
23
hw/misc/meson.build | 1 +
22
create mode 100644 hw/gpio/bcm2835_gpio.c
24
5 files changed, 204 insertions(+), 2 deletions(-)
23
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
24
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
26
create mode 100644 hw/misc/bcm2835_powermgt.c
27
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
25
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/gpio/Makefile.objs
30
--- a/include/hw/arm/bcm2835_peripherals.h
27
+++ b/hw/gpio/Makefile.objs
31
+++ b/include/hw/arm/bcm2835_peripherals.h
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
32
@@ -XXX,XX +XXX,XX @@
29
33
#include "hw/misc/bcm2835_mphi.h"
30
obj-$(CONFIG_OMAP) += omap_gpio.o
34
#include "hw/misc/bcm2835_thermal.h"
31
obj-$(CONFIG_IMX) += imx_gpio.o
35
#include "hw/misc/bcm2835_cprman.h"
32
+obj-$(CONFIG_RASPI) += bcm2835_gpio.o
36
+#include "hw/misc/bcm2835_powermgt.h"
33
diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpio.h
37
#include "hw/sd/sdhci.h"
38
#include "hw/sd/bcm2835_sdhost.h"
39
#include "hw/gpio/bcm2835_gpio.h"
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
41
BCM2835MphiState mphi;
42
UnimplementedDeviceState txp;
43
UnimplementedDeviceState armtmr;
44
- UnimplementedDeviceState powermgt;
45
+ BCM2835PowerMgtState powermgt;
46
BCM2835CprmanState cprman;
47
PL011State uart0;
48
BCM2835AuxState aux;
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
34
new file mode 100644
50
new file mode 100644
35
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
36
--- /dev/null
52
--- /dev/null
37
+++ b/include/hw/gpio/bcm2835_gpio.h
53
+++ b/include/hw/misc/bcm2835_powermgt.h
38
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
39
+/*
55
+/*
40
+ * Raspberry Pi (BCM2835) GPIO Controller
56
+ * BCM2835 Power Management emulation
41
+ *
57
+ *
42
+ * Copyright (c) 2017 Antfield SAS
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
43
+ *
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
44
+ * Authors:
45
+ * Clement Deschamps <clement.deschamps@antfield.fr>
46
+ * Luc Michel <luc.michel@antfield.fr>
47
+ *
60
+ *
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
49
+ * See the COPYING file in the top-level directory.
62
+ * See the COPYING file in the top-level directory.
50
+ */
63
+ */
51
+
64
+
52
+#ifndef BCM2835_GPIO_H
65
+#ifndef BCM2835_POWERMGT_H
53
+#define BCM2835_GPIO_H
66
+#define BCM2835_POWERMGT_H
54
+
67
+
55
+#include "hw/sd/sd.h"
68
+#include "hw/sysbus.h"
56
+
69
+#include "qom/object.h"
57
+typedef struct BCM2835GpioState {
70
+
58
+ SysBusDevice parent_obj;
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
59
+
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
60
+ MemoryRegion iomem;
76
+ MemoryRegion iomem;
61
+
77
+
62
+ /* SDBus selector */
78
+ uint32_t rstc;
63
+ SDBus sdbus;
79
+ uint32_t rsts;
64
+ SDBus *sdbus_sdhci;
80
+ uint32_t wdog;
65
+ SDBus *sdbus_sdhost;
81
+};
66
+
67
+ uint8_t fsel[54];
68
+ uint32_t lev0, lev1;
69
+ uint8_t sd_fsel;
70
+ qemu_irq out[54];
71
+} BCM2835GpioState;
72
+
73
+#define TYPE_BCM2835_GPIO "bcm2835_gpio"
74
+#define BCM2835_GPIO(obj) \
75
+ OBJECT_CHECK(BCM2835GpioState, (obj), TYPE_BCM2835_GPIO)
76
+
82
+
77
+#endif
83
+#endif
78
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
87
+++ b/hw/arm/bcm2835_peripherals.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
89
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
96
}
97
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
101
INTERRUPT_USB));
102
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
105
+ return;
106
+ }
107
+
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
79
new file mode 100644
118
new file mode 100644
80
index XXXXXXX..XXXXXXX
119
index XXXXXXX..XXXXXXX
81
--- /dev/null
120
--- /dev/null
82
+++ b/hw/gpio/bcm2835_gpio.c
121
+++ b/hw/misc/bcm2835_powermgt.c
83
@@ -XXX,XX +XXX,XX @@
122
@@ -XXX,XX +XXX,XX @@
84
+/*
123
+/*
85
+ * Raspberry Pi (BCM2835) GPIO Controller
124
+ * BCM2835 Power Management emulation
86
+ *
125
+ *
87
+ * Copyright (c) 2017 Antfield SAS
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
88
+ *
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
89
+ * Authors:
90
+ * Clement Deschamps <clement.deschamps@antfield.fr>
91
+ * Luc Michel <luc.michel@antfield.fr>
92
+ *
128
+ *
93
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
94
+ * See the COPYING file in the top-level directory.
130
+ * See the COPYING file in the top-level directory.
95
+ */
131
+ */
96
+
132
+
97
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
98
+#include "qemu/log.h"
134
+#include "qemu/log.h"
99
+#include "qemu/timer.h"
135
+#include "qemu/module.h"
100
+#include "qapi/error.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
101
+#include "hw/sysbus.h"
137
+#include "migration/vmstate.h"
102
+#include "hw/sd/sd.h"
138
+#include "sysemu/runstate.h"
103
+#include "hw/gpio/bcm2835_gpio.h"
139
+
104
+
140
+#define PASSWORD 0x5a000000
105
+#define GPFSEL0 0x00
141
+#define PASSWORD_MASK 0xff000000
106
+#define GPFSEL1 0x04
142
+
107
+#define GPFSEL2 0x08
143
+#define R_RSTC 0x1c
108
+#define GPFSEL3 0x0C
144
+#define V_RSTC_RESET 0x20
109
+#define GPFSEL4 0x10
145
+#define R_RSTS 0x20
110
+#define GPFSEL5 0x14
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
111
+#define GPSET0 0x1C
147
+#define R_WDOG 0x24
112
+#define GPSET1 0x20
148
+
113
+#define GPCLR0 0x28
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
114
+#define GPCLR1 0x2C
150
+ unsigned size)
115
+#define GPLEV0 0x34
151
+{
116
+#define GPLEV1 0x38
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
117
+#define GPEDS0 0x40
153
+ uint32_t res = 0;
118
+#define GPEDS1 0x44
154
+
119
+#define GPREN0 0x4C
155
+ switch (offset) {
120
+#define GPREN1 0x50
156
+ case R_RSTC:
121
+#define GPFEN0 0x58
157
+ res = s->rstc;
122
+#define GPFEN1 0x5C
158
+ break;
123
+#define GPHEN0 0x64
159
+ case R_RSTS:
124
+#define GPHEN1 0x68
160
+ res = s->rsts;
125
+#define GPLEN0 0x70
161
+ break;
126
+#define GPLEN1 0x74
162
+ case R_WDOG:
127
+#define GPAREN0 0x7C
163
+ res = s->wdog;
128
+#define GPAREN1 0x80
164
+ break;
129
+#define GPAFEN0 0x88
165
+
130
+#define GPAFEN1 0x8C
166
+ default:
131
+#define GPPUD 0x94
167
+ qemu_log_mask(LOG_UNIMP,
132
+#define GPPUDCLK0 0x98
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
133
+#define GPPUDCLK1 0x9C
169
+ "\n", offset);
134
+
170
+ res = 0;
135
+static uint32_t gpfsel_get(BCM2835GpioState *s, uint8_t reg)
171
+ break;
136
+{
172
+ }
137
+ int i;
173
+
138
+ uint32_t value = 0;
174
+ return res;
139
+ for (i = 0; i < 10; i++) {
175
+}
140
+ uint32_t index = 10 * reg + i;
176
+
141
+ if (index < sizeof(s->fsel)) {
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
142
+ value |= (s->fsel[index] & 0x7) << (3 * i);
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
191
+
192
+ switch (offset) {
193
+ case R_RSTC:
194
+ s->rstc = value;
195
+ if (value & V_RSTC_RESET) {
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
198
+ } else {
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200
+ }
143
+ }
201
+ }
144
+ }
202
+ break;
145
+ return value;
203
+ case R_RSTS:
146
+}
204
+ qemu_log_mask(LOG_UNIMP,
147
+
205
+ "bcm2835_powermgt_write: RSTS\n");
148
+static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value)
206
+ s->rsts = value;
149
+{
207
+ break;
150
+ int i;
208
+ case R_WDOG:
151
+ for (i = 0; i < 10; i++) {
209
+ qemu_log_mask(LOG_UNIMP,
152
+ uint32_t index = 10 * reg + i;
210
+ "bcm2835_powermgt_write: WDOG\n");
153
+ if (index < sizeof(s->fsel)) {
211
+ s->wdog = value;
154
+ int fsel = (value >> (3 * i)) & 0x7;
212
+ break;
155
+ s->fsel[index] = fsel;
213
+
156
+ }
157
+ }
158
+
159
+ /* SD controller selection (48-53) */
160
+ if (s->sd_fsel != 0
161
+ && (s->fsel[48] == 0) /* SD_CLK_R */
162
+ && (s->fsel[49] == 0) /* SD_CMD_R */
163
+ && (s->fsel[50] == 0) /* SD_DATA0_R */
164
+ && (s->fsel[51] == 0) /* SD_DATA1_R */
165
+ && (s->fsel[52] == 0) /* SD_DATA2_R */
166
+ && (s->fsel[53] == 0) /* SD_DATA3_R */
167
+ ) {
168
+ /* SDHCI controller selected */
169
+ sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci);
170
+ s->sd_fsel = 0;
171
+ } else if (s->sd_fsel != 4
172
+ && (s->fsel[48] == 4) /* SD_CLK_R */
173
+ && (s->fsel[49] == 4) /* SD_CMD_R */
174
+ && (s->fsel[50] == 4) /* SD_DATA0_R */
175
+ && (s->fsel[51] == 4) /* SD_DATA1_R */
176
+ && (s->fsel[52] == 4) /* SD_DATA2_R */
177
+ && (s->fsel[53] == 4) /* SD_DATA3_R */
178
+ ) {
179
+ /* SDHost controller selected */
180
+ sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost);
181
+ s->sd_fsel = 4;
182
+ }
183
+}
184
+
185
+static int gpfsel_is_out(BCM2835GpioState *s, int index)
186
+{
187
+ if (index >= 0 && index < 54) {
188
+ return s->fsel[index] == 1;
189
+ }
190
+ return 0;
191
+}
192
+
193
+static void gpset(BCM2835GpioState *s,
194
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
195
+{
196
+ uint32_t changes = val & ~*lev;
197
+ uint32_t cur = 1;
198
+
199
+ int i;
200
+ for (i = 0; i < count; i++) {
201
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
202
+ qemu_set_irq(s->out[start + i], 1);
203
+ }
204
+ cur <<= 1;
205
+ }
206
+
207
+ *lev |= val;
208
+}
209
+
210
+static void gpclr(BCM2835GpioState *s,
211
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
212
+{
213
+ uint32_t changes = val & *lev;
214
+ uint32_t cur = 1;
215
+
216
+ int i;
217
+ for (i = 0; i < count; i++) {
218
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
219
+ qemu_set_irq(s->out[start + i], 0);
220
+ }
221
+ cur <<= 1;
222
+ }
223
+
224
+ *lev &= ~val;
225
+}
226
+
227
+static uint64_t bcm2835_gpio_read(void *opaque, hwaddr offset,
228
+ unsigned size)
229
+{
230
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
231
+
232
+ switch (offset) {
233
+ case GPFSEL0:
234
+ case GPFSEL1:
235
+ case GPFSEL2:
236
+ case GPFSEL3:
237
+ case GPFSEL4:
238
+ case GPFSEL5:
239
+ return gpfsel_get(s, offset / 4);
240
+ case GPSET0:
241
+ case GPSET1:
242
+ /* Write Only */
243
+ return 0;
244
+ case GPCLR0:
245
+ case GPCLR1:
246
+ /* Write Only */
247
+ return 0;
248
+ case GPLEV0:
249
+ return s->lev0;
250
+ case GPLEV1:
251
+ return s->lev1;
252
+ case GPEDS0:
253
+ case GPEDS1:
254
+ case GPREN0:
255
+ case GPREN1:
256
+ case GPFEN0:
257
+ case GPFEN1:
258
+ case GPHEN0:
259
+ case GPHEN1:
260
+ case GPLEN0:
261
+ case GPLEN1:
262
+ case GPAREN0:
263
+ case GPAREN1:
264
+ case GPAFEN0:
265
+ case GPAFEN1:
266
+ case GPPUD:
267
+ case GPPUDCLK0:
268
+ case GPPUDCLK1:
269
+ /* Not implemented */
270
+ return 0;
271
+ default:
214
+ default:
272
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
215
+ qemu_log_mask(LOG_UNIMP,
273
+ __func__, offset);
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
274
+ break;
217
+ "\n", offset);
275
+ }
218
+ break;
276
+
219
+ }
277
+ return 0;
220
+}
278
+}
221
+
279
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
280
+static void bcm2835_gpio_write(void *opaque, hwaddr offset,
223
+ .read = bcm2835_powermgt_read,
281
+ uint64_t value, unsigned size)
224
+ .write = bcm2835_powermgt_write,
282
+{
283
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
284
+
285
+ switch (offset) {
286
+ case GPFSEL0:
287
+ case GPFSEL1:
288
+ case GPFSEL2:
289
+ case GPFSEL3:
290
+ case GPFSEL4:
291
+ case GPFSEL5:
292
+ gpfsel_set(s, offset / 4, value);
293
+ break;
294
+ case GPSET0:
295
+ gpset(s, value, 0, 32, &s->lev0);
296
+ break;
297
+ case GPSET1:
298
+ gpset(s, value, 32, 22, &s->lev1);
299
+ break;
300
+ case GPCLR0:
301
+ gpclr(s, value, 0, 32, &s->lev0);
302
+ break;
303
+ case GPCLR1:
304
+ gpclr(s, value, 32, 22, &s->lev1);
305
+ break;
306
+ case GPLEV0:
307
+ case GPLEV1:
308
+ /* Read Only */
309
+ break;
310
+ case GPEDS0:
311
+ case GPEDS1:
312
+ case GPREN0:
313
+ case GPREN1:
314
+ case GPFEN0:
315
+ case GPFEN1:
316
+ case GPHEN0:
317
+ case GPHEN1:
318
+ case GPLEN0:
319
+ case GPLEN1:
320
+ case GPAREN0:
321
+ case GPAREN1:
322
+ case GPAFEN0:
323
+ case GPAFEN1:
324
+ case GPPUD:
325
+ case GPPUDCLK0:
326
+ case GPPUDCLK1:
327
+ /* Not implemented */
328
+ break;
329
+ default:
330
+ goto err_out;
331
+ }
332
+ return;
333
+
334
+err_out:
335
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
336
+ __func__, offset);
337
+}
338
+
339
+static void bcm2835_gpio_reset(DeviceState *dev)
340
+{
341
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
342
+
343
+ int i;
344
+ for (i = 0; i < 6; i++) {
345
+ gpfsel_set(s, i, 0);
346
+ }
347
+
348
+ s->sd_fsel = 0;
349
+
350
+ /* SDHCI is selected by default */
351
+ sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci);
352
+
353
+ s->lev0 = 0;
354
+ s->lev1 = 0;
355
+}
356
+
357
+static const MemoryRegionOps bcm2835_gpio_ops = {
358
+ .read = bcm2835_gpio_read,
359
+ .write = bcm2835_gpio_write,
360
+ .endianness = DEVICE_NATIVE_ENDIAN,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
361
+};
226
+ .impl.min_access_size = 4,
362
+
227
+ .impl.max_access_size = 4,
363
+static const VMStateDescription vmstate_bcm2835_gpio = {
228
+};
364
+ .name = "bcm2835_gpio",
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
365
+ .version_id = 1,
232
+ .version_id = 1,
366
+ .minimum_version_id = 1,
233
+ .minimum_version_id = 1,
367
+ .fields = (VMStateField[]) {
234
+ .fields = (VMStateField[]) {
368
+ VMSTATE_UINT8_ARRAY(fsel, BCM2835GpioState, 54),
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
369
+ VMSTATE_UINT32(lev0, BCM2835GpioState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
370
+ VMSTATE_UINT32(lev1, BCM2835GpioState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
371
+ VMSTATE_UINT8(sd_fsel, BCM2835GpioState),
372
+ VMSTATE_END_OF_LIST()
238
+ VMSTATE_END_OF_LIST()
373
+ }
239
+ }
374
+};
240
+};
375
+
241
+
376
+static void bcm2835_gpio_init(Object *obj)
242
+static void bcm2835_powermgt_init(Object *obj)
377
+{
243
+{
378
+ BCM2835GpioState *s = BCM2835_GPIO(obj);
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
379
+ DeviceState *dev = DEVICE(obj);
245
+
380
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
381
+
247
+ TYPE_BCM2835_POWERMGT, 0x200);
382
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
383
+ TYPE_SD_BUS, DEVICE(s), "sd-bus");
249
+}
384
+
250
+
385
+ memory_region_init_io(&s->iomem, obj,
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
386
+ &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
252
+{
387
+ sysbus_init_mmio(sbd, &s->iomem);
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
388
+ qdev_init_gpio_out(dev, s->out, 54);
254
+
389
+}
255
+ /* https://elinux.org/BCM2835_registers#PM */
390
+
256
+ s->rstc = 0x00000102;
391
+static void bcm2835_gpio_realize(DeviceState *dev, Error **errp)
257
+ s->rsts = 0x00001000;
392
+{
258
+ s->wdog = 0x00000000;
393
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
259
+}
394
+ Object *obj;
260
+
395
+ Error *err = NULL;
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
396
+
397
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhci", &err);
398
+ if (obj == NULL) {
399
+ error_setg(errp, "%s: required sdhci link not found: %s",
400
+ __func__, error_get_pretty(err));
401
+ return;
402
+ }
403
+ s->sdbus_sdhci = SD_BUS(obj);
404
+
405
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhost", &err);
406
+ if (obj == NULL) {
407
+ error_setg(errp, "%s: required sdhost link not found: %s",
408
+ __func__, error_get_pretty(err));
409
+ return;
410
+ }
411
+ s->sdbus_sdhost = SD_BUS(obj);
412
+}
413
+
414
+static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
415
+{
262
+{
416
+ DeviceClass *dc = DEVICE_CLASS(klass);
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
417
+
264
+
418
+ dc->vmsd = &vmstate_bcm2835_gpio;
265
+ dc->reset = bcm2835_powermgt_reset;
419
+ dc->realize = &bcm2835_gpio_realize;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
420
+ dc->reset = &bcm2835_gpio_reset;
267
+}
421
+}
268
+
422
+
269
+static TypeInfo bcm2835_powermgt_info = {
423
+static const TypeInfo bcm2835_gpio_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
424
+ .name = TYPE_BCM2835_GPIO,
425
+ .parent = TYPE_SYS_BUS_DEVICE,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
426
+ .instance_size = sizeof(BCM2835GpioState),
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
427
+ .instance_init = bcm2835_gpio_init,
273
+ .class_init = bcm2835_powermgt_class_init,
428
+ .class_init = bcm2835_gpio_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
429
+};
275
+};
430
+
276
+
431
+static void bcm2835_gpio_register_types(void)
277
+static void bcm2835_powermgt_register_types(void)
432
+{
278
+{
433
+ type_register_static(&bcm2835_gpio_info);
279
+ type_register_static(&bcm2835_powermgt_info);
434
+}
280
+}
435
+
281
+
436
+type_init(bcm2835_gpio_register_types)
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
437
--
295
--
438
2.7.4
296
2.20.1
439
297
440
298
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/21] update-linux-headers: update for 4.11
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The linux-headers/asm-arm/unistd.h file has been split in three
3
Add a test booting and quickly shutdown a raspi2 machine,
4
sub-files, copy them along. However, building them requires
4
to test the power management model:
5
setting ARCH rather than SRCARCH.
6
5
7
SRCARCH defaults to $(ARCH) anyway; to avoid future occurrence of
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
8
the same problem use ARCH for all architectures where SRCARCH=ARCH.
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
9
Currently these are all except x86, sparc, sh and tile.
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
10
44
11
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20170221122920.16245-2-pbonzini@redhat.com
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
49
---
15
scripts/update-linux-headers.sh | 13 ++++++++++++-
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
16
1 file changed, 12 insertions(+), 1 deletion(-)
51
1 file changed, 43 insertions(+)
17
52
18
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
19
index XXXXXXX..XXXXXXX 100755
54
index XXXXXXX..XXXXXXX 100644
20
--- a/scripts/update-linux-headers.sh
55
--- a/tests/acceptance/boot_linux_console.py
21
+++ b/scripts/update-linux-headers.sh
56
+++ b/tests/acceptance/boot_linux_console.py
22
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
57
@@ -XXX,XX +XXX,XX @@
23
continue
58
from avocado import skip
24
fi
59
from avocado import skipUnless
25
60
from avocado_qemu import Test
26
- make -C "$linux" INSTALL_HDR_PATH="$tmpdir" SRCARCH=$arch headers_install
61
+from avocado_qemu import exec_command
27
+ if [ "$arch" = x86 ]; then
62
from avocado_qemu import exec_command_and_wait_for_pattern
28
+ arch_var=SRCARCH
63
from avocado_qemu import interrupt_interactive_console_until_pattern
29
+ else
64
from avocado_qemu import wait_for_console_pattern
30
+ arch_var=ARCH
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
31
+ fi
66
"""
67
self.do_test_arm_raspi2(0)
68
69
+ def test_arm_raspi2_initrd(self):
70
+ """
71
+ :avocado: tags=arch:arm
72
+ :avocado: tags=machine:raspi2
73
+ """
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
75
+ 'pool/main/r/raspberrypi-firmware/'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
32
+
81
+
33
+ make -C "$linux" INSTALL_HDR_PATH="$tmpdir" $arch_var=$arch headers_install
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
34
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
35
rm -rf "$output/linux-headers/asm-$arch"
84
+ 'arm/rootfs-armv7a.cpio.gz')
36
mkdir -p "$output/linux-headers/asm-$arch"
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
37
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
38
cp_portable "$tmpdir/include/asm/kvm_virtio.h" "$output/include/standard-headers/asm-s390/"
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
39
cp_portable "$tmpdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/"
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
40
fi
89
+
41
+ if [ $arch = arm ]; then
90
+ self.vm.set_console()
42
+ cp "$tmpdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/"
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
43
+ cp "$tmpdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/"
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
44
+ cp "$tmpdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/"
93
+ 'panic=-1 noreboot ' +
45
+ fi
94
+ 'dwc_otg.fiq_fsm_enable=0')
46
if [ $arch = x86 ]; then
95
+ self.vm.add_args('-kernel', kernel_path,
47
cp_portable "$tmpdir/include/asm/hyperv.h" "$output/include/standard-headers/asm-x86/"
96
+ '-dtb', dtb_path,
48
cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/"
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
49
--
114
--
50
2.7.4
115
2.20.1
51
116
52
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/21] bcm2835: add sdhost and gpio controllers
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform.
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
4
6
5
For supporting the SD controller selection (alternate function of GPIOs
7
To avoid this, we check to see what NaN mode we're running in before we call
6
48-53), the bcm2835_gpio now exposes an sdbus.
8
floatxx_silence_nan().
7
It also has a link to both the sdbus of sdhci and sdhost controllers,
8
and the card is reparented from one bus to another when the alternate
9
function of GPIOs 48-53 is modified.
10
9
11
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
14
Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org
15
Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
15
---
19
include/hw/arm/bcm2835_peripherals.h | 4 ++++
16
target/arm/helper-a64.c | 12 +++++++++---
20
hw/arm/bcm2835_peripherals.c | 43 ++++++++++++++++++++++++++++++++++--
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
21
2 files changed, 45 insertions(+), 2 deletions(-)
18
2 files changed, 27 insertions(+), 9 deletions(-)
22
19
23
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
24
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/bcm2835_peripherals.h
22
--- a/target/arm/helper-a64.c
26
+++ b/include/hw/arm/bcm2835_peripherals.h
23
+++ b/target/arm/helper-a64.c
27
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
28
#include "hw/misc/bcm2835_rng.h"
25
float16 nan = a;
29
#include "hw/misc/bcm2835_mbox.h"
26
if (float16_is_signaling_nan(a, fpst)) {
30
#include "hw/sd/sdhci.h"
27
float_raise(float_flag_invalid, fpst);
31
+#include "hw/sd/bcm2835_sdhost.h"
28
- nan = float16_silence_nan(a, fpst);
32
+#include "hw/gpio/bcm2835_gpio.h"
29
+ if (!fpst->default_nan_mode) {
33
30
+ nan = float16_silence_nan(a, fpst);
34
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
31
+ }
35
#define BCM2835_PERIPHERALS(obj) \
32
}
36
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
33
if (fpst->default_nan_mode) {
37
BCM2835RngState rng;
34
nan = float16_default_nan(fpst);
38
BCM2835MboxState mboxes;
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
39
SDHCIState sdhci;
36
float32 nan = a;
40
+ BCM2835SDHostState sdhost;
37
if (float32_is_signaling_nan(a, fpst)) {
41
+ BCM2835GpioState gpio;
38
float_raise(float_flag_invalid, fpst);
42
} BCM2835PeripheralState;
39
- nan = float32_silence_nan(a, fpst);
43
40
+ if (!fpst->default_nan_mode) {
44
#endif /* BCM2835_PERIPHERALS_H */
41
+ nan = float32_silence_nan(a, fpst);
45
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
42
+ }
43
}
44
if (fpst->default_nan_mode) {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
46
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/bcm2835_peripherals.c
59
--- a/target/arm/vfp_helper.c
48
+++ b/hw/arm/bcm2835_peripherals.c
60
+++ b/target/arm/vfp_helper.c
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
50
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
62
float16 nan = f16;
51
qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
63
if (float16_is_signaling_nan(f16, fpst)) {
52
64
float_raise(float_flag_invalid, fpst);
53
+ /* SDHOST */
65
- nan = float16_silence_nan(f16, fpst);
54
+ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
66
+ if (!fpst->default_nan_mode) {
55
+ object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
67
+ nan = float16_silence_nan(f16, fpst);
56
+ qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
68
+ }
57
+
69
}
58
/* DMA Channels */
70
if (fpst->default_nan_mode) {
59
object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
71
nan = float16_default_nan(fpst);
60
object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
61
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
73
float32 nan = f32;
62
74
if (float32_is_signaling_nan(f32, fpst)) {
63
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
75
float_raise(float_flag_invalid, fpst);
64
OBJECT(&s->gpu_bus_mr), &error_abort);
76
- nan = float32_silence_nan(f32, fpst);
65
+
77
+ if (!fpst->default_nan_mode) {
66
+ /* GPIO */
78
+ nan = float32_silence_nan(f32, fpst);
67
+ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
79
+ }
68
+ object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
80
}
69
+ qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
81
if (fpst->default_nan_mode) {
70
+
82
nan = float32_default_nan(fpst);
71
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
72
+ OBJECT(&s->sdhci.sdbus), &error_abort);
84
float64 nan = f64;
73
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
85
if (float64_is_signaling_nan(f64, fpst)) {
74
+ OBJECT(&s->sdhost.sdbus), &error_abort);
86
float_raise(float_flag_invalid, fpst);
75
}
87
- nan = float64_silence_nan(f64, fpst);
76
88
+ if (!fpst->default_nan_mode) {
77
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
89
+ nan = float64_silence_nan(f64, fpst);
78
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
90
+ }
79
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
91
}
80
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
92
if (fpst->default_nan_mode) {
81
INTERRUPT_ARASANSDIO));
93
nan = float64_default_nan(fpst);
82
- object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "sd-bus",
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
83
- &err);
95
float16 nan = f16;
84
+
96
if (float16_is_signaling_nan(f16, s)) {
85
+ /* SDHOST */
97
float_raise(float_flag_invalid, s);
86
+ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
98
- nan = float16_silence_nan(f16, s);
87
if (err) {
99
+ if (!s->default_nan_mode) {
88
error_propagate(errp, err);
100
+ nan = float16_silence_nan(f16, fpstp);
89
return;
101
+ }
90
}
102
}
91
103
if (s->default_nan_mode) {
92
+ memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
104
nan = float16_default_nan(s);
93
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
106
float32 nan = f32;
95
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
107
if (float32_is_signaling_nan(f32, s)) {
96
+ INTERRUPT_SDIO));
108
float_raise(float_flag_invalid, s);
97
+
109
- nan = float32_silence_nan(f32, s);
98
/* DMA Channels */
110
+ if (!s->default_nan_mode) {
99
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
111
+ nan = float32_silence_nan(f32, fpstp);
100
if (err) {
112
+ }
101
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
113
}
102
BCM2835_IC_GPU_IRQ,
114
if (s->default_nan_mode) {
103
INTERRUPT_DMA0 + n));
115
nan = float32_default_nan(s);
104
}
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
105
+
117
float64 nan = f64;
106
+ /* GPIO */
118
if (float64_is_signaling_nan(f64, s)) {
107
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
119
float_raise(float_flag_invalid, s);
108
+ if (err) {
120
- nan = float64_silence_nan(f64, s);
109
+ error_propagate(errp, err);
121
+ if (!s->default_nan_mode) {
110
+ return;
122
+ nan = float64_silence_nan(f64, fpstp);
111
+ }
123
+ }
112
+
124
}
113
+ memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
125
if (s->default_nan_mode) {
114
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
126
nan = float64_default_nan(s);
115
+
116
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
117
+ &err);
118
+ if (err) {
119
+ error_propagate(errp, err);
120
+ return;
121
+ }
122
}
123
124
static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
125
--
127
--
126
2.7.4
128
2.20.1
127
129
128
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/21] target-arm: Add GICv3CPUState in CPUARMState struct
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
Add gicv3state void pointer to CPUARMState struct
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
to store GICv3CPUState.
4
function has to be used for machine shutdown. Otherwise we cause
5
a reset with a bogus "cause" value, when we intended a shutdown.
5
6
6
In case of usecase like CPU reset, we need to reset
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
GICv3CPUState of the CPU. In such scenario, this pointer
8
becomes handy.
9
10
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
13
Message-id: 1487850673-26455-5-git-send-email-vijay.kilari@gmail.com
10
[PMM: tweaked commit message]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
hw/intc/gicv3_internal.h | 2 ++
13
hw/gpio/gpio_pwr.c | 2 +-
17
target/arm/cpu.h | 2 ++
14
1 file changed, 1 insertion(+), 1 deletion(-)
18
hw/intc/arm_gicv3_common.c | 2 ++
19
hw/intc/arm_gicv3_cpuif.c | 8 ++++++++
20
4 files changed, 14 insertions(+)
21
15
22
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/gicv3_internal.h
18
--- a/hw/gpio/gpio_pwr.c
25
+++ b/hw/intc/gicv3_internal.h
19
+++ b/hw/gpio/gpio_pwr.c
26
@@ -XXX,XX +XXX,XX @@ static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
22
{
23
if (level) {
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
27
}
26
}
28
}
27
}
29
28
30
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
31
+
32
#endif /* QEMU_ARM_GICV3_INTERNAL_H */
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
38
39
void *nvic;
40
const struct arm_boot_info *boot_info;
41
+ /* Store GICv3CPUState to access from this struct */
42
+ void *gicv3state;
43
} CPUARMState;
44
45
/**
46
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_common.c
49
+++ b/hw/intc/arm_gicv3_common.c
50
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
51
52
s->cpu[i].cpu = cpu;
53
s->cpu[i].gic = s;
54
+ /* Store GICv3CPUState in CPUARMState gicv3state pointer */
55
+ gicv3_set_gicv3state(cpu, &s->cpu[i]);
56
57
/* Pre-construct the GICR_TYPER:
58
* For our implementation:
59
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/intc/arm_gicv3_cpuif.c
62
+++ b/hw/intc/arm_gicv3_cpuif.c
63
@@ -XXX,XX +XXX,XX @@
64
#include "gicv3_internal.h"
65
#include "cpu.h"
66
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
68
+{
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
70
+ CPUARMState *env = &arm_cpu->env;
71
+
72
+ env->gicv3state = (void *)s;
73
+};
74
+
75
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
76
{
77
/* Given the CPU, find the right GICv3CPUState struct.
78
--
29
--
79
2.7.4
30
2.20.1
80
31
81
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/21] armv7m: Make NVIC expose a memory region rather than mapping itself
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
Make the NVIC device expose a memory region for its users
1
In do_ldst(), the calculation of the offset needs to be based on the
2
to map, rather than mapping itself into the system memory
2
size of the memory access, not the size of the elements in the
3
space on realize, and get the one user (the ARMv7M object)
3
vector. This meant we were getting it wrong for the widening and
4
to do this.
4
narrowing variants of the various VLDR and VSTR insns.
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1487604965-23220-7-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
9
---
9
---
10
hw/arm/armv7m.c | 7 ++++++-
10
target/arm/translate-mve.c | 17 +++++++++--------
11
hw/intc/armv7m_nvic.c | 7 ++-----
11
1 file changed, 9 insertions(+), 8 deletions(-)
12
2 files changed, 8 insertions(+), 6 deletions(-)
13
12
14
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/armv7m.c
15
--- a/target/arm/translate-mve.c
17
+++ b/hw/arm/armv7m.c
16
+++ b/target/arm/translate-mve.c
18
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
19
static void armv7m_realize(DeviceState *dev, Error **errp)
18
}
19
}
20
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
23
+ unsigned msize)
20
{
24
{
21
ARMv7MState *s = ARMV7M(dev);
25
TCGv_i32 addr;
22
+ SysBusDevice *sbd;
26
uint32_t offset;
23
Error *err = NULL;
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
24
int i;
28
return true;
25
char **cpustr;
29
}
26
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
30
27
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
31
- offset = a->imm << a->size;
28
32
+ offset = a->imm << msize;
29
/* Wire the NVIC up to the CPU */
33
if (!a->a) {
30
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
34
offset = -offset;
31
+ sbd = SYS_BUS_DEVICE(&s->nvic);
35
}
32
+ sysbus_connect_irq(sbd, 0,
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
33
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
34
s->cpu->env.nvic = &s->nvic;
38
{ NULL, NULL }
35
39
};
36
+ memory_region_add_subregion(&s->container, 0xe000e000,
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
37
+ sysbus_mmio_get_region(sbd, 0));
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
38
+
39
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
40
Object *obj = OBJECT(&s->bitband[i]);
41
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
42
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/intc/armv7m_nvic.c
45
+++ b/hw/intc/armv7m_nvic.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/arm/arm.h"
48
#include "hw/arm/armv7m_nvic.h"
49
#include "target/arm/cpu.h"
50
-#include "exec/address-spaces.h"
51
#include "qemu/log.h"
52
#include "trace.h"
53
54
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
55
"nvic_sysregs", 0x1000);
56
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
57
58
- /* Map the whole thing into system memory at the location required
59
- * by the v7M architecture.
60
- */
61
- memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
62
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
63
+
64
s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
65
}
42
}
66
43
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
67
--
65
--
68
2.7.4
66
2.20.1
69
67
70
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/21] armv7m: Abstract out the "load kernel" code
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
Abstract the "load kernel" code out of armv7m_init() into its own
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
function. This includes the registration of the CPU reset function,
2
insns had some bugs:
3
to parallel how we handle this for A profile cores.
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
4
9
5
We make the function public so that boards which choose to
10
In particular, fixing the second of these allows us to recast
6
directly instantiate an ARMv7M device object can call it.
11
the implementation to avoid 128-bit arithmetic entirely.
7
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
13
---
20
---
14
include/hw/arm/arm.h | 12 ++++++++++++
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
15
hw/arm/armv7m.c | 23 ++++++++++++++++++-----
22
1 file changed, 21 insertions(+), 17 deletions(-)
16
2 files changed, 30 insertions(+), 5 deletions(-)
17
23
18
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/arm.h
26
--- a/target/arm/mve_helper.c
21
+++ b/include/hw/arm/arm.h
27
+++ b/target/arm/mve_helper.c
22
@@ -XXX,XX +XXX,XX @@ typedef enum {
28
@@ -XXX,XX +XXX,XX @@
23
/* armv7m.c */
29
*/
24
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
30
25
const char *kernel_filename, const char *cpu_model);
31
#include "qemu/osdep.h"
26
+/**
32
-#include "qemu/int128.h"
27
+ * armv7m_load_kernel:
33
#include "cpu.h"
28
+ * @cpu: CPU
34
#include "internals.h"
29
+ * @kernel_filename: file to load
35
#include "vec_internal.h"
30
+ * @mem_size: mem_size: maximum image size to load
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
31
+ *
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
32
+ * Load the guest image for an ARMv7M system. This must be called by
33
+ * any ARMv7M board, either directly or via armv7m_init(). (This is
34
+ * necessary to ensure that the CPU resets correctly on system reset,
35
+ * as well as for kernel loading.)
36
+ */
37
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
38
38
39
/*
39
/*
40
* struct used as a parameter of the arm_load_kernel machine init
40
- * Rounding multiply add long dual accumulate high: we must keep
41
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
41
- * a 72-bit internal accumulator value and return the top 64 bits.
42
index XXXXXXX..XXXXXXX 100644
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
43
--- a/hw/arm/armv7m.c
43
+ * this is implemented with a 72-bit internal accumulator value of which
44
+++ b/hw/arm/armv7m.c
44
+ * the top 64 bits are returned. We optimize this to avoid having to
45
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
46
ARMCPU *cpu;
46
+ * is squashed back into 64-bits after each beat.
47
CPUARMState *env;
47
*/
48
DeviceState *nvic;
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
49
- int image_size;
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
50
- uint64_t entry;
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
51
- uint64_t lowaddr;
51
void *vm, uint64_t a) \
52
- int big_endian;
52
{ \
53
53
uint16_t mask = mve_element_mask(env); \
54
if (cpu_model == NULL) {
54
unsigned e; \
55
    cpu_model = "cortex-m3";
55
TYPE *n = vn, *m = vm; \
56
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
56
- Int128 acc = int128_lshift(TO128(a), 8); \
57
qdev_init_nofail(nvic);
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
58
sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
59
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
59
if (mask & 1) { \
60
+ armv7m_load_kernel(cpu, kernel_filename, mem_size);
60
+ LTYPE mul; \
61
+ return nvic;
61
if (e & 1) { \
62
+}
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
63
+
63
- m[H##ESIZE(e)])); \
64
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
65
+{
65
+ if (SUB) { \
66
+ int image_size;
66
+ mul = -mul; \
67
+ uint64_t entry;
67
+ } \
68
+ uint64_t lowaddr;
68
} else { \
69
+ int big_endian;
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
70
70
- m[H##ESIZE(e)])); \
71
#ifdef TARGET_WORDS_BIGENDIAN
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
72
big_endian = 1;
72
} \
73
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
74
}
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
75
+ a += mul; \
76
} \
77
} \
78
mve_advance_vpt(env); \
79
- return int128_getlo(int128_rshift(acc, 8)); \
80
+ return a; \
75
}
81
}
76
82
77
+ /* CPU objects (unlike devices) are not automatically reset on system
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
78
+ * reset, so we must always register a handler to do so. Unlike
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
79
+ * A-profile CPUs, we don't need to do anything special in the
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
80
+ * handler to arrange that it starts correctly.
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
81
+ * This is arguably the wrong place to do this, but it matches the
87
82
+ * way A-profile does it. Note that this means that every M profile
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
83
+ * board must call this function!
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
84
+ */
90
85
qemu_register_reset(armv7m_reset, cpu);
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
86
- return nvic;
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
87
}
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
88
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
89
static Property bitband_properties[] = {
95
96
/* Vector add across vector */
97
#define DO_VADDV(OP, ESIZE, TYPE) \
90
--
98
--
91
2.7.4
99
2.20.1
92
100
93
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/21] armv7m: Use QOMified armv7m object in armv7m_init()
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
Make the legacy armv7m_init() function use the newly QOMified
1
The function asimd_imm_const() in translate-neon.c is an
2
armv7m object rather than doing everything by hand.
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
3
also want for MVE. Move the implementation to translate.c, with a
4
We can return the armv7m object rather than the NVIC from
4
prototype in translate.h.
5
armv7m_init() because its interface to the rest of the
6
board (GPIOs, etc) is identical.
7
5
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
11
Message-id: 1487604965-23220-5-git-send-email-peter.maydell@linaro.org
12
---
9
---
13
hw/arm/armv7m.c | 49 ++++++++++++-------------------------------------
10
target/arm/translate.h | 16 ++++++++++
14
1 file changed, 12 insertions(+), 37 deletions(-)
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
15
14
16
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/armv7m.c
17
--- a/target/arm/translate.h
19
+++ b/hw/arm/armv7m.c
18
+++ b/target/arm/translate.h
20
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
21
sysbus_init_mmio(dev, &s->iomem);
20
return opc | s->be_data;
22
}
21
}
23
22
24
-static void armv7m_bitband_init(void)
23
+/**
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
25
+ *
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
25
-{
49
-{
26
- DeviceState *dev;
50
- /*
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
27
-
90
-
28
- dev = qdev_create(NULL, TYPE_BITBAND);
91
- for (n = 0; n < 8; n++) {
29
- qdev_prop_set_uint32(dev, "base", 0x20000000);
92
- if (imm & (1 << n)) {
30
- qdev_init_nofail(dev);
93
- imm64 |= (0xffULL << (n * 8));
31
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
94
- }
32
-
95
- }
33
- dev = qdev_create(NULL, TYPE_BITBAND);
96
- return imm64;
34
- qdev_prop_set_uint32(dev, "base", 0x40000000);
97
- }
35
- qdev_init_nofail(dev);
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
36
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
37
-}
109
-}
38
-
110
-
39
/* Board init. */
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
40
112
GVecGen2iFn *fn)
41
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
43
44
/* Init CPU and memory for a v7-M based board.
45
mem_size is in bytes.
46
- Returns the NVIC array. */
47
+ Returns the ARMv7M device. */
48
49
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
50
const char *kernel_filename, const char *cpu_model)
51
{
113
{
52
- ARMCPU *cpu;
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
53
- CPUARMState *env;
115
index XXXXXXX..XXXXXXX 100644
54
- DeviceState *nvic;
116
--- a/target/arm/translate.c
55
+ DeviceState *armv7m;
117
+++ b/target/arm/translate.c
56
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
57
if (cpu_model == NULL) {
119
a64_translate_init();
58
-    cpu_model = "cortex-m3";
120
}
59
+ cpu_model = "cortex-m3";
121
60
}
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
61
- cpu = cpu_arm_init(cpu_model);
123
+{
62
- if (cpu == NULL) {
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
63
- fprintf(stderr, "Unable to find CPU definition\n");
125
+ switch (cmode) {
64
- exit(1);
126
+ case 0: case 1:
65
- }
127
+ /* no-op */
66
- env = &cpu->env;
128
+ break;
67
-
129
+ case 2: case 3:
68
- armv7m_bitband_init();
130
+ imm <<= 8;
69
-
131
+ break;
70
- nvic = qdev_create(NULL, "armv7m_nvic");
132
+ case 4: case 5:
71
- qdev_prop_set_uint32(nvic, "num-irq", num_irq);
133
+ imm <<= 16;
72
- env->nvic = nvic;
134
+ break;
73
- qdev_init_nofail(nvic);
135
+ case 6: case 7:
74
- sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
136
+ imm <<= 24;
75
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
137
+ break;
76
- armv7m_load_kernel(cpu, kernel_filename, mem_size);
138
+ case 8: case 9:
77
- return nvic;
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
78
+
158
+
79
+ armv7m = qdev_create(NULL, "armv7m");
159
+ for (n = 0; n < 8; n++) {
80
+ qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
160
+ if (imm & (1 << n)) {
81
+ qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
161
+ imm64 |= (0xffULL << (n * 8));
82
+ /* This will exit with an error if the user passed us a bad cpu_model */
162
+ }
83
+ qdev_init_nofail(armv7m);
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
84
+
178
+
85
+ armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
179
/* Generate a label used for skipping this instruction */
86
+ return armv7m;
180
void arm_gen_condlabel(DisasContext *s)
87
}
181
{
88
89
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
90
--
182
--
91
2.7.4
183
2.20.1
92
184
93
185
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/21] armv7m: Make ARMv7M object take memory region link
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
Make the ARMv7M object take a memory region link which it uses
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
to wire up the bitband rather than having them always put
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
themselves in the system address space.
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
4
5
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
8
---
9
---
9
include/hw/arm/armv7m.h | 10 ++++++++++
10
target/arm/translate.h | 3 +-
10
hw/arm/armv7m.c | 23 ++++++++++++++++++++++-
11
target/arm/translate-a64.c | 86 ++++----------------------------------
11
2 files changed, 32 insertions(+), 1 deletion(-)
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
12
14
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/armv7m.h
17
--- a/target/arm/translate.h
16
+++ b/include/hw/arm/armv7m.h
18
+++ b/target/arm/translate.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
18
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
20
* VMVN and VBIC (when cmode < 14 && op == 1).
19
* + Property "cpu-model": CPU model to instantiate
21
*
20
* + Property "num-irq": number of external IRQ lines
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
21
+ * + Property "memory": MemoryRegion defining the physical address space
23
- * callers must catch this.
22
+ * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
24
+ * callers must catch this; we return the 64-bit constant value defined
23
+ * devices will be automatically layered on top of this view.)
25
+ * for AArch64.
24
*/
26
*
25
typedef struct ARMv7MState {
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
26
/*< private >*/
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
28
BitBandState bitband[ARMV7M_NUM_BITBANDS];
29
ARMCPU *cpu;
30
31
+ /* MemoryRegion we pass to the CPU, with our devices layered on
32
+ * top of the ones the board provides in board_memory.
33
+ */
34
+ MemoryRegion container;
35
+
36
/* Properties */
37
char *cpu_model;
38
+ /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
39
+ MemoryRegion *board_memory;
40
} ARMv7MState;
41
42
#endif
43
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
44
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/armv7m.c
31
--- a/target/arm/translate-a64.c
46
+++ b/hw/arm/armv7m.c
32
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
48
#include "elf.h"
34
{
49
#include "sysemu/qtest.h"
35
int rd = extract32(insn, 0, 5);
50
#include "qemu/error-report.h"
36
int cmode = extract32(insn, 12, 4);
51
+#include "exec/address-spaces.h"
37
- int cmode_3_1 = extract32(cmode, 1, 3);
52
38
- int cmode_0 = extract32(cmode, 0, 1);
53
/* Bitbanded IO. Each word corresponds to a single bit. */
39
int o2 = extract32(insn, 11, 1);
54
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
55
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
41
bool is_neg = extract32(insn, 29, 1);
56
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
57
/* Can't init the cpu here, we don't yet know which model to use */
58
59
+ object_property_add_link(obj, "memory",
60
+ TYPE_MEMORY_REGION,
61
+ (Object **)&s->board_memory,
62
+ qdev_prop_allow_set_link_before_realize,
63
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
64
+ &error_abort);
65
+ memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
66
+
67
object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
68
qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
69
object_property_add_alias(obj, "num-irq",
70
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
71
const char *typename;
72
CPUClass *cc;
73
74
+ if (!s->board_memory) {
75
+ error_setg(errp, "memory property was not set");
76
+ return;
77
+ }
78
+
79
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
80
+
81
cpustr = g_strsplit(s->cpu_model, ",", 2);
82
83
oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
84
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
85
return;
43
return;
86
}
44
}
87
45
88
+ object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
46
- /* See AdvSIMDExpandImm() in ARM ARM */
89
+ &error_abort);
47
- switch (cmode_3_1) {
90
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
91
if (err != NULL) {
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
92
error_propagate(errp, err);
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
93
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
94
return;
52
- {
95
}
53
- int shift = cmode_3_1 * 8;
96
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
97
- sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
55
- break;
98
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
56
- }
99
+ sysbus_mmio_get_region(sbd, 0));
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
100
}
130
}
101
}
131
102
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
103
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
104
armv7m = qdev_create(NULL, "armv7m");
134
index XXXXXXX..XXXXXXX 100644
105
qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
135
--- a/target/arm/translate.c
106
qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
136
+++ b/target/arm/translate.c
107
+ object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
108
+ "memory", &error_abort);
138
case 14:
109
/* This will exit with an error if the user passed us a bad cpu_model */
139
if (op) {
110
qdev_init_nofail(armv7m);
140
/*
111
141
- * This is the only case where the top and bottom 32 bits
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
112
--
168
--
113
2.7.4
169
2.20.1
114
170
115
171
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/21] qdev: Have qdev_set_parent_bus() handle devices already on a bus
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
Instead of qdev_set_parent_bus() silently doing the wrong
1
Use dup_const() instead of bitfield_replicate() in
2
thing if it's handed a device that's already on a bus,
2
disas_simd_mod_imm().
3
have it remove the device from the old bus and add it to
3
4
the new one. This is useful for the raspi2 sdcard.
4
(We can't replace the other use of bitfield_replicate() in this file,
5
in logic_imm_decode_wmask(), because that location needs to handle 2
6
and 4 bit elements, which dup_const() cannot.)
5
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1488293711-14195-2-git-send-email-peter.maydell@linaro.org
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
9
---
11
---
10
hw/core/qdev.c | 14 ++++++++++++++
12
target/arm/translate-a64.c | 2 +-
11
1 file changed, 14 insertions(+)
13
1 file changed, 1 insertion(+), 1 deletion(-)
12
14
13
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/core/qdev.c
17
--- a/target/arm/translate-a64.c
16
+++ b/hw/core/qdev.c
18
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
18
20
/* FMOV (vector, immediate) - half-precision */
19
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
21
imm = vfp_expand_imm(MO_16, abcdefgh);
20
{
22
/* now duplicate across the lanes */
21
+ bool replugging = dev->parent_bus != NULL;
23
- imm = bitfield_replicate(imm, 16);
22
+
24
+ imm = dup_const(MO_16, imm);
23
+ if (replugging) {
25
} else {
24
+ /* Keep a reference to the device while it's not plugged into
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
25
+ * any bus, to avoid it potentially evaporating when it is
27
}
26
+ * dereffed in bus_remove_child().
27
+ */
28
+ object_ref(OBJECT(dev));
29
+ bus_remove_child(dev->parent_bus, dev);
30
+ object_unref(OBJECT(dev->parent_bus));
31
+ }
32
dev->parent_bus = bus;
33
object_ref(OBJECT(bus));
34
bus_add_child(bus, dev);
35
+ if (replugging) {
36
+ object_unref(OBJECT(dev));
37
+ }
38
}
39
40
/* Create a new device. This only initializes the device state
41
--
28
--
42
2.7.4
29
2.20.1
43
30
44
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/21] hw/sd: add card-reparenting function
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
2
5
3
Provide a new function sdbus_reparent_card() in sd core for reparenting
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
a card from a SDBus to another one.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
5
15
6
This function is required by the raspi platform, where the two SD
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
controllers can be dynamically switched.
8
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org
13
Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a doc comment to the header file; changed to
16
use new behaviour of qdev_set_parent_bus()]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/sd/sd.h | 11 +++++++++++
20
hw/sd/core.c | 27 +++++++++++++++++++++++++++
21
2 files changed, 38 insertions(+)
22
23
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/sd/sd.h
18
--- a/target/arm/helper-mve.h
26
+++ b/include/hw/sd/sd.h
19
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ uint8_t sdbus_read_data(SDBus *sd);
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
28
bool sdbus_data_ready(SDBus *sd);
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
29
bool sdbus_get_inserted(SDBus *sd);
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
30
bool sdbus_get_readonly(SDBus *sd);
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
31
+/**
24
+
32
+ * sdbus_reparent_card: Reparent an SD card from one controller to another
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
33
+ * @from: controller bus to remove card from
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
34
+ * @to: controller bus to move card to
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
35
+ *
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
36
+ * Reparent an SD card, effectively unplugging it from one controller
29
index XXXXXXX..XXXXXXX 100644
37
+ * and inserting it into another. This is useful for SoCs like the
30
--- a/target/arm/mve.decode
38
+ * bcm2835 which have two SD controllers and connect a single SD card
31
+++ b/target/arm/mve.decode
39
+ * to them, selected by the guest reprogramming GPIO line routing.
32
@@ -XXX,XX +XXX,XX @@
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
34
%size_28 28:1 !function=plus_1
35
36
+# 1imm format immediate
37
+%imm_28_16_0 28:1 16:3 0:4
38
+
39
&vldr_vstr rn qd imm p a w size l u
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
40
+ */
82
+ */
41
+void sdbus_reparent_card(SDBus *from, SDBus *to);
83
+#define DO_1OP_IMM(OP, FN) \
42
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
43
/* Functions to be used by SD devices to report back to qdevified controllers */
85
+ { \
44
void sdbus_set_inserted(SDBus *sd, bool inserted);
86
+ uint64_t *da = vda; \
45
diff --git a/hw/sd/core.c b/hw/sd/core.c
87
+ uint16_t mask = mve_element_mask(env); \
46
index XXXXXXX..XXXXXXX 100644
88
+ unsigned e; \
47
--- a/hw/sd/core.c
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
48
+++ b/hw/sd/core.c
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
49
@@ -XXX,XX +XXX,XX @@ void sdbus_set_readonly(SDBus *sdbus, bool readonly)
91
+ } \
50
}
92
+ mve_advance_vpt(env); \
51
}
52
53
+void sdbus_reparent_card(SDBus *from, SDBus *to)
54
+{
55
+ SDState *card = get_card(from);
56
+ SDCardClass *sc;
57
+ bool readonly;
58
+
59
+ /* We directly reparent the card object rather than implementing this
60
+ * as a hotpluggable connection because we don't want to expose SD cards
61
+ * to users as being hotpluggable, and we can get away with it in this
62
+ * limited use case. This could perhaps be implemented more cleanly in
63
+ * future by adding support to the hotplug infrastructure for "device
64
+ * can be hotplugged only via code, not by user".
65
+ */
66
+
67
+ if (!card) {
68
+ return;
69
+ }
93
+ }
70
+
94
+
71
+ sc = SD_CARD_GET_CLASS(card);
95
+#define DO_MOVI(N, I) (I)
72
+ readonly = sc->get_readonly(card);
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
73
+
98
+
74
+ sdbus_set_inserted(from, false);
99
+DO_1OP_IMM(vmovi, DO_MOVI)
75
+ qdev_set_parent_bus(DEVICE(card), &to->qbus);
100
+DO_1OP_IMM(vandi, DO_ANDI)
76
+ sdbus_set_inserted(to, true);
101
+DO_1OP_IMM(vorri, DO_ORRI)
77
+ sdbus_set_readonly(to, readonly);
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
122
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
124
+{
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
135
+ }
136
+
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
138
+
139
+ qd = mve_qreg_ptr(a->qd);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
78
+}
144
+}
79
+
145
+
80
static const TypeInfo sd_bus_info = {
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
81
.name = TYPE_SD_BUS,
147
+{
82
.parent = TYPE_BUS,
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
168
+ }
169
+ return do_1imm(s, a, fn);
170
+}
83
--
171
--
84
2.7.4
172
2.20.1
85
173
86
174
diff view generated by jsdifflib
New patch
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
and VQSHLU.
3
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
10
---
11
target/arm/helper-mve.h | 16 +++++++++++
12
target/arm/mve.decode | 23 +++++++++++++++
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
15
4 files changed, 147 insertions(+)
16
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
224
--
225
2.20.1
226
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
Reset CPU interface registers of GICv3 when CPU is reset.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
For this, ARMCPRegInfo struct is registered with one ICC
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
register whose resetfn is called when cpu is reset.
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
6
17
7
All the ICC registers are reset under one single register
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
reset function instead of calling resetfn for each ICC
9
register.
10
11
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1487850673-26455-6-git-send-email-vijay.kilari@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/intc/arm_gicv3_kvm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
18
1 file changed, 60 insertions(+)
19
20
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_kvm.c
20
--- a/target/arm/helper-mve.h
23
+++ b/hw/intc/arm_gicv3_kvm.c
21
+++ b/target/arm/helper-mve.h
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
25
}
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
48
+++ b/target/arm/translate.h
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
50
return x * 2 + 1;
26
}
51
}
27
52
28
+static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
53
+static inline int rsub_64(DisasContext *s, int x)
29
+{
54
+{
30
+ ARMCPU *cpu;
55
+ return 64 - x;
31
+ GICv3State *s;
32
+ GICv3CPUState *c;
33
+
34
+ c = (GICv3CPUState *)env->gicv3state;
35
+ s = c->gic;
36
+ cpu = ARM_CPU(c->cpu);
37
+
38
+ /* Initialize to actual HW supported configuration */
39
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
40
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
41
+ &c->icc_ctlr_el1[GICV3_NS], false);
42
+
43
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
44
+ c->icc_pmr_el1 = 0;
45
+ c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
46
+ c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
47
+ c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
48
+
49
+ c->icc_sre_el1 = 0x7;
50
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
51
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
52
+}
56
+}
53
+
57
+
54
static void kvm_arm_gicv3_reset(DeviceState *dev)
58
+static inline int rsub_32(DisasContext *s, int x)
59
+{
60
+ return 32 - x;
61
+}
62
+
63
+static inline int rsub_16(DisasContext *s, int x)
64
+{
65
+ return 16 - x;
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
55
{
74
{
56
GICv3State *s = ARM_GICV3_COMMON(dev);
75
return (dc->features & (1ULL << feature)) != 0;
57
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
58
kvm_arm_gicv3_put(s);
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/mve.decode
79
+++ b/target/arm/mve.decode
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
88
+
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
59
}
163
}
60
164
61
+/*
165
-static inline int rsub_64(DisasContext *s, int x)
62
+ * CPU interface registers of GIC needs to be reset on CPU reset.
166
-{
63
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
167
- return 64 - x;
64
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
168
-}
65
+ * register reset, we define only one register of CPU interface instead
169
-
66
+ * of defining all the registers.
170
-static inline int rsub_32(DisasContext *s, int x)
67
+ */
171
-{
68
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
172
- return 32 - x;
69
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
173
-}
70
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
174
-static inline int rsub_16(DisasContext *s, int x)
71
+ /*
175
-{
72
+ * If ARM_CP_NOP is used, resetfn is not called,
176
- return 16 - x;
73
+ * So ARM_CP_NO_RAW is appropriate type.
177
-}
74
+ */
178
-static inline int rsub_8(DisasContext *s, int x)
75
+ .type = ARM_CP_NO_RAW,
179
-{
76
+ .access = PL1_RW,
180
- return 8 - x;
77
+ .readfn = arm_cp_read_zero,
181
-}
78
+ .writefn = arm_cp_write_ignore,
182
-
79
+ /*
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
80
+ * We hang the whole cpu interface reset routine off here
81
+ * rather than parcelling it out into one little function
82
+ * per register
83
+ */
84
+ .resetfn = arm_gicv3_icc_reset,
85
+ },
86
+ REGINFO_SENTINEL
87
+};
88
+
89
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
90
{
184
{
91
GICv3State *s = KVM_ARM_GICV3(dev);
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
92
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
93
94
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
95
96
+ for (i = 0; i < s->num_cpu; i++) {
97
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
98
+
99
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
100
+ }
101
+
102
/* Try to create the device via the device control API */
103
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
104
if (s->dev_fd < 0) {
105
--
186
--
106
2.7.4
187
2.20.1
107
188
108
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/21] hw/intc/arm_gicv3_kvm: Implement get/put functions
[PULL 15/24] target/arm: Implement MVE VSHLL
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
This actually implements pre_save and post_load methods for in-kernel
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
vGICv3.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 9 +++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
5
15
6
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
10
Message-id: 1487850673-26455-4-git-send-email-vijay.kilari@gmail.com
11
[PMM:
12
* use decimal, not 0bnnn
13
* fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1
14
* completely rearranged the get and put functions to read and write
15
the state in a natural order, rather than mixing distributor and
16
redistributor state together]
17
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
18
[Vijay:
19
* Update macro KVM_VGIC_ATTR
20
* Use 32 bit access for gicd and gicr
21
* GICD_IROUTER, GICD_TYPER, GICR_PROPBASER and GICR_PENDBASER reg
22
access are changed from 64-bit to 32-bit access
23
* Add ICC_SRE_EL1 save and restore
24
* Dropped translate_fn mechanism and coded functions to handle
25
save and restore of edge_trigger and priority
26
* Number of APnR register saved/restored based on number of
27
priority bits supported]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
---
30
hw/intc/gicv3_internal.h | 1 +
31
hw/intc/arm_gicv3_kvm.c | 573 +++++++++++++++++++++++++++++++++++++++++++++--
32
2 files changed, 558 insertions(+), 16 deletions(-)
33
34
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
35
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/intc/gicv3_internal.h
18
--- a/target/arm/helper-mve.h
37
+++ b/hw/intc/gicv3_internal.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
38
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
39
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
40
#define ICC_CTLR_EL1_PMHE (1U << 6)
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
41
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
40
42
+#define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
43
#define ICC_CTLR_EL1_IDBITS_SHIFT 11
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
44
#define ICC_CTLR_EL1_SEIS (1U << 14)
43
+# VSHLL encoding T2 where shift == esize
45
#define ICC_CTLR_EL1_A3V (1U << 15)
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
46
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
45
+ qd=%qd qm=%qm size=0 shift=8
47
index XXXXXXX..XXXXXXX 100644
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
48
--- a/hw/intc/arm_gicv3_kvm.c
47
+ qd=%qd qm=%qm size=1 shift=16
49
+++ b/hw/intc/arm_gicv3_kvm.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "qapi/error.h"
52
#include "hw/intc/arm_gicv3_common.h"
53
#include "hw/sysbus.h"
54
+#include "qemu/error-report.h"
55
#include "sysemu/kvm.h"
56
#include "kvm_arm.h"
57
+#include "gicv3_internal.h"
58
#include "vgic_common.h"
59
#include "migration/migration.h"
60
61
@@ -XXX,XX +XXX,XX @@
62
#define KVM_ARM_GICV3_GET_CLASS(obj) \
63
OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
64
65
+#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
66
+ (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
67
+ ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
68
+ ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
69
+ ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
70
+ ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
71
+
48
+
72
+#define ICC_PMR_EL1 \
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
73
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
50
%rshift_i5 16:5 !function=rsub_32
74
+#define ICC_BPR0_EL1 \
51
%rshift_i4 16:4 !function=rsub_16
75
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
76
+#define ICC_AP0R_EL1(n) \
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
77
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
78
+#define ICC_AP1R_EL1(n) \
55
79
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
80
+#define ICC_BPR1_EL1 \
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
81
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
82
+#define ICC_CTLR_EL1 \
59
+# overlaps what would be size=0b11 VMULH/VRMULH
83
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
84
+#define ICC_SRE_EL1 \
85
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
86
+#define ICC_IGRPEN0_EL1 \
87
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
88
+#define ICC_IGRPEN1_EL1 \
89
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
90
+
91
typedef struct KVMARMGICv3Class {
92
ARMGICv3CommonClass parent_class;
93
DeviceRealize parent_realize;
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
95
kvm_arm_gic_set_irq(s->num_irq, irq, level);
96
}
97
98
+#define KVM_VGIC_ATTR(reg, typer) \
99
+ ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
100
+
101
+static inline void kvm_gicd_access(GICv3State *s, int offset,
102
+ uint32_t *val, bool write)
103
+{
60
+{
104
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
105
+ KVM_VGIC_ATTR(offset, 0),
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
106
+ val, write);
63
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
107
+}
67
+}
108
+
68
+
109
+static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
110
+ uint32_t *val, bool write)
111
+{
69
+{
112
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
113
+ KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
114
+ val, write);
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
115
+}
74
+}
116
+
75
+
117
+static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
118
+ uint64_t *val, bool write)
119
+{
76
+{
120
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
121
+ KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
122
+ val, write);
79
+
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
123
+}
81
+}
124
+
82
+
125
+static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
126
+ uint32_t *val, bool write)
127
+{
83
+{
128
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
129
+ KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
130
+ (VGIC_LEVEL_INFO_LINE_LEVEL <<
86
+
131
+ KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
132
+ val, write);
133
+}
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
134
+
96
+
135
+/* Loop through each distributor IRQ related register; since bits
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
136
+ * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
137
+ * is enabled, we skip those.
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
112
+++ b/target/arm/mve_helper.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
138
+ */
124
+ */
139
+#define for_each_dist_irq_reg(_irq, _max, _field_width) \
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
140
+ for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
141
+
127
+ void *vm, uint32_t shift) \
142
+static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
128
+ { \
143
+{
129
+ LTYPE *d = vd; \
144
+ uint32_t reg, *field;
130
+ TYPE *m = vm; \
145
+ int irq;
131
+ uint16_t mask = mve_element_mask(env); \
146
+
132
+ unsigned le; \
147
+ field = (uint32_t *)bmp;
133
+ assert(shift <= 16); \
148
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
149
+ kvm_gicd_access(s, offset, &reg, false);
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
150
+ *field = reg;
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
151
+ offset += 4;
137
+ } \
152
+ field++;
138
+ mve_advance_vpt(env); \
153
+ }
154
+}
155
+
156
+static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
157
+{
158
+ uint32_t reg, *field;
159
+ int irq;
160
+
161
+ field = (uint32_t *)bmp;
162
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
163
+ reg = *field;
164
+ kvm_gicd_access(s, offset, &reg, true);
165
+ offset += 4;
166
+ field++;
167
+ }
168
+}
169
+
170
+static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
171
+ uint32_t *bmp)
172
+{
173
+ uint32_t reg;
174
+ int irq;
175
+
176
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
177
+ kvm_gicd_access(s, offset, &reg, false);
178
+ reg = half_unshuffle32(reg >> 1);
179
+ if (irq % 32 != 0) {
180
+ reg = (reg << 16);
181
+ }
182
+ *gic_bmp_ptr32(bmp, irq) |= reg;
183
+ offset += 4;
184
+ }
185
+}
186
+
187
+static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
188
+ uint32_t *bmp)
189
+{
190
+ uint32_t reg;
191
+ int irq;
192
+
193
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
194
+ reg = *gic_bmp_ptr32(bmp, irq);
195
+ if (irq % 32 != 0) {
196
+ reg = (reg & 0xffff0000) >> 16;
197
+ } else {
198
+ reg = reg & 0xffff;
199
+ }
200
+ reg = half_shuffle32(reg) << 1;
201
+ kvm_gicd_access(s, offset, &reg, true);
202
+ offset += 4;
203
+ }
204
+}
205
+
206
+static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
207
+{
208
+ uint32_t reg;
209
+ int irq;
210
+
211
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
212
+ kvm_gic_line_level_access(s, irq, 0, &reg, false);
213
+ *gic_bmp_ptr32(bmp, irq) = reg;
214
+ }
215
+}
216
+
217
+static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
218
+{
219
+ uint32_t reg;
220
+ int irq;
221
+
222
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
223
+ reg = *gic_bmp_ptr32(bmp, irq);
224
+ kvm_gic_line_level_access(s, irq, 0, &reg, true);
225
+ }
226
+}
227
+
228
+/* Read a bitmap register group from the kernel VGIC. */
229
+static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
230
+{
231
+ uint32_t reg;
232
+ int irq;
233
+
234
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
235
+ kvm_gicd_access(s, offset, &reg, false);
236
+ *gic_bmp_ptr32(bmp, irq) = reg;
237
+ offset += 4;
238
+ }
239
+}
240
+
241
+static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
242
+ uint32_t clroffset, uint32_t *bmp)
243
+{
244
+ uint32_t reg;
245
+ int irq;
246
+
247
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
248
+ /* If this bitmap is a set/clear register pair, first write to the
249
+ * clear-reg to clear all bits before using the set-reg to write
250
+ * the 1 bits.
251
+ */
252
+ if (clroffset != 0) {
253
+ reg = 0;
254
+ kvm_gicd_access(s, clroffset, &reg, true);
255
+ }
256
+ reg = *gic_bmp_ptr32(bmp, irq);
257
+ kvm_gicd_access(s, offset, &reg, true);
258
+ offset += 4;
259
+ }
260
+}
261
+
262
+static void kvm_arm_gicv3_check(GICv3State *s)
263
+{
264
+ uint32_t reg;
265
+ uint32_t num_irq;
266
+
267
+ /* Sanity checking s->num_irq */
268
+ kvm_gicd_access(s, GICD_TYPER, &reg, false);
269
+ num_irq = ((reg & 0x1f) + 1) * 32;
270
+
271
+ if (num_irq < s->num_irq) {
272
+ error_report("Model requests %u IRQs, but kernel supports max %u",
273
+ s->num_irq, num_irq);
274
+ abort();
275
+ }
276
+}
277
+
278
static void kvm_arm_gicv3_put(GICv3State *s)
279
{
280
- /* TODO */
281
- DPRINTF("Cannot put kernel gic state, no kernel interface\n");
282
+ uint32_t regl, regh, reg;
283
+ uint64_t reg64, redist_typer;
284
+ int ncpu, i;
285
+
286
+ kvm_arm_gicv3_check(s);
287
+
288
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
289
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
290
+ redist_typer = ((uint64_t)regh << 32) | regl;
291
+
292
+ reg = s->gicd_ctlr;
293
+ kvm_gicd_access(s, GICD_CTLR, &reg, true);
294
+
295
+ if (redist_typer & GICR_TYPER_PLPIS) {
296
+ /* Set base addresses before LPIs are enabled by GICR_CTLR write */
297
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
298
+ GICv3CPUState *c = &s->cpu[ncpu];
299
+
300
+ reg64 = c->gicr_propbaser;
301
+ regl = (uint32_t)reg64;
302
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, true);
303
+ regh = (uint32_t)(reg64 >> 32);
304
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
305
+
306
+ reg64 = c->gicr_pendbaser;
307
+ if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
308
+ /* Setting PTZ is advised if LPIs are disabled, to reduce
309
+ * GIC initialization time.
310
+ */
311
+ reg64 |= GICR_PENDBASER_PTZ;
312
+ }
313
+ regl = (uint32_t)reg64;
314
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
315
+ regh = (uint32_t)(reg64 >> 32);
316
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, true);
317
+ }
318
+ }
139
+ }
319
+
140
+
320
+ /* Redistributor state (one per CPU) */
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
321
+
146
+
322
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
147
+DO_VSHLL_ALL(vshllb, false)
323
+ GICv3CPUState *c = &s->cpu[ncpu];
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
324
+
157
+
325
+ reg = c->gicr_ctlr;
158
+#define DO_VSHLL(INSN, FN) \
326
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, true);
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
327
+
160
+ { \
328
+ reg = c->gicr_statusr[GICV3_NS];
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
329
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, true);
162
+ gen_helper_mve_##FN##b, \
330
+
163
+ gen_helper_mve_##FN##h, \
331
+ reg = c->gicr_waker;
164
+ }; \
332
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, true);
165
+ return do_2shift(s, a, fns[a->size], false); \
333
+
334
+ reg = c->gicr_igroupr0;
335
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, true);
336
+
337
+ reg = ~0;
338
+ kvm_gicr_access(s, GICR_ICENABLER0, ncpu, &reg, true);
339
+ reg = c->gicr_ienabler0;
340
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, true);
341
+
342
+ /* Restore config before pending so we treat level/edge correctly */
343
+ reg = half_shuffle32(c->edge_trigger >> 16) << 1;
344
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, true);
345
+
346
+ reg = c->level;
347
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, true);
348
+
349
+ reg = ~0;
350
+ kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true);
351
+ reg = c->gicr_ipendr0;
352
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true);
353
+
354
+ reg = ~0;
355
+ kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, &reg, true);
356
+ reg = c->gicr_iactiver0;
357
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true);
358
+
359
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
360
+ reg = c->gicr_ipriorityr[i] |
361
+ (c->gicr_ipriorityr[i + 1] << 8) |
362
+ (c->gicr_ipriorityr[i + 2] << 16) |
363
+ (c->gicr_ipriorityr[i + 3] << 24);
364
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, true);
365
+ }
366
+ }
166
+ }
367
+
167
+
368
+ /* Distributor state (shared between all CPUs */
168
+DO_VSHLL(VSHLL_BS, vshllbs)
369
+ reg = s->gicd_statusr[GICV3_NS];
169
+DO_VSHLL(VSHLL_BU, vshllbu)
370
+ kvm_gicd_access(s, GICD_STATUSR, &reg, true);
170
+DO_VSHLL(VSHLL_TS, vshllts)
371
+
171
+DO_VSHLL(VSHLL_TU, vshlltu)
372
+ /* s->enable bitmap -> GICD_ISENABLERn */
373
+ kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
374
+
375
+ /* s->group bitmap -> GICD_IGROUPRn */
376
+ kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
377
+
378
+ /* Restore targets before pending to ensure the pending state is set on
379
+ * the appropriate CPU interfaces in the kernel
380
+ */
381
+
382
+ /* s->gicd_irouter[irq] -> GICD_IROUTERn
383
+ * We can't use kvm_dist_put() here because the registers are 64-bit
384
+ */
385
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
386
+ uint32_t offset;
387
+
388
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
389
+ reg = (uint32_t)s->gicd_irouter[i];
390
+ kvm_gicd_access(s, offset, &reg, true);
391
+
392
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
393
+ reg = (uint32_t)(s->gicd_irouter[i] >> 32);
394
+ kvm_gicd_access(s, offset, &reg, true);
395
+ }
396
+
397
+ /* s->trigger bitmap -> GICD_ICFGRn
398
+ * (restore configuration registers before pending IRQs so we treat
399
+ * level/edge correctly)
400
+ */
401
+ kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
402
+
403
+ /* s->level bitmap -> line_level */
404
+ kvm_gic_put_line_level_bmp(s, s->level);
405
+
406
+ /* s->pending bitmap -> GICD_ISPENDRn */
407
+ kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
408
+
409
+ /* s->active bitmap -> GICD_ISACTIVERn */
410
+ kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
411
+
412
+ /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
413
+ kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
414
+
415
+ /* CPU Interface state (one per CPU) */
416
+
417
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
418
+ GICv3CPUState *c = &s->cpu[ncpu];
419
+ int num_pri_bits;
420
+
421
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
422
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
423
+ &c->icc_ctlr_el1[GICV3_NS], true);
424
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
425
+ &c->icc_igrpen[GICV3_G0], true);
426
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
427
+ &c->icc_igrpen[GICV3_G1NS], true);
428
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
429
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
430
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
431
+
432
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
433
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
434
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
435
+
436
+ switch (num_pri_bits) {
437
+ case 7:
438
+ reg64 = c->icc_apr[GICV3_G0][3];
439
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, true);
440
+ reg64 = c->icc_apr[GICV3_G0][2];
441
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, true);
442
+ case 6:
443
+ reg64 = c->icc_apr[GICV3_G0][1];
444
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, true);
445
+ default:
446
+ reg64 = c->icc_apr[GICV3_G0][0];
447
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, true);
448
+ }
449
+
450
+ switch (num_pri_bits) {
451
+ case 7:
452
+ reg64 = c->icc_apr[GICV3_G1NS][3];
453
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true);
454
+ reg64 = c->icc_apr[GICV3_G1NS][2];
455
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true);
456
+ case 6:
457
+ reg64 = c->icc_apr[GICV3_G1NS][1];
458
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true);
459
+ default:
460
+ reg64 = c->icc_apr[GICV3_G1NS][0];
461
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true);
462
+ }
463
+ }
464
}
465
466
static void kvm_arm_gicv3_get(GICv3State *s)
467
{
468
- /* TODO */
469
- DPRINTF("Cannot get kernel gic state, no kernel interface\n");
470
+ uint32_t regl, regh, reg;
471
+ uint64_t reg64, redist_typer;
472
+ int ncpu, i;
473
+
474
+ kvm_arm_gicv3_check(s);
475
+
476
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
477
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
478
+ redist_typer = ((uint64_t)regh << 32) | regl;
479
+
480
+ kvm_gicd_access(s, GICD_CTLR, &reg, false);
481
+ s->gicd_ctlr = reg;
482
+
483
+ /* Redistributor state (one per CPU) */
484
+
485
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
486
+ GICv3CPUState *c = &s->cpu[ncpu];
487
+
488
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, false);
489
+ c->gicr_ctlr = reg;
490
+
491
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, false);
492
+ c->gicr_statusr[GICV3_NS] = reg;
493
+
494
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, false);
495
+ c->gicr_waker = reg;
496
+
497
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, false);
498
+ c->gicr_igroupr0 = reg;
499
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, false);
500
+ c->gicr_ienabler0 = reg;
501
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, false);
502
+ c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
503
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, false);
504
+ c->level = reg;
505
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, false);
506
+ c->gicr_ipendr0 = reg;
507
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false);
508
+ c->gicr_iactiver0 = reg;
509
+
510
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
511
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false);
512
+ c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
513
+ c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
514
+ c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
515
+ c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
516
+ }
517
+ }
518
+
519
+ if (redist_typer & GICR_TYPER_PLPIS) {
520
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
521
+ GICv3CPUState *c = &s->cpu[ncpu];
522
+
523
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, false);
524
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, false);
525
+ c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
526
+
527
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, false);
528
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, false);
529
+ c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
530
+ }
531
+ }
532
+
533
+ /* Distributor state (shared between all CPUs */
534
+
535
+ kvm_gicd_access(s, GICD_STATUSR, &reg, false);
536
+ s->gicd_statusr[GICV3_NS] = reg;
537
+
538
+ /* GICD_IGROUPRn -> s->group bitmap */
539
+ kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
540
+
541
+ /* GICD_ISENABLERn -> s->enabled bitmap */
542
+ kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
543
+
544
+ /* Line level of irq */
545
+ kvm_gic_get_line_level_bmp(s, s->level);
546
+ /* GICD_ISPENDRn -> s->pending bitmap */
547
+ kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
548
+
549
+ /* GICD_ISACTIVERn -> s->active bitmap */
550
+ kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
551
+
552
+ /* GICD_ICFGRn -> s->trigger bitmap */
553
+ kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
554
+
555
+ /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
556
+ kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
557
+
558
+ /* GICD_IROUTERn -> s->gicd_irouter[irq] */
559
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
560
+ uint32_t offset;
561
+
562
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
563
+ kvm_gicd_access(s, offset, &regl, false);
564
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
565
+ kvm_gicd_access(s, offset, &regh, false);
566
+ s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
567
+ }
568
+
569
+ /*****************************************************************
570
+ * CPU Interface(s) State
571
+ */
572
+
573
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
574
+ GICv3CPUState *c = &s->cpu[ncpu];
575
+ int num_pri_bits;
576
+
577
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
578
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
579
+ &c->icc_ctlr_el1[GICV3_NS], false);
580
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
581
+ &c->icc_igrpen[GICV3_G0], false);
582
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
583
+ &c->icc_igrpen[GICV3_G1NS], false);
584
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
585
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
586
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
587
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
588
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
589
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
590
+
591
+ switch (num_pri_bits) {
592
+ case 7:
593
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, false);
594
+ c->icc_apr[GICV3_G0][3] = reg64;
595
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, false);
596
+ c->icc_apr[GICV3_G0][2] = reg64;
597
+ case 6:
598
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, false);
599
+ c->icc_apr[GICV3_G0][1] = reg64;
600
+ default:
601
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, false);
602
+ c->icc_apr[GICV3_G0][0] = reg64;
603
+ }
604
+
605
+ switch (num_pri_bits) {
606
+ case 7:
607
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false);
608
+ c->icc_apr[GICV3_G1NS][3] = reg64;
609
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false);
610
+ c->icc_apr[GICV3_G1NS][2] = reg64;
611
+ case 6:
612
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false);
613
+ c->icc_apr[GICV3_G1NS][1] = reg64;
614
+ default:
615
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);
616
+ c->icc_apr[GICV3_G1NS][0] = reg64;
617
+ }
618
+ }
619
}
620
621
static void kvm_arm_gicv3_reset(DeviceState *dev)
622
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
623
DPRINTF("Reset\n");
624
625
kgc->parent_reset(dev);
626
+
627
+ if (s->migration_blocker) {
628
+ DPRINTF("Cannot put kernel gic state, no kernel interface\n");
629
+ return;
630
+ }
631
+
632
kvm_arm_gicv3_put(s);
633
}
634
635
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
636
637
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
638
639
- /* Block migration of a KVM GICv3 device: the API for saving and restoring
640
- * the state in the kernel is not yet finalised in the kernel or
641
- * implemented in QEMU.
642
- */
643
- error_setg(&s->migration_blocker, "vGICv3 migration is not implemented");
644
- migrate_add_blocker(s->migration_blocker, &local_err);
645
- if (local_err) {
646
- error_propagate(errp, local_err);
647
- error_free(s->migration_blocker);
648
- return;
649
- }
650
-
651
/* Try to create the device via the device control API */
652
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
653
if (s->dev_fd < 0) {
654
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
655
656
kvm_irqchip_commit_routes(kvm_state);
657
}
658
+
659
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
660
+ GICD_CTLR)) {
661
+ error_setg(&s->migration_blocker, "This operating system kernel does "
662
+ "not support vGICv3 migration");
663
+ migrate_add_blocker(s->migration_blocker, &local_err);
664
+ if (local_err) {
665
+ error_propagate(errp, local_err);
666
+ error_free(s->migration_blocker);
667
+ return;
668
+ }
669
+ }
670
}
671
672
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
673
--
172
--
674
2.7.4
173
2.20.1
675
174
676
175
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/21] armv7m: Don't put core v7M devices under CONFIG_STELLARIS
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
The NVIC is a core v7M device that exists for all v7M CPUs;
1
Implement the MVE VSRI and VSLI insns, which perform a
2
put it under a CONFIG_ARM_V7M rather than hiding it under
2
shift-and-insert operation.
3
CONFIG_STELLARIS.
4
5
(We'll use CONFIG_ARM_V7M for the SysTick device too
6
when we split it out of the NVIC.)
7
3
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
11
Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
12
---
7
---
13
hw/intc/Makefile.objs | 2 +-
8
target/arm/helper-mve.h | 8 ++++++++
14
default-configs/arm-softmmu.mak | 2 ++
9
target/arm/mve.decode | 9 ++++++++
15
2 files changed, 3 insertions(+), 1 deletion(-)
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
16
13
17
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/Makefile.objs
16
--- a/target/arm/helper-mve.h
20
+++ b/hw/intc/Makefile.objs
17
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_APIC) += apic.o apic_common.o
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
-obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
22
+
26
+obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
obj-$(CONFIG_IOAPIC) += ioapic.o
26
+
30
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
32
--- a/default-configs/arm-softmmu.mak
32
--- a/target/arm/mve.decode
33
+++ b/default-configs/arm-softmmu.mak
33
+++ b/target/arm/mve.decode
34
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM11MPCORE=y
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
CONFIG_A9MPCORE=y
35
36
CONFIG_A15MPCORE=y
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
+CONFIG_ARM_V7M=y
39
+
38
+
40
CONFIG_ARM_GIC=y
39
+# Shift-and-insert
41
CONFIG_ARM_GIC_KVM=$(CONFIG_KVM)
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
42
CONFIG_ARM_TIMER=y
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
43
--
114
--
44
2.7.4
115
2.20.1
45
116
46
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/21] armv7m: QOMify the armv7m container
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
Create a proper QOM object for the armv7m container, which
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
holds the CPU, the NVIC and the bitband regions.
2
3
do_urshr() is borrowed from sve_helper.c.
3
4
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
7
---
8
---
8
include/hw/arm/armv7m.h | 51 ++++++++++++++++++
9
target/arm/helper-mve.h | 10 ++++++++++
9
hw/arm/armv7m.c | 139 +++++++++++++++++++++++++++++++++++++++++++-----
10
target/arm/mve.decode | 11 +++++++++++
10
2 files changed, 178 insertions(+), 12 deletions(-)
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
11
create mode 100644 include/hw/arm/armv7m.h
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
12
14
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX
17
--- a/target/arm/helper-mve.h
16
--- /dev/null
18
+++ b/target/arm/helper-mve.h
17
+++ b/include/hw/arm/armv7m.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
@@ -XXX,XX +XXX,XX @@
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
19
+/*
61
+/*
20
+ * ARMv7M CPU object
62
+ * Narrowing right shifts, taking a double sized input, shifting it
21
+ *
63
+ * and putting the result in either the top or bottom half of the output.
22
+ * Copyright (c) 2017 Linaro Ltd
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
23
+ * Written by Peter Maydell <peter.maydell@linaro.org>
24
+ *
25
+ * This code is licensed under the GPL version 2 or later.
26
+ */
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
27
+
80
+
28
+#ifndef HW_ARM_ARMV7M_H
81
+#define DO_VSHRN_ALL(OP, FN) \
29
+#define HW_ARM_ARMV7M_H
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
30
+
86
+
31
+#include "hw/sysbus.h"
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
32
+#include "hw/arm/armv7m_nvic.h"
33
+
34
+#define TYPE_BITBAND "ARM,bitband-memory"
35
+#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
36
+
37
+typedef struct {
38
+ /*< private >*/
39
+ SysBusDevice parent_obj;
40
+ /*< public >*/
41
+
42
+ MemoryRegion iomem;
43
+ uint32_t base;
44
+} BitBandState;
45
+
46
+#define TYPE_ARMV7M "armv7m"
47
+#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
48
+
49
+#define ARMV7M_NUM_BITBANDS 2
50
+
51
+/* ARMv7M container object.
52
+ * + Unnamed GPIO input lines: external IRQ lines for the NVIC
53
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
54
+ * + Property "cpu-model": CPU model to instantiate
55
+ * + Property "num-irq": number of external IRQ lines
56
+ */
57
+typedef struct ARMv7MState {
58
+ /*< private >*/
59
+ SysBusDevice parent_obj;
60
+ /*< public >*/
61
+ NVICState nvic;
62
+ BitBandState bitband[ARMV7M_NUM_BITBANDS];
63
+ ARMCPU *cpu;
64
+
65
+ /* Properties */
66
+ char *cpu_model;
67
+} ARMv7MState;
68
+
69
+#endif
70
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/armv7m.c
73
+++ b/hw/arm/armv7m.c
74
@@ -XXX,XX +XXX,XX @@
75
*/
76
77
#include "qemu/osdep.h"
78
+#include "hw/arm/armv7m.h"
79
#include "qapi/error.h"
80
#include "qemu-common.h"
81
#include "cpu.h"
82
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bitband_ops = {
83
.endianness = DEVICE_NATIVE_ENDIAN,
84
};
85
86
-#define TYPE_BITBAND "ARM,bitband-memory"
87
-#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
88
-
89
-typedef struct {
90
- /*< private >*/
91
- SysBusDevice parent_obj;
92
- /*< public >*/
93
-
94
- MemoryRegion iomem;
95
- uint32_t base;
96
-} BitBandState;
97
-
98
static void bitband_init(Object *obj)
99
{
100
BitBandState *s = BITBAND(obj);
101
@@ -XXX,XX +XXX,XX @@ static void armv7m_bitband_init(void)
102
103
/* Board init. */
104
105
+static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
106
+ 0x20000000, 0x40000000
107
+};
108
+
109
+static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
110
+ 0x22000000, 0x42000000
111
+};
112
+
113
+static void armv7m_instance_init(Object *obj)
114
+{
88
+{
115
+ ARMv7MState *s = ARMV7M(obj);
89
+ if (likely(sh < 64)) {
116
+ int i;
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
117
+
91
+ } else if (sh == 64) {
118
+ /* Can't init the cpu here, we don't yet know which model to use */
92
+ return x >> 63;
119
+
93
+ } else {
120
+ object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
94
+ return 0;
121
+ qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
122
+ object_property_add_alias(obj, "num-irq",
123
+ OBJECT(&s->nvic), "num-irq", &error_abort);
124
+
125
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
126
+ object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
127
+ qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
128
+ }
95
+ }
129
+}
96
+}
130
+
97
+
131
+static void armv7m_realize(DeviceState *dev, Error **errp)
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
132
+{
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
133
+ ARMv7MState *s = ARMV7M(dev);
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
134
+ Error *err = NULL;
101
index XXXXXXX..XXXXXXX 100644
135
+ int i;
102
--- a/target/arm/translate-mve.c
136
+ char **cpustr;
103
+++ b/target/arm/translate-mve.c
137
+ ObjectClass *oc;
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
138
+ const char *typename;
105
DO_VSHLL(VSHLL_BU, vshllbu)
139
+ CPUClass *cc;
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
140
+
108
+
141
+ cpustr = g_strsplit(s->cpu_model, ",", 2);
109
+#define DO_2SHIFT_N(INSN, FN) \
142
+
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
143
+ oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
111
+ { \
144
+ if (!oc) {
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
145
+ error_setg(errp, "Unknown CPU model %s", cpustr[0]);
113
+ gen_helper_mve_##FN##b, \
146
+ g_strfreev(cpustr);
114
+ gen_helper_mve_##FN##h, \
147
+ return;
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
148
+ }
117
+ }
149
+
118
+
150
+ cc = CPU_CLASS(oc);
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
151
+ typename = object_class_get_name(oc);
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
152
+ cc->parse_features(typename, cpustr[1], &err);
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
153
+ g_strfreev(cpustr);
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
154
+ if (err) {
155
+ error_propagate(errp, err);
156
+ return;
157
+ }
158
+
159
+ s->cpu = ARM_CPU(object_new(typename));
160
+ if (!s->cpu) {
161
+ error_setg(errp, "Unknown CPU model %s", s->cpu_model);
162
+ return;
163
+ }
164
+
165
+ object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
166
+ if (err != NULL) {
167
+ error_propagate(errp, err);
168
+ return;
169
+ }
170
+
171
+ /* Note that we must realize the NVIC after the CPU */
172
+ object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
173
+ if (err != NULL) {
174
+ error_propagate(errp, err);
175
+ return;
176
+ }
177
+
178
+ /* Alias the NVIC's input and output GPIOs as our own so the board
179
+ * code can wire them up. (We do this in realize because the
180
+ * NVIC doesn't create the input GPIO array until realize.)
181
+ */
182
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
183
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
184
+
185
+ /* Wire the NVIC up to the CPU */
186
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
187
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
188
+ s->cpu->env.nvic = &s->nvic;
189
+
190
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
191
+ Object *obj = OBJECT(&s->bitband[i]);
192
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
193
+
194
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
195
+ if (err != NULL) {
196
+ error_propagate(errp, err);
197
+ return;
198
+ }
199
+ object_property_set_bool(obj, true, "realized", &err);
200
+ if (err != NULL) {
201
+ error_propagate(errp, err);
202
+ return;
203
+ }
204
+
205
+ sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
206
+ }
207
+}
208
+
209
+static Property armv7m_properties[] = {
210
+ DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
211
+ DEFINE_PROP_END_OF_LIST(),
212
+};
213
+
214
+static void armv7m_class_init(ObjectClass *klass, void *data)
215
+{
216
+ DeviceClass *dc = DEVICE_CLASS(klass);
217
+
218
+ dc->realize = armv7m_realize;
219
+ dc->props = armv7m_properties;
220
+}
221
+
222
+static const TypeInfo armv7m_info = {
223
+ .name = TYPE_ARMV7M,
224
+ .parent = TYPE_SYS_BUS_DEVICE,
225
+ .instance_size = sizeof(ARMv7MState),
226
+ .instance_init = armv7m_instance_init,
227
+ .class_init = armv7m_class_init,
228
+};
229
+
230
static void armv7m_reset(void *opaque)
231
{
232
ARMCPU *cpu = opaque;
233
@@ -XXX,XX +XXX,XX @@ static const TypeInfo bitband_info = {
234
static void armv7m_register_types(void)
235
{
236
type_register_static(&bitband_info);
237
+ type_register_static(&armv7m_info);
238
}
239
240
type_init(armv7m_register_types)
241
--
123
--
242
2.7.4
124
2.20.1
243
125
244
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/21] stm32f205: Rename 'nvic' local to 'armv7m'
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
The local variable 'nvic' in stm32f205_soc_realize() no longer
1
Implement the MVE saturating shift-right-and-narrow insns
2
holds a direct pointer to the NVIC device; it is a pointer to
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
the ARMv7M container object. Rename it 'armv7m' accordingly.
3
4
do_srshr() is borrowed from sve_helper.c.
4
5
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 1487604965-23220-12-git-send-email-peter.maydell@linaro.org
10
---
9
---
11
hw/arm/stm32f205_soc.c | 18 +++++++++---------
10
target/arm/helper-mve.h | 30 +++++++++++
12
1 file changed, 9 insertions(+), 9 deletions(-)
11
target/arm/mve.decode | 28 ++++++++++
13
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
14
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
13
target/arm/translate-mve.c | 12 +++++
15
index XXXXXXX..XXXXXXX 100644
14
4 files changed, 174 insertions(+)
16
--- a/hw/arm/stm32f205_soc.c
15
17
+++ b/hw/arm/stm32f205_soc.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
17
index XXXXXXX..XXXXXXX 100644
19
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
18
--- a/target/arm/helper-mve.h
20
{
19
+++ b/target/arm/helper-mve.h
21
STM32F205State *s = STM32F205_SOC(dev_soc);
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
- DeviceState *dev, *nvic;
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ DeviceState *dev, *armv7m;
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
SysBusDevice *busdev;
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
Error *err = NULL;
24
+
26
int i;
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
vmstate_register_ram_global(sram);
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
29
+
31
- nvic = DEVICE(&s->armv7m);
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
- qdev_prop_set_uint32(nvic, "num-irq", 96);
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
- qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+ armv7m = DEVICE(&s->armv7m);
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
34
+
36
+ qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
"memory", &error_abort);
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
39
+
41
}
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
busdev = SYS_BUS_DEVICE(dev);
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
sysbus_mmio_map(busdev, 0, 0x40013800);
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
44
+
46
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
/* Attach UART (uses USART registers) and USART controllers */
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
for (i = 0; i < STM_NUM_USARTS; i++) {
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
50
}
49
+
51
busdev = SYS_BUS_DEVICE(dev);
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
sysbus_mmio_map(busdev, 0, usart_addr[i]);
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
55
}
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
56
55
index XXXXXXX..XXXXXXX 100644
57
/* Timer 2 to 5 */
56
--- a/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
57
+++ b/target/arm/mve.decode
59
}
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
60
busdev = SYS_BUS_DEVICE(dev);
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
61
sysbus_mmio_map(busdev, 0, timer_addr[i]);
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
62
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
63
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
62
+
64
}
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
65
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
66
/* ADC 1 to 3 */
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
67
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
68
return;
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
69
}
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
70
qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
71
- qdev_get_gpio_in(nvic, ADC_IRQ));
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
72
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
71
+
73
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
74
for (i = 0; i < STM_NUM_ADCS; i++) {
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
75
dev = DEVICE(&(s->adc[i]));
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
76
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
77
}
76
+
78
busdev = SYS_BUS_DEVICE(dev);
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
79
sysbus_mmio_map(busdev, 0, spi_addr[i]);
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
80
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
81
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
82
}
95
}
83
}
96
}
84
97
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
99
+{
100
+ if (likely(sh < 64)) {
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
102
+ } else {
103
+ /* Rounding the sign bit always produces 0. */
104
+ return 0;
105
+ }
106
+}
107
+
108
DO_VSHRN_ALL(vshrn, DO_SHR)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
113
+{
114
+ if (val > max) {
115
+ *satp = true;
116
+ return max;
117
+ } else if (val < min) {
118
+ *satp = true;
119
+ return min;
120
+ } else {
121
+ return val;
122
+ }
123
+}
124
+
125
+/* Saturating narrowing right shifts */
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
128
+ void *vm, uint32_t shift) \
129
+ { \
130
+ LTYPE *m = vm; \
131
+ TYPE *d = vd; \
132
+ uint16_t mask = mve_element_mask(env); \
133
+ bool qc = false; \
134
+ unsigned le; \
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
136
+ bool sat = false; \
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
85
--
224
--
86
2.7.4
225
2.20.1
87
226
88
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/21] armv7m: Move NVICState struct definition into header
[PULL 19/24] target/arm: Implement MVE VSHLC
1
Move the NVICState struct definition into a header, so we can
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
embed it into other QOM objects like SoCs.
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
3
4
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
7
Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
8
---
8
---
9
include/hw/arm/armv7m_nvic.h | 66 ++++++++++++++++++++++++++++++++++++++++++++
9
target/arm/helper-mve.h | 2 ++
10
hw/intc/armv7m_nvic.c | 49 +-------------------------------
10
target/arm/mve.decode | 2 ++
11
2 files changed, 67 insertions(+), 48 deletions(-)
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
create mode 100644 include/hw/arm/armv7m_nvic.h
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
13
14
14
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX
17
--- a/target/arm/helper-mve.h
17
--- /dev/null
18
+++ b/target/arm/helper-mve.h
18
+++ b/include/hw/arm/armv7m_nvic.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
@@ -XXX,XX +XXX,XX @@
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
+/*
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
+ * ARMv7M NVIC object
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+ *
23
+ * Copyright (c) 2017 Linaro Ltd
24
+ * Written by Peter Maydell <peter.maydell@linaro.org>
25
+ *
26
+ * This code is licensed under the GPL version 2 or later.
27
+ */
28
+
23
+
29
+#ifndef HW_ARM_ARMV7M_NVIC_H
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
30
+#define HW_ARM_ARMV7M_NVIC_H
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/mve.decode
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
31
+
33
+
32
+#include "target/arm/cpu.h"
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
33
+#include "hw/sysbus.h"
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
34
+
43
+
35
+#define TYPE_NVIC "armv7m_nvic"
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
36
+
51
+
37
+#define NVIC(obj) \
52
+ /*
38
+ OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
39
+
69
+
40
+/* Highest permitted number of exceptions (architectural limit) */
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
41
+#define NVIC_MAX_VECTORS 512
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
42
+
89
+
43
+typedef struct VecInfo {
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
44
+ /* Exception priorities can range from -3 to 255; only the unmodifiable
91
+{
45
+ * priority values for RESET, NMI and HardFault can be negative.
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
46
+ */
96
+ */
47
+ int16_t prio;
97
+ TCGv_ptr qd;
48
+ uint8_t enabled;
98
+ TCGv_i32 rdm;
49
+ uint8_t pending;
50
+ uint8_t active;
51
+ uint8_t level; /* exceptions <=15 never set level */
52
+} VecInfo;
53
+
99
+
54
+typedef struct NVICState {
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
55
+ /*< private >*/
101
+ return false;
56
+ SysBusDevice parent_obj;
102
+ }
57
+ /*< public >*/
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
58
+
110
+
59
+ ARMCPU *cpu;
111
+ qd = mve_qreg_ptr(a->qd);
60
+
112
+ rdm = load_reg(s, a->rdm);
61
+ VecInfo vectors[NVIC_MAX_VECTORS];
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
62
+ uint32_t prigroup;
114
+ store_reg(s, a->rdm, rdm);
63
+
115
+ tcg_temp_free_ptr(qd);
64
+ /* vectpending and exception_prio are both cached state that can
116
+ mve_update_eci(s);
65
+ * be recalculated from the vectors[] array and the prigroup field.
117
+ return true;
66
+ */
118
+}
67
+ unsigned int vectpending; /* highest prio pending enabled exception */
68
+ int exception_prio; /* group prio of the highest prio active exception */
69
+
70
+ struct {
71
+ uint32_t control;
72
+ uint32_t reload;
73
+ int64_t tick;
74
+ QEMUTimer *timer;
75
+ } systick;
76
+
77
+ MemoryRegion sysregmem;
78
+ MemoryRegion container;
79
+
80
+ uint32_t num_irq;
81
+ qemu_irq excpout;
82
+ qemu_irq sysresetreq;
83
+} NVICState;
84
+
85
+#endif
86
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/intc/armv7m_nvic.c
89
+++ b/hw/intc/armv7m_nvic.c
90
@@ -XXX,XX +XXX,XX @@
91
#include "hw/sysbus.h"
92
#include "qemu/timer.h"
93
#include "hw/arm/arm.h"
94
+#include "hw/arm/armv7m_nvic.h"
95
#include "target/arm/cpu.h"
96
#include "exec/address-spaces.h"
97
#include "qemu/log.h"
98
@@ -XXX,XX +XXX,XX @@
99
* "exception" more or less interchangeably.
100
*/
101
#define NVIC_FIRST_IRQ 16
102
-#define NVIC_MAX_VECTORS 512
103
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
104
105
/* Effective running priority of the CPU when no exception is active
106
@@ -XXX,XX +XXX,XX @@
107
*/
108
#define NVIC_NOEXC_PRIO 0x100
109
110
-typedef struct VecInfo {
111
- /* Exception priorities can range from -3 to 255; only the unmodifiable
112
- * priority values for RESET, NMI and HardFault can be negative.
113
- */
114
- int16_t prio;
115
- uint8_t enabled;
116
- uint8_t pending;
117
- uint8_t active;
118
- uint8_t level; /* exceptions <=15 never set level */
119
-} VecInfo;
120
-
121
-typedef struct NVICState {
122
- /*< private >*/
123
- SysBusDevice parent_obj;
124
- /*< public >*/
125
-
126
- ARMCPU *cpu;
127
-
128
- VecInfo vectors[NVIC_MAX_VECTORS];
129
- uint32_t prigroup;
130
-
131
- /* vectpending and exception_prio are both cached state that can
132
- * be recalculated from the vectors[] array and the prigroup field.
133
- */
134
- unsigned int vectpending; /* highest prio pending enabled exception */
135
- int exception_prio; /* group prio of the highest prio active exception */
136
-
137
- struct {
138
- uint32_t control;
139
- uint32_t reload;
140
- int64_t tick;
141
- QEMUTimer *timer;
142
- } systick;
143
-
144
- MemoryRegion sysregmem;
145
- MemoryRegion container;
146
-
147
- uint32_t num_irq;
148
- qemu_irq excpout;
149
- qemu_irq sysresetreq;
150
-} NVICState;
151
-
152
-#define TYPE_NVIC "armv7m_nvic"
153
-
154
-#define NVIC(obj) \
155
- OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
156
-
157
static const uint8_t nvic_id[] = {
158
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
159
};
160
--
119
--
161
2.7.4
120
2.20.1
162
121
163
122
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/21] armv7m: Make bitband device take the address space to access
[PULL 20/24] target/arm: Implement MVE VADDLV
1
Instead of the bitband device doing a cpu_physical_memory_read/write,
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
make it take a MemoryRegion which specifies where it should be
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
accessing, and use address_space_read/write to access the
3
stored in a pair of general-purpose registers.
4
corresponding AddressSpace.
5
6
Since this entails pretty much a rewrite, convert away from
7
old_mmio in the process.
8
4
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
12
---
8
---
13
include/hw/arm/armv7m.h | 2 +
9
target/arm/helper-mve.h | 3 ++
14
hw/arm/armv7m.c | 166 +++++++++++++++++++++++-------------------------
10
target/arm/mve.decode | 6 +++-
15
2 files changed, 81 insertions(+), 87 deletions(-)
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
16
14
17
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/armv7m.h
17
--- a/target/arm/helper-mve.h
20
+++ b/include/hw/arm/armv7m.h
18
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
SysBusDevice parent_obj;
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
/*< public >*/
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
22
25
+ AddressSpace *source_as;
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
26
MemoryRegion iomem;
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
27
uint32_t base;
25
+
28
+ MemoryRegion *source_memory;
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
29
} BitBandState;
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
30
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
31
#define TYPE_ARMV7M "armv7m"
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
32
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
33
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/armv7m.c
31
--- a/target/arm/mve.decode
35
+++ b/hw/arm/armv7m.c
32
+++ b/target/arm/mve.decode
36
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
37
/* Bitbanded IO. Each word corresponds to a single bit. */
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
38
35
39
/* Get the byte address of the real memory for a bitband access. */
36
# Vector add across vector
40
-static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
41
+static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
38
+{
42
{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
43
- uint32_t res;
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
44
-
41
+ rdahi=%rdahi rdalo=%rdalo
45
- res = *(uint32_t *)opaque;
42
+}
46
- res |= (addr & 0x1ffffff) >> 5;
43
47
- return res;
44
# Predicate operations
48
-
45
%mask_22_13 22:1 13:3
49
-}
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
50
-
47
index XXXXXXX..XXXXXXX 100644
51
-static uint32_t bitband_readb(void *opaque, hwaddr offset)
48
--- a/target/arm/mve_helper.c
52
-{
49
+++ b/target/arm/mve_helper.c
53
- uint8_t v;
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
54
- cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
51
DO_VADDV(vaddvuh, 2, uint16_t)
55
- return (v & (1 << ((offset >> 2) & 7))) != 0;
52
DO_VADDV(vaddvuw, 4, uint32_t)
56
-}
53
57
-
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
58
-static void bitband_writeb(void *opaque, hwaddr offset,
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
59
- uint32_t value)
56
+ uint64_t ra) \
60
-{
57
+ { \
61
- uint32_t addr;
58
+ uint16_t mask = mve_element_mask(env); \
62
- uint8_t mask;
59
+ unsigned e; \
63
- uint8_t v;
60
+ TYPE *m = vm; \
64
- addr = bitband_addr(opaque, offset);
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
65
- mask = (1 << ((offset >> 2) & 7));
62
+ if (mask & 1) { \
66
- cpu_physical_memory_read(addr, &v, 1);
63
+ ra += (LTYPE)m[H4(e)]; \
67
- if (value & 1)
64
+ } \
68
- v |= mask;
65
+ } \
69
- else
66
+ mve_advance_vpt(env); \
70
- v &= ~mask;
67
+ return ra; \
71
- cpu_physical_memory_write(addr, &v, 1);
68
+ } \
72
-}
69
+
73
-
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
74
-static uint32_t bitband_readw(void *opaque, hwaddr offset)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
75
-{
72
+
76
- uint32_t addr;
73
/* Shifts by immediate */
77
- uint16_t mask;
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
78
- uint16_t v;
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
79
- addr = bitband_addr(opaque, offset) & ~1;
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
80
- mask = (1 << ((offset >> 2) & 15));
77
index XXXXXXX..XXXXXXX 100644
81
- mask = tswap16(mask);
78
--- a/target/arm/translate-mve.c
82
- cpu_physical_memory_read(addr, &v, 2);
79
+++ b/target/arm/translate-mve.c
83
- return (v & mask) != 0;
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
84
-}
81
return true;
85
-
86
-static void bitband_writew(void *opaque, hwaddr offset,
87
- uint32_t value)
88
-{
89
- uint32_t addr;
90
- uint16_t mask;
91
- uint16_t v;
92
- addr = bitband_addr(opaque, offset) & ~1;
93
- mask = (1 << ((offset >> 2) & 15));
94
- mask = tswap16(mask);
95
- cpu_physical_memory_read(addr, &v, 2);
96
- if (value & 1)
97
- v |= mask;
98
- else
99
- v &= ~mask;
100
- cpu_physical_memory_write(addr, &v, 2);
101
+ return s->base | (offset & 0x1ffffff) >> 5;
102
}
82
}
103
83
104
-static uint32_t bitband_readl(void *opaque, hwaddr offset)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
105
+static MemTxResult bitband_read(void *opaque, hwaddr offset,
85
+{
106
+ uint64_t *data, unsigned size, MemTxAttrs attrs)
86
+ /*
107
{
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
108
- uint32_t addr;
88
+ * elements of the vector into a 64-bit result stored in
109
- uint32_t mask;
89
+ * a pair of general-purpose registers.
110
- uint32_t v;
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
111
- addr = bitband_addr(opaque, offset) & ~3;
91
+ */
112
- mask = (1 << ((offset >> 2) & 31));
92
+ TCGv_ptr qm;
113
- mask = tswap32(mask);
93
+ TCGv_i64 rda;
114
- cpu_physical_memory_read(addr, &v, 4);
94
+ TCGv_i32 rdalo, rdahi;
115
- return (v & mask) != 0;
116
+ BitBandState *s = opaque;
117
+ uint8_t buf[4];
118
+ MemTxResult res;
119
+ int bitpos, bit;
120
+ hwaddr addr;
121
+
95
+
122
+ assert(size <= 4);
96
+ if (!dc_isar_feature(aa32_mve, s)) {
123
+
97
+ return false;
124
+ /* Find address in underlying memory and round down to multiple of size */
125
+ addr = bitband_addr(s, offset) & (-size);
126
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
127
+ if (res) {
128
+ return res;
129
+ }
98
+ }
130
+ /* Bit position in the N bytes read... */
99
+ /*
131
+ bitpos = (offset >> 2) & ((size * 8) - 1);
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
132
+ /* ...converted to byte in buffer and bit in byte */
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
133
+ bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
102
+ */
134
+ *data = bit;
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
135
+ return MEMTX_OK;
104
+ return false;
136
}
137
138
-static void bitband_writel(void *opaque, hwaddr offset,
139
- uint32_t value)
140
+static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
141
+ unsigned size, MemTxAttrs attrs)
142
{
143
- uint32_t addr;
144
- uint32_t mask;
145
- uint32_t v;
146
- addr = bitband_addr(opaque, offset) & ~3;
147
- mask = (1 << ((offset >> 2) & 31));
148
- mask = tswap32(mask);
149
- cpu_physical_memory_read(addr, &v, 4);
150
- if (value & 1)
151
- v |= mask;
152
- else
153
- v &= ~mask;
154
- cpu_physical_memory_write(addr, &v, 4);
155
+ BitBandState *s = opaque;
156
+ uint8_t buf[4];
157
+ MemTxResult res;
158
+ int bitpos, bit;
159
+ hwaddr addr;
160
+
161
+ assert(size <= 4);
162
+
163
+ /* Find address in underlying memory and round down to multiple of size */
164
+ addr = bitband_addr(s, offset) & (-size);
165
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
166
+ if (res) {
167
+ return res;
168
+ }
105
+ }
169
+ /* Bit position in the N bytes read... */
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
170
+ bitpos = (offset >> 2) & ((size * 8) - 1);
107
+ return true;
171
+ /* ...converted to byte in buffer and bit in byte */
172
+ bit = 1 << (bitpos & 7);
173
+ if (value & 1) {
174
+ buf[bitpos >> 3] |= bit;
175
+ } else {
176
+ buf[bitpos >> 3] &= ~bit;
177
+ }
178
+ return address_space_write(s->source_as, addr, attrs, buf, size);
179
}
180
181
static const MemoryRegionOps bitband_ops = {
182
- .old_mmio = {
183
- .read = { bitband_readb, bitband_readw, bitband_readl, },
184
- .write = { bitband_writeb, bitband_writew, bitband_writel, },
185
- },
186
+ .read_with_attrs = bitband_read,
187
+ .write_with_attrs = bitband_write,
188
.endianness = DEVICE_NATIVE_ENDIAN,
189
+ .impl.min_access_size = 1,
190
+ .impl.max_access_size = 4,
191
+ .valid.min_access_size = 1,
192
+ .valid.max_access_size = 4,
193
};
194
195
static void bitband_init(Object *obj)
196
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
197
BitBandState *s = BITBAND(obj);
198
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
199
200
- memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
201
+ object_property_add_link(obj, "source-memory",
202
+ TYPE_MEMORY_REGION,
203
+ (Object **)&s->source_memory,
204
+ qdev_prop_allow_set_link_before_realize,
205
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
206
+ &error_abort);
207
+ memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
208
"bitband", 0x02000000);
209
sysbus_init_mmio(dev, &s->iomem);
210
}
211
212
+static void bitband_realize(DeviceState *dev, Error **errp)
213
+{
214
+ BitBandState *s = BITBAND(dev);
215
+
216
+ if (!s->source_memory) {
217
+ error_setg(errp, "source-memory property not set");
218
+ return;
219
+ }
108
+ }
220
+
109
+
221
+ s->source_as = address_space_init_shareable(s->source_memory,
110
+ /*
222
+ "bitband-source");
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
223
+}
145
+}
224
+
146
+
225
/* Board init. */
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
226
227
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
228
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
229
error_propagate(errp, err);
230
return;
231
}
232
+ object_property_set_link(obj, OBJECT(s->board_memory),
233
+ "source-memory", &error_abort);
234
object_property_set_bool(obj, true, "realized", &err);
235
if (err != NULL) {
236
error_propagate(errp, err);
237
@@ -XXX,XX +XXX,XX @@ static void bitband_class_init(ObjectClass *klass, void *data)
238
{
148
{
239
DeviceClass *dc = DEVICE_CLASS(klass);
149
TCGv_ptr qd;
240
241
+ dc->realize = bitband_realize;
242
dc->props = bitband_properties;
243
}
244
245
--
150
--
246
2.7.4
151
2.20.1
247
152
248
153
diff view generated by jsdifflib
New patch
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
1
The MVE extension to v8.1M includes some new shift instructions which
2
sit entirely within the non-coprocessor part of the encoding space
3
and which operate only on general-purpose registers. They take up
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
with Rm == 13 or 15.
6
7
Implement the long shifts by immediate, which perform shifts on a
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
an immediate shift count between 1 and 32.
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
27
---
28
target/arm/helper-mve.h | 3 ++
29
target/arm/translate.h | 1 +
30
target/arm/t32.decode | 28 +++++++++++++
31
target/arm/mve_helper.c | 10 +++++
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
33
5 files changed, 132 insertions(+)
34
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
38
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
83
{
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
133
return true;
134
}
135
136
+/*
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
229
--
230
2.20.1
231
232
diff view generated by jsdifflib
New patch
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
1
Implement the MVE long shifts by register, which perform shifts on a
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
the shift count in another general-purpose register, which might be
4
either positive or negative.
5
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
15
---
16
target/arm/helper-mve.h | 6 +++
17
target/arm/translate.h | 1 +
18
target/arm/t32.decode | 16 +++++--
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
21
5 files changed, 182 insertions(+), 3 deletions(-)
22
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-mve.h
26
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
30
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
55
@@ -XXX,XX +XXX,XX @@
56
&mcrr !extern cp opc1 crm rt rt2
57
58
&mve_shl_ri rdalo rdahi shim
59
+&mve_shl_rr rdalo rdahi rm
60
61
# rdahi: bits [3:1] from insn, bit 0 is 1
62
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
291
--
292
2.20.1
293
294
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/21] stm32f205: Create armv7m object without using armv7m_init()
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
Switch the stm32f205 SoC to create the armv7m object directly
1
Implement the MVE shifts by immediate, which perform shifts
2
rather than via the armv7m_init() wrapper. This fits better
2
on a single general-purpose register.
3
with the SoC model's very QOMified design.
3
4
4
These patterns overlap with the long-shift-by-immediates,
5
In particular this means we can push loading the guest image
5
so we have to rearrange the grouping a little here.
6
out to the top level board code where it belongs, rather
7
than the SoC object having a QOM property for the filename
8
to load.
9
6
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
15
---
10
---
16
include/hw/arm/stm32f205_soc.h | 4 +++-
11
target/arm/helper-mve.h | 3 ++
17
hw/arm/netduino2.c | 7 ++++---
12
target/arm/translate.h | 1 +
18
hw/arm/stm32f205_soc.c | 16 +++++++++++++---
13
target/arm/t32.decode | 31 ++++++++++++++-----
19
3 files changed, 20 insertions(+), 7 deletions(-)
14
target/arm/mve_helper.c | 10 ++++++
20
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
21
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
16
5 files changed, 104 insertions(+), 9 deletions(-)
22
index XXXXXXX..XXXXXXX 100644
17
23
--- a/include/hw/arm/stm32f205_soc.h
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
+++ b/include/hw/arm/stm32f205_soc.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
21
+++ b/target/arm/helper-mve.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
25
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@
26
#include "hw/adc/stm32f2xx_adc.h"
46
27
#include "hw/or-irq.h"
47
&mve_shl_ri rdalo rdahi shim
28
#include "hw/ssi/stm32f2xx_spi.h"
48
&mve_shl_rr rdalo rdahi rm
29
+#include "hw/arm/armv7m.h"
49
+&mve_sh_ri rda shim
30
50
31
#define TYPE_STM32F205_SOC "stm32f205-soc"
51
# rdahi: bits [3:1] from insn, bit 0 is 1
32
#define STM32F205_SOC(obj) \
52
# rdalo: bits [3:1] from insn, bit 0 is 0
33
@@ -XXX,XX +XXX,XX @@ typedef struct STM32F205State {
34
SysBusDevice parent_obj;
35
/*< public >*/
36
37
- char *kernel_filename;
38
char *cpu_model;
39
40
+ ARMv7MState armv7m;
41
+
42
STM32F2XXSyscfgState syscfg;
43
STM32F2XXUsartState usart[STM_NUM_USARTS];
44
STM32F2XXTimerState timer[STM_NUM_TIMERS];
45
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/netduino2.c
48
+++ b/hw/arm/netduino2.c
49
@@ -XXX,XX +XXX,XX @@
53
@@ -XXX,XX +XXX,XX @@
50
#include "hw/boards.h"
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
51
#include "qemu/error-report.h"
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
52
#include "hw/arm/stm32f205_soc.h"
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
53
+#include "hw/arm/arm.h"
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
54
58
+ &mve_sh_ri shim=%imm5_12_6
55
static void netduino2_init(MachineState *machine)
59
56
{
60
{
57
DeviceState *dev;
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
58
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
59
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
60
- if (machine->kernel_filename) {
64
# handling them as r13 and r15 accesses with the same semantics as A32).
61
- qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
65
[
62
- }
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
63
qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
64
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
65
+
69
+ {
66
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
67
+ FLASH_SIZE);
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
68
}
105
}
69
106
+
70
static void netduino2_machine_init(MachineClass *mc)
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
71
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
108
+{
72
index XXXXXXX..XXXXXXX 100644
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
73
--- a/hw/arm/stm32f205_soc.c
110
+}
74
+++ b/hw/arm/stm32f205_soc.c
111
+
75
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
76
STM32F205State *s = STM32F205_SOC(obj);
113
+{
77
int i;
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
78
115
+}
79
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
80
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
117
index XXXXXXX..XXXXXXX 100644
81
+
118
--- a/target/arm/translate.c
82
object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
119
+++ b/target/arm/translate.c
83
qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
84
121
85
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
86
vmstate_register_ram_global(sram);
123
{
87
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
124
- TCGv_i32 t = tcg_temp_new_i32();
88
125
+ TCGv_i32 t;
89
- nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
126
90
- s->kernel_filename, s->cpu_model);
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
91
+ nvic = DEVICE(&s->armv7m);
128
+ if (sh == 32) {
92
+ qdev_prop_set_uint32(nvic, "num-irq", 96);
129
+ tcg_gen_movi_i32(d, 0);
93
+ qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
94
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
95
+ "memory", &error_abort);
96
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
97
+ if (err != NULL) {
98
+ error_propagate(errp, err);
99
+ return;
130
+ return;
100
+ }
131
+ }
101
132
+ t = tcg_temp_new_i32();
102
/* System configuration controller */
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
103
dev = DEVICE(&s->syscfg);
134
tcg_gen_sari_i32(d, a, sh);
104
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
105
}
154
}
106
155
107
static Property stm32f205_soc_properties[] = {
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
108
- DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
157
+{
109
DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
110
DEFINE_PROP_END_OF_LIST(),
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
111
};
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
112
--
211
--
113
2.7.4
212
2.20.1
114
213
115
214
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/21] armv7m: Split systick out from NVIC
[PULL 24/24] target/arm: Implement MVE shifts by register
1
The SysTick timer isn't really part of the NVIC proper;
1
Implement the MVE shifts by register, which perform
2
we just modelled it that way back when we couldn't
2
shifts on a single general-purpose register.
3
easily have devices that only occupied a small chunk
4
of a memory region. Split it out into its own device.
5
3
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
9
---
7
---
10
hw/timer/Makefile.objs | 1 +
8
target/arm/helper-mve.h | 2 ++
11
include/hw/arm/armv7m_nvic.h | 10 +-
9
target/arm/translate.h | 1 +
12
include/hw/timer/armv7m_systick.h | 34 ++++++
10
target/arm/t32.decode | 18 ++++++++++++++----
13
hw/intc/armv7m_nvic.c | 160 ++++++-------------------
11
target/arm/mve_helper.c | 10 ++++++++++
14
hw/timer/armv7m_systick.c | 240 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
15
hw/timer/trace-events | 6 +
13
5 files changed, 57 insertions(+), 4 deletions(-)
16
6 files changed, 318 insertions(+), 133 deletions(-)
17
create mode 100644 include/hw/timer/armv7m_systick.h
18
create mode 100644 hw/timer/armv7m_systick.c
19
14
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
17
--- a/target/arm/helper-mve.h
23
+++ b/hw/timer/Makefile.objs
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
20
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/translate.h
28
+++ b/target/arm/translate.h
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
24
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
25
common-obj-$(CONFIG_ARM_TIMER) += arm_timer.o
42
&mve_shl_ri rdalo rdahi shim
26
common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
43
&mve_shl_rr rdalo rdahi rm
27
+common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o
44
&mve_sh_ri rda shim
28
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
45
+&mve_sh_rr rda rm
29
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
46
30
common-obj-$(CONFIG_DS1338) += ds1338.o
47
# rdahi: bits [3:1] from insn, bit 0 is 1
31
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
48
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
55
{
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
59
}
60
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
65
+ {
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
69
+ }
70
+
71
+ {
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
76
+
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
32
index XXXXXXX..XXXXXXX 100644
81
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armv7m_nvic.h
82
--- a/target/arm/mve_helper.c
34
+++ b/include/hw/arm/armv7m_nvic.h
83
+++ b/target/arm/mve_helper.c
35
@@ -XXX,XX +XXX,XX @@
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
36
85
{
37
#include "target/arm/cpu.h"
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
38
#include "hw/sysbus.h"
87
}
39
+#include "hw/timer/armv7m_systick.h"
40
41
#define TYPE_NVIC "armv7m_nvic"
42
43
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
44
unsigned int vectpending; /* highest prio pending enabled exception */
45
int exception_prio; /* group prio of the highest prio active exception */
46
47
- struct {
48
- uint32_t control;
49
- uint32_t reload;
50
- int64_t tick;
51
- QEMUTimer *timer;
52
- } systick;
53
-
54
MemoryRegion sysregmem;
55
MemoryRegion container;
56
57
uint32_t num_irq;
58
qemu_irq excpout;
59
qemu_irq sysresetreq;
60
+
88
+
61
+ SysTickState systick;
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
62
} NVICState;
63
64
#endif
65
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
66
new file mode 100644
67
index XXXXXXX..XXXXXXX
68
--- /dev/null
69
+++ b/include/hw/timer/armv7m_systick.h
70
@@ -XXX,XX +XXX,XX @@
71
+/*
72
+ * ARMv7M SysTick timer
73
+ *
74
+ * Copyright (c) 2006-2007 CodeSourcery.
75
+ * Written by Paul Brook
76
+ * Copyright (c) 2017 Linaro Ltd
77
+ * Written by Peter Maydell
78
+ *
79
+ * This code is licensed under the GPL (version 2 or later).
80
+ */
81
+
82
+#ifndef HW_TIMER_ARMV7M_SYSTICK_H
83
+#define HW_TIMER_ARMV7M_SYSTICK_H
84
+
85
+#include "hw/sysbus.h"
86
+
87
+#define TYPE_SYSTICK "armv7m_systick"
88
+
89
+#define SYSTICK(obj) OBJECT_CHECK(SysTickState, (obj), TYPE_SYSTICK)
90
+
91
+typedef struct SysTickState {
92
+ /*< private >*/
93
+ SysBusDevice parent_obj;
94
+ /*< public >*/
95
+
96
+ uint32_t control;
97
+ uint32_t reload;
98
+ int64_t tick;
99
+ QEMUTimer *timer;
100
+ MemoryRegion iomem;
101
+ qemu_irq irq;
102
+} SysTickState;
103
+
104
+#endif
105
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/intc/armv7m_nvic.c
108
+++ b/hw/intc/armv7m_nvic.c
109
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
110
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
111
};
112
113
-/* qemu timers run at 1GHz. We want something closer to 1MHz. */
114
-#define SYSTICK_SCALE 1000ULL
115
-
116
-#define SYSTICK_ENABLE (1 << 0)
117
-#define SYSTICK_TICKINT (1 << 1)
118
-#define SYSTICK_CLKSOURCE (1 << 2)
119
-#define SYSTICK_COUNTFLAG (1 << 16)
120
-
121
-int system_clock_scale;
122
-
123
-/* Conversion factor from qemu timer to SysTick frequencies. */
124
-static inline int64_t systick_scale(NVICState *s)
125
-{
126
- if (s->systick.control & SYSTICK_CLKSOURCE)
127
- return system_clock_scale;
128
- else
129
- return 1000;
130
-}
131
-
132
-static void systick_reload(NVICState *s, int reset)
133
-{
134
- /* The Cortex-M3 Devices Generic User Guide says that "When the
135
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
136
- * SYST RVR register and then counts down". So, we need to check the
137
- * ENABLE bit before reloading the value.
138
- */
139
- if ((s->systick.control & SYSTICK_ENABLE) == 0) {
140
- return;
141
- }
142
-
143
- if (reset)
144
- s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
145
- s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
146
- timer_mod(s->systick.timer, s->systick.tick);
147
-}
148
-
149
-static void systick_timer_tick(void * opaque)
150
-{
151
- NVICState *s = (NVICState *)opaque;
152
- s->systick.control |= SYSTICK_COUNTFLAG;
153
- if (s->systick.control & SYSTICK_TICKINT) {
154
- /* Trigger the interrupt. */
155
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
156
- }
157
- if (s->systick.reload == 0) {
158
- s->systick.control &= ~SYSTICK_ENABLE;
159
- } else {
160
- systick_reload(s, 0);
161
- }
162
-}
163
-
164
-static void systick_reset(NVICState *s)
165
-{
166
- s->systick.control = 0;
167
- s->systick.reload = 0;
168
- s->systick.tick = 0;
169
- timer_del(s->systick.timer);
170
-}
171
-
172
static int nvic_pending_prio(NVICState *s)
173
{
174
/* return the priority of the current pending interrupt,
175
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
176
switch (offset) {
177
case 4: /* Interrupt Control Type. */
178
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
179
- case 0x10: /* SysTick Control and Status. */
180
- val = s->systick.control;
181
- s->systick.control &= ~SYSTICK_COUNTFLAG;
182
- return val;
183
- case 0x14: /* SysTick Reload Value. */
184
- return s->systick.reload;
185
- case 0x18: /* SysTick Current Value. */
186
- {
187
- int64_t t;
188
- if ((s->systick.control & SYSTICK_ENABLE) == 0)
189
- return 0;
190
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
191
- if (t >= s->systick.tick)
192
- return 0;
193
- val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
194
- /* The interrupt in triggered when the timer reaches zero.
195
- However the counter is not reloaded until the next clock
196
- tick. This is a hack to return zero during the first tick. */
197
- if (val > s->systick.reload)
198
- val = 0;
199
- return val;
200
- }
201
- case 0x1c: /* SysTick Calibration Value. */
202
- return 10000;
203
case 0xd00: /* CPUID Base. */
204
return cpu->midr;
205
case 0xd04: /* Interrupt Control State. */
206
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
207
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
208
{
209
ARMCPU *cpu = s->cpu;
210
- uint32_t oldval;
211
+
212
switch (offset) {
213
- case 0x10: /* SysTick Control and Status. */
214
- oldval = s->systick.control;
215
- s->systick.control &= 0xfffffff8;
216
- s->systick.control |= value & 7;
217
- if ((oldval ^ value) & SYSTICK_ENABLE) {
218
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
219
- if (value & SYSTICK_ENABLE) {
220
- if (s->systick.tick) {
221
- s->systick.tick += now;
222
- timer_mod(s->systick.timer, s->systick.tick);
223
- } else {
224
- systick_reload(s, 1);
225
- }
226
- } else {
227
- timer_del(s->systick.timer);
228
- s->systick.tick -= now;
229
- if (s->systick.tick < 0)
230
- s->systick.tick = 0;
231
- }
232
- } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
233
- /* This is a hack. Force the timer to be reloaded
234
- when the reference clock is changed. */
235
- systick_reload(s, 1);
236
- }
237
- break;
238
- case 0x14: /* SysTick Reload Value. */
239
- s->systick.reload = value;
240
- break;
241
- case 0x18: /* SysTick Current Value. Writes reload the timer. */
242
- systick_reload(s, 1);
243
- s->systick.control &= ~SYSTICK_COUNTFLAG;
244
- break;
245
case 0xd04: /* Interrupt Control State. */
246
if (value & (1 << 31)) {
247
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
248
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
249
250
static const VMStateDescription vmstate_nvic = {
251
.name = "armv7m_nvic",
252
- .version_id = 3,
253
- .minimum_version_id = 3,
254
+ .version_id = 4,
255
+ .minimum_version_id = 4,
256
.post_load = &nvic_post_load,
257
.fields = (VMStateField[]) {
258
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
259
vmstate_VecInfo, VecInfo),
260
- VMSTATE_UINT32(systick.control, NVICState),
261
- VMSTATE_UINT32(systick.reload, NVICState),
262
- VMSTATE_INT64(systick.tick, NVICState),
263
- VMSTATE_TIMER_PTR(systick.timer, NVICState),
264
VMSTATE_UINT32(prigroup, NVICState),
265
VMSTATE_END_OF_LIST()
266
}
267
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
268
269
s->exception_prio = NVIC_NOEXC_PRIO;
270
s->vectpending = 0;
271
+}
272
273
- systick_reset(s);
274
+static void nvic_systick_trigger(void *opaque, int n, int level)
275
+{
90
+{
276
+ NVICState *s = opaque;
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
277
+
278
+ if (level) {
279
+ /* SysTick just asked us to pend its exception.
280
+ * (This is different from an external interrupt line's
281
+ * behaviour.)
282
+ */
283
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
284
+ }
285
}
286
287
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
288
{
289
NVICState *s = NVIC(dev);
290
+ SysBusDevice *systick_sbd;
291
+ Error *err = NULL;
292
293
s->cpu = ARM_CPU(qemu_get_cpu(0));
294
assert(s->cpu);
295
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
296
/* include space for internal exception vectors */
297
s->num_irq += NVIC_FIRST_IRQ;
298
299
+ object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
300
+ if (err != NULL) {
301
+ error_propagate(errp, err);
302
+ return;
303
+ }
304
+ systick_sbd = SYS_BUS_DEVICE(&s->systick);
305
+ sysbus_connect_irq(systick_sbd, 0,
306
+ qdev_get_gpio_in_named(dev, "systick-trigger", 0));
307
+
308
/* The NVIC and System Control Space (SCS) starts at 0xe000e000
309
* and looks like this:
310
* 0x004 - ICTR
311
- * 0x010 - 0x1c - systick
312
+ * 0x010 - 0xff - systick
313
* 0x100..0x7ec - NVIC
314
* 0x7f0..0xcff - Reserved
315
* 0xd00..0xd3c - SCS registers
316
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
317
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
318
"nvic_sysregs", 0x1000);
319
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
320
+ memory_region_add_subregion_overlap(&s->container, 0x10,
321
+ sysbus_mmio_get_region(systick_sbd, 0),
322
+ 1);
323
324
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
325
-
326
- s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
327
}
328
329
static void armv7m_nvic_instance_init(Object *obj)
330
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_instance_init(Object *obj)
331
NVICState *nvic = NVIC(obj);
332
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
333
334
+ object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
335
+ qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
336
+
337
sysbus_init_irq(sbd, &nvic->excpout);
338
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
339
+ qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
340
}
341
342
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
343
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
344
new file mode 100644
345
index XXXXXXX..XXXXXXX
346
--- /dev/null
347
+++ b/hw/timer/armv7m_systick.c
348
@@ -XXX,XX +XXX,XX @@
349
+/*
350
+ * ARMv7M SysTick timer
351
+ *
352
+ * Copyright (c) 2006-2007 CodeSourcery.
353
+ * Written by Paul Brook
354
+ * Copyright (c) 2017 Linaro Ltd
355
+ * Written by Peter Maydell
356
+ *
357
+ * This code is licensed under the GPL (version 2 or later).
358
+ */
359
+
360
+#include "qemu/osdep.h"
361
+#include "hw/timer/armv7m_systick.h"
362
+#include "qemu-common.h"
363
+#include "hw/sysbus.h"
364
+#include "qemu/timer.h"
365
+#include "qemu/log.h"
366
+#include "trace.h"
367
+
368
+/* qemu timers run at 1GHz. We want something closer to 1MHz. */
369
+#define SYSTICK_SCALE 1000ULL
370
+
371
+#define SYSTICK_ENABLE (1 << 0)
372
+#define SYSTICK_TICKINT (1 << 1)
373
+#define SYSTICK_CLKSOURCE (1 << 2)
374
+#define SYSTICK_COUNTFLAG (1 << 16)
375
+
376
+int system_clock_scale;
377
+
378
+/* Conversion factor from qemu timer to SysTick frequencies. */
379
+static inline int64_t systick_scale(SysTickState *s)
380
+{
381
+ if (s->control & SYSTICK_CLKSOURCE) {
382
+ return system_clock_scale;
383
+ } else {
384
+ return 1000;
385
+ }
386
+}
92
+}
387
+
93
+
388
+static void systick_reload(SysTickState *s, int reset)
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
389
+{
95
+{
390
+ /* The Cortex-M3 Devices Generic User Guide says that "When the
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
391
+ * ENABLE bit is set to 1, the counter loads the RELOAD value from the
97
+}
392
+ * SYST RVR register and then counts down". So, we need to check the
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
393
+ * ENABLE bit before reloading the value.
99
index XXXXXXX..XXXXXXX 100644
394
+ */
100
--- a/target/arm/translate.c
395
+ trace_systick_reload();
101
+++ b/target/arm/translate.c
396
+
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
397
+ if ((s->control & SYSTICK_ENABLE) == 0) {
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
398
+ return;
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
399
+ }
119
+ }
400
+
120
+
401
+ if (reset) {
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
402
+ s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
403
+ }
123
+ return true;
404
+ s->tick += (s->reload + 1) * systick_scale(s);
405
+ timer_mod(s->timer, s->tick);
406
+}
124
+}
407
+
125
+
408
+static void systick_timer_tick(void *opaque)
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
409
+{
127
+{
410
+ SysTickState *s = (SysTickState *)opaque;
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
411
+
412
+ trace_systick_timer_tick();
413
+
414
+ s->control |= SYSTICK_COUNTFLAG;
415
+ if (s->control & SYSTICK_TICKINT) {
416
+ /* Tell the NVIC to pend the SysTick exception */
417
+ qemu_irq_pulse(s->irq);
418
+ }
419
+ if (s->reload == 0) {
420
+ s->control &= ~SYSTICK_ENABLE;
421
+ } else {
422
+ systick_reload(s, 0);
423
+ }
424
+}
129
+}
425
+
130
+
426
+static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
427
+{
132
+{
428
+ SysTickState *s = opaque;
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
429
+ uint32_t val;
430
+
431
+ switch (addr) {
432
+ case 0x0: /* SysTick Control and Status. */
433
+ val = s->control;
434
+ s->control &= ~SYSTICK_COUNTFLAG;
435
+ break;
436
+ case 0x4: /* SysTick Reload Value. */
437
+ val = s->reload;
438
+ break;
439
+ case 0x8: /* SysTick Current Value. */
440
+ {
441
+ int64_t t;
442
+
443
+ if ((s->control & SYSTICK_ENABLE) == 0) {
444
+ val = 0;
445
+ break;
446
+ }
447
+ t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
448
+ if (t >= s->tick) {
449
+ val = 0;
450
+ break;
451
+ }
452
+ val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
453
+ /* The interrupt in triggered when the timer reaches zero.
454
+ However the counter is not reloaded until the next clock
455
+ tick. This is a hack to return zero during the first tick. */
456
+ if (val > s->reload) {
457
+ val = 0;
458
+ }
459
+ break;
460
+ }
461
+ case 0xc: /* SysTick Calibration Value. */
462
+ val = 10000;
463
+ break;
464
+ default:
465
+ val = 0;
466
+ qemu_log_mask(LOG_GUEST_ERROR,
467
+ "SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
468
+ break;
469
+ }
470
+
471
+ trace_systick_read(addr, val, size);
472
+ return val;
473
+}
134
+}
474
+
135
+
475
+static void systick_write(void *opaque, hwaddr addr,
136
/*
476
+ uint64_t value, unsigned size)
137
* Multiply and multiply accumulate
477
+{
138
*/
478
+ SysTickState *s = opaque;
479
+
480
+ trace_systick_write(addr, value, size);
481
+
482
+ switch (addr) {
483
+ case 0x0: /* SysTick Control and Status. */
484
+ {
485
+ uint32_t oldval = s->control;
486
+
487
+ s->control &= 0xfffffff8;
488
+ s->control |= value & 7;
489
+ if ((oldval ^ value) & SYSTICK_ENABLE) {
490
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
491
+ if (value & SYSTICK_ENABLE) {
492
+ if (s->tick) {
493
+ s->tick += now;
494
+ timer_mod(s->timer, s->tick);
495
+ } else {
496
+ systick_reload(s, 1);
497
+ }
498
+ } else {
499
+ timer_del(s->timer);
500
+ s->tick -= now;
501
+ if (s->tick < 0) {
502
+ s->tick = 0;
503
+ }
504
+ }
505
+ } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
506
+ /* This is a hack. Force the timer to be reloaded
507
+ when the reference clock is changed. */
508
+ systick_reload(s, 1);
509
+ }
510
+ break;
511
+ }
512
+ case 0x4: /* SysTick Reload Value. */
513
+ s->reload = value;
514
+ break;
515
+ case 0x8: /* SysTick Current Value. Writes reload the timer. */
516
+ systick_reload(s, 1);
517
+ s->control &= ~SYSTICK_COUNTFLAG;
518
+ break;
519
+ default:
520
+ qemu_log_mask(LOG_GUEST_ERROR,
521
+ "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
522
+ }
523
+}
524
+
525
+static const MemoryRegionOps systick_ops = {
526
+ .read = systick_read,
527
+ .write = systick_write,
528
+ .endianness = DEVICE_NATIVE_ENDIAN,
529
+ .valid.min_access_size = 4,
530
+ .valid.max_access_size = 4,
531
+};
532
+
533
+static void systick_reset(DeviceState *dev)
534
+{
535
+ SysTickState *s = SYSTICK(dev);
536
+
537
+ s->control = 0;
538
+ s->reload = 0;
539
+ s->tick = 0;
540
+ timer_del(s->timer);
541
+}
542
+
543
+static void systick_instance_init(Object *obj)
544
+{
545
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
546
+ SysTickState *s = SYSTICK(obj);
547
+
548
+ memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
549
+ sysbus_init_mmio(sbd, &s->iomem);
550
+ sysbus_init_irq(sbd, &s->irq);
551
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
552
+}
553
+
554
+static const VMStateDescription vmstate_systick = {
555
+ .name = "armv7m_systick",
556
+ .version_id = 1,
557
+ .minimum_version_id = 1,
558
+ .fields = (VMStateField[]) {
559
+ VMSTATE_UINT32(control, SysTickState),
560
+ VMSTATE_UINT32(reload, SysTickState),
561
+ VMSTATE_INT64(tick, SysTickState),
562
+ VMSTATE_TIMER_PTR(timer, SysTickState),
563
+ VMSTATE_END_OF_LIST()
564
+ }
565
+};
566
+
567
+static void systick_class_init(ObjectClass *klass, void *data)
568
+{
569
+ DeviceClass *dc = DEVICE_CLASS(klass);
570
+
571
+ dc->vmsd = &vmstate_systick;
572
+ dc->reset = systick_reset;
573
+}
574
+
575
+static const TypeInfo armv7m_systick_info = {
576
+ .name = TYPE_SYSTICK,
577
+ .parent = TYPE_SYS_BUS_DEVICE,
578
+ .instance_init = systick_instance_init,
579
+ .instance_size = sizeof(SysTickState),
580
+ .class_init = systick_class_init,
581
+};
582
+
583
+static void armv7m_systick_register_types(void)
584
+{
585
+ type_register_static(&armv7m_systick_info);
586
+}
587
+
588
+type_init(armv7m_systick_register_types)
589
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
590
index XXXXXXX..XXXXXXX 100644
591
--- a/hw/timer/trace-events
592
+++ b/hw/timer/trace-events
593
@@ -XXX,XX +XXX,XX @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
594
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
595
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
596
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
597
+
598
+# hw/timer/armv7m_systick.c
599
+systick_reload(void) "systick reload"
600
+systick_timer_tick(void) "systick reload"
601
+systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
602
+systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
603
--
139
--
604
2.7.4
140
2.20.1
605
141
606
142
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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