1
Second lot of ARM changes to sneak in before freeze:
1
Arm queue; not huge but I figured I might as well send it out since
2
* fixed version of the raspi2 sd controller patches
2
I've been doing code review today and there's no queue of unprocessed
3
* GICv3 save/restore
3
pullreqs...
4
* v7M QOMify
5
6
I've also included the Linux header update patches stolen
7
from Paolo's pullreq since it hasn't quite hit master yet.
8
4
9
thanks
5
thanks
10
-- PMM
6
-- PMM
11
7
12
The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:
8
The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
13
9
14
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging (2017-02-28 14:50:17 +0000)
10
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
15
11
16
are available in the git repository at:
12
are available in the Git repository at:
17
13
18
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228-1
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
19
15
20
for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:
16
for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
21
17
22
bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +0000)
18
ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
23
19
24
----------------------------------------------------------------
20
----------------------------------------------------------------
25
target-arm queue:
21
target-arm queue:
26
* raspi2: add gpio controller and sdhost controller, with
22
* arm: Support emulation of ARMv8.4-TTST extension
27
the wiring so the guest can switch which controller the
23
* arm: Update cpu.h ID register field definitions
28
SD card is attached to
24
* arm: Fix breakage of XScale instruction emulation
29
(this is sufficient to get raspbian kernels to boot)
25
* hw/net/lan9118: Fix RX Status FIFO PEEK value
30
* GICv3: support state save/restore from KVM
26
* npcm7xx: Add ADC and PWM emulation
31
* update Linux headers to 4.11
27
* ui/cocoa: Make "open docs" help menu entry work again when binary
32
* refactor and QOMify the ARMv7M container object
28
is run from the build tree
29
* ui/cocoa: Fix openFile: deprecation on Big Sur
30
* docs: Add qemu-storage-daemon(1) manpage to meson.build
31
* docs: Build and install all the docs in a single manual
33
32
34
----------------------------------------------------------------
33
----------------------------------------------------------------
35
Clement Deschamps (3):
34
Hao Wu (6):
36
hw/sd: add card-reparenting function
35
hw/misc: Add clock converter in NPCM7XX CLK module
37
bcm2835_gpio: add bcm2835 gpio controller
36
hw/timer: Refactor NPCM7XX Timer to use CLK clock
38
bcm2835: add sdhost and gpio controllers
37
hw/adc: Add an ADC module for NPCM7XX
38
hw/misc: Add a PWM module for NPCM7XX
39
hw/misc: Add QTest for NPCM7XX PWM Module
40
hw/*: Use type casting for SysBusDevice in NPCM7XX
39
41
40
Paolo Bonzini (2):
42
Leif Lindholm (6):
41
update-linux-headers: update for 4.11
43
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
42
update Linux headers to 4.11
44
target/arm: make ARMCPU.clidr 64-bit
45
target/arm: make ARMCPU.ctr 64-bit
46
target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
47
target/arm: add aarch64 ID register fields to cpu.h
48
target/arm: add aarch32 ID register fields to cpu.h
43
49
44
Peter Maydell (12):
50
Peter Maydell (5):
45
armv7m: Abstract out the "load kernel" code
51
docs: Add qemu-storage-daemon(1) manpage to meson.build
46
armv7m: Move NVICState struct definition into header
52
docs: Build and install all the docs in a single manual
47
armv7m: QOMify the armv7m container
53
target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
48
armv7m: Use QOMified armv7m object in armv7m_init()
54
hw/net/lan9118: Fix RX Status FIFO PEEK value
49
armv7m: Make ARMv7M object take memory region link
55
hw/net/lan9118: Add symbolic constants for register offsets
50
armv7m: Make NVIC expose a memory region rather than mapping itself
51
armv7m: Make bitband device take the address space to access
52
armv7m: Don't put core v7M devices under CONFIG_STELLARIS
53
armv7m: Split systick out from NVIC
54
stm32f205: Create armv7m object without using armv7m_init()
55
stm32f205: Rename 'nvic' local to 'armv7m'
56
qdev: Have qdev_set_parent_bus() handle devices already on a bus
57
56
58
Vijaya Kumar K (4):
57
Roman Bolshakov (2):
59
hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
58
ui/cocoa: Update path to docs in build tree
60
hw/intc/arm_gicv3_kvm: Implement get/put functions
59
ui/cocoa: Fix openFile: deprecation on Big Sur
61
target-arm: Add GICv3CPUState in CPUARMState struct
62
hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
63
60
64
hw/gpio/Makefile.objs | 1 +
61
Rémi Denis-Courmont (2):
65
hw/intc/Makefile.objs | 2 +-
62
target/arm: ARMv8.4-TTST extension
66
hw/timer/Makefile.objs | 1 +
63
target/arm: enable Small Translation tables in max CPU
67
hw/intc/gicv3_internal.h | 3 +
68
include/hw/arm/arm.h | 12 +
69
include/hw/arm/armv7m.h | 63 +++
70
include/hw/arm/armv7m_nvic.h | 62 ++
71
include/hw/arm/bcm2835_peripherals.h | 4 +
72
include/hw/arm/stm32f205_soc.h | 4 +-
73
include/hw/gpio/bcm2835_gpio.h | 39 ++
74
include/hw/intc/arm_gicv3_common.h | 1 +
75
include/hw/sd/sd.h | 11 +
76
include/hw/timer/armv7m_systick.h | 34 ++
77
include/standard-headers/asm-x86/hyperv.h | 8 +
78
include/standard-headers/linux/input-event-codes.h | 2 +-
79
include/standard-headers/linux/pci_regs.h | 25 +
80
include/standard-headers/linux/virtio_ids.h | 1 +
81
linux-headers/asm-arm/kvm.h | 15 +
82
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++
83
linux-headers/asm-arm/unistd-eabi.h | 5 +
84
linux-headers/asm-arm/unistd-oabi.h | 17 +
85
linux-headers/asm-arm/unistd.h | 419 +-------------
86
linux-headers/asm-arm64/kvm.h | 13 +
87
linux-headers/asm-powerpc/kvm.h | 27 +
88
linux-headers/asm-powerpc/unistd.h | 1 +
89
linux-headers/asm-x86/kvm_para.h | 13 +-
90
linux-headers/linux/kvm.h | 24 +-
91
linux-headers/linux/kvm_para.h | 2 +
92
linux-headers/linux/userfaultfd.h | 67 ++-
93
linux-headers/linux/vfio.h | 10 +
94
target/arm/cpu.h | 2 +
95
hw/arm/armv7m.c | 379 ++++++++-----
96
hw/arm/bcm2835_peripherals.c | 43 +-
97
hw/arm/netduino2.c | 7 +-
98
hw/arm/stm32f205_soc.c | 28 +-
99
hw/core/qdev.c | 14 +
100
hw/gpio/bcm2835_gpio.c | 353 ++++++++++++
101
hw/intc/arm_gicv3_common.c | 38 ++
102
hw/intc/arm_gicv3_cpuif.c | 8 +
103
hw/intc/arm_gicv3_kvm.c | 629 ++++++++++++++++++++-
104
hw/intc/armv7m_nvic.c | 214 ++-----
105
hw/sd/core.c | 27 +
106
hw/timer/armv7m_systick.c | 240 ++++++++
107
default-configs/arm-softmmu.mak | 2 +
108
hw/timer/trace-events | 6 +
109
scripts/update-linux-headers.sh | 13 +-
110
46 files changed, 2479 insertions(+), 767 deletions(-)
111
create mode 100644 include/hw/arm/armv7m.h
112
create mode 100644 include/hw/arm/armv7m_nvic.h
113
create mode 100644 include/hw/gpio/bcm2835_gpio.h
114
create mode 100644 include/hw/timer/armv7m_systick.h
115
create mode 100644 linux-headers/asm-arm/unistd-common.h
116
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
117
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
118
create mode 100644 hw/gpio/bcm2835_gpio.c
119
create mode 100644 hw/timer/armv7m_systick.c
120
64
65
docs/conf.py | 46 ++-
66
docs/devel/conf.py | 15 -
67
docs/index.html.in | 17 -
68
docs/interop/conf.py | 28 --
69
docs/meson.build | 65 ++--
70
docs/specs/conf.py | 16 -
71
docs/system/arm/nuvoton.rst | 4 +-
72
docs/system/conf.py | 28 --
73
docs/tools/conf.py | 37 --
74
docs/user/conf.py | 15 -
75
meson.build | 1 +
76
hw/adc/trace.h | 1 +
77
include/hw/adc/npcm7xx_adc.h | 69 ++++
78
include/hw/arm/npcm7xx.h | 4 +
79
include/hw/misc/npcm7xx_clk.h | 146 ++++++-
80
include/hw/misc/npcm7xx_pwm.h | 105 +++++
81
include/hw/timer/npcm7xx_timer.h | 1 +
82
target/arm/cpu.h | 85 ++++-
83
hw/adc/npcm7xx_adc.c | 301 +++++++++++++++
84
hw/arm/npcm7xx.c | 55 ++-
85
hw/arm/npcm7xx_boards.c | 2 +-
86
hw/mem/npcm7xx_mc.c | 2 +-
87
hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-
88
hw/misc/npcm7xx_gcr.c | 2 +-
89
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++
90
hw/misc/npcm7xx_rng.c | 2 +-
91
hw/net/lan9118.c | 26 +-
92
hw/nvram/npcm7xx_otp.c | 2 +-
93
hw/ssi/npcm7xx_fiu.c | 2 +-
94
hw/timer/npcm7xx_timer.c | 39 +-
95
target/arm/cpu64.c | 1 +
96
target/arm/helper.c | 15 +-
97
target/arm/translate.c | 7 +
98
tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++
99
tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++
100
hw/adc/meson.build | 1 +
101
hw/adc/trace-events | 5 +
102
hw/misc/meson.build | 1 +
103
hw/misc/trace-events | 6 +
104
tests/qtest/meson.build | 4 +-
105
ui/cocoa.m | 7 +-
106
41 files changed, 3124 insertions(+), 263 deletions(-)
107
delete mode 100644 docs/devel/conf.py
108
delete mode 100644 docs/index.html.in
109
delete mode 100644 docs/interop/conf.py
110
delete mode 100644 docs/specs/conf.py
111
delete mode 100644 docs/system/conf.py
112
delete mode 100644 docs/tools/conf.py
113
delete mode 100644 docs/user/conf.py
114
create mode 100644 hw/adc/trace.h
115
create mode 100644 include/hw/adc/npcm7xx_adc.h
116
create mode 100644 include/hw/misc/npcm7xx_pwm.h
117
create mode 100644 hw/adc/npcm7xx_adc.c
118
create mode 100644 hw/misc/npcm7xx_pwm.c
119
create mode 100644 tests/qtest/npcm7xx_adc-test.c
120
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
121
create mode 100644 hw/adc/trace-events
122
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Reset CPU interface registers of GICv3 when CPU is reset.
3
This adds for the Small Translation tables extension in AArch64 state.
4
For this, ARMCPRegInfo struct is registered with one ICC
5
register whose resetfn is called when cpu is reset.
6
4
7
All the ICC registers are reset under one single register
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
8
reset function instead of calling resetfn for each ICC
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
register.
10
11
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1487850673-26455-6-git-send-email-vijay.kilari@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
8
---
17
hw/intc/arm_gicv3_kvm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
9
target/arm/cpu.h | 5 +++++
18
1 file changed, 60 insertions(+)
10
target/arm/helper.c | 15 +++++++++++++--
11
2 files changed, 18 insertions(+), 2 deletions(-)
19
12
20
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_kvm.c
15
--- a/target/arm/cpu.h
23
+++ b/hw/intc/arm_gicv3_kvm.c
16
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
25
}
18
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
26
}
19
}
27
20
28
+static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
21
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
29
+{
22
+{
30
+ ARMCPU *cpu;
23
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
31
+ GICv3State *s;
32
+ GICv3CPUState *c;
33
+
34
+ c = (GICv3CPUState *)env->gicv3state;
35
+ s = c->gic;
36
+ cpu = ARM_CPU(c->cpu);
37
+
38
+ /* Initialize to actual HW supported configuration */
39
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
40
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
41
+ &c->icc_ctlr_el1[GICV3_NS], false);
42
+
43
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
44
+ c->icc_pmr_el1 = 0;
45
+ c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
46
+ c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
47
+ c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
48
+
49
+ c->icc_sre_el1 = 0x7;
50
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
51
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
52
+}
24
+}
53
+
25
+
54
static void kvm_arm_gicv3_reset(DeviceState *dev)
26
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
55
{
27
{
56
GICv3State *s = ARM_GICV3_COMMON(dev);
28
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
57
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
58
kvm_arm_gicv3_put(s);
30
index XXXXXXX..XXXXXXX 100644
59
}
31
--- a/target/arm/helper.c
60
32
+++ b/target/arm/helper.c
61
+/*
33
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
62
+ * CPU interface registers of GIC needs to be reset on CPU reset.
34
{
63
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
35
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
64
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
36
bool epd, hpd, using16k, using64k;
65
+ * register reset, we define only one register of CPU interface instead
37
- int select, tsz, tbi;
66
+ * of defining all the registers.
38
+ int select, tsz, tbi, max_tsz;
67
+ */
39
68
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
40
if (!regime_has_2_ranges(mmu_idx)) {
69
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
41
select = 0;
70
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
42
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
71
+ /*
43
hpd = extract64(tcr, 42, 1);
72
+ * If ARM_CP_NOP is used, resetfn is not called,
44
}
73
+ * So ARM_CP_NO_RAW is appropriate type.
45
}
74
+ */
46
- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
75
+ .type = ARM_CP_NO_RAW,
76
+ .access = PL1_RW,
77
+ .readfn = arm_cp_read_zero,
78
+ .writefn = arm_cp_write_ignore,
79
+ /*
80
+ * We hang the whole cpu interface reset routine off here
81
+ * rather than parcelling it out into one little function
82
+ * per register
83
+ */
84
+ .resetfn = arm_gicv3_icc_reset,
85
+ },
86
+ REGINFO_SENTINEL
87
+};
88
+
47
+
89
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
48
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
90
{
49
+ max_tsz = 48 - using64k;
91
GICv3State *s = KVM_ARM_GICV3(dev);
50
+ } else {
92
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
51
+ max_tsz = 39;
93
94
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
95
96
+ for (i = 0; i < s->num_cpu; i++) {
97
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
98
+
99
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
100
+ }
52
+ }
101
+
53
+
102
/* Try to create the device via the device control API */
54
+ tsz = MIN(tsz, max_tsz);
103
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
55
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
104
if (s->dev_fd < 0) {
56
57
/* Present TBI as a composite with TBID. */
58
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
59
if (!aarch64 || stride == 9) {
60
/* AArch32 or 4KB pages */
61
startlevel = 2 - sl0;
62
+
63
+ if (cpu_isar_feature(aa64_st, cpu)) {
64
+ startlevel &= 3;
65
+ }
66
} else {
67
/* 16KB or 64KB pages */
68
startlevel = 3 - sl0;
105
--
69
--
106
2.7.4
70
2.20.1
107
71
108
72
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Provide a new function sdbus_reparent_card() in sd core for reparenting
3
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
4
a card from a SDBus to another one.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
6
This function is required by the raspi platform, where the two SD
7
controllers can be dynamically switched.
8
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org
13
Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a doc comment to the header file; changed to
16
use new behaviour of qdev_set_parent_bus()]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
6
---
19
include/hw/sd/sd.h | 11 +++++++++++
7
target/arm/cpu64.c | 1 +
20
hw/sd/core.c | 27 +++++++++++++++++++++++++++
8
1 file changed, 1 insertion(+)
21
2 files changed, 38 insertions(+)
22
9
23
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
10
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/sd/sd.h
12
--- a/target/arm/cpu64.c
26
+++ b/include/hw/sd/sd.h
13
+++ b/target/arm/cpu64.c
27
@@ -XXX,XX +XXX,XX @@ uint8_t sdbus_read_data(SDBus *sd);
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
28
bool sdbus_data_ready(SDBus *sd);
15
t = cpu->isar.id_aa64mmfr2;
29
bool sdbus_get_inserted(SDBus *sd);
16
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
30
bool sdbus_get_readonly(SDBus *sd);
17
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
31
+/**
18
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
32
+ * sdbus_reparent_card: Reparent an SD card from one controller to another
19
cpu->isar.id_aa64mmfr2 = t;
33
+ * @from: controller bus to remove card from
20
34
+ * @to: controller bus to move card to
21
/* Replicate the same data to the 32-bit id registers. */
35
+ *
36
+ * Reparent an SD card, effectively unplugging it from one controller
37
+ * and inserting it into another. This is useful for SoCs like the
38
+ * bcm2835 which have two SD controllers and connect a single SD card
39
+ * to them, selected by the guest reprogramming GPIO line routing.
40
+ */
41
+void sdbus_reparent_card(SDBus *from, SDBus *to);
42
43
/* Functions to be used by SD devices to report back to qdevified controllers */
44
void sdbus_set_inserted(SDBus *sd, bool inserted);
45
diff --git a/hw/sd/core.c b/hw/sd/core.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/sd/core.c
48
+++ b/hw/sd/core.c
49
@@ -XXX,XX +XXX,XX @@ void sdbus_set_readonly(SDBus *sdbus, bool readonly)
50
}
51
}
52
53
+void sdbus_reparent_card(SDBus *from, SDBus *to)
54
+{
55
+ SDState *card = get_card(from);
56
+ SDCardClass *sc;
57
+ bool readonly;
58
+
59
+ /* We directly reparent the card object rather than implementing this
60
+ * as a hotpluggable connection because we don't want to expose SD cards
61
+ * to users as being hotpluggable, and we can get away with it in this
62
+ * limited use case. This could perhaps be implemented more cleanly in
63
+ * future by adding support to the hotplug infrastructure for "device
64
+ * can be hotplugged only via code, not by user".
65
+ */
66
+
67
+ if (!card) {
68
+ return;
69
+ }
70
+
71
+ sc = SD_CARD_GET_CLASS(card);
72
+ readonly = sc->get_readonly(card);
73
+
74
+ sdbus_set_inserted(from, false);
75
+ qdev_set_parent_bus(DEVICE(card), &to->qbus);
76
+ sdbus_set_inserted(to, true);
77
+ sdbus_set_readonly(to, readonly);
78
+}
79
+
80
static const TypeInfo sd_bus_info = {
81
.name = TYPE_SD_BUS,
82
.parent = TYPE_BUS,
83
--
22
--
84
2.7.4
23
2.20.1
85
24
86
25
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
To Save and Restore ICC_SRE_EL1 register introduce vmstate
3
SBSS -> SSBS
4
subsection and load only if non-zero.
5
Also initialize icc_sre_el1 with to 0x7 in pre_load
6
function.
7
4
8
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com
9
Message-id: 20210108185154.8108-2-leif@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
include/hw/intc/arm_gicv3_common.h | 1 +
12
target/arm/cpu.h | 2 +-
15
hw/intc/arm_gicv3_common.c | 36 ++++++++++++++++++++++++++++++++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
16
2 files changed, 37 insertions(+)
17
14
18
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/arm_gicv3_common.h
17
--- a/target/arm/cpu.h
21
+++ b/include/hw/intc/arm_gicv3_common.h
18
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
19
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
23
uint8_t gicr_ipriorityr[GIC_INTERNAL];
20
FIELD(ID_AA64PFR0, SVE, 32, 4)
24
21
25
/* CPU interface */
22
FIELD(ID_AA64PFR1, BT, 0, 4)
26
+ uint64_t icc_sre_el1;
23
-FIELD(ID_AA64PFR1, SBSS, 4, 4)
27
uint64_t icc_ctlr_el1[2];
24
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
28
uint64_t icc_pmr_el1;
25
FIELD(ID_AA64PFR1, MTE, 8, 4)
29
uint64_t icc_bpr[3];
26
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
30
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_common.c
33
+++ b/hw/intc/arm_gicv3_common.c
34
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu_virt = {
35
}
36
};
37
38
+static int icc_sre_el1_reg_pre_load(void *opaque)
39
+{
40
+ GICv3CPUState *cs = opaque;
41
+
42
+ /*
43
+ * If the sre_el1 subsection is not transferred this
44
+ * means SRE_EL1 is 0x7 (which might not be the same as
45
+ * our reset value).
46
+ */
47
+ cs->icc_sre_el1 = 0x7;
48
+ return 0;
49
+}
50
+
51
+static bool icc_sre_el1_reg_needed(void *opaque)
52
+{
53
+ GICv3CPUState *cs = opaque;
54
+
55
+ return cs->icc_sre_el1 != 7;
56
+}
57
+
58
+const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
59
+ .name = "arm_gicv3_cpu/sre_el1",
60
+ .version_id = 1,
61
+ .minimum_version_id = 1,
62
+ .pre_load = icc_sre_el1_reg_pre_load,
63
+ .needed = icc_sre_el1_reg_needed,
64
+ .fields = (VMStateField[]) {
65
+ VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
66
+ VMSTATE_END_OF_LIST()
67
+ }
68
+};
69
+
70
static const VMStateDescription vmstate_gicv3_cpu = {
71
.name = "arm_gicv3_cpu",
72
.version_id = 1,
73
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
74
.subsections = (const VMStateDescription * []) {
75
&vmstate_gicv3_cpu_virt,
76
NULL
77
+ },
78
+ .subsections = (const VMStateDescription * []) {
79
+ &vmstate_gicv3_cpu_sre_el1,
80
+ NULL
81
}
82
};
83
27
84
--
28
--
85
2.7.4
29
2.20.1
86
30
87
31
diff view generated by jsdifflib
1
Instead of qdev_set_parent_bus() silently doing the wrong
1
From: Leif Lindholm <leif@nuviainc.com>
2
thing if it's handed a device that's already on a bus,
3
have it remove the device from the old bus and add it to
4
the new one. This is useful for the raspi2 sdcard.
5
2
3
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
4
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
5
Extend the clidr field to be able to hold this context.
6
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-3-leif@nuviainc.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
Message-id: 1488293711-14195-2-git-send-email-peter.maydell@linaro.org
9
---
13
---
10
hw/core/qdev.c | 14 ++++++++++++++
14
target/arm/cpu.h | 2 +-
11
1 file changed, 14 insertions(+)
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
16
13
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/core/qdev.c
19
--- a/target/arm/cpu.h
16
+++ b/hw/core/qdev.c
20
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
18
22
uint32_t id_afr0;
19
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
23
uint64_t id_aa64afr0;
20
{
24
uint64_t id_aa64afr1;
21
+ bool replugging = dev->parent_bus != NULL;
25
- uint32_t clidr;
22
+
26
+ uint64_t clidr;
23
+ if (replugging) {
27
uint64_t mp_affinity; /* MP ID without feature bits */
24
+ /* Keep a reference to the device while it's not plugged into
28
/* The elements of this array are the CCSIDR values for each cache,
25
+ * any bus, to avoid it potentially evaporating when it is
29
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
26
+ * dereffed in bus_remove_child().
27
+ */
28
+ object_ref(OBJECT(dev));
29
+ bus_remove_child(dev->parent_bus, dev);
30
+ object_unref(OBJECT(dev->parent_bus));
31
+ }
32
dev->parent_bus = bus;
33
object_ref(OBJECT(bus));
34
bus_add_child(bus, dev);
35
+ if (replugging) {
36
+ object_unref(OBJECT(dev));
37
+ }
38
}
39
40
/* Create a new device. This only initializes the device state
41
--
30
--
42
2.7.4
31
2.20.1
43
32
44
33
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Add gicv3state void pointer to CPUARMState struct
3
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
4
to store GICv3CPUState.
4
TminLine field in bits [37:32].
5
Extend the ctr field to be able to hold this context.
5
6
6
In case of usecase like CPU reset, we need to reset
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
7
GICv3CPUState of the CPU. In such scenario, this pointer
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
8
becomes handy.
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
11
Message-id: 20210108185154.8108-4-leif@nuviainc.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 1487850673-26455-5-git-send-email-vijay.kilari@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
13
---
16
hw/intc/gicv3_internal.h | 2 ++
14
target/arm/cpu.h | 2 +-
17
target/arm/cpu.h | 2 ++
15
1 file changed, 1 insertion(+), 1 deletion(-)
18
hw/intc/arm_gicv3_common.c | 2 ++
19
hw/intc/arm_gicv3_cpuif.c | 8 ++++++++
20
4 files changed, 14 insertions(+)
21
16
22
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/gicv3_internal.h
25
+++ b/hw/intc/gicv3_internal.h
26
@@ -XXX,XX +XXX,XX @@ static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
27
}
28
}
29
30
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
31
+
32
#endif /* QEMU_ARM_GICV3_INTERNAL_H */
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
19
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
38
22
uint64_t midr;
39
void *nvic;
23
uint32_t revidr;
40
const struct arm_boot_info *boot_info;
24
uint32_t reset_fpsid;
41
+ /* Store GICv3CPUState to access from this struct */
25
- uint32_t ctr;
42
+ void *gicv3state;
26
+ uint64_t ctr;
43
} CPUARMState;
27
uint32_t reset_sctlr;
44
28
uint64_t pmceid0;
45
/**
29
uint64_t pmceid1;
46
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_common.c
49
+++ b/hw/intc/arm_gicv3_common.c
50
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
51
52
s->cpu[i].cpu = cpu;
53
s->cpu[i].gic = s;
54
+ /* Store GICv3CPUState in CPUARMState gicv3state pointer */
55
+ gicv3_set_gicv3state(cpu, &s->cpu[i]);
56
57
/* Pre-construct the GICR_TYPER:
58
* For our implementation:
59
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/intc/arm_gicv3_cpuif.c
62
+++ b/hw/intc/arm_gicv3_cpuif.c
63
@@ -XXX,XX +XXX,XX @@
64
#include "gicv3_internal.h"
65
#include "cpu.h"
66
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
68
+{
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
70
+ CPUARMState *env = &arm_cpu->env;
71
+
72
+ env->gicv3state = (void *)s;
73
+};
74
+
75
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
76
{
77
/* Given the CPU, find the right GICv3CPUState struct.
78
--
30
--
79
2.7.4
31
2.20.1
80
32
81
33
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
virtio_mmio.h would be deleted; I am leaving it in though it was a
3
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
4
mistake to add it.
4
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
5
5
Message-id: 20210108185154.8108-5-leif@nuviainc.com
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
7
---
9
include/standard-headers/asm-x86/hyperv.h | 8 +
8
target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
10
include/standard-headers/linux/input-event-codes.h | 2 +-
9
1 file changed, 31 insertions(+)
11
include/standard-headers/linux/pci_regs.h | 25 ++
12
include/standard-headers/linux/virtio_ids.h | 1 +
13
linux-headers/asm-arm/kvm.h | 15 +
14
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++++++++
15
linux-headers/asm-arm/unistd-eabi.h | 5 +
16
linux-headers/asm-arm/unistd-oabi.h | 17 +
17
linux-headers/asm-arm/unistd.h | 419 +--------------------
18
linux-headers/asm-arm64/kvm.h | 13 +
19
linux-headers/asm-powerpc/kvm.h | 27 ++
20
linux-headers/asm-powerpc/unistd.h | 1 +
21
linux-headers/asm-x86/kvm_para.h | 13 +-
22
linux-headers/linux/kvm.h | 24 +-
23
linux-headers/linux/kvm_para.h | 2 +
24
linux-headers/linux/userfaultfd.h | 67 +++-
25
linux-headers/linux/vfio.h | 10 +
26
17 files changed, 577 insertions(+), 429 deletions(-)
27
create mode 100644 linux-headers/asm-arm/unistd-common.h
28
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
29
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
30
10
31
diff --git a/include/standard-headers/asm-x86/hyperv.h b/include/standard-headers/asm-x86/hyperv.h
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
33
--- a/include/standard-headers/asm-x86/hyperv.h
13
--- a/target/arm/cpu.h
34
+++ b/include/standard-headers/asm-x86/hyperv.h
14
+++ b/target/arm/cpu.h
35
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
36
*/
16
/*
37
#define HV_X64_MSR_STAT_PAGES_AVAILABLE        (1 << 8)
17
* System register ID fields.
38
18
*/
39
+/* Crash MSR available */
19
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
40
+#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
20
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
21
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
22
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
23
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
24
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
25
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
26
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
27
+FIELD(CLIDR_EL1, LOC, 24, 3)
28
+FIELD(CLIDR_EL1, LOUU, 27, 3)
29
+FIELD(CLIDR_EL1, ICB, 30, 3)
41
+
30
+
42
/*
31
+/* When FEAT_CCIDX is implemented */
43
* Feature identification: EBX indicates which flags were specified at
32
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
44
* partition creation. The format is the same as the partition creation
33
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
45
@@ -XXX,XX +XXX,XX @@
34
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
46
*/
47
#define HV_X64_RELAXED_TIMING_RECOMMENDED    (1 << 5)
48
49
+/*
50
+ * Crash notification flag.
51
+ */
52
+#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
53
+
35
+
54
/* MSR used to identify the guest OS. */
36
+/* When FEAT_CCIDX is not implemented */
55
#define HV_X64_MSR_GUEST_OS_ID            0x40000000
37
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
56
38
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
57
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
39
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/standard-headers/linux/input-event-codes.h
60
+++ b/include/standard-headers/linux/input-event-codes.h
61
@@ -XXX,XX +XXX,XX @@
62
* Control a data application associated with the currently viewed channel,
63
* e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
64
*/
65
-#define KEY_DATA            0x275
66
+#define KEY_DATA            0x277
67
68
#define BTN_TRIGGER_HAPPY        0x2c0
69
#define BTN_TRIGGER_HAPPY1        0x2c0
70
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/standard-headers/linux/pci_regs.h
73
+++ b/include/standard-headers/linux/pci_regs.h
74
@@ -XXX,XX +XXX,XX @@
75
#define LINUX_PCI_REGS_H
76
77
/*
78
+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
79
+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
80
+ * configuration space.
81
+ */
82
+#define PCI_CFG_SPACE_SIZE    256
83
+#define PCI_CFG_SPACE_EXP_SIZE    4096
84
+
40
+
85
+/*
41
+FIELD(CTR_EL0, IMINLINE, 0, 4)
86
* Under PCI, each device has 256 bytes of configuration address space,
42
+FIELD(CTR_EL0, L1IP, 14, 2)
87
* of which the first 64 bytes are standardized as follows:
43
+FIELD(CTR_EL0, DMINLINE, 16, 4)
88
*/
44
+FIELD(CTR_EL0, ERG, 20, 4)
89
@@ -XXX,XX +XXX,XX @@
45
+FIELD(CTR_EL0, CWG, 24, 4)
90
#define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
46
+FIELD(CTR_EL0, IDC, 28, 1)
91
#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
47
+FIELD(CTR_EL0, DIC, 29, 1)
92
#define PCI_EXT_CAP_ID_DPC    0x1D    /* Downstream Port Containment */
48
+FIELD(CTR_EL0, TMINLINE, 32, 6)
93
+#define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
94
#define PCI_EXT_CAP_ID_PTM    0x1F    /* Precision Time Measurement */
95
#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PTM
96
97
@@ -XXX,XX +XXX,XX @@
98
#define PCI_EXP_DPC_STATUS        8    /* DPC Status */
99
#define PCI_EXP_DPC_STATUS_TRIGGER    0x01    /* Trigger Status */
100
#define PCI_EXP_DPC_STATUS_INTERRUPT    0x08    /* Interrupt Status */
101
+#define PCI_EXP_DPC_RP_BUSY        0x10    /* Root Port Busy */
102
103
#define PCI_EXP_DPC_SOURCE_ID        10    /* DPC Source Identifier */
104
105
@@ -XXX,XX +XXX,XX @@
106
#define PCI_PTM_CTRL_ENABLE        0x00000001 /* PTM enable */
107
#define PCI_PTM_CTRL_ROOT        0x00000002 /* Root select */
108
109
+/* L1 PM Substates */
110
+#define PCI_L1SS_CAP         4    /* capability register */
111
+#define PCI_L1SS_CAP_PCIPM_L1_2     1    /* PCI PM L1.2 Support */
112
+#define PCI_L1SS_CAP_PCIPM_L1_1     2    /* PCI PM L1.1 Support */
113
+#define PCI_L1SS_CAP_ASPM_L1_2         4    /* ASPM L1.2 Support */
114
+#define PCI_L1SS_CAP_ASPM_L1_1         8    /* ASPM L1.1 Support */
115
+#define PCI_L1SS_CAP_L1_PM_SS        16    /* L1 PM Substates Support */
116
+#define PCI_L1SS_CTL1         8    /* Control Register 1 */
117
+#define PCI_L1SS_CTL1_PCIPM_L1_2    1    /* PCI PM L1.2 Enable */
118
+#define PCI_L1SS_CTL1_PCIPM_L1_1    2    /* PCI PM L1.1 Support */
119
+#define PCI_L1SS_CTL1_ASPM_L1_2    4    /* ASPM L1.2 Support */
120
+#define PCI_L1SS_CTL1_ASPM_L1_1    8    /* ASPM L1.1 Support */
121
+#define PCI_L1SS_CTL1_L1SS_MASK    0x0000000F
122
+#define PCI_L1SS_CTL2         0xC    /* Control Register 2 */
123
+
49
+
124
#endif /* LINUX_PCI_REGS_H */
50
FIELD(MIDR_EL1, REVISION, 0, 4)
125
diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h
51
FIELD(MIDR_EL1, PARTNUM, 4, 12)
126
index XXXXXXX..XXXXXXX 100644
52
FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
127
--- a/include/standard-headers/linux/virtio_ids.h
128
+++ b/include/standard-headers/linux/virtio_ids.h
129
@@ -XXX,XX +XXX,XX @@
130
#define VIRTIO_ID_INPUT 18 /* virtio input */
131
#define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */
132
#define VIRTIO_ID_CRYPTO 20 /* virtio crypto */
133
+
134
#endif /* _LINUX_VIRTIO_IDS_H */
135
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-headers/asm-arm/kvm.h
138
+++ b/linux-headers/asm-arm/kvm.h
139
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
140
/* Supported VGICv3 address types */
141
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
142
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
143
+#define KVM_VGIC_ITS_ADDR_TYPE        4
144
145
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
146
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
147
+#define KVM_VGIC_V3_ITS_SIZE        (2 * SZ_64K)
148
149
#define KVM_ARM_VCPU_POWER_OFF        0 /* CPU is started in OFF state */
150
#define KVM_ARM_VCPU_PSCI_0_2        1 /* CPU uses PSCI v0.2 */
151
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
152
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
153
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
154
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
155
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
156
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
157
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
158
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
159
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
160
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
161
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
162
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
163
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
164
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
165
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
166
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
167
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
168
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
169
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
170
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
171
+
172
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
173
174
/* KVM_IRQ_LINE irq field index values */
175
diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h
176
new file mode 100644
177
index XXXXXXX..XXXXXXX
178
--- /dev/null
179
+++ b/linux-headers/asm-arm/unistd-common.h
180
@@ -XXX,XX +XXX,XX @@
181
+#ifndef _ASM_ARM_UNISTD_COMMON_H
182
+#define _ASM_ARM_UNISTD_COMMON_H 1
183
+
184
+#define __NR_restart_syscall (__NR_SYSCALL_BASE + 0)
185
+#define __NR_exit (__NR_SYSCALL_BASE + 1)
186
+#define __NR_fork (__NR_SYSCALL_BASE + 2)
187
+#define __NR_read (__NR_SYSCALL_BASE + 3)
188
+#define __NR_write (__NR_SYSCALL_BASE + 4)
189
+#define __NR_open (__NR_SYSCALL_BASE + 5)
190
+#define __NR_close (__NR_SYSCALL_BASE + 6)
191
+#define __NR_creat (__NR_SYSCALL_BASE + 8)
192
+#define __NR_link (__NR_SYSCALL_BASE + 9)
193
+#define __NR_unlink (__NR_SYSCALL_BASE + 10)
194
+#define __NR_execve (__NR_SYSCALL_BASE + 11)
195
+#define __NR_chdir (__NR_SYSCALL_BASE + 12)
196
+#define __NR_mknod (__NR_SYSCALL_BASE + 14)
197
+#define __NR_chmod (__NR_SYSCALL_BASE + 15)
198
+#define __NR_lchown (__NR_SYSCALL_BASE + 16)
199
+#define __NR_lseek (__NR_SYSCALL_BASE + 19)
200
+#define __NR_getpid (__NR_SYSCALL_BASE + 20)
201
+#define __NR_mount (__NR_SYSCALL_BASE + 21)
202
+#define __NR_setuid (__NR_SYSCALL_BASE + 23)
203
+#define __NR_getuid (__NR_SYSCALL_BASE + 24)
204
+#define __NR_ptrace (__NR_SYSCALL_BASE + 26)
205
+#define __NR_pause (__NR_SYSCALL_BASE + 29)
206
+#define __NR_access (__NR_SYSCALL_BASE + 33)
207
+#define __NR_nice (__NR_SYSCALL_BASE + 34)
208
+#define __NR_sync (__NR_SYSCALL_BASE + 36)
209
+#define __NR_kill (__NR_SYSCALL_BASE + 37)
210
+#define __NR_rename (__NR_SYSCALL_BASE + 38)
211
+#define __NR_mkdir (__NR_SYSCALL_BASE + 39)
212
+#define __NR_rmdir (__NR_SYSCALL_BASE + 40)
213
+#define __NR_dup (__NR_SYSCALL_BASE + 41)
214
+#define __NR_pipe (__NR_SYSCALL_BASE + 42)
215
+#define __NR_times (__NR_SYSCALL_BASE + 43)
216
+#define __NR_brk (__NR_SYSCALL_BASE + 45)
217
+#define __NR_setgid (__NR_SYSCALL_BASE + 46)
218
+#define __NR_getgid (__NR_SYSCALL_BASE + 47)
219
+#define __NR_geteuid (__NR_SYSCALL_BASE + 49)
220
+#define __NR_getegid (__NR_SYSCALL_BASE + 50)
221
+#define __NR_acct (__NR_SYSCALL_BASE + 51)
222
+#define __NR_umount2 (__NR_SYSCALL_BASE + 52)
223
+#define __NR_ioctl (__NR_SYSCALL_BASE + 54)
224
+#define __NR_fcntl (__NR_SYSCALL_BASE + 55)
225
+#define __NR_setpgid (__NR_SYSCALL_BASE + 57)
226
+#define __NR_umask (__NR_SYSCALL_BASE + 60)
227
+#define __NR_chroot (__NR_SYSCALL_BASE + 61)
228
+#define __NR_ustat (__NR_SYSCALL_BASE + 62)
229
+#define __NR_dup2 (__NR_SYSCALL_BASE + 63)
230
+#define __NR_getppid (__NR_SYSCALL_BASE + 64)
231
+#define __NR_getpgrp (__NR_SYSCALL_BASE + 65)
232
+#define __NR_setsid (__NR_SYSCALL_BASE + 66)
233
+#define __NR_sigaction (__NR_SYSCALL_BASE + 67)
234
+#define __NR_setreuid (__NR_SYSCALL_BASE + 70)
235
+#define __NR_setregid (__NR_SYSCALL_BASE + 71)
236
+#define __NR_sigsuspend (__NR_SYSCALL_BASE + 72)
237
+#define __NR_sigpending (__NR_SYSCALL_BASE + 73)
238
+#define __NR_sethostname (__NR_SYSCALL_BASE + 74)
239
+#define __NR_setrlimit (__NR_SYSCALL_BASE + 75)
240
+#define __NR_getrusage (__NR_SYSCALL_BASE + 77)
241
+#define __NR_gettimeofday (__NR_SYSCALL_BASE + 78)
242
+#define __NR_settimeofday (__NR_SYSCALL_BASE + 79)
243
+#define __NR_getgroups (__NR_SYSCALL_BASE + 80)
244
+#define __NR_setgroups (__NR_SYSCALL_BASE + 81)
245
+#define __NR_symlink (__NR_SYSCALL_BASE + 83)
246
+#define __NR_readlink (__NR_SYSCALL_BASE + 85)
247
+#define __NR_uselib (__NR_SYSCALL_BASE + 86)
248
+#define __NR_swapon (__NR_SYSCALL_BASE + 87)
249
+#define __NR_reboot (__NR_SYSCALL_BASE + 88)
250
+#define __NR_munmap (__NR_SYSCALL_BASE + 91)
251
+#define __NR_truncate (__NR_SYSCALL_BASE + 92)
252
+#define __NR_ftruncate (__NR_SYSCALL_BASE + 93)
253
+#define __NR_fchmod (__NR_SYSCALL_BASE + 94)
254
+#define __NR_fchown (__NR_SYSCALL_BASE + 95)
255
+#define __NR_getpriority (__NR_SYSCALL_BASE + 96)
256
+#define __NR_setpriority (__NR_SYSCALL_BASE + 97)
257
+#define __NR_statfs (__NR_SYSCALL_BASE + 99)
258
+#define __NR_fstatfs (__NR_SYSCALL_BASE + 100)
259
+#define __NR_syslog (__NR_SYSCALL_BASE + 103)
260
+#define __NR_setitimer (__NR_SYSCALL_BASE + 104)
261
+#define __NR_getitimer (__NR_SYSCALL_BASE + 105)
262
+#define __NR_stat (__NR_SYSCALL_BASE + 106)
263
+#define __NR_lstat (__NR_SYSCALL_BASE + 107)
264
+#define __NR_fstat (__NR_SYSCALL_BASE + 108)
265
+#define __NR_vhangup (__NR_SYSCALL_BASE + 111)
266
+#define __NR_wait4 (__NR_SYSCALL_BASE + 114)
267
+#define __NR_swapoff (__NR_SYSCALL_BASE + 115)
268
+#define __NR_sysinfo (__NR_SYSCALL_BASE + 116)
269
+#define __NR_fsync (__NR_SYSCALL_BASE + 118)
270
+#define __NR_sigreturn (__NR_SYSCALL_BASE + 119)
271
+#define __NR_clone (__NR_SYSCALL_BASE + 120)
272
+#define __NR_setdomainname (__NR_SYSCALL_BASE + 121)
273
+#define __NR_uname (__NR_SYSCALL_BASE + 122)
274
+#define __NR_adjtimex (__NR_SYSCALL_BASE + 124)
275
+#define __NR_mprotect (__NR_SYSCALL_BASE + 125)
276
+#define __NR_sigprocmask (__NR_SYSCALL_BASE + 126)
277
+#define __NR_init_module (__NR_SYSCALL_BASE + 128)
278
+#define __NR_delete_module (__NR_SYSCALL_BASE + 129)
279
+#define __NR_quotactl (__NR_SYSCALL_BASE + 131)
280
+#define __NR_getpgid (__NR_SYSCALL_BASE + 132)
281
+#define __NR_fchdir (__NR_SYSCALL_BASE + 133)
282
+#define __NR_bdflush (__NR_SYSCALL_BASE + 134)
283
+#define __NR_sysfs (__NR_SYSCALL_BASE + 135)
284
+#define __NR_personality (__NR_SYSCALL_BASE + 136)
285
+#define __NR_setfsuid (__NR_SYSCALL_BASE + 138)
286
+#define __NR_setfsgid (__NR_SYSCALL_BASE + 139)
287
+#define __NR__llseek (__NR_SYSCALL_BASE + 140)
288
+#define __NR_getdents (__NR_SYSCALL_BASE + 141)
289
+#define __NR__newselect (__NR_SYSCALL_BASE + 142)
290
+#define __NR_flock (__NR_SYSCALL_BASE + 143)
291
+#define __NR_msync (__NR_SYSCALL_BASE + 144)
292
+#define __NR_readv (__NR_SYSCALL_BASE + 145)
293
+#define __NR_writev (__NR_SYSCALL_BASE + 146)
294
+#define __NR_getsid (__NR_SYSCALL_BASE + 147)
295
+#define __NR_fdatasync (__NR_SYSCALL_BASE + 148)
296
+#define __NR__sysctl (__NR_SYSCALL_BASE + 149)
297
+#define __NR_mlock (__NR_SYSCALL_BASE + 150)
298
+#define __NR_munlock (__NR_SYSCALL_BASE + 151)
299
+#define __NR_mlockall (__NR_SYSCALL_BASE + 152)
300
+#define __NR_munlockall (__NR_SYSCALL_BASE + 153)
301
+#define __NR_sched_setparam (__NR_SYSCALL_BASE + 154)
302
+#define __NR_sched_getparam (__NR_SYSCALL_BASE + 155)
303
+#define __NR_sched_setscheduler (__NR_SYSCALL_BASE + 156)
304
+#define __NR_sched_getscheduler (__NR_SYSCALL_BASE + 157)
305
+#define __NR_sched_yield (__NR_SYSCALL_BASE + 158)
306
+#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE + 159)
307
+#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE + 160)
308
+#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE + 161)
309
+#define __NR_nanosleep (__NR_SYSCALL_BASE + 162)
310
+#define __NR_mremap (__NR_SYSCALL_BASE + 163)
311
+#define __NR_setresuid (__NR_SYSCALL_BASE + 164)
312
+#define __NR_getresuid (__NR_SYSCALL_BASE + 165)
313
+#define __NR_poll (__NR_SYSCALL_BASE + 168)
314
+#define __NR_nfsservctl (__NR_SYSCALL_BASE + 169)
315
+#define __NR_setresgid (__NR_SYSCALL_BASE + 170)
316
+#define __NR_getresgid (__NR_SYSCALL_BASE + 171)
317
+#define __NR_prctl (__NR_SYSCALL_BASE + 172)
318
+#define __NR_rt_sigreturn (__NR_SYSCALL_BASE + 173)
319
+#define __NR_rt_sigaction (__NR_SYSCALL_BASE + 174)
320
+#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE + 175)
321
+#define __NR_rt_sigpending (__NR_SYSCALL_BASE + 176)
322
+#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE + 177)
323
+#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE + 178)
324
+#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE + 179)
325
+#define __NR_pread64 (__NR_SYSCALL_BASE + 180)
326
+#define __NR_pwrite64 (__NR_SYSCALL_BASE + 181)
327
+#define __NR_chown (__NR_SYSCALL_BASE + 182)
328
+#define __NR_getcwd (__NR_SYSCALL_BASE + 183)
329
+#define __NR_capget (__NR_SYSCALL_BASE + 184)
330
+#define __NR_capset (__NR_SYSCALL_BASE + 185)
331
+#define __NR_sigaltstack (__NR_SYSCALL_BASE + 186)
332
+#define __NR_sendfile (__NR_SYSCALL_BASE + 187)
333
+#define __NR_vfork (__NR_SYSCALL_BASE + 190)
334
+#define __NR_ugetrlimit (__NR_SYSCALL_BASE + 191)
335
+#define __NR_mmap2 (__NR_SYSCALL_BASE + 192)
336
+#define __NR_truncate64 (__NR_SYSCALL_BASE + 193)
337
+#define __NR_ftruncate64 (__NR_SYSCALL_BASE + 194)
338
+#define __NR_stat64 (__NR_SYSCALL_BASE + 195)
339
+#define __NR_lstat64 (__NR_SYSCALL_BASE + 196)
340
+#define __NR_fstat64 (__NR_SYSCALL_BASE + 197)
341
+#define __NR_lchown32 (__NR_SYSCALL_BASE + 198)
342
+#define __NR_getuid32 (__NR_SYSCALL_BASE + 199)
343
+#define __NR_getgid32 (__NR_SYSCALL_BASE + 200)
344
+#define __NR_geteuid32 (__NR_SYSCALL_BASE + 201)
345
+#define __NR_getegid32 (__NR_SYSCALL_BASE + 202)
346
+#define __NR_setreuid32 (__NR_SYSCALL_BASE + 203)
347
+#define __NR_setregid32 (__NR_SYSCALL_BASE + 204)
348
+#define __NR_getgroups32 (__NR_SYSCALL_BASE + 205)
349
+#define __NR_setgroups32 (__NR_SYSCALL_BASE + 206)
350
+#define __NR_fchown32 (__NR_SYSCALL_BASE + 207)
351
+#define __NR_setresuid32 (__NR_SYSCALL_BASE + 208)
352
+#define __NR_getresuid32 (__NR_SYSCALL_BASE + 209)
353
+#define __NR_setresgid32 (__NR_SYSCALL_BASE + 210)
354
+#define __NR_getresgid32 (__NR_SYSCALL_BASE + 211)
355
+#define __NR_chown32 (__NR_SYSCALL_BASE + 212)
356
+#define __NR_setuid32 (__NR_SYSCALL_BASE + 213)
357
+#define __NR_setgid32 (__NR_SYSCALL_BASE + 214)
358
+#define __NR_setfsuid32 (__NR_SYSCALL_BASE + 215)
359
+#define __NR_setfsgid32 (__NR_SYSCALL_BASE + 216)
360
+#define __NR_getdents64 (__NR_SYSCALL_BASE + 217)
361
+#define __NR_pivot_root (__NR_SYSCALL_BASE + 218)
362
+#define __NR_mincore (__NR_SYSCALL_BASE + 219)
363
+#define __NR_madvise (__NR_SYSCALL_BASE + 220)
364
+#define __NR_fcntl64 (__NR_SYSCALL_BASE + 221)
365
+#define __NR_gettid (__NR_SYSCALL_BASE + 224)
366
+#define __NR_readahead (__NR_SYSCALL_BASE + 225)
367
+#define __NR_setxattr (__NR_SYSCALL_BASE + 226)
368
+#define __NR_lsetxattr (__NR_SYSCALL_BASE + 227)
369
+#define __NR_fsetxattr (__NR_SYSCALL_BASE + 228)
370
+#define __NR_getxattr (__NR_SYSCALL_BASE + 229)
371
+#define __NR_lgetxattr (__NR_SYSCALL_BASE + 230)
372
+#define __NR_fgetxattr (__NR_SYSCALL_BASE + 231)
373
+#define __NR_listxattr (__NR_SYSCALL_BASE + 232)
374
+#define __NR_llistxattr (__NR_SYSCALL_BASE + 233)
375
+#define __NR_flistxattr (__NR_SYSCALL_BASE + 234)
376
+#define __NR_removexattr (__NR_SYSCALL_BASE + 235)
377
+#define __NR_lremovexattr (__NR_SYSCALL_BASE + 236)
378
+#define __NR_fremovexattr (__NR_SYSCALL_BASE + 237)
379
+#define __NR_tkill (__NR_SYSCALL_BASE + 238)
380
+#define __NR_sendfile64 (__NR_SYSCALL_BASE + 239)
381
+#define __NR_futex (__NR_SYSCALL_BASE + 240)
382
+#define __NR_sched_setaffinity (__NR_SYSCALL_BASE + 241)
383
+#define __NR_sched_getaffinity (__NR_SYSCALL_BASE + 242)
384
+#define __NR_io_setup (__NR_SYSCALL_BASE + 243)
385
+#define __NR_io_destroy (__NR_SYSCALL_BASE + 244)
386
+#define __NR_io_getevents (__NR_SYSCALL_BASE + 245)
387
+#define __NR_io_submit (__NR_SYSCALL_BASE + 246)
388
+#define __NR_io_cancel (__NR_SYSCALL_BASE + 247)
389
+#define __NR_exit_group (__NR_SYSCALL_BASE + 248)
390
+#define __NR_lookup_dcookie (__NR_SYSCALL_BASE + 249)
391
+#define __NR_epoll_create (__NR_SYSCALL_BASE + 250)
392
+#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 251)
393
+#define __NR_epoll_wait (__NR_SYSCALL_BASE + 252)
394
+#define __NR_remap_file_pages (__NR_SYSCALL_BASE + 253)
395
+#define __NR_set_tid_address (__NR_SYSCALL_BASE + 256)
396
+#define __NR_timer_create (__NR_SYSCALL_BASE + 257)
397
+#define __NR_timer_settime (__NR_SYSCALL_BASE + 258)
398
+#define __NR_timer_gettime (__NR_SYSCALL_BASE + 259)
399
+#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 260)
400
+#define __NR_timer_delete (__NR_SYSCALL_BASE + 261)
401
+#define __NR_clock_settime (__NR_SYSCALL_BASE + 262)
402
+#define __NR_clock_gettime (__NR_SYSCALL_BASE + 263)
403
+#define __NR_clock_getres (__NR_SYSCALL_BASE + 264)
404
+#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 265)
405
+#define __NR_statfs64 (__NR_SYSCALL_BASE + 266)
406
+#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 267)
407
+#define __NR_tgkill (__NR_SYSCALL_BASE + 268)
408
+#define __NR_utimes (__NR_SYSCALL_BASE + 269)
409
+#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE + 270)
410
+#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE + 271)
411
+#define __NR_pciconfig_read (__NR_SYSCALL_BASE + 272)
412
+#define __NR_pciconfig_write (__NR_SYSCALL_BASE + 273)
413
+#define __NR_mq_open (__NR_SYSCALL_BASE + 274)
414
+#define __NR_mq_unlink (__NR_SYSCALL_BASE + 275)
415
+#define __NR_mq_timedsend (__NR_SYSCALL_BASE + 276)
416
+#define __NR_mq_timedreceive (__NR_SYSCALL_BASE + 277)
417
+#define __NR_mq_notify (__NR_SYSCALL_BASE + 278)
418
+#define __NR_mq_getsetattr (__NR_SYSCALL_BASE + 279)
419
+#define __NR_waitid (__NR_SYSCALL_BASE + 280)
420
+#define __NR_socket (__NR_SYSCALL_BASE + 281)
421
+#define __NR_bind (__NR_SYSCALL_BASE + 282)
422
+#define __NR_connect (__NR_SYSCALL_BASE + 283)
423
+#define __NR_listen (__NR_SYSCALL_BASE + 284)
424
+#define __NR_accept (__NR_SYSCALL_BASE + 285)
425
+#define __NR_getsockname (__NR_SYSCALL_BASE + 286)
426
+#define __NR_getpeername (__NR_SYSCALL_BASE + 287)
427
+#define __NR_socketpair (__NR_SYSCALL_BASE + 288)
428
+#define __NR_send (__NR_SYSCALL_BASE + 289)
429
+#define __NR_sendto (__NR_SYSCALL_BASE + 290)
430
+#define __NR_recv (__NR_SYSCALL_BASE + 291)
431
+#define __NR_recvfrom (__NR_SYSCALL_BASE + 292)
432
+#define __NR_shutdown (__NR_SYSCALL_BASE + 293)
433
+#define __NR_setsockopt (__NR_SYSCALL_BASE + 294)
434
+#define __NR_getsockopt (__NR_SYSCALL_BASE + 295)
435
+#define __NR_sendmsg (__NR_SYSCALL_BASE + 296)
436
+#define __NR_recvmsg (__NR_SYSCALL_BASE + 297)
437
+#define __NR_semop (__NR_SYSCALL_BASE + 298)
438
+#define __NR_semget (__NR_SYSCALL_BASE + 299)
439
+#define __NR_semctl (__NR_SYSCALL_BASE + 300)
440
+#define __NR_msgsnd (__NR_SYSCALL_BASE + 301)
441
+#define __NR_msgrcv (__NR_SYSCALL_BASE + 302)
442
+#define __NR_msgget (__NR_SYSCALL_BASE + 303)
443
+#define __NR_msgctl (__NR_SYSCALL_BASE + 304)
444
+#define __NR_shmat (__NR_SYSCALL_BASE + 305)
445
+#define __NR_shmdt (__NR_SYSCALL_BASE + 306)
446
+#define __NR_shmget (__NR_SYSCALL_BASE + 307)
447
+#define __NR_shmctl (__NR_SYSCALL_BASE + 308)
448
+#define __NR_add_key (__NR_SYSCALL_BASE + 309)
449
+#define __NR_request_key (__NR_SYSCALL_BASE + 310)
450
+#define __NR_keyctl (__NR_SYSCALL_BASE + 311)
451
+#define __NR_semtimedop (__NR_SYSCALL_BASE + 312)
452
+#define __NR_vserver (__NR_SYSCALL_BASE + 313)
453
+#define __NR_ioprio_set (__NR_SYSCALL_BASE + 314)
454
+#define __NR_ioprio_get (__NR_SYSCALL_BASE + 315)
455
+#define __NR_inotify_init (__NR_SYSCALL_BASE + 316)
456
+#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 317)
457
+#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 318)
458
+#define __NR_mbind (__NR_SYSCALL_BASE + 319)
459
+#define __NR_get_mempolicy (__NR_SYSCALL_BASE + 320)
460
+#define __NR_set_mempolicy (__NR_SYSCALL_BASE + 321)
461
+#define __NR_openat (__NR_SYSCALL_BASE + 322)
462
+#define __NR_mkdirat (__NR_SYSCALL_BASE + 323)
463
+#define __NR_mknodat (__NR_SYSCALL_BASE + 324)
464
+#define __NR_fchownat (__NR_SYSCALL_BASE + 325)
465
+#define __NR_futimesat (__NR_SYSCALL_BASE + 326)
466
+#define __NR_fstatat64 (__NR_SYSCALL_BASE + 327)
467
+#define __NR_unlinkat (__NR_SYSCALL_BASE + 328)
468
+#define __NR_renameat (__NR_SYSCALL_BASE + 329)
469
+#define __NR_linkat (__NR_SYSCALL_BASE + 330)
470
+#define __NR_symlinkat (__NR_SYSCALL_BASE + 331)
471
+#define __NR_readlinkat (__NR_SYSCALL_BASE + 332)
472
+#define __NR_fchmodat (__NR_SYSCALL_BASE + 333)
473
+#define __NR_faccessat (__NR_SYSCALL_BASE + 334)
474
+#define __NR_pselect6 (__NR_SYSCALL_BASE + 335)
475
+#define __NR_ppoll (__NR_SYSCALL_BASE + 336)
476
+#define __NR_unshare (__NR_SYSCALL_BASE + 337)
477
+#define __NR_set_robust_list (__NR_SYSCALL_BASE + 338)
478
+#define __NR_get_robust_list (__NR_SYSCALL_BASE + 339)
479
+#define __NR_splice (__NR_SYSCALL_BASE + 340)
480
+#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE + 341)
481
+#define __NR_tee (__NR_SYSCALL_BASE + 342)
482
+#define __NR_vmsplice (__NR_SYSCALL_BASE + 343)
483
+#define __NR_move_pages (__NR_SYSCALL_BASE + 344)
484
+#define __NR_getcpu (__NR_SYSCALL_BASE + 345)
485
+#define __NR_epoll_pwait (__NR_SYSCALL_BASE + 346)
486
+#define __NR_kexec_load (__NR_SYSCALL_BASE + 347)
487
+#define __NR_utimensat (__NR_SYSCALL_BASE + 348)
488
+#define __NR_signalfd (__NR_SYSCALL_BASE + 349)
489
+#define __NR_timerfd_create (__NR_SYSCALL_BASE + 350)
490
+#define __NR_eventfd (__NR_SYSCALL_BASE + 351)
491
+#define __NR_fallocate (__NR_SYSCALL_BASE + 352)
492
+#define __NR_timerfd_settime (__NR_SYSCALL_BASE + 353)
493
+#define __NR_timerfd_gettime (__NR_SYSCALL_BASE + 354)
494
+#define __NR_signalfd4 (__NR_SYSCALL_BASE + 355)
495
+#define __NR_eventfd2 (__NR_SYSCALL_BASE + 356)
496
+#define __NR_epoll_create1 (__NR_SYSCALL_BASE + 357)
497
+#define __NR_dup3 (__NR_SYSCALL_BASE + 358)
498
+#define __NR_pipe2 (__NR_SYSCALL_BASE + 359)
499
+#define __NR_inotify_init1 (__NR_SYSCALL_BASE + 360)
500
+#define __NR_preadv (__NR_SYSCALL_BASE + 361)
501
+#define __NR_pwritev (__NR_SYSCALL_BASE + 362)
502
+#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE + 363)
503
+#define __NR_perf_event_open (__NR_SYSCALL_BASE + 364)
504
+#define __NR_recvmmsg (__NR_SYSCALL_BASE + 365)
505
+#define __NR_accept4 (__NR_SYSCALL_BASE + 366)
506
+#define __NR_fanotify_init (__NR_SYSCALL_BASE + 367)
507
+#define __NR_fanotify_mark (__NR_SYSCALL_BASE + 368)
508
+#define __NR_prlimit64 (__NR_SYSCALL_BASE + 369)
509
+#define __NR_name_to_handle_at (__NR_SYSCALL_BASE + 370)
510
+#define __NR_open_by_handle_at (__NR_SYSCALL_BASE + 371)
511
+#define __NR_clock_adjtime (__NR_SYSCALL_BASE + 372)
512
+#define __NR_syncfs (__NR_SYSCALL_BASE + 373)
513
+#define __NR_sendmmsg (__NR_SYSCALL_BASE + 374)
514
+#define __NR_setns (__NR_SYSCALL_BASE + 375)
515
+#define __NR_process_vm_readv (__NR_SYSCALL_BASE + 376)
516
+#define __NR_process_vm_writev (__NR_SYSCALL_BASE + 377)
517
+#define __NR_kcmp (__NR_SYSCALL_BASE + 378)
518
+#define __NR_finit_module (__NR_SYSCALL_BASE + 379)
519
+#define __NR_sched_setattr (__NR_SYSCALL_BASE + 380)
520
+#define __NR_sched_getattr (__NR_SYSCALL_BASE + 381)
521
+#define __NR_renameat2 (__NR_SYSCALL_BASE + 382)
522
+#define __NR_seccomp (__NR_SYSCALL_BASE + 383)
523
+#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
524
+#define __NR_memfd_create (__NR_SYSCALL_BASE + 385)
525
+#define __NR_bpf (__NR_SYSCALL_BASE + 386)
526
+#define __NR_execveat (__NR_SYSCALL_BASE + 387)
527
+#define __NR_userfaultfd (__NR_SYSCALL_BASE + 388)
528
+#define __NR_membarrier (__NR_SYSCALL_BASE + 389)
529
+#define __NR_mlock2 (__NR_SYSCALL_BASE + 390)
530
+#define __NR_copy_file_range (__NR_SYSCALL_BASE + 391)
531
+#define __NR_preadv2 (__NR_SYSCALL_BASE + 392)
532
+#define __NR_pwritev2 (__NR_SYSCALL_BASE + 393)
533
+#define __NR_pkey_mprotect (__NR_SYSCALL_BASE + 394)
534
+#define __NR_pkey_alloc (__NR_SYSCALL_BASE + 395)
535
+#define __NR_pkey_free (__NR_SYSCALL_BASE + 396)
536
+
537
+#endif /* _ASM_ARM_UNISTD_COMMON_H */
538
diff --git a/linux-headers/asm-arm/unistd-eabi.h b/linux-headers/asm-arm/unistd-eabi.h
539
new file mode 100644
540
index XXXXXXX..XXXXXXX
541
--- /dev/null
542
+++ b/linux-headers/asm-arm/unistd-eabi.h
543
@@ -XXX,XX +XXX,XX @@
544
+#ifndef _ASM_ARM_UNISTD_EABI_H
545
+#define _ASM_ARM_UNISTD_EABI_H 1
546
+
547
+
548
+#endif /* _ASM_ARM_UNISTD_EABI_H */
549
diff --git a/linux-headers/asm-arm/unistd-oabi.h b/linux-headers/asm-arm/unistd-oabi.h
550
new file mode 100644
551
index XXXXXXX..XXXXXXX
552
--- /dev/null
553
+++ b/linux-headers/asm-arm/unistd-oabi.h
554
@@ -XXX,XX +XXX,XX @@
555
+#ifndef _ASM_ARM_UNISTD_OABI_H
556
+#define _ASM_ARM_UNISTD_OABI_H 1
557
+
558
+#define __NR_time (__NR_SYSCALL_BASE + 13)
559
+#define __NR_umount (__NR_SYSCALL_BASE + 22)
560
+#define __NR_stime (__NR_SYSCALL_BASE + 25)
561
+#define __NR_alarm (__NR_SYSCALL_BASE + 27)
562
+#define __NR_utime (__NR_SYSCALL_BASE + 30)
563
+#define __NR_getrlimit (__NR_SYSCALL_BASE + 76)
564
+#define __NR_select (__NR_SYSCALL_BASE + 82)
565
+#define __NR_readdir (__NR_SYSCALL_BASE + 89)
566
+#define __NR_mmap (__NR_SYSCALL_BASE + 90)
567
+#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
568
+#define __NR_syscall (__NR_SYSCALL_BASE + 113)
569
+#define __NR_ipc (__NR_SYSCALL_BASE + 117)
570
+
571
+#endif /* _ASM_ARM_UNISTD_OABI_H */
572
diff --git a/linux-headers/asm-arm/unistd.h b/linux-headers/asm-arm/unistd.h
573
index XXXXXXX..XXXXXXX 100644
574
--- a/linux-headers/asm-arm/unistd.h
575
+++ b/linux-headers/asm-arm/unistd.h
576
@@ -XXX,XX +XXX,XX @@
577
578
#if defined(__thumb__) || defined(__ARM_EABI__)
579
#define __NR_SYSCALL_BASE    0
580
+#include <asm/unistd-eabi.h>
581
#else
582
#define __NR_SYSCALL_BASE    __NR_OABI_SYSCALL_BASE
583
+#include <asm/unistd-oabi.h>
584
#endif
585
586
-/*
587
- * This file contains the system call numbers.
588
- */
589
-
590
-#define __NR_restart_syscall        (__NR_SYSCALL_BASE+ 0)
591
-#define __NR_exit            (__NR_SYSCALL_BASE+ 1)
592
-#define __NR_fork            (__NR_SYSCALL_BASE+ 2)
593
-#define __NR_read            (__NR_SYSCALL_BASE+ 3)
594
-#define __NR_write            (__NR_SYSCALL_BASE+ 4)
595
-#define __NR_open            (__NR_SYSCALL_BASE+ 5)
596
-#define __NR_close            (__NR_SYSCALL_BASE+ 6)
597
-                    /* 7 was sys_waitpid */
598
-#define __NR_creat            (__NR_SYSCALL_BASE+ 8)
599
-#define __NR_link            (__NR_SYSCALL_BASE+ 9)
600
-#define __NR_unlink            (__NR_SYSCALL_BASE+ 10)
601
-#define __NR_execve            (__NR_SYSCALL_BASE+ 11)
602
-#define __NR_chdir            (__NR_SYSCALL_BASE+ 12)
603
-#define __NR_time            (__NR_SYSCALL_BASE+ 13)
604
-#define __NR_mknod            (__NR_SYSCALL_BASE+ 14)
605
-#define __NR_chmod            (__NR_SYSCALL_BASE+ 15)
606
-#define __NR_lchown            (__NR_SYSCALL_BASE+ 16)
607
-                    /* 17 was sys_break */
608
-                    /* 18 was sys_stat */
609
-#define __NR_lseek            (__NR_SYSCALL_BASE+ 19)
610
-#define __NR_getpid            (__NR_SYSCALL_BASE+ 20)
611
-#define __NR_mount            (__NR_SYSCALL_BASE+ 21)
612
-#define __NR_umount            (__NR_SYSCALL_BASE+ 22)
613
-#define __NR_setuid            (__NR_SYSCALL_BASE+ 23)
614
-#define __NR_getuid            (__NR_SYSCALL_BASE+ 24)
615
-#define __NR_stime            (__NR_SYSCALL_BASE+ 25)
616
-#define __NR_ptrace            (__NR_SYSCALL_BASE+ 26)
617
-#define __NR_alarm            (__NR_SYSCALL_BASE+ 27)
618
-                    /* 28 was sys_fstat */
619
-#define __NR_pause            (__NR_SYSCALL_BASE+ 29)
620
-#define __NR_utime            (__NR_SYSCALL_BASE+ 30)
621
-                    /* 31 was sys_stty */
622
-                    /* 32 was sys_gtty */
623
-#define __NR_access            (__NR_SYSCALL_BASE+ 33)
624
-#define __NR_nice            (__NR_SYSCALL_BASE+ 34)
625
-                    /* 35 was sys_ftime */
626
-#define __NR_sync            (__NR_SYSCALL_BASE+ 36)
627
-#define __NR_kill            (__NR_SYSCALL_BASE+ 37)
628
-#define __NR_rename            (__NR_SYSCALL_BASE+ 38)
629
-#define __NR_mkdir            (__NR_SYSCALL_BASE+ 39)
630
-#define __NR_rmdir            (__NR_SYSCALL_BASE+ 40)
631
-#define __NR_dup            (__NR_SYSCALL_BASE+ 41)
632
-#define __NR_pipe            (__NR_SYSCALL_BASE+ 42)
633
-#define __NR_times            (__NR_SYSCALL_BASE+ 43)
634
-                    /* 44 was sys_prof */
635
-#define __NR_brk            (__NR_SYSCALL_BASE+ 45)
636
-#define __NR_setgid            (__NR_SYSCALL_BASE+ 46)
637
-#define __NR_getgid            (__NR_SYSCALL_BASE+ 47)
638
-                    /* 48 was sys_signal */
639
-#define __NR_geteuid            (__NR_SYSCALL_BASE+ 49)
640
-#define __NR_getegid            (__NR_SYSCALL_BASE+ 50)
641
-#define __NR_acct            (__NR_SYSCALL_BASE+ 51)
642
-#define __NR_umount2            (__NR_SYSCALL_BASE+ 52)
643
-                    /* 53 was sys_lock */
644
-#define __NR_ioctl            (__NR_SYSCALL_BASE+ 54)
645
-#define __NR_fcntl            (__NR_SYSCALL_BASE+ 55)
646
-                    /* 56 was sys_mpx */
647
-#define __NR_setpgid            (__NR_SYSCALL_BASE+ 57)
648
-                    /* 58 was sys_ulimit */
649
-                    /* 59 was sys_olduname */
650
-#define __NR_umask            (__NR_SYSCALL_BASE+ 60)
651
-#define __NR_chroot            (__NR_SYSCALL_BASE+ 61)
652
-#define __NR_ustat            (__NR_SYSCALL_BASE+ 62)
653
-#define __NR_dup2            (__NR_SYSCALL_BASE+ 63)
654
-#define __NR_getppid            (__NR_SYSCALL_BASE+ 64)
655
-#define __NR_getpgrp            (__NR_SYSCALL_BASE+ 65)
656
-#define __NR_setsid            (__NR_SYSCALL_BASE+ 66)
657
-#define __NR_sigaction            (__NR_SYSCALL_BASE+ 67)
658
-                    /* 68 was sys_sgetmask */
659
-                    /* 69 was sys_ssetmask */
660
-#define __NR_setreuid            (__NR_SYSCALL_BASE+ 70)
661
-#define __NR_setregid            (__NR_SYSCALL_BASE+ 71)
662
-#define __NR_sigsuspend            (__NR_SYSCALL_BASE+ 72)
663
-#define __NR_sigpending            (__NR_SYSCALL_BASE+ 73)
664
-#define __NR_sethostname        (__NR_SYSCALL_BASE+ 74)
665
-#define __NR_setrlimit            (__NR_SYSCALL_BASE+ 75)
666
-#define __NR_getrlimit            (__NR_SYSCALL_BASE+ 76)    /* Back compat 2GB limited rlimit */
667
-#define __NR_getrusage            (__NR_SYSCALL_BASE+ 77)
668
-#define __NR_gettimeofday        (__NR_SYSCALL_BASE+ 78)
669
-#define __NR_settimeofday        (__NR_SYSCALL_BASE+ 79)
670
-#define __NR_getgroups            (__NR_SYSCALL_BASE+ 80)
671
-#define __NR_setgroups            (__NR_SYSCALL_BASE+ 81)
672
-#define __NR_select            (__NR_SYSCALL_BASE+ 82)
673
-#define __NR_symlink            (__NR_SYSCALL_BASE+ 83)
674
-                    /* 84 was sys_lstat */
675
-#define __NR_readlink            (__NR_SYSCALL_BASE+ 85)
676
-#define __NR_uselib            (__NR_SYSCALL_BASE+ 86)
677
-#define __NR_swapon            (__NR_SYSCALL_BASE+ 87)
678
-#define __NR_reboot            (__NR_SYSCALL_BASE+ 88)
679
-#define __NR_readdir            (__NR_SYSCALL_BASE+ 89)
680
-#define __NR_mmap            (__NR_SYSCALL_BASE+ 90)
681
-#define __NR_munmap            (__NR_SYSCALL_BASE+ 91)
682
-#define __NR_truncate            (__NR_SYSCALL_BASE+ 92)
683
-#define __NR_ftruncate            (__NR_SYSCALL_BASE+ 93)
684
-#define __NR_fchmod            (__NR_SYSCALL_BASE+ 94)
685
-#define __NR_fchown            (__NR_SYSCALL_BASE+ 95)
686
-#define __NR_getpriority        (__NR_SYSCALL_BASE+ 96)
687
-#define __NR_setpriority        (__NR_SYSCALL_BASE+ 97)
688
-                    /* 98 was sys_profil */
689
-#define __NR_statfs            (__NR_SYSCALL_BASE+ 99)
690
-#define __NR_fstatfs            (__NR_SYSCALL_BASE+100)
691
-                    /* 101 was sys_ioperm */
692
-#define __NR_socketcall            (__NR_SYSCALL_BASE+102)
693
-#define __NR_syslog            (__NR_SYSCALL_BASE+103)
694
-#define __NR_setitimer            (__NR_SYSCALL_BASE+104)
695
-#define __NR_getitimer            (__NR_SYSCALL_BASE+105)
696
-#define __NR_stat            (__NR_SYSCALL_BASE+106)
697
-#define __NR_lstat            (__NR_SYSCALL_BASE+107)
698
-#define __NR_fstat            (__NR_SYSCALL_BASE+108)
699
-                    /* 109 was sys_uname */
700
-                    /* 110 was sys_iopl */
701
-#define __NR_vhangup            (__NR_SYSCALL_BASE+111)
702
-                    /* 112 was sys_idle */
703
-#define __NR_syscall            (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
704
-#define __NR_wait4            (__NR_SYSCALL_BASE+114)
705
-#define __NR_swapoff            (__NR_SYSCALL_BASE+115)
706
-#define __NR_sysinfo            (__NR_SYSCALL_BASE+116)
707
-#define __NR_ipc            (__NR_SYSCALL_BASE+117)
708
-#define __NR_fsync            (__NR_SYSCALL_BASE+118)
709
-#define __NR_sigreturn            (__NR_SYSCALL_BASE+119)
710
-#define __NR_clone            (__NR_SYSCALL_BASE+120)
711
-#define __NR_setdomainname        (__NR_SYSCALL_BASE+121)
712
-#define __NR_uname            (__NR_SYSCALL_BASE+122)
713
-                    /* 123 was sys_modify_ldt */
714
-#define __NR_adjtimex            (__NR_SYSCALL_BASE+124)
715
-#define __NR_mprotect            (__NR_SYSCALL_BASE+125)
716
-#define __NR_sigprocmask        (__NR_SYSCALL_BASE+126)
717
-                    /* 127 was sys_create_module */
718
-#define __NR_init_module        (__NR_SYSCALL_BASE+128)
719
-#define __NR_delete_module        (__NR_SYSCALL_BASE+129)
720
-                    /* 130 was sys_get_kernel_syms */
721
-#define __NR_quotactl            (__NR_SYSCALL_BASE+131)
722
-#define __NR_getpgid            (__NR_SYSCALL_BASE+132)
723
-#define __NR_fchdir            (__NR_SYSCALL_BASE+133)
724
-#define __NR_bdflush            (__NR_SYSCALL_BASE+134)
725
-#define __NR_sysfs            (__NR_SYSCALL_BASE+135)
726
-#define __NR_personality        (__NR_SYSCALL_BASE+136)
727
-                    /* 137 was sys_afs_syscall */
728
-#define __NR_setfsuid            (__NR_SYSCALL_BASE+138)
729
-#define __NR_setfsgid            (__NR_SYSCALL_BASE+139)
730
-#define __NR__llseek            (__NR_SYSCALL_BASE+140)
731
-#define __NR_getdents            (__NR_SYSCALL_BASE+141)
732
-#define __NR__newselect            (__NR_SYSCALL_BASE+142)
733
-#define __NR_flock            (__NR_SYSCALL_BASE+143)
734
-#define __NR_msync            (__NR_SYSCALL_BASE+144)
735
-#define __NR_readv            (__NR_SYSCALL_BASE+145)
736
-#define __NR_writev            (__NR_SYSCALL_BASE+146)
737
-#define __NR_getsid            (__NR_SYSCALL_BASE+147)
738
-#define __NR_fdatasync            (__NR_SYSCALL_BASE+148)
739
-#define __NR__sysctl            (__NR_SYSCALL_BASE+149)
740
-#define __NR_mlock            (__NR_SYSCALL_BASE+150)
741
-#define __NR_munlock            (__NR_SYSCALL_BASE+151)
742
-#define __NR_mlockall            (__NR_SYSCALL_BASE+152)
743
-#define __NR_munlockall            (__NR_SYSCALL_BASE+153)
744
-#define __NR_sched_setparam        (__NR_SYSCALL_BASE+154)
745
-#define __NR_sched_getparam        (__NR_SYSCALL_BASE+155)
746
-#define __NR_sched_setscheduler        (__NR_SYSCALL_BASE+156)
747
-#define __NR_sched_getscheduler        (__NR_SYSCALL_BASE+157)
748
-#define __NR_sched_yield        (__NR_SYSCALL_BASE+158)
749
-#define __NR_sched_get_priority_max    (__NR_SYSCALL_BASE+159)
750
-#define __NR_sched_get_priority_min    (__NR_SYSCALL_BASE+160)
751
-#define __NR_sched_rr_get_interval    (__NR_SYSCALL_BASE+161)
752
-#define __NR_nanosleep            (__NR_SYSCALL_BASE+162)
753
-#define __NR_mremap            (__NR_SYSCALL_BASE+163)
754
-#define __NR_setresuid            (__NR_SYSCALL_BASE+164)
755
-#define __NR_getresuid            (__NR_SYSCALL_BASE+165)
756
-                    /* 166 was sys_vm86 */
757
-                    /* 167 was sys_query_module */
758
-#define __NR_poll            (__NR_SYSCALL_BASE+168)
759
-#define __NR_nfsservctl            (__NR_SYSCALL_BASE+169)
760
-#define __NR_setresgid            (__NR_SYSCALL_BASE+170)
761
-#define __NR_getresgid            (__NR_SYSCALL_BASE+171)
762
-#define __NR_prctl            (__NR_SYSCALL_BASE+172)
763
-#define __NR_rt_sigreturn        (__NR_SYSCALL_BASE+173)
764
-#define __NR_rt_sigaction        (__NR_SYSCALL_BASE+174)
765
-#define __NR_rt_sigprocmask        (__NR_SYSCALL_BASE+175)
766
-#define __NR_rt_sigpending        (__NR_SYSCALL_BASE+176)
767
-#define __NR_rt_sigtimedwait        (__NR_SYSCALL_BASE+177)
768
-#define __NR_rt_sigqueueinfo        (__NR_SYSCALL_BASE+178)
769
-#define __NR_rt_sigsuspend        (__NR_SYSCALL_BASE+179)
770
-#define __NR_pread64            (__NR_SYSCALL_BASE+180)
771
-#define __NR_pwrite64            (__NR_SYSCALL_BASE+181)
772
-#define __NR_chown            (__NR_SYSCALL_BASE+182)
773
-#define __NR_getcwd            (__NR_SYSCALL_BASE+183)
774
-#define __NR_capget            (__NR_SYSCALL_BASE+184)
775
-#define __NR_capset            (__NR_SYSCALL_BASE+185)
776
-#define __NR_sigaltstack        (__NR_SYSCALL_BASE+186)
777
-#define __NR_sendfile            (__NR_SYSCALL_BASE+187)
778
-                    /* 188 reserved */
779
-                    /* 189 reserved */
780
-#define __NR_vfork            (__NR_SYSCALL_BASE+190)
781
-#define __NR_ugetrlimit            (__NR_SYSCALL_BASE+191)    /* SuS compliant getrlimit */
782
-#define __NR_mmap2            (__NR_SYSCALL_BASE+192)
783
-#define __NR_truncate64            (__NR_SYSCALL_BASE+193)
784
-#define __NR_ftruncate64        (__NR_SYSCALL_BASE+194)
785
-#define __NR_stat64            (__NR_SYSCALL_BASE+195)
786
-#define __NR_lstat64            (__NR_SYSCALL_BASE+196)
787
-#define __NR_fstat64            (__NR_SYSCALL_BASE+197)
788
-#define __NR_lchown32            (__NR_SYSCALL_BASE+198)
789
-#define __NR_getuid32            (__NR_SYSCALL_BASE+199)
790
-#define __NR_getgid32            (__NR_SYSCALL_BASE+200)
791
-#define __NR_geteuid32            (__NR_SYSCALL_BASE+201)
792
-#define __NR_getegid32            (__NR_SYSCALL_BASE+202)
793
-#define __NR_setreuid32            (__NR_SYSCALL_BASE+203)
794
-#define __NR_setregid32            (__NR_SYSCALL_BASE+204)
795
-#define __NR_getgroups32        (__NR_SYSCALL_BASE+205)
796
-#define __NR_setgroups32        (__NR_SYSCALL_BASE+206)
797
-#define __NR_fchown32            (__NR_SYSCALL_BASE+207)
798
-#define __NR_setresuid32        (__NR_SYSCALL_BASE+208)
799
-#define __NR_getresuid32        (__NR_SYSCALL_BASE+209)
800
-#define __NR_setresgid32        (__NR_SYSCALL_BASE+210)
801
-#define __NR_getresgid32        (__NR_SYSCALL_BASE+211)
802
-#define __NR_chown32            (__NR_SYSCALL_BASE+212)
803
-#define __NR_setuid32            (__NR_SYSCALL_BASE+213)
804
-#define __NR_setgid32            (__NR_SYSCALL_BASE+214)
805
-#define __NR_setfsuid32            (__NR_SYSCALL_BASE+215)
806
-#define __NR_setfsgid32            (__NR_SYSCALL_BASE+216)
807
-#define __NR_getdents64            (__NR_SYSCALL_BASE+217)
808
-#define __NR_pivot_root            (__NR_SYSCALL_BASE+218)
809
-#define __NR_mincore            (__NR_SYSCALL_BASE+219)
810
-#define __NR_madvise            (__NR_SYSCALL_BASE+220)
811
-#define __NR_fcntl64            (__NR_SYSCALL_BASE+221)
812
-                    /* 222 for tux */
813
-                    /* 223 is unused */
814
-#define __NR_gettid            (__NR_SYSCALL_BASE+224)
815
-#define __NR_readahead            (__NR_SYSCALL_BASE+225)
816
-#define __NR_setxattr            (__NR_SYSCALL_BASE+226)
817
-#define __NR_lsetxattr            (__NR_SYSCALL_BASE+227)
818
-#define __NR_fsetxattr            (__NR_SYSCALL_BASE+228)
819
-#define __NR_getxattr            (__NR_SYSCALL_BASE+229)
820
-#define __NR_lgetxattr            (__NR_SYSCALL_BASE+230)
821
-#define __NR_fgetxattr            (__NR_SYSCALL_BASE+231)
822
-#define __NR_listxattr            (__NR_SYSCALL_BASE+232)
823
-#define __NR_llistxattr            (__NR_SYSCALL_BASE+233)
824
-#define __NR_flistxattr            (__NR_SYSCALL_BASE+234)
825
-#define __NR_removexattr        (__NR_SYSCALL_BASE+235)
826
-#define __NR_lremovexattr        (__NR_SYSCALL_BASE+236)
827
-#define __NR_fremovexattr        (__NR_SYSCALL_BASE+237)
828
-#define __NR_tkill            (__NR_SYSCALL_BASE+238)
829
-#define __NR_sendfile64            (__NR_SYSCALL_BASE+239)
830
-#define __NR_futex            (__NR_SYSCALL_BASE+240)
831
-#define __NR_sched_setaffinity        (__NR_SYSCALL_BASE+241)
832
-#define __NR_sched_getaffinity        (__NR_SYSCALL_BASE+242)
833
-#define __NR_io_setup            (__NR_SYSCALL_BASE+243)
834
-#define __NR_io_destroy            (__NR_SYSCALL_BASE+244)
835
-#define __NR_io_getevents        (__NR_SYSCALL_BASE+245)
836
-#define __NR_io_submit            (__NR_SYSCALL_BASE+246)
837
-#define __NR_io_cancel            (__NR_SYSCALL_BASE+247)
838
-#define __NR_exit_group            (__NR_SYSCALL_BASE+248)
839
-#define __NR_lookup_dcookie        (__NR_SYSCALL_BASE+249)
840
-#define __NR_epoll_create        (__NR_SYSCALL_BASE+250)
841
-#define __NR_epoll_ctl            (__NR_SYSCALL_BASE+251)
842
-#define __NR_epoll_wait            (__NR_SYSCALL_BASE+252)
843
-#define __NR_remap_file_pages        (__NR_SYSCALL_BASE+253)
844
-                    /* 254 for set_thread_area */
845
-                    /* 255 for get_thread_area */
846
-#define __NR_set_tid_address        (__NR_SYSCALL_BASE+256)
847
-#define __NR_timer_create        (__NR_SYSCALL_BASE+257)
848
-#define __NR_timer_settime        (__NR_SYSCALL_BASE+258)
849
-#define __NR_timer_gettime        (__NR_SYSCALL_BASE+259)
850
-#define __NR_timer_getoverrun        (__NR_SYSCALL_BASE+260)
851
-#define __NR_timer_delete        (__NR_SYSCALL_BASE+261)
852
-#define __NR_clock_settime        (__NR_SYSCALL_BASE+262)
853
-#define __NR_clock_gettime        (__NR_SYSCALL_BASE+263)
854
-#define __NR_clock_getres        (__NR_SYSCALL_BASE+264)
855
-#define __NR_clock_nanosleep        (__NR_SYSCALL_BASE+265)
856
-#define __NR_statfs64            (__NR_SYSCALL_BASE+266)
857
-#define __NR_fstatfs64            (__NR_SYSCALL_BASE+267)
858
-#define __NR_tgkill            (__NR_SYSCALL_BASE+268)
859
-#define __NR_utimes            (__NR_SYSCALL_BASE+269)
860
-#define __NR_arm_fadvise64_64        (__NR_SYSCALL_BASE+270)
861
-#define __NR_pciconfig_iobase        (__NR_SYSCALL_BASE+271)
862
-#define __NR_pciconfig_read        (__NR_SYSCALL_BASE+272)
863
-#define __NR_pciconfig_write        (__NR_SYSCALL_BASE+273)
864
-#define __NR_mq_open            (__NR_SYSCALL_BASE+274)
865
-#define __NR_mq_unlink            (__NR_SYSCALL_BASE+275)
866
-#define __NR_mq_timedsend        (__NR_SYSCALL_BASE+276)
867
-#define __NR_mq_timedreceive        (__NR_SYSCALL_BASE+277)
868
-#define __NR_mq_notify            (__NR_SYSCALL_BASE+278)
869
-#define __NR_mq_getsetattr        (__NR_SYSCALL_BASE+279)
870
-#define __NR_waitid            (__NR_SYSCALL_BASE+280)
871
-#define __NR_socket            (__NR_SYSCALL_BASE+281)
872
-#define __NR_bind            (__NR_SYSCALL_BASE+282)
873
-#define __NR_connect            (__NR_SYSCALL_BASE+283)
874
-#define __NR_listen            (__NR_SYSCALL_BASE+284)
875
-#define __NR_accept            (__NR_SYSCALL_BASE+285)
876
-#define __NR_getsockname        (__NR_SYSCALL_BASE+286)
877
-#define __NR_getpeername        (__NR_SYSCALL_BASE+287)
878
-#define __NR_socketpair            (__NR_SYSCALL_BASE+288)
879
-#define __NR_send            (__NR_SYSCALL_BASE+289)
880
-#define __NR_sendto            (__NR_SYSCALL_BASE+290)
881
-#define __NR_recv            (__NR_SYSCALL_BASE+291)
882
-#define __NR_recvfrom            (__NR_SYSCALL_BASE+292)
883
-#define __NR_shutdown            (__NR_SYSCALL_BASE+293)
884
-#define __NR_setsockopt            (__NR_SYSCALL_BASE+294)
885
-#define __NR_getsockopt            (__NR_SYSCALL_BASE+295)
886
-#define __NR_sendmsg            (__NR_SYSCALL_BASE+296)
887
-#define __NR_recvmsg            (__NR_SYSCALL_BASE+297)
888
-#define __NR_semop            (__NR_SYSCALL_BASE+298)
889
-#define __NR_semget            (__NR_SYSCALL_BASE+299)
890
-#define __NR_semctl            (__NR_SYSCALL_BASE+300)
891
-#define __NR_msgsnd            (__NR_SYSCALL_BASE+301)
892
-#define __NR_msgrcv            (__NR_SYSCALL_BASE+302)
893
-#define __NR_msgget            (__NR_SYSCALL_BASE+303)
894
-#define __NR_msgctl            (__NR_SYSCALL_BASE+304)
895
-#define __NR_shmat            (__NR_SYSCALL_BASE+305)
896
-#define __NR_shmdt            (__NR_SYSCALL_BASE+306)
897
-#define __NR_shmget            (__NR_SYSCALL_BASE+307)
898
-#define __NR_shmctl            (__NR_SYSCALL_BASE+308)
899
-#define __NR_add_key            (__NR_SYSCALL_BASE+309)
900
-#define __NR_request_key        (__NR_SYSCALL_BASE+310)
901
-#define __NR_keyctl            (__NR_SYSCALL_BASE+311)
902
-#define __NR_semtimedop            (__NR_SYSCALL_BASE+312)
903
-#define __NR_vserver            (__NR_SYSCALL_BASE+313)
904
-#define __NR_ioprio_set            (__NR_SYSCALL_BASE+314)
905
-#define __NR_ioprio_get            (__NR_SYSCALL_BASE+315)
906
-#define __NR_inotify_init        (__NR_SYSCALL_BASE+316)
907
-#define __NR_inotify_add_watch        (__NR_SYSCALL_BASE+317)
908
-#define __NR_inotify_rm_watch        (__NR_SYSCALL_BASE+318)
909
-#define __NR_mbind            (__NR_SYSCALL_BASE+319)
910
-#define __NR_get_mempolicy        (__NR_SYSCALL_BASE+320)
911
-#define __NR_set_mempolicy        (__NR_SYSCALL_BASE+321)
912
-#define __NR_openat            (__NR_SYSCALL_BASE+322)
913
-#define __NR_mkdirat            (__NR_SYSCALL_BASE+323)
914
-#define __NR_mknodat            (__NR_SYSCALL_BASE+324)
915
-#define __NR_fchownat            (__NR_SYSCALL_BASE+325)
916
-#define __NR_futimesat            (__NR_SYSCALL_BASE+326)
917
-#define __NR_fstatat64            (__NR_SYSCALL_BASE+327)
918
-#define __NR_unlinkat            (__NR_SYSCALL_BASE+328)
919
-#define __NR_renameat            (__NR_SYSCALL_BASE+329)
920
-#define __NR_linkat            (__NR_SYSCALL_BASE+330)
921
-#define __NR_symlinkat            (__NR_SYSCALL_BASE+331)
922
-#define __NR_readlinkat            (__NR_SYSCALL_BASE+332)
923
-#define __NR_fchmodat            (__NR_SYSCALL_BASE+333)
924
-#define __NR_faccessat            (__NR_SYSCALL_BASE+334)
925
-#define __NR_pselect6            (__NR_SYSCALL_BASE+335)
926
-#define __NR_ppoll            (__NR_SYSCALL_BASE+336)
927
-#define __NR_unshare            (__NR_SYSCALL_BASE+337)
928
-#define __NR_set_robust_list        (__NR_SYSCALL_BASE+338)
929
-#define __NR_get_robust_list        (__NR_SYSCALL_BASE+339)
930
-#define __NR_splice            (__NR_SYSCALL_BASE+340)
931
-#define __NR_arm_sync_file_range    (__NR_SYSCALL_BASE+341)
932
+#include <asm/unistd-common.h>
933
#define __NR_sync_file_range2        __NR_arm_sync_file_range
934
-#define __NR_tee            (__NR_SYSCALL_BASE+342)
935
-#define __NR_vmsplice            (__NR_SYSCALL_BASE+343)
936
-#define __NR_move_pages            (__NR_SYSCALL_BASE+344)
937
-#define __NR_getcpu            (__NR_SYSCALL_BASE+345)
938
-#define __NR_epoll_pwait        (__NR_SYSCALL_BASE+346)
939
-#define __NR_kexec_load            (__NR_SYSCALL_BASE+347)
940
-#define __NR_utimensat            (__NR_SYSCALL_BASE+348)
941
-#define __NR_signalfd            (__NR_SYSCALL_BASE+349)
942
-#define __NR_timerfd_create        (__NR_SYSCALL_BASE+350)
943
-#define __NR_eventfd            (__NR_SYSCALL_BASE+351)
944
-#define __NR_fallocate            (__NR_SYSCALL_BASE+352)
945
-#define __NR_timerfd_settime        (__NR_SYSCALL_BASE+353)
946
-#define __NR_timerfd_gettime        (__NR_SYSCALL_BASE+354)
947
-#define __NR_signalfd4            (__NR_SYSCALL_BASE+355)
948
-#define __NR_eventfd2            (__NR_SYSCALL_BASE+356)
949
-#define __NR_epoll_create1        (__NR_SYSCALL_BASE+357)
950
-#define __NR_dup3            (__NR_SYSCALL_BASE+358)
951
-#define __NR_pipe2            (__NR_SYSCALL_BASE+359)
952
-#define __NR_inotify_init1        (__NR_SYSCALL_BASE+360)
953
-#define __NR_preadv            (__NR_SYSCALL_BASE+361)
954
-#define __NR_pwritev            (__NR_SYSCALL_BASE+362)
955
-#define __NR_rt_tgsigqueueinfo        (__NR_SYSCALL_BASE+363)
956
-#define __NR_perf_event_open        (__NR_SYSCALL_BASE+364)
957
-#define __NR_recvmmsg            (__NR_SYSCALL_BASE+365)
958
-#define __NR_accept4            (__NR_SYSCALL_BASE+366)
959
-#define __NR_fanotify_init        (__NR_SYSCALL_BASE+367)
960
-#define __NR_fanotify_mark        (__NR_SYSCALL_BASE+368)
961
-#define __NR_prlimit64            (__NR_SYSCALL_BASE+369)
962
-#define __NR_name_to_handle_at        (__NR_SYSCALL_BASE+370)
963
-#define __NR_open_by_handle_at        (__NR_SYSCALL_BASE+371)
964
-#define __NR_clock_adjtime        (__NR_SYSCALL_BASE+372)
965
-#define __NR_syncfs            (__NR_SYSCALL_BASE+373)
966
-#define __NR_sendmmsg            (__NR_SYSCALL_BASE+374)
967
-#define __NR_setns            (__NR_SYSCALL_BASE+375)
968
-#define __NR_process_vm_readv        (__NR_SYSCALL_BASE+376)
969
-#define __NR_process_vm_writev        (__NR_SYSCALL_BASE+377)
970
-#define __NR_kcmp            (__NR_SYSCALL_BASE+378)
971
-#define __NR_finit_module        (__NR_SYSCALL_BASE+379)
972
-#define __NR_sched_setattr        (__NR_SYSCALL_BASE+380)
973
-#define __NR_sched_getattr        (__NR_SYSCALL_BASE+381)
974
-#define __NR_renameat2            (__NR_SYSCALL_BASE+382)
975
-#define __NR_seccomp            (__NR_SYSCALL_BASE+383)
976
-#define __NR_getrandom            (__NR_SYSCALL_BASE+384)
977
-#define __NR_memfd_create        (__NR_SYSCALL_BASE+385)
978
-#define __NR_bpf            (__NR_SYSCALL_BASE+386)
979
-#define __NR_execveat            (__NR_SYSCALL_BASE+387)
980
-#define __NR_userfaultfd        (__NR_SYSCALL_BASE+388)
981
-#define __NR_membarrier            (__NR_SYSCALL_BASE+389)
982
-#define __NR_mlock2            (__NR_SYSCALL_BASE+390)
983
-#define __NR_copy_file_range        (__NR_SYSCALL_BASE+391)
984
-#define __NR_preadv2            (__NR_SYSCALL_BASE+392)
985
-#define __NR_pwritev2            (__NR_SYSCALL_BASE+393)
986
987
/*
988
* The following SWIs are ARM private.
989
@@ -XXX,XX +XXX,XX @@
990
#define __ARM_NR_usr32            (__ARM_NR_BASE+4)
991
#define __ARM_NR_set_tls        (__ARM_NR_BASE+5)
992
993
-/*
994
- * The following syscalls are obsolete and no longer available for EABI.
995
- */
996
-#if defined(__ARM_EABI__)
997
-#undef __NR_time
998
-#undef __NR_umount
999
-#undef __NR_stime
1000
-#undef __NR_alarm
1001
-#undef __NR_utime
1002
-#undef __NR_getrlimit
1003
-#undef __NR_select
1004
-#undef __NR_readdir
1005
-#undef __NR_mmap
1006
-#undef __NR_socketcall
1007
-#undef __NR_syscall
1008
-#undef __NR_ipc
1009
-#endif
1010
-
1011
#endif /* __ASM_ARM_UNISTD_H */
1012
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
1013
index XXXXXXX..XXXXXXX 100644
1014
--- a/linux-headers/asm-arm64/kvm.h
1015
+++ b/linux-headers/asm-arm64/kvm.h
1016
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
1017
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
1018
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
1019
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
1020
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
1021
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
1022
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
1023
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
1024
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
1025
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
1026
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
1027
#define KVM_DEV_ARM_VGIC_GRP_CTRL    4
1028
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
1029
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
1030
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
1031
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
1032
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
1033
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
1034
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK    0x3ff
1035
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
1036
+
1037
#define KVM_DEV_ARM_VGIC_CTRL_INIT    0
1038
1039
/* Device Control API on vcpu fd */
1040
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
1041
index XXXXXXX..XXXXXXX 100644
1042
--- a/linux-headers/asm-powerpc/kvm.h
1043
+++ b/linux-headers/asm-powerpc/kvm.h
1044
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1045
    __u16    n_invalid;
1046
};
1047
1048
+/* For KVM_PPC_CONFIGURE_V3_MMU */
1049
+struct kvm_ppc_mmuv3_cfg {
1050
+    __u64    flags;
1051
+    __u64    process_table;    /* second doubleword of partition table entry */
1052
+};
1053
+
1054
+/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
1055
+#define KVM_PPC_MMUV3_RADIX    1    /* 1 = radix mode, 0 = HPT */
1056
+#define KVM_PPC_MMUV3_GTSE    2    /* global translation shootdown enb. */
1057
+
1058
+/* For KVM_PPC_GET_RMMU_INFO */
1059
+struct kvm_ppc_rmmu_info {
1060
+    struct kvm_ppc_radix_geom {
1061
+        __u8    page_shift;
1062
+        __u8    level_bits[4];
1063
+        __u8    pad[3];
1064
+    }    geometries[8];
1065
+    __u32    ap_encodings[8];
1066
+};
1067
+
1068
/* Per-vcpu XICS interrupt controller state */
1069
#define KVM_REG_PPC_ICP_STATE    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
1070
1071
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1072
#define KVM_REG_PPC_SPRG9    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
1073
#define KVM_REG_PPC_DBSR    (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
1074
1075
+/* POWER9 registers */
1076
+#define KVM_REG_PPC_TIDR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
1077
+#define KVM_REG_PPC_PSSCR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
1078
+
1079
/* Transactional Memory checkpointed state:
1080
* This is all GPRs, all VSX regs and a subset of SPRs
1081
*/
1082
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1083
#define KVM_REG_PPC_TM_VSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
1084
#define KVM_REG_PPC_TM_DSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
1085
#define KVM_REG_PPC_TM_TAR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
1086
+#define KVM_REG_PPC_TM_XER    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
1087
1088
/* PPC64 eXternal Interrupt Controller Specification */
1089
#define KVM_DEV_XICS_GRP_SOURCES    1    /* 64-bit source attributes */
1090
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1091
#define KVM_XICS_LEVEL_SENSITIVE    (1ULL << 40)
1092
#define KVM_XICS_MASKED        (1ULL << 41)
1093
#define KVM_XICS_PENDING        (1ULL << 42)
1094
+#define KVM_XICS_PRESENTED        (1ULL << 43)
1095
+#define KVM_XICS_QUEUED        (1ULL << 44)
1096
1097
#endif /* __LINUX_KVM_POWERPC_H */
1098
diff --git a/linux-headers/asm-powerpc/unistd.h b/linux-headers/asm-powerpc/unistd.h
1099
index XXXXXXX..XXXXXXX 100644
1100
--- a/linux-headers/asm-powerpc/unistd.h
1101
+++ b/linux-headers/asm-powerpc/unistd.h
1102
@@ -XXX,XX +XXX,XX @@
1103
#define __NR_copy_file_range    379
1104
#define __NR_preadv2        380
1105
#define __NR_pwritev2        381
1106
+#define __NR_kexec_file_load    382
1107
1108
#endif /* _ASM_POWERPC_UNISTD_H_ */
1109
diff --git a/linux-headers/asm-x86/kvm_para.h b/linux-headers/asm-x86/kvm_para.h
1110
index XXXXXXX..XXXXXXX 100644
1111
--- a/linux-headers/asm-x86/kvm_para.h
1112
+++ b/linux-headers/asm-x86/kvm_para.h
1113
@@ -XXX,XX +XXX,XX @@ struct kvm_steal_time {
1114
    __u64 steal;
1115
    __u32 version;
1116
    __u32 flags;
1117
-    __u32 pad[12];
1118
+    __u8 preempted;
1119
+    __u8 u8_pad[3];
1120
+    __u32 pad[11];
1121
+};
1122
+
1123
+#define KVM_CLOCK_PAIRING_WALLCLOCK 0
1124
+struct kvm_clock_pairing {
1125
+    __s64 sec;
1126
+    __s64 nsec;
1127
+    __u64 tsc;
1128
+    __u32 flags;
1129
+    __u32 pad[9];
1130
};
1131
1132
#define KVM_STEAL_ALIGNMENT_BITS 5
1133
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/linux-headers/linux/kvm.h
1136
+++ b/linux-headers/linux/kvm.h
1137
@@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit {
1138
struct kvm_run {
1139
    /* in */
1140
    __u8 request_interrupt_window;
1141
-    __u8 padding1[7];
1142
+    __u8 immediate_exit;
1143
+    __u8 padding1[6];
1144
1145
    /* out */
1146
    __u32 exit_reason;
1147
@@ -XXX,XX +XXX,XX @@ struct kvm_enable_cap {
1148
};
1149
1150
/* for KVM_PPC_GET_PVINFO */
1151
+
1152
+#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1153
+
1154
struct kvm_ppc_pvinfo {
1155
    /* out */
1156
    __u32 flags;
1157
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1158
    struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
1159
};
1160
1161
-#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1162
+/* for KVM_PPC_RESIZE_HPT_{PREPARE,COMMIT} */
1163
+struct kvm_ppc_resize_hpt {
1164
+    __u64 flags;
1165
+    __u32 shift;
1166
+    __u32 pad;
1167
+};
1168
1169
#define KVMIO 0xAE
1170
1171
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1172
#define KVM_CAP_S390_USER_INSTR0 130
1173
#define KVM_CAP_MSI_DEVID 131
1174
#define KVM_CAP_PPC_HTM 132
1175
+#define KVM_CAP_SPAPR_RESIZE_HPT 133
1176
+#define KVM_CAP_PPC_MMU_RADIX 134
1177
+#define KVM_CAP_PPC_MMU_HASH_V3 135
1178
+#define KVM_CAP_IMMEDIATE_EXIT 136
1179
1180
#ifdef KVM_CAP_IRQ_ROUTING
1181
1182
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
1183
#define KVM_ARM_SET_DEVICE_ADDR     _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
1184
/* Available with KVM_CAP_PPC_RTAS */
1185
#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
1186
+/* Available with KVM_CAP_SPAPR_RESIZE_HPT */
1187
+#define KVM_PPC_RESIZE_HPT_PREPARE _IOR(KVMIO, 0xad, struct kvm_ppc_resize_hpt)
1188
+#define KVM_PPC_RESIZE_HPT_COMMIT _IOR(KVMIO, 0xae, struct kvm_ppc_resize_hpt)
1189
+/* Available with KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3 */
1190
+#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
1191
+/* Available with KVM_CAP_PPC_RADIX_MMU */
1192
+#define KVM_PPC_GET_RMMU_INFO     _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
1193
1194
/* ioctl for vm fd */
1195
#define KVM_CREATE_DEVICE     _IOWR(KVMIO, 0xe0, struct kvm_create_device)
1196
diff --git a/linux-headers/linux/kvm_para.h b/linux-headers/linux/kvm_para.h
1197
index XXXXXXX..XXXXXXX 100644
1198
--- a/linux-headers/linux/kvm_para.h
1199
+++ b/linux-headers/linux/kvm_para.h
1200
@@ -XXX,XX +XXX,XX @@
1201
#define KVM_EFAULT        EFAULT
1202
#define KVM_E2BIG        E2BIG
1203
#define KVM_EPERM        EPERM
1204
+#define KVM_EOPNOTSUPP        95
1205
1206
#define KVM_HC_VAPIC_POLL_IRQ        1
1207
#define KVM_HC_MMU_OP            2
1208
@@ -XXX,XX +XXX,XX @@
1209
#define KVM_HC_MIPS_GET_CLOCK_FREQ    6
1210
#define KVM_HC_MIPS_EXIT_VM        7
1211
#define KVM_HC_MIPS_CONSOLE_OUTPUT    8
1212
+#define KVM_HC_CLOCK_PAIRING        9
1213
1214
/*
1215
* hypercalls use architecture specific
1216
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
1217
index XXXXXXX..XXXXXXX 100644
1218
--- a/linux-headers/linux/userfaultfd.h
1219
+++ b/linux-headers/linux/userfaultfd.h
1220
@@ -XXX,XX +XXX,XX @@
1221
1222
#include <linux/types.h>
1223
1224
-#define UFFD_API ((__u64)0xAA)
1225
/*
1226
- * After implementing the respective features it will become:
1227
- * #define UFFD_API_FEATURES (UFFD_FEATURE_PAGEFAULT_FLAG_WP | \
1228
- *             UFFD_FEATURE_EVENT_FORK)
1229
+ * If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and
1230
+ * UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In
1231
+ * userfaultfd.h we assumed the kernel was reading (instead _IOC_READ
1232
+ * means the userland is reading).
1233
*/
1234
-#define UFFD_API_FEATURES (0)
1235
+#define UFFD_API ((__u64)0xAA)
1236
+#define UFFD_API_FEATURES (UFFD_FEATURE_EVENT_FORK |        \
1237
+             UFFD_FEATURE_EVENT_REMAP |        \
1238
+             UFFD_FEATURE_EVENT_MADVDONTNEED |    \
1239
+             UFFD_FEATURE_MISSING_HUGETLBFS |    \
1240
+             UFFD_FEATURE_MISSING_SHMEM)
1241
#define UFFD_API_IOCTLS                \
1242
    ((__u64)1 << _UFFDIO_REGISTER |        \
1243
     (__u64)1 << _UFFDIO_UNREGISTER |    \
1244
@@ -XXX,XX +XXX,XX @@
1245
    ((__u64)1 << _UFFDIO_WAKE |        \
1246
     (__u64)1 << _UFFDIO_COPY |        \
1247
     (__u64)1 << _UFFDIO_ZEROPAGE)
1248
+#define UFFD_API_RANGE_IOCTLS_BASIC        \
1249
+    ((__u64)1 << _UFFDIO_WAKE |        \
1250
+     (__u64)1 << _UFFDIO_COPY)
1251
1252
/*
1253
* Valid ioctl command number range with this API is from 0x00 to
1254
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1255
        } pagefault;
1256
1257
        struct {
1258
+            __u32    ufd;
1259
+        } fork;
1260
+
1261
+        struct {
1262
+            __u64    from;
1263
+            __u64    to;
1264
+            __u64    len;
1265
+        } remap;
1266
+
1267
+        struct {
1268
+            __u64    start;
1269
+            __u64    end;
1270
+        } madv_dn;
1271
+
1272
+        struct {
1273
            /* unused reserved fields */
1274
            __u64    reserved1;
1275
            __u64    reserved2;
1276
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1277
* Start at 0x12 and not at 0 to be more strict against bugs.
1278
*/
1279
#define UFFD_EVENT_PAGEFAULT    0x12
1280
-#if 0 /* not available yet */
1281
#define UFFD_EVENT_FORK        0x13
1282
-#endif
1283
+#define UFFD_EVENT_REMAP    0x14
1284
+#define UFFD_EVENT_MADVDONTNEED    0x15
1285
1286
/* flags for UFFD_EVENT_PAGEFAULT */
1287
#define UFFD_PAGEFAULT_FLAG_WRITE    (1<<0)    /* If this was a write fault */
1288
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
1289
     * Note: UFFD_EVENT_PAGEFAULT and UFFD_PAGEFAULT_FLAG_WRITE
1290
     * are to be considered implicitly always enabled in all kernels as
1291
     * long as the uffdio_api.api requested matches UFFD_API.
1292
+     *
1293
+     * UFFD_FEATURE_MISSING_HUGETLBFS means an UFFDIO_REGISTER
1294
+     * with UFFDIO_REGISTER_MODE_MISSING mode will succeed on
1295
+     * hugetlbfs virtual memory ranges. Adding or not adding
1296
+     * UFFD_FEATURE_MISSING_HUGETLBFS to uffdio_api.features has
1297
+     * no real functional effect after UFFDIO_API returns, but
1298
+     * it's only useful for an initial feature set probe at
1299
+     * UFFDIO_API time. There are two ways to use it:
1300
+     *
1301
+     * 1) by adding UFFD_FEATURE_MISSING_HUGETLBFS to the
1302
+     * uffdio_api.features before calling UFFDIO_API, an error
1303
+     * will be returned by UFFDIO_API on a kernel without
1304
+     * hugetlbfs missing support
1305
+     *
1306
+     * 2) the UFFD_FEATURE_MISSING_HUGETLBFS can not be added in
1307
+     * uffdio_api.features and instead it will be set by the
1308
+     * kernel in the uffdio_api.features if the kernel supports
1309
+     * it, so userland can later check if the feature flag is
1310
+     * present in uffdio_api.features after UFFDIO_API
1311
+     * succeeded.
1312
+     *
1313
+     * UFFD_FEATURE_MISSING_SHMEM works the same as
1314
+     * UFFD_FEATURE_MISSING_HUGETLBFS, but it applies to shmem
1315
+     * (i.e. tmpfs and other shmem based APIs).
1316
     */
1317
-#if 0 /* not available yet */
1318
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
1319
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
1320
-#endif
1321
+#define UFFD_FEATURE_EVENT_REMAP        (1<<2)
1322
+#define UFFD_FEATURE_EVENT_MADVDONTNEED        (1<<3)
1323
+#define UFFD_FEATURE_MISSING_HUGETLBFS        (1<<4)
1324
+#define UFFD_FEATURE_MISSING_SHMEM        (1<<5)
1325
    __u64 features;
1326
1327
    __u64 ioctls;
1328
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
1329
index XXXXXXX..XXXXXXX 100644
1330
--- a/linux-headers/linux/vfio.h
1331
+++ b/linux-headers/linux/vfio.h
1332
@@ -XXX,XX +XXX,XX @@ struct vfio_device_info {
1333
};
1334
#define VFIO_DEVICE_GET_INFO        _IO(VFIO_TYPE, VFIO_BASE + 7)
1335
1336
+/*
1337
+ * Vendor driver using Mediated device framework should provide device_api
1338
+ * attribute in supported type attribute groups. Device API string should be one
1339
+ * of the following corresponding to device flags in vfio_device_info structure.
1340
+ */
1341
+
1342
+#define VFIO_DEVICE_API_PCI_STRING        "vfio-pci"
1343
+#define VFIO_DEVICE_API_PLATFORM_STRING        "vfio-platform"
1344
+#define VFIO_DEVICE_API_AMBA_STRING        "vfio-amba"
1345
+
1346
/**
1347
* VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8,
1348
*                 struct vfio_region_info)
1349
--
53
--
1350
2.7.4
54
2.20.1
1351
55
1352
56
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
The linux-headers/asm-arm/unistd.h file has been split in three
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
sub-files, copy them along. However, building them requires
5
setting ARCH rather than SRCARCH.
6
4
7
SRCARCH defaults to $(ARCH) anyway; to avoid future occurrence of
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
8
the same problem use ARCH for all architectures where SRCARCH=ARCH.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Currently these are all except x86, sparc, sh and tile.
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
8
Message-id: 20210108185154.8108-6-leif@nuviainc.com
11
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12
Message-id: 20170221122920.16245-2-pbonzini@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
scripts/update-linux-headers.sh | 13 ++++++++++++-
11
target/arm/cpu.h | 15 +++++++++++++++
16
1 file changed, 12 insertions(+), 1 deletion(-)
12
1 file changed, 15 insertions(+)
17
13
18
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100755
15
index XXXXXXX..XXXXXXX 100644
20
--- a/scripts/update-linux-headers.sh
16
--- a/target/arm/cpu.h
21
+++ b/scripts/update-linux-headers.sh
17
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
23
continue
19
FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
24
fi
20
FIELD(ID_AA64ISAR1, SB, 36, 4)
25
21
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
26
- make -C "$linux" INSTALL_HDR_PATH="$tmpdir" SRCARCH=$arch headers_install
22
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
27
+ if [ "$arch" = x86 ]; then
23
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
28
+ arch_var=SRCARCH
24
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
29
+ else
25
30
+ arch_var=ARCH
26
FIELD(ID_AA64PFR0, EL0, 0, 4)
31
+ fi
27
FIELD(ID_AA64PFR0, EL1, 4, 4)
32
+
28
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
33
+ make -C "$linux" INSTALL_HDR_PATH="$tmpdir" $arch_var=$arch headers_install
29
FIELD(ID_AA64PFR0, GIC, 24, 4)
34
30
FIELD(ID_AA64PFR0, RAS, 28, 4)
35
rm -rf "$output/linux-headers/asm-$arch"
31
FIELD(ID_AA64PFR0, SVE, 32, 4)
36
mkdir -p "$output/linux-headers/asm-$arch"
32
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
37
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
33
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
38
cp_portable "$tmpdir/include/asm/kvm_virtio.h" "$output/include/standard-headers/asm-s390/"
34
+FIELD(ID_AA64PFR0, AMU, 44, 4)
39
cp_portable "$tmpdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/"
35
+FIELD(ID_AA64PFR0, DIT, 48, 4)
40
fi
36
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
41
+ if [ $arch = arm ]; then
37
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
42
+ cp "$tmpdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/"
38
43
+ cp "$tmpdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/"
39
FIELD(ID_AA64PFR1, BT, 0, 4)
44
+ cp "$tmpdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/"
40
FIELD(ID_AA64PFR1, SSBS, 4, 4)
45
+ fi
41
FIELD(ID_AA64PFR1, MTE, 8, 4)
46
if [ $arch = x86 ]; then
42
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
47
cp_portable "$tmpdir/include/asm/hyperv.h" "$output/include/standard-headers/asm-x86/"
43
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
48
cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/"
44
45
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
46
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
47
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
48
FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
49
FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
50
FIELD(ID_AA64MMFR0, EXS, 44, 4)
51
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
52
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
53
54
FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
55
FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
56
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
57
FIELD(ID_AA64MMFR1, PAN, 20, 4)
58
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
59
FIELD(ID_AA64MMFR1, XNX, 28, 4)
60
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
61
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
62
63
FIELD(ID_AA64MMFR2, CNP, 0, 4)
64
FIELD(ID_AA64MMFR2, UAO, 4, 4)
65
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
66
FIELD(ID_AA64DFR0, PMSVER, 32, 4)
67
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
68
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
69
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
70
71
FIELD(ID_DFR0, COPDBG, 0, 4)
72
FIELD(ID_DFR0, COPSDBG, 4, 4)
49
--
73
--
50
2.7.4
74
2.20.1
51
75
52
76
diff view generated by jsdifflib
1
The local variable 'nvic' in stm32f205_soc_realize() no longer
1
From: Leif Lindholm <leif@nuviainc.com>
2
holds a direct pointer to the NVIC device; it is a pointer to
3
the ARMv7M container object. Rename it 'armv7m' accordingly.
4
2
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-7-leif@nuviainc.com
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 1487604965-23220-12-git-send-email-peter.maydell@linaro.org
10
---
10
---
11
hw/arm/stm32f205_soc.c | 18 +++++++++---------
11
target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
12
1 file changed, 9 insertions(+), 9 deletions(-)
12
1 file changed, 28 insertions(+)
13
13
14
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/stm32f205_soc.c
16
--- a/target/arm/cpu.h
17
+++ b/hw/arm/stm32f205_soc.c
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
19
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
19
FIELD(ID_ISAR6, FHM, 8, 4)
20
{
20
FIELD(ID_ISAR6, SB, 12, 4)
21
STM32F205State *s = STM32F205_SOC(dev_soc);
21
FIELD(ID_ISAR6, SPECRES, 16, 4)
22
- DeviceState *dev, *nvic;
22
+FIELD(ID_ISAR6, BF16, 20, 4)
23
+ DeviceState *dev, *armv7m;
23
+FIELD(ID_ISAR6, I8MM, 24, 4)
24
SysBusDevice *busdev;
24
25
Error *err = NULL;
25
FIELD(ID_MMFR0, VMSA, 0, 4)
26
int i;
26
FIELD(ID_MMFR0, PMSA, 4, 4)
27
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
27
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
28
vmstate_register_ram_global(sram);
28
FIELD(ID_MMFR0, FCSE, 24, 4)
29
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
29
FIELD(ID_MMFR0, INNERSHR, 28, 4)
30
30
31
- nvic = DEVICE(&s->armv7m);
31
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
32
- qdev_prop_set_uint32(nvic, "num-irq", 96);
32
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
33
- qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
33
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
34
+ armv7m = DEVICE(&s->armv7m);
34
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
35
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
35
+FIELD(ID_MMFR1, L1HVD, 16, 4)
36
+ qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
36
+FIELD(ID_MMFR1, L1UNI, 20, 4)
37
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
37
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
38
"memory", &error_abort);
38
+FIELD(ID_MMFR1, BPRED, 28, 4)
39
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
39
+
40
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
40
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
41
}
41
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
42
busdev = SYS_BUS_DEVICE(dev);
42
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
43
sysbus_mmio_map(busdev, 0, 0x40013800);
43
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
44
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
44
+FIELD(ID_MMFR2, UNITLB, 16, 4)
45
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
45
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
46
46
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
47
/* Attach UART (uses USART registers) and USART controllers */
47
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
48
for (i = 0; i < STM_NUM_USARTS; i++) {
48
+
49
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
49
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
50
}
50
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
51
busdev = SYS_BUS_DEVICE(dev);
51
FIELD(ID_MMFR3, BPMAINT, 8, 4)
52
sysbus_mmio_map(busdev, 0, usart_addr[i]);
52
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
53
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
53
FIELD(ID_MMFR4, CCIDX, 24, 4)
54
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
54
FIELD(ID_MMFR4, EVT, 28, 4)
55
}
55
56
56
+FIELD(ID_MMFR5, ETS, 0, 4)
57
/* Timer 2 to 5 */
57
+
58
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
58
FIELD(ID_PFR0, STATE0, 0, 4)
59
}
59
FIELD(ID_PFR0, STATE1, 4, 4)
60
busdev = SYS_BUS_DEVICE(dev);
60
FIELD(ID_PFR0, STATE2, 8, 4)
61
sysbus_mmio_map(busdev, 0, timer_addr[i]);
61
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
62
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
62
FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
63
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
63
FIELD(ID_PFR1, GIC, 28, 4)
64
}
64
65
65
+FIELD(ID_PFR2, CSV3, 0, 4)
66
/* ADC 1 to 3 */
66
+FIELD(ID_PFR2, SSBS, 4, 4)
67
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
67
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
68
return;
68
+
69
}
69
FIELD(ID_AA64ISAR0, AES, 4, 4)
70
qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
70
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
71
- qdev_get_gpio_in(nvic, ADC_IRQ));
71
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
72
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
72
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
73
73
FIELD(ID_DFR0, PERFMON, 24, 4)
74
for (i = 0; i < STM_NUM_ADCS; i++) {
74
FIELD(ID_DFR0, TRACEFILT, 28, 4)
75
dev = DEVICE(&(s->adc[i]));
75
76
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
76
+FIELD(ID_DFR1, MTPMU, 0, 4)
77
}
77
+
78
busdev = SYS_BUS_DEVICE(dev);
78
FIELD(DBGDIDR, SE_IMP, 12, 1)
79
sysbus_mmio_map(busdev, 0, spi_addr[i]);
79
FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
80
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
80
FIELD(DBGDIDR, VERSION, 16, 4)
81
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
82
}
83
}
84
85
--
81
--
86
2.7.4
82
2.20.1
87
83
88
84
diff view generated by jsdifflib
1
Switch the stm32f205 SoC to create the armv7m object directly
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
rather than via the armv7m_init() wrapper. This fits better
3
with the SoC model's very QOMified design.
4
2
5
In particular this means we can push loading the guest image
3
QEMU documentation can't be opened if QEMU is run from build tree
6
out to the top level board code where it belongs, rather
4
because executables are placed in the top of build tree after conversion
7
than the SoC object having a QOM property for the filename
5
to meson.
8
to load.
9
6
7
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
15
---
12
---
16
include/hw/arm/stm32f205_soc.h | 4 +++-
13
ui/cocoa.m | 2 +-
17
hw/arm/netduino2.c | 7 ++++---
14
1 file changed, 1 insertion(+), 1 deletion(-)
18
hw/arm/stm32f205_soc.c | 16 +++++++++++++---
19
3 files changed, 20 insertions(+), 7 deletions(-)
20
15
21
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
16
diff --git a/ui/cocoa.m b/ui/cocoa.m
22
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/stm32f205_soc.h
18
--- a/ui/cocoa.m
24
+++ b/include/hw/arm/stm32f205_soc.h
19
+++ b/ui/cocoa.m
25
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
26
#include "hw/adc/stm32f2xx_adc.h"
21
- (void) openDocumentation: (NSString *) filename
27
#include "hw/or-irq.h"
28
#include "hw/ssi/stm32f2xx_spi.h"
29
+#include "hw/arm/armv7m.h"
30
31
#define TYPE_STM32F205_SOC "stm32f205-soc"
32
#define STM32F205_SOC(obj) \
33
@@ -XXX,XX +XXX,XX @@ typedef struct STM32F205State {
34
SysBusDevice parent_obj;
35
/*< public >*/
36
37
- char *kernel_filename;
38
char *cpu_model;
39
40
+ ARMv7MState armv7m;
41
+
42
STM32F2XXSyscfgState syscfg;
43
STM32F2XXUsartState usart[STM_NUM_USARTS];
44
STM32F2XXTimerState timer[STM_NUM_TIMERS];
45
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/netduino2.c
48
+++ b/hw/arm/netduino2.c
49
@@ -XXX,XX +XXX,XX @@
50
#include "hw/boards.h"
51
#include "qemu/error-report.h"
52
#include "hw/arm/stm32f205_soc.h"
53
+#include "hw/arm/arm.h"
54
55
static void netduino2_init(MachineState *machine)
56
{
22
{
57
DeviceState *dev;
23
/* Where to look for local files */
58
24
- NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
59
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
25
+ NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
60
- if (machine->kernel_filename) {
26
NSString *full_file_path;
61
- qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
27
62
- }
28
/* iterate thru the possible paths until the file is found */
63
qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
64
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
65
+
66
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
67
+ FLASH_SIZE);
68
}
69
70
static void netduino2_machine_init(MachineClass *mc)
71
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/arm/stm32f205_soc.c
74
+++ b/hw/arm/stm32f205_soc.c
75
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
76
STM32F205State *s = STM32F205_SOC(obj);
77
int i;
78
79
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
80
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
81
+
82
object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
83
qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
84
85
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
86
vmstate_register_ram_global(sram);
87
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
88
89
- nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
90
- s->kernel_filename, s->cpu_model);
91
+ nvic = DEVICE(&s->armv7m);
92
+ qdev_prop_set_uint32(nvic, "num-irq", 96);
93
+ qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
94
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
95
+ "memory", &error_abort);
96
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
97
+ if (err != NULL) {
98
+ error_propagate(errp, err);
99
+ return;
100
+ }
101
102
/* System configuration controller */
103
dev = DEVICE(&s->syscfg);
104
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
105
}
106
107
static Property stm32f205_soc_properties[] = {
108
- DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
109
DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
110
DEFINE_PROP_END_OF_LIST(),
111
};
112
--
29
--
113
2.7.4
30
2.20.1
114
31
115
32
diff view generated by jsdifflib
1
Make the NVIC device expose a memory region for its users
1
In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
2
to map, rather than mapping itself into the system memory
2
At the moment new manpages have to be listed both in the conf.py for
3
space on realize, and get the one user (the ARMv7M object)
3
Sphinx and also in docs/meson.build for Meson. We forgot the second
4
to do this.
4
of those -- correct the omission.
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 1487604965-23220-7-git-send-email-peter.maydell@linaro.org
9
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
9
---
10
---
10
hw/arm/armv7m.c | 7 ++++++-
11
docs/meson.build | 1 +
11
hw/intc/armv7m_nvic.c | 7 ++-----
12
1 file changed, 1 insertion(+)
12
2 files changed, 8 insertions(+), 6 deletions(-)
13
13
14
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
14
diff --git a/docs/meson.build b/docs/meson.build
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/armv7m.c
16
--- a/docs/meson.build
17
+++ b/hw/arm/armv7m.c
17
+++ b/docs/meson.build
18
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
18
@@ -XXX,XX +XXX,XX @@ if build_docs
19
static void armv7m_realize(DeviceState *dev, Error **errp)
19
'qemu-img.1': (have_tools ? 'man1' : ''),
20
{
20
'qemu-nbd.8': (have_tools ? 'man8' : ''),
21
ARMv7MState *s = ARMV7M(dev);
21
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
22
+ SysBusDevice *sbd;
22
+ 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
23
Error *err = NULL;
23
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
24
int i;
24
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
25
char **cpustr;
25
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
26
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
27
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
28
29
/* Wire the NVIC up to the CPU */
30
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
31
+ sbd = SYS_BUS_DEVICE(&s->nvic);
32
+ sysbus_connect_irq(sbd, 0,
33
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
34
s->cpu->env.nvic = &s->nvic;
35
36
+ memory_region_add_subregion(&s->container, 0xe000e000,
37
+ sysbus_mmio_get_region(sbd, 0));
38
+
39
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
40
Object *obj = OBJECT(&s->bitband[i]);
41
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
42
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/intc/armv7m_nvic.c
45
+++ b/hw/intc/armv7m_nvic.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/arm/arm.h"
48
#include "hw/arm/armv7m_nvic.h"
49
#include "target/arm/cpu.h"
50
-#include "exec/address-spaces.h"
51
#include "qemu/log.h"
52
#include "trace.h"
53
54
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
55
"nvic_sysregs", 0x1000);
56
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
57
58
- /* Map the whole thing into system memory at the location required
59
- * by the v7M architecture.
60
- */
61
- memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
62
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
63
+
64
s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
65
}
66
67
--
26
--
68
2.7.4
27
2.20.1
69
28
70
29
diff view generated by jsdifflib
1
Make the legacy armv7m_init() function use the newly QOMified
1
When we first converted our documentation to Sphinx, we split it into
2
armv7m object rather than doing everything by hand.
2
multiple manuals (system, interop, tools, etc), which are all built
3
3
separately. The primary driver for this was wanting to be able to
4
We can return the armv7m object rather than the NVIC from
4
avoid shipping the 'devel' manual to end-users. However, this is
5
armv7m_init() because its interface to the rest of the
5
working against the grain of the way Sphinx wants to be used and
6
board (GPIOs, etc) is identical.
6
causes some annoyances:
7
* Cross-references between documents become much harder or
8
possibly impossible
9
* There is no single index to the whole documentation
10
* Within one manual there's no links or table-of-contents info
11
that lets you easily navigate to the others
12
* The devel manual doesn't get published on the QEMU website
13
(it would be nice to able to refer to it there)
14
15
Merely hiding our developer documentation from end users seems like
16
it's not enough benefit for these costs. Combine all the
17
documentation into a single manual (the same way that the readthedocs
18
site builds it) and install the whole thing. The previous manual
19
divisions remain as the new top level sections in the manual.
20
21
* The per-manual conf.py files are no longer needed
22
* The man_pages[] specifications previously in each per-manual
23
conf.py move to the top level conf.py
24
* docs/meson.build logic is simplified as we now only need to run
25
Sphinx once for the HTML and then once for the manpages5B
26
* The old index.html.in that produced the top-level page with
27
links to each manual is no longer needed
28
29
Unfortunately this means that we now have to build the HTML
30
documentation into docs/manual in the build tree rather than directly
31
into docs/; otherwise it is too awkward to ensure we install only the
32
built manual and not also the dependency info, stamp file, etc. The
33
manual still ends up in the same place in the final installed
34
directory, but anybody who was consulting documentation from within
35
the build tree will have to adjust where they're looking.
7
36
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
38
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
39
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
11
Message-id: 1487604965-23220-5-git-send-email-peter.maydell@linaro.org
12
---
40
---
13
hw/arm/armv7m.c | 49 ++++++++++++-------------------------------------
41
docs/conf.py | 46 ++++++++++++++++++++++++++++++-
14
1 file changed, 12 insertions(+), 37 deletions(-)
42
docs/devel/conf.py | 15 -----------
15
43
docs/index.html.in | 17 ------------
16
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
44
docs/interop/conf.py | 28 -------------------
45
docs/meson.build | 64 +++++++++++++++++---------------------------
46
docs/specs/conf.py | 16 -----------
47
docs/system/conf.py | 28 -------------------
48
docs/tools/conf.py | 37 -------------------------
49
docs/user/conf.py | 15 -----------
50
9 files changed, 70 insertions(+), 196 deletions(-)
51
delete mode 100644 docs/devel/conf.py
52
delete mode 100644 docs/index.html.in
53
delete mode 100644 docs/interop/conf.py
54
delete mode 100644 docs/specs/conf.py
55
delete mode 100644 docs/system/conf.py
56
delete mode 100644 docs/tools/conf.py
57
delete mode 100644 docs/user/conf.py
58
59
diff --git a/docs/conf.py b/docs/conf.py
17
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/armv7m.c
61
--- a/docs/conf.py
19
+++ b/hw/arm/armv7m.c
62
+++ b/docs/conf.py
20
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
63
@@ -XXX,XX +XXX,XX @@ latex_documents = [
21
sysbus_init_mmio(dev, &s->iomem);
64
22
}
65
# -- Options for manual page output ---------------------------------------
23
66
# Individual manual/conf.py can override this to create man pages
24
-static void armv7m_bitband_init(void)
67
-man_pages = []
25
-{
68
+man_pages = [
26
- DeviceState *dev;
69
+ ('interop/qemu-ga', 'qemu-ga',
27
-
70
+ 'QEMU Guest Agent',
28
- dev = qdev_create(NULL, TYPE_BITBAND);
71
+ ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
29
- qdev_prop_set_uint32(dev, "base", 0x20000000);
72
+ ('interop/qemu-ga-ref', 'qemu-ga-ref',
30
- qdev_init_nofail(dev);
73
+ 'QEMU Guest Agent Protocol Reference',
31
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
74
+ [], 7),
32
-
75
+ ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
33
- dev = qdev_create(NULL, TYPE_BITBAND);
76
+ 'QEMU QMP Reference Manual',
34
- qdev_prop_set_uint32(dev, "base", 0x40000000);
77
+ [], 7),
35
- qdev_init_nofail(dev);
78
+ ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
36
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
79
+ 'QEMU Storage Daemon QMP Reference Manual',
37
-}
80
+ [], 7),
38
-
81
+ ('system/qemu-manpage', 'qemu',
39
/* Board init. */
82
+ 'QEMU User Documentation',
40
83
+ ['Fabrice Bellard'], 1),
41
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
84
+ ('system/qemu-block-drivers', 'qemu-block-drivers',
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
85
+ 'QEMU block drivers reference',
43
86
+ ['Fabrice Bellard and the QEMU Project developers'], 7),
44
/* Init CPU and memory for a v7-M based board.
87
+ ('system/qemu-cpu-models', 'qemu-cpu-models',
45
mem_size is in bytes.
88
+ 'QEMU CPU Models',
46
- Returns the NVIC array. */
89
+ ['The QEMU Project developers'], 7),
47
+ Returns the ARMv7M device. */
90
+ ('tools/qemu-img', 'qemu-img',
48
91
+ 'QEMU disk image utility',
49
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
92
+ ['Fabrice Bellard'], 1),
50
const char *kernel_filename, const char *cpu_model)
93
+ ('tools/qemu-nbd', 'qemu-nbd',
51
{
94
+ 'QEMU Disk Network Block Device Server',
52
- ARMCPU *cpu;
95
+ ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
53
- CPUARMState *env;
96
+ ('tools/qemu-pr-helper', 'qemu-pr-helper',
54
- DeviceState *nvic;
97
+ 'QEMU persistent reservation helper',
55
+ DeviceState *armv7m;
98
+ [], 8),
56
99
+ ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
57
if (cpu_model == NULL) {
100
+ 'QEMU storage daemon',
58
-    cpu_model = "cortex-m3";
101
+ [], 1),
59
+ cpu_model = "cortex-m3";
102
+ ('tools/qemu-trace-stap', 'qemu-trace-stap',
60
}
103
+ 'QEMU SystemTap trace tool',
61
- cpu = cpu_arm_init(cpu_model);
104
+ [], 1),
62
- if (cpu == NULL) {
105
+ ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
63
- fprintf(stderr, "Unable to find CPU definition\n");
106
+ 'QEMU 9p virtfs proxy filesystem helper',
64
- exit(1);
107
+ ['M. Mohan Kumar'], 1),
65
- }
108
+ ('tools/virtiofsd', 'virtiofsd',
66
- env = &cpu->env;
109
+ 'QEMU virtio-fs shared file system daemon',
67
-
110
+ ['Stefan Hajnoczi <stefanha@redhat.com>',
68
- armv7m_bitband_init();
111
+ 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
69
-
112
+]
70
- nvic = qdev_create(NULL, "armv7m_nvic");
113
71
- qdev_prop_set_uint32(nvic, "num-irq", num_irq);
114
# -- Options for Texinfo output -------------------------------------------
72
- env->nvic = nvic;
115
73
- qdev_init_nofail(nvic);
116
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
74
- sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
117
deleted file mode 100644
75
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
118
index XXXXXXX..XXXXXXX
76
- armv7m_load_kernel(cpu, kernel_filename, mem_size);
119
--- a/docs/devel/conf.py
77
- return nvic;
120
+++ /dev/null
121
@@ -XXX,XX +XXX,XX @@
122
-# -*- coding: utf-8 -*-
123
-#
124
-# QEMU documentation build configuration file for the 'devel' manual.
125
-#
126
-# This includes the top level conf file and then makes any necessary tweaks.
127
-import sys
128
-import os
129
-
130
-qemu_docdir = os.path.abspath("..")
131
-parent_config = os.path.join(qemu_docdir, "conf.py")
132
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
133
-
134
-# This slightly misuses the 'description', but is the best way to get
135
-# the manual title to appear in the sidebar.
136
-html_theme_options['description'] = u'Developer''s Guide'
137
diff --git a/docs/index.html.in b/docs/index.html.in
138
deleted file mode 100644
139
index XXXXXXX..XXXXXXX
140
--- a/docs/index.html.in
141
+++ /dev/null
142
@@ -XXX,XX +XXX,XX @@
143
-<!DOCTYPE html>
144
-<html lang="en">
145
- <head>
146
- <meta charset="UTF-8">
147
- <title>QEMU @VERSION@ Documentation</title>
148
- </head>
149
- <body>
150
- <h1>QEMU @VERSION@ Documentation</h1>
151
- <ul>
152
- <li><a href="system/index.html">System Emulation User's Guide</a></li>
153
- <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
154
- <li><a href="tools/index.html">Tools Guide</a></li>
155
- <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
156
- <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
157
- </ul>
158
- </body>
159
-</html>
160
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
161
deleted file mode 100644
162
index XXXXXXX..XXXXXXX
163
--- a/docs/interop/conf.py
164
+++ /dev/null
165
@@ -XXX,XX +XXX,XX @@
166
-# -*- coding: utf-8 -*-
167
-#
168
-# QEMU documentation build configuration file for the 'interop' manual.
169
-#
170
-# This includes the top level conf file and then makes any necessary tweaks.
171
-import sys
172
-import os
173
-
174
-qemu_docdir = os.path.abspath("..")
175
-parent_config = os.path.join(qemu_docdir, "conf.py")
176
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
177
-
178
-# This slightly misuses the 'description', but is the best way to get
179
-# the manual title to appear in the sidebar.
180
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
181
-
182
-# One entry per manual page. List of tuples
183
-# (source start file, name, description, authors, manual section).
184
-man_pages = [
185
- ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
186
- ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
187
- ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
188
- [], 7),
189
- ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
190
- [], 7),
191
- ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
192
- 'QEMU Storage Daemon QMP Reference Manual', [], 7),
193
-]
194
diff --git a/docs/meson.build b/docs/meson.build
195
index XXXXXXX..XXXXXXX 100644
196
--- a/docs/meson.build
197
+++ b/docs/meson.build
198
@@ -XXX,XX +XXX,XX @@ if build_docs
199
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
200
qapi_gen_depends ]
201
202
- configure_file(output: 'index.html',
203
- input: files('index.html.in'),
204
- configuration: {'VERSION': meson.project_version()},
205
- install_dir: qemu_docdir)
206
- manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
207
man_pages = {
208
- 'interop' : {
209
'qemu-ga.8': (have_tools ? 'man8' : ''),
210
'qemu-ga-ref.7': 'man7',
211
'qemu-qmp-ref.7': 'man7',
212
'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
213
- },
214
- 'tools': {
215
'qemu-img.1': (have_tools ? 'man1' : ''),
216
'qemu-nbd.8': (have_tools ? 'man8' : ''),
217
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
218
@@ -XXX,XX +XXX,XX @@ if build_docs
219
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
220
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
221
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
222
- },
223
- 'system': {
224
'qemu.1': 'man1',
225
'qemu-block-drivers.7': 'man7',
226
'qemu-cpu-models.7': 'man7'
227
- },
228
}
229
230
sphinxdocs = []
231
sphinxmans = []
232
- foreach manual : manuals
233
- private_dir = meson.current_build_dir() / (manual + '.p')
234
- output_dir = meson.current_build_dir() / manual
235
- input_dir = meson.current_source_dir() / manual
236
237
- this_manual = custom_target(manual + ' manual',
238
+ private_dir = meson.current_build_dir() / 'manual.p'
239
+ output_dir = meson.current_build_dir() / 'manual'
240
+ input_dir = meson.current_source_dir()
78
+
241
+
79
+ armv7m = qdev_create(NULL, "armv7m");
242
+ this_manual = custom_target('QEMU manual',
80
+ qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
243
build_by_default: build_docs,
81
+ qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
244
- output: [manual + '.stamp'],
82
+ /* This will exit with an error if the user passed us a bad cpu_model */
245
- input: [files('conf.py'), files(manual / 'conf.py')],
83
+ qdev_init_nofail(armv7m);
246
- depfile: manual + '.d',
247
+ output: 'docs.stamp',
248
+ input: files('conf.py'),
249
+ depfile: 'docs.d',
250
depend_files: sphinx_extn_depends,
251
command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
252
'-Ddepfile_stamp=@OUTPUT0@',
253
'-b', 'html', '-d', private_dir,
254
input_dir, output_dir])
255
- sphinxdocs += this_manual
256
- if build_docs and manual != 'devel'
257
- install_subdir(output_dir, install_dir: qemu_docdir)
258
- endif
259
+ sphinxdocs += this_manual
260
+ install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
261
262
- these_man_pages = []
263
- install_dirs = []
264
- foreach page, section : man_pages.get(manual, {})
265
- these_man_pages += page
266
- install_dirs += section == '' ? false : get_option('mandir') / section
267
- endforeach
268
- if these_man_pages.length() > 0
269
- sphinxmans += custom_target(manual + ' man pages',
270
- build_by_default: build_docs,
271
- output: these_man_pages,
272
- input: this_manual,
273
- install: build_docs,
274
- install_dir: install_dirs,
275
- command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
276
- input_dir, meson.current_build_dir()])
277
- endif
278
+ these_man_pages = []
279
+ install_dirs = []
280
+ foreach page, section : man_pages
281
+ these_man_pages += page
282
+ install_dirs += section == '' ? false : get_option('mandir') / section
283
endforeach
84
+
284
+
85
+ armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
285
+ sphinxmans += custom_target('QEMU man pages',
86
+ return armv7m;
286
+ build_by_default: build_docs,
87
}
287
+ output: these_man_pages,
88
288
+ input: this_manual,
89
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
289
+ install: build_docs,
290
+ install_dir: install_dirs,
291
+ command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
292
+ input_dir, meson.current_build_dir()])
293
+
294
alias_target('sphinxdocs', sphinxdocs)
295
alias_target('html', sphinxdocs)
296
alias_target('man', sphinxmans)
297
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
298
deleted file mode 100644
299
index XXXXXXX..XXXXXXX
300
--- a/docs/specs/conf.py
301
+++ /dev/null
302
@@ -XXX,XX +XXX,XX @@
303
-# -*- coding: utf-8 -*-
304
-#
305
-# QEMU documentation build configuration file for the 'specs' manual.
306
-#
307
-# This includes the top level conf file and then makes any necessary tweaks.
308
-import sys
309
-import os
310
-
311
-qemu_docdir = os.path.abspath("..")
312
-parent_config = os.path.join(qemu_docdir, "conf.py")
313
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
314
-
315
-# This slightly misuses the 'description', but is the best way to get
316
-# the manual title to appear in the sidebar.
317
-html_theme_options['description'] = \
318
- u'System Emulation Guest Hardware Specifications'
319
diff --git a/docs/system/conf.py b/docs/system/conf.py
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/docs/system/conf.py
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-# -*- coding: utf-8 -*-
326
-#
327
-# QEMU documentation build configuration file for the 'system' manual.
328
-#
329
-# This includes the top level conf file and then makes any necessary tweaks.
330
-import sys
331
-import os
332
-
333
-qemu_docdir = os.path.abspath("..")
334
-parent_config = os.path.join(qemu_docdir, "conf.py")
335
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
336
-
337
-# This slightly misuses the 'description', but is the best way to get
338
-# the manual title to appear in the sidebar.
339
-html_theme_options['description'] = u'System Emulation User''s Guide'
340
-
341
-# One entry per manual page. List of tuples
342
-# (source start file, name, description, authors, manual section).
343
-man_pages = [
344
- ('qemu-manpage', 'qemu', u'QEMU User Documentation',
345
- ['Fabrice Bellard'], 1),
346
- ('qemu-block-drivers', 'qemu-block-drivers',
347
- u'QEMU block drivers reference',
348
- ['Fabrice Bellard and the QEMU Project developers'], 7),
349
- ('qemu-cpu-models', 'qemu-cpu-models',
350
- u'QEMU CPU Models',
351
- ['The QEMU Project developers'], 7)
352
-]
353
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
354
deleted file mode 100644
355
index XXXXXXX..XXXXXXX
356
--- a/docs/tools/conf.py
357
+++ /dev/null
358
@@ -XXX,XX +XXX,XX @@
359
-# -*- coding: utf-8 -*-
360
-#
361
-# QEMU documentation build configuration file for the 'tools' manual.
362
-#
363
-# This includes the top level conf file and then makes any necessary tweaks.
364
-import sys
365
-import os
366
-
367
-qemu_docdir = os.path.abspath("..")
368
-parent_config = os.path.join(qemu_docdir, "conf.py")
369
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
370
-
371
-# This slightly misuses the 'description', but is the best way to get
372
-# the manual title to appear in the sidebar.
373
-html_theme_options['description'] = \
374
- u'Tools Guide'
375
-
376
-# One entry per manual page. List of tuples
377
-# (source start file, name, description, authors, manual section).
378
-man_pages = [
379
- ('qemu-img', 'qemu-img', u'QEMU disk image utility',
380
- ['Fabrice Bellard'], 1),
381
- ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
382
- [], 1),
383
- ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
384
- ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
385
- ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
386
- [], 8),
387
- ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
388
- [], 1),
389
- ('virtfs-proxy-helper', 'virtfs-proxy-helper',
390
- u'QEMU 9p virtfs proxy filesystem helper',
391
- ['M. Mohan Kumar'], 1),
392
- ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
393
- ['Stefan Hajnoczi <stefanha@redhat.com>',
394
- 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
395
-]
396
diff --git a/docs/user/conf.py b/docs/user/conf.py
397
deleted file mode 100644
398
index XXXXXXX..XXXXXXX
399
--- a/docs/user/conf.py
400
+++ /dev/null
401
@@ -XXX,XX +XXX,XX @@
402
-# -*- coding: utf-8 -*-
403
-#
404
-# QEMU documentation build configuration file for the 'user' manual.
405
-#
406
-# This includes the top level conf file and then makes any necessary tweaks.
407
-import sys
408
-import os
409
-
410
-qemu_docdir = os.path.abspath("..")
411
-parent_config = os.path.join(qemu_docdir, "conf.py")
412
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
413
-
414
-# This slightly misuses the 'description', but is the best way to get
415
-# the manual title to appear in the sidebar.
416
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
90
--
417
--
91
2.7.4
418
2.20.1
92
419
93
420
diff view generated by jsdifflib
1
Instead of the bitband device doing a cpu_physical_memory_read/write,
1
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
2
make it take a MemoryRegion which specifies where it should be
2
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
3
accessing, and use address_space_read/write to access the
3
because it moved the handling of "cp insns which are handled
4
corresponding AddressSpace.
4
by looking up the cp register in the hashtable" from after the
5
call to the legacy disas_xscale_insn() decode to before it,
6
with the result that all XScale/iWMMXt insns now UNDEF.
5
7
6
Since this entails pretty much a rewrite, convert away from
8
Update valid_cp() so that it knows that on XScale cp 0 and 1
7
old_mmio in the process.
9
are not standard coprocessor instructions; this will cause
10
the decodetree trans_ functions to ignore them, so that
11
execution will correctly get through to the legacy decode again.
8
12
13
Cc: qemu-stable@nongnu.org
14
Reported-by: Guenter Roeck <linux@roeck-us.net>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
18
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
12
---
19
---
13
include/hw/arm/armv7m.h | 2 +
20
target/arm/translate.c | 7 +++++++
14
hw/arm/armv7m.c | 166 +++++++++++++++++++++++-------------------------
21
1 file changed, 7 insertions(+)
15
2 files changed, 81 insertions(+), 87 deletions(-)
16
22
17
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
23
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/armv7m.h
25
--- a/target/arm/translate.c
20
+++ b/include/hw/arm/armv7m.h
26
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct {
27
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
22
SysBusDevice parent_obj;
28
* only cp14 and cp15 are valid, and other values aren't considered
23
/*< public >*/
29
* to be in the coprocessor-instruction space at all. v8M still
24
30
* permits coprocessors 0..7.
25
+ AddressSpace *source_as;
31
+ * For XScale, we must not decode the XScale cp0, cp1 space as
26
MemoryRegion iomem;
32
+ * a standard coprocessor insn, because we want to fall through to
27
uint32_t base;
33
+ * the legacy disas_xscale_insn() decoder after decodetree is done.
28
+ MemoryRegion *source_memory;
34
*/
29
} BitBandState;
35
+ if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
30
36
+ return false;
31
#define TYPE_ARMV7M "armv7m"
32
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/armv7m.c
35
+++ b/hw/arm/armv7m.c
36
@@ -XXX,XX +XXX,XX @@
37
/* Bitbanded IO. Each word corresponds to a single bit. */
38
39
/* Get the byte address of the real memory for a bitband access. */
40
-static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
41
+static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
42
{
43
- uint32_t res;
44
-
45
- res = *(uint32_t *)opaque;
46
- res |= (addr & 0x1ffffff) >> 5;
47
- return res;
48
-
49
-}
50
-
51
-static uint32_t bitband_readb(void *opaque, hwaddr offset)
52
-{
53
- uint8_t v;
54
- cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
55
- return (v & (1 << ((offset >> 2) & 7))) != 0;
56
-}
57
-
58
-static void bitband_writeb(void *opaque, hwaddr offset,
59
- uint32_t value)
60
-{
61
- uint32_t addr;
62
- uint8_t mask;
63
- uint8_t v;
64
- addr = bitband_addr(opaque, offset);
65
- mask = (1 << ((offset >> 2) & 7));
66
- cpu_physical_memory_read(addr, &v, 1);
67
- if (value & 1)
68
- v |= mask;
69
- else
70
- v &= ~mask;
71
- cpu_physical_memory_write(addr, &v, 1);
72
-}
73
-
74
-static uint32_t bitband_readw(void *opaque, hwaddr offset)
75
-{
76
- uint32_t addr;
77
- uint16_t mask;
78
- uint16_t v;
79
- addr = bitband_addr(opaque, offset) & ~1;
80
- mask = (1 << ((offset >> 2) & 15));
81
- mask = tswap16(mask);
82
- cpu_physical_memory_read(addr, &v, 2);
83
- return (v & mask) != 0;
84
-}
85
-
86
-static void bitband_writew(void *opaque, hwaddr offset,
87
- uint32_t value)
88
-{
89
- uint32_t addr;
90
- uint16_t mask;
91
- uint16_t v;
92
- addr = bitband_addr(opaque, offset) & ~1;
93
- mask = (1 << ((offset >> 2) & 15));
94
- mask = tswap16(mask);
95
- cpu_physical_memory_read(addr, &v, 2);
96
- if (value & 1)
97
- v |= mask;
98
- else
99
- v &= ~mask;
100
- cpu_physical_memory_write(addr, &v, 2);
101
+ return s->base | (offset & 0x1ffffff) >> 5;
102
}
103
104
-static uint32_t bitband_readl(void *opaque, hwaddr offset)
105
+static MemTxResult bitband_read(void *opaque, hwaddr offset,
106
+ uint64_t *data, unsigned size, MemTxAttrs attrs)
107
{
108
- uint32_t addr;
109
- uint32_t mask;
110
- uint32_t v;
111
- addr = bitband_addr(opaque, offset) & ~3;
112
- mask = (1 << ((offset >> 2) & 31));
113
- mask = tswap32(mask);
114
- cpu_physical_memory_read(addr, &v, 4);
115
- return (v & mask) != 0;
116
+ BitBandState *s = opaque;
117
+ uint8_t buf[4];
118
+ MemTxResult res;
119
+ int bitpos, bit;
120
+ hwaddr addr;
121
+
122
+ assert(size <= 4);
123
+
124
+ /* Find address in underlying memory and round down to multiple of size */
125
+ addr = bitband_addr(s, offset) & (-size);
126
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
127
+ if (res) {
128
+ return res;
129
+ }
130
+ /* Bit position in the N bytes read... */
131
+ bitpos = (offset >> 2) & ((size * 8) - 1);
132
+ /* ...converted to byte in buffer and bit in byte */
133
+ bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
134
+ *data = bit;
135
+ return MEMTX_OK;
136
}
137
138
-static void bitband_writel(void *opaque, hwaddr offset,
139
- uint32_t value)
140
+static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
141
+ unsigned size, MemTxAttrs attrs)
142
{
143
- uint32_t addr;
144
- uint32_t mask;
145
- uint32_t v;
146
- addr = bitband_addr(opaque, offset) & ~3;
147
- mask = (1 << ((offset >> 2) & 31));
148
- mask = tswap32(mask);
149
- cpu_physical_memory_read(addr, &v, 4);
150
- if (value & 1)
151
- v |= mask;
152
- else
153
- v &= ~mask;
154
- cpu_physical_memory_write(addr, &v, 4);
155
+ BitBandState *s = opaque;
156
+ uint8_t buf[4];
157
+ MemTxResult res;
158
+ int bitpos, bit;
159
+ hwaddr addr;
160
+
161
+ assert(size <= 4);
162
+
163
+ /* Find address in underlying memory and round down to multiple of size */
164
+ addr = bitband_addr(s, offset) & (-size);
165
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
166
+ if (res) {
167
+ return res;
168
+ }
169
+ /* Bit position in the N bytes read... */
170
+ bitpos = (offset >> 2) & ((size * 8) - 1);
171
+ /* ...converted to byte in buffer and bit in byte */
172
+ bit = 1 << (bitpos & 7);
173
+ if (value & 1) {
174
+ buf[bitpos >> 3] |= bit;
175
+ } else {
176
+ buf[bitpos >> 3] &= ~bit;
177
+ }
178
+ return address_space_write(s->source_as, addr, attrs, buf, size);
179
}
180
181
static const MemoryRegionOps bitband_ops = {
182
- .old_mmio = {
183
- .read = { bitband_readb, bitband_readw, bitband_readl, },
184
- .write = { bitband_writeb, bitband_writew, bitband_writel, },
185
- },
186
+ .read_with_attrs = bitband_read,
187
+ .write_with_attrs = bitband_write,
188
.endianness = DEVICE_NATIVE_ENDIAN,
189
+ .impl.min_access_size = 1,
190
+ .impl.max_access_size = 4,
191
+ .valid.min_access_size = 1,
192
+ .valid.max_access_size = 4,
193
};
194
195
static void bitband_init(Object *obj)
196
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
197
BitBandState *s = BITBAND(obj);
198
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
199
200
- memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
201
+ object_property_add_link(obj, "source-memory",
202
+ TYPE_MEMORY_REGION,
203
+ (Object **)&s->source_memory,
204
+ qdev_prop_allow_set_link_before_realize,
205
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
206
+ &error_abort);
207
+ memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
208
"bitband", 0x02000000);
209
sysbus_init_mmio(dev, &s->iomem);
210
}
211
212
+static void bitband_realize(DeviceState *dev, Error **errp)
213
+{
214
+ BitBandState *s = BITBAND(dev);
215
+
216
+ if (!s->source_memory) {
217
+ error_setg(errp, "source-memory property not set");
218
+ return;
219
+ }
37
+ }
220
+
38
+
221
+ s->source_as = address_space_init_shareable(s->source_memory,
39
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
222
+ "bitband-source");
40
!arm_dc_feature(s, ARM_FEATURE_M)) {
223
+}
41
return cp >= 14;
224
+
225
/* Board init. */
226
227
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
228
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
229
error_propagate(errp, err);
230
return;
231
}
232
+ object_property_set_link(obj, OBJECT(s->board_memory),
233
+ "source-memory", &error_abort);
234
object_property_set_bool(obj, true, "realized", &err);
235
if (err != NULL) {
236
error_propagate(errp, err);
237
@@ -XXX,XX +XXX,XX @@ static void bitband_class_init(ObjectClass *klass, void *data)
238
{
239
DeviceClass *dc = DEVICE_CLASS(klass);
240
241
+ dc->realize = bitband_realize;
242
dc->props = bitband_properties;
243
}
244
245
--
42
--
246
2.7.4
43
2.20.1
247
44
248
45
diff view generated by jsdifflib
1
The NVIC is a core v7M device that exists for all v7M CPUs;
1
A copy-and-paste error meant that the return value for register offset 0x44
2
put it under a CONFIG_ARM_V7M rather than hiding it under
2
(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
3
CONFIG_STELLARIS.
3
the rx status FIFO. Fix the typo.
4
4
5
(We'll use CONFIG_ARM_V7M for the SysTick device too
5
Cc: qemu-stable@nongnu.org
6
when we split it out of the NVIC.)
6
Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
11
Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
12
---
10
---
13
hw/intc/Makefile.objs | 2 +-
11
hw/net/lan9118.c | 2 +-
14
default-configs/arm-softmmu.mak | 2 ++
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
2 files changed, 3 insertions(+), 1 deletion(-)
16
13
17
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
14
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/Makefile.objs
16
--- a/hw/net/lan9118.c
20
+++ b/hw/intc/Makefile.objs
17
+++ b/hw/net/lan9118.c
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_APIC) += apic.o apic_common.o
18
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
22
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
19
case 0x40:
23
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
20
return rx_status_fifo_pop(s);
24
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
21
case 0x44:
25
-obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
22
- return s->rx_status_fifo[s->tx_status_fifo_head];
26
+obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o
23
+ return s->rx_status_fifo[s->rx_status_fifo_head];
27
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
24
case 0x48:
28
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
25
return tx_status_fifo_pop(s);
29
obj-$(CONFIG_IOAPIC) += ioapic.o
26
case 0x4c:
30
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
31
index XXXXXXX..XXXXXXX 100644
32
--- a/default-configs/arm-softmmu.mak
33
+++ b/default-configs/arm-softmmu.mak
34
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM11MPCORE=y
35
CONFIG_A9MPCORE=y
36
CONFIG_A15MPCORE=y
37
38
+CONFIG_ARM_V7M=y
39
+
40
CONFIG_ARM_GIC=y
41
CONFIG_ARM_GIC_KVM=$(CONFIG_KVM)
42
CONFIG_ARM_TIMER=y
43
--
27
--
44
2.7.4
28
2.20.1
45
29
46
30
diff view generated by jsdifflib
1
Abstract the "load kernel" code out of armv7m_init() into its own
1
The lan9118 code mostly uses symbolic constants for register offsets;
2
function. This includes the registration of the CPU reset function,
2
the exceptions are those which the datasheet doesn't give an official
3
to parallel how we handle this for A profile cores.
3
symbolic name to.
4
4
5
We make the function public so that boards which choose to
5
Add some names for the registers which don't already have them, based
6
directly instantiate an ARMv7M device object can call it.
6
on the longer names they are given in the memory map.
7
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
13
---
11
---
14
include/hw/arm/arm.h | 12 ++++++++++++
12
hw/net/lan9118.c | 24 ++++++++++++++++++------
15
hw/arm/armv7m.c | 23 ++++++++++++++++++-----
13
1 file changed, 18 insertions(+), 6 deletions(-)
16
2 files changed, 30 insertions(+), 5 deletions(-)
17
14
18
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
15
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/arm.h
17
--- a/hw/net/lan9118.c
21
+++ b/include/hw/arm/arm.h
18
+++ b/hw/net/lan9118.c
22
@@ -XXX,XX +XXX,XX @@ typedef enum {
19
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
23
/* armv7m.c */
20
do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
24
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
21
#endif
25
const char *kernel_filename, const char *cpu_model);
22
26
+/**
23
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
27
+ * armv7m_load_kernel:
24
+#define RX_DATA_FIFO_PORT_FIRST 0x00
28
+ * @cpu: CPU
25
+#define RX_DATA_FIFO_PORT_LAST 0x1f
29
+ * @kernel_filename: file to load
26
+#define TX_DATA_FIFO_PORT_FIRST 0x20
30
+ * @mem_size: mem_size: maximum image size to load
27
+#define TX_DATA_FIFO_PORT_LAST 0x3f
31
+ *
32
+ * Load the guest image for an ARMv7M system. This must be called by
33
+ * any ARMv7M board, either directly or via armv7m_init(). (This is
34
+ * necessary to ensure that the CPU resets correctly on system reset,
35
+ * as well as for kernel loading.)
36
+ */
37
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
38
39
/*
40
* struct used as a parameter of the arm_load_kernel machine init
41
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/armv7m.c
44
+++ b/hw/arm/armv7m.c
45
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
46
ARMCPU *cpu;
47
CPUARMState *env;
48
DeviceState *nvic;
49
- int image_size;
50
- uint64_t entry;
51
- uint64_t lowaddr;
52
- int big_endian;
53
54
if (cpu_model == NULL) {
55
    cpu_model = "cortex-m3";
56
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
57
qdev_init_nofail(nvic);
58
sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
59
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
60
+ armv7m_load_kernel(cpu, kernel_filename, mem_size);
61
+ return nvic;
62
+}
63
+
28
+
64
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
29
+#define RX_STATUS_FIFO_PORT 0x40
65
+{
30
+#define RX_STATUS_FIFO_PEEK 0x44
66
+ int image_size;
31
+#define TX_STATUS_FIFO_PORT 0x48
67
+ uint64_t entry;
32
+#define TX_STATUS_FIFO_PEEK 0x4c
68
+ uint64_t lowaddr;
33
+
69
+ int big_endian;
34
#define CSR_ID_REV 0x50
70
35
#define CSR_IRQ_CFG 0x54
71
#ifdef TARGET_WORDS_BIGENDIAN
36
#define CSR_INT_STS 0x58
72
big_endian = 1;
37
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
73
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
38
offset &= 0xff;
74
}
39
40
//DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
41
- if (offset >= 0x20 && offset < 0x40) {
42
+ if (offset >= TX_DATA_FIFO_PORT_FIRST &&
43
+ offset <= TX_DATA_FIFO_PORT_LAST) {
44
/* TX FIFO */
45
tx_fifo_push(s, val);
46
return;
47
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
48
lan9118_state *s = (lan9118_state *)opaque;
49
50
//DPRINTF("Read reg 0x%02x\n", (int)offset);
51
- if (offset < 0x20) {
52
+ if (offset <= RX_DATA_FIFO_PORT_LAST) {
53
/* RX FIFO */
54
return rx_fifo_pop(s);
75
}
55
}
76
56
switch (offset) {
77
+ /* CPU objects (unlike devices) are not automatically reset on system
57
- case 0x40:
78
+ * reset, so we must always register a handler to do so. Unlike
58
+ case RX_STATUS_FIFO_PORT:
79
+ * A-profile CPUs, we don't need to do anything special in the
59
return rx_status_fifo_pop(s);
80
+ * handler to arrange that it starts correctly.
60
- case 0x44:
81
+ * This is arguably the wrong place to do this, but it matches the
61
+ case RX_STATUS_FIFO_PEEK:
82
+ * way A-profile does it. Note that this means that every M profile
62
return s->rx_status_fifo[s->rx_status_fifo_head];
83
+ * board must call this function!
63
- case 0x48:
84
+ */
64
+ case TX_STATUS_FIFO_PORT:
85
qemu_register_reset(armv7m_reset, cpu);
65
return tx_status_fifo_pop(s);
86
- return nvic;
66
- case 0x4c:
87
}
67
+ case TX_STATUS_FIFO_PEEK:
88
68
return s->tx_status_fifo[s->tx_status_fifo_head];
89
static Property bitband_properties[] = {
69
case CSR_ID_REV:
70
return 0x01180001;
90
--
71
--
91
2.7.4
72
2.20.1
92
73
93
74
diff view generated by jsdifflib
1
Create a proper QOM object for the armv7m container, which
1
From: Hao Wu <wuhaotsh@google.com>
2
holds the CPU, the NVIC and the bitband regions.
3
2
3
This patch allows NPCM7XX CLK module to compute clocks that are used by
4
other NPCM7XX modules.
5
6
Add a new struct NPCM7xxClockConverterState which represents a
7
single converter. Each clock converter in CLK module represents one
8
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
9
takes one or more input clocks and converts them into one output clock.
10
They form a clock hierarchy in the CLK module and are responsible for
11
outputing clocks for various other modules in an NPCM7XX SoC.
12
13
Each converter has a function pointer called "convert" which represents
14
the unique logic for that converter.
15
16
The clock contains two initialization information: ConverterInitInfo and
17
ConverterConnectionInfo. They represent the vertices and edges in the
18
clock diagram respectively.
19
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
21
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
22
Signed-off-by: Hao Wu <wuhaotsh@google.com>
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
7
---
26
---
8
include/hw/arm/armv7m.h | 51 ++++++++++++++++++
27
include/hw/misc/npcm7xx_clk.h | 140 +++++-
9
hw/arm/armv7m.c | 139 +++++++++++++++++++++++++++++++++++++++++++-----
28
hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++-
10
2 files changed, 178 insertions(+), 12 deletions(-)
29
2 files changed, 932 insertions(+), 13 deletions(-)
11
create mode 100644 include/hw/arm/armv7m.h
12
30
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
31
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
14
new file mode 100644
32
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX
33
--- a/include/hw/misc/npcm7xx_clk.h
16
--- /dev/null
34
+++ b/include/hw/misc/npcm7xx_clk.h
17
+++ b/include/hw/arm/armv7m.h
18
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@
36
#define NPCM7XX_CLK_H
37
38
#include "exec/memory.h"
39
+#include "hw/clock.h"
40
#include "hw/sysbus.h"
41
42
/*
43
@@ -XXX,XX +XXX,XX @@
44
45
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
46
47
-typedef struct NPCM7xxCLKState {
48
+/* Maximum amount of clock inputs in a SEL module. */
49
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
50
+
51
+/* PLLs in CLK module. */
52
+typedef enum NPCM7xxClockPLL {
53
+ NPCM7XX_CLOCK_PLL0,
54
+ NPCM7XX_CLOCK_PLL1,
55
+ NPCM7XX_CLOCK_PLL2,
56
+ NPCM7XX_CLOCK_PLLG,
57
+ NPCM7XX_CLOCK_NR_PLLS,
58
+} NPCM7xxClockPLL;
59
+
60
+/* SEL/MUX in CLK module. */
61
+typedef enum NPCM7xxClockSEL {
62
+ NPCM7XX_CLOCK_PIXCKSEL,
63
+ NPCM7XX_CLOCK_MCCKSEL,
64
+ NPCM7XX_CLOCK_CPUCKSEL,
65
+ NPCM7XX_CLOCK_CLKOUTSEL,
66
+ NPCM7XX_CLOCK_UARTCKSEL,
67
+ NPCM7XX_CLOCK_TIMCKSEL,
68
+ NPCM7XX_CLOCK_SDCKSEL,
69
+ NPCM7XX_CLOCK_GFXMSEL,
70
+ NPCM7XX_CLOCK_SUCKSEL,
71
+ NPCM7XX_CLOCK_NR_SELS,
72
+} NPCM7xxClockSEL;
73
+
74
+/* Dividers in CLK module. */
75
+typedef enum NPCM7xxClockDivider {
76
+ NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
77
+ NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
78
+ NPCM7XX_CLOCK_MC_DIVIDER,
79
+ NPCM7XX_CLOCK_AXI_DIVIDER,
80
+ NPCM7XX_CLOCK_AHB_DIVIDER,
81
+ NPCM7XX_CLOCK_AHB3_DIVIDER,
82
+ NPCM7XX_CLOCK_SPI0_DIVIDER,
83
+ NPCM7XX_CLOCK_SPIX_DIVIDER,
84
+ NPCM7XX_CLOCK_APB1_DIVIDER,
85
+ NPCM7XX_CLOCK_APB2_DIVIDER,
86
+ NPCM7XX_CLOCK_APB3_DIVIDER,
87
+ NPCM7XX_CLOCK_APB4_DIVIDER,
88
+ NPCM7XX_CLOCK_APB5_DIVIDER,
89
+ NPCM7XX_CLOCK_CLKOUT_DIVIDER,
90
+ NPCM7XX_CLOCK_UART_DIVIDER,
91
+ NPCM7XX_CLOCK_TIMER_DIVIDER,
92
+ NPCM7XX_CLOCK_ADC_DIVIDER,
93
+ NPCM7XX_CLOCK_MMC_DIVIDER,
94
+ NPCM7XX_CLOCK_SDHC_DIVIDER,
95
+ NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
96
+ NPCM7XX_CLOCK_UTMI_DIVIDER,
97
+ NPCM7XX_CLOCK_NR_DIVIDERS,
98
+} NPCM7xxClockConverter;
99
+
100
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
101
+
102
+/**
103
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
104
+ * @name: The name of the module.
105
+ * @clk: The CLK module that owns this module.
106
+ * @clock_in: The input clock of this module.
107
+ * @clock_out: The output clock of this module.
108
+ * @reg: The control registers for this PLL module.
109
+ */
110
+typedef struct NPCM7xxClockPLLState {
111
+ DeviceState parent;
112
+
113
+ const char *name;
114
+ NPCM7xxCLKState *clk;
115
+ Clock *clock_in;
116
+ Clock *clock_out;
117
+
118
+ int reg;
119
+} NPCM7xxClockPLLState;
120
+
121
+/**
122
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
123
+ * @name: The name of the module.
124
+ * @clk: The CLK module that owns this module.
125
+ * @input_size: The size of inputs of this module.
126
+ * @clock_in: The input clocks of this module.
127
+ * @clock_out: The output clocks of this module.
128
+ * @offset: The offset of this module in the control register.
129
+ * @len: The length of this module in the control register.
130
+ */
131
+typedef struct NPCM7xxClockSELState {
132
+ DeviceState parent;
133
+
134
+ const char *name;
135
+ NPCM7xxCLKState *clk;
136
+ uint8_t input_size;
137
+ Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
138
+ Clock *clock_out;
139
+
140
+ int offset;
141
+ int len;
142
+} NPCM7xxClockSELState;
143
+
144
+/**
145
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
146
+ * @name: The name of the module.
147
+ * @clk: The CLK module that owns this module.
148
+ * @clock_in: The input clock of this module.
149
+ * @clock_out: The output clock of this module.
150
+ * @divide: The function the divider uses to divide the input.
151
+ * @reg: The index of the control register that contains the divisor.
152
+ * @offset: The offset of the divisor in the control register.
153
+ * @len: The length of the divisor in the control register.
154
+ * @divisor: The divisor for a constant divisor
155
+ */
156
+typedef struct NPCM7xxClockDividerState {
157
+ DeviceState parent;
158
+
159
+ const char *name;
160
+ NPCM7xxCLKState *clk;
161
+ Clock *clock_in;
162
+ Clock *clock_out;
163
+
164
+ uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
165
+ union {
166
+ struct {
167
+ int reg;
168
+ int offset;
169
+ int len;
170
+ };
171
+ int divisor;
172
+ };
173
+} NPCM7xxClockDividerState;
174
+
175
+struct NPCM7xxCLKState {
176
SysBusDevice parent;
177
178
MemoryRegion iomem;
179
180
+ /* Clock converters */
181
+ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
182
+ NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
183
+ NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
184
+
185
uint32_t regs[NPCM7XX_CLK_NR_REGS];
186
187
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
188
int64_t ref_ns;
189
-} NPCM7xxCLKState;
190
+
191
+ /* The incoming reference clock. */
192
+ Clock *clkref;
193
+};
194
195
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
196
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
197
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
198
index XXXXXXX..XXXXXXX 100644
199
--- a/hw/misc/npcm7xx_clk.c
200
+++ b/hw/misc/npcm7xx_clk.c
201
@@ -XXX,XX +XXX,XX @@
202
203
#include "hw/misc/npcm7xx_clk.h"
204
#include "hw/timer/npcm7xx_timer.h"
205
+#include "hw/qdev-clock.h"
206
#include "migration/vmstate.h"
207
#include "qemu/error-report.h"
208
#include "qemu/log.h"
209
@@ -XXX,XX +XXX,XX @@
210
#include "trace.h"
211
#include "sysemu/watchdog.h"
212
19
+/*
213
+/*
20
+ * ARMv7M CPU object
214
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
21
+ *
215
+ * is always 25 MHz.
22
+ * Copyright (c) 2017 Linaro Ltd
23
+ * Written by Peter Maydell <peter.maydell@linaro.org>
24
+ *
25
+ * This code is licensed under the GPL version 2 or later.
26
+ */
216
+ */
27
+
217
+#define NPCM7XX_CLOCK_REF_HZ (25000000)
28
+#ifndef HW_ARM_ARMV7M_H
218
+
29
+#define HW_ARM_ARMV7M_H
219
+/* Register Field Definitions */
30
+
220
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
31
+#include "hw/sysbus.h"
221
+
32
+#include "hw/arm/armv7m_nvic.h"
222
#define PLLCON_LOKI BIT(31)
33
+
223
#define PLLCON_LOKS BIT(30)
34
+#define TYPE_BITBAND "ARM,bitband-memory"
224
#define PLLCON_PWDEN BIT(12)
35
+#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
225
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
36
+
226
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
37
+typedef struct {
227
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
38
+ /*< private >*/
228
+#define PLLCON_INDV(con) extract32((con), 0, 6)
39
+ SysBusDevice parent_obj;
229
40
+ /*< public >*/
230
enum NPCM7xxCLKRegisters {
41
+
231
NPCM7XX_CLK_CLKEN1,
42
+ MemoryRegion iomem;
232
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
43
+ uint32_t base;
233
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
44
+} BitBandState;
45
+
46
+#define TYPE_ARMV7M "armv7m"
47
+#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
48
+
49
+#define ARMV7M_NUM_BITBANDS 2
50
+
51
+/* ARMv7M container object.
52
+ * + Unnamed GPIO input lines: external IRQ lines for the NVIC
53
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
54
+ * + Property "cpu-model": CPU model to instantiate
55
+ * + Property "num-irq": number of external IRQ lines
56
+ */
57
+typedef struct ARMv7MState {
58
+ /*< private >*/
59
+ SysBusDevice parent_obj;
60
+ /*< public >*/
61
+ NVICState nvic;
62
+ BitBandState bitband[ARMV7M_NUM_BITBANDS];
63
+ ARMCPU *cpu;
64
+
65
+ /* Properties */
66
+ char *cpu_model;
67
+} ARMv7MState;
68
+
69
+#endif
70
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/armv7m.c
73
+++ b/hw/arm/armv7m.c
74
@@ -XXX,XX +XXX,XX @@
75
*/
76
77
#include "qemu/osdep.h"
78
+#include "hw/arm/armv7m.h"
79
#include "qapi/error.h"
80
#include "qemu-common.h"
81
#include "cpu.h"
82
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bitband_ops = {
83
.endianness = DEVICE_NATIVE_ENDIAN,
84
};
234
};
85
235
86
-#define TYPE_BITBAND "ARM,bitband-memory"
236
-/* Register Field Definitions */
87
-#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
237
-#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
88
-
238
-
89
-typedef struct {
239
/* The number of watchdogs that can trigger a reset. */
90
- /*< private >*/
240
#define NPCM7XX_NR_WATCHDOGS (3)
91
- SysBusDevice parent_obj;
241
92
- /*< public >*/
242
+/* Clock converter functions */
93
-
243
+
94
- MemoryRegion iomem;
244
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
95
- uint32_t base;
245
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
96
-} BitBandState;
246
+ (obj), TYPE_NPCM7XX_CLOCK_PLL)
97
-
247
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
98
static void bitband_init(Object *obj)
248
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
249
+ (obj), TYPE_NPCM7XX_CLOCK_SEL)
250
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
251
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
252
+ (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
253
+
254
+static void npcm7xx_clk_update_pll(void *opaque)
255
+{
256
+ NPCM7xxClockPLLState *s = opaque;
257
+ uint32_t con = s->clk->regs[s->reg];
258
+ uint64_t freq;
259
+
260
+ /* The PLL is grounded if it is not locked yet. */
261
+ if (con & PLLCON_LOKI) {
262
+ freq = clock_get_hz(s->clock_in);
263
+ freq *= PLLCON_FBDV(con);
264
+ freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
265
+ } else {
266
+ freq = 0;
267
+ }
268
+
269
+ clock_update_hz(s->clock_out, freq);
270
+}
271
+
272
+static void npcm7xx_clk_update_sel(void *opaque)
273
+{
274
+ NPCM7xxClockSELState *s = opaque;
275
+ uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
276
+ s->len);
277
+
278
+ if (index >= s->input_size) {
279
+ qemu_log_mask(LOG_GUEST_ERROR,
280
+ "%s: SEL index: %u out of range\n",
281
+ __func__, index);
282
+ index = 0;
283
+ }
284
+ clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
285
+}
286
+
287
+static void npcm7xx_clk_update_divider(void *opaque)
288
+{
289
+ NPCM7xxClockDividerState *s = opaque;
290
+ uint32_t freq;
291
+
292
+ freq = s->divide(s);
293
+ clock_update_hz(s->clock_out, freq);
294
+}
295
+
296
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
297
+{
298
+ return clock_get_hz(s->clock_in) / s->divisor;
299
+}
300
+
301
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
302
+{
303
+ return clock_get_hz(s->clock_in) /
304
+ (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
305
+}
306
+
307
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
308
+{
309
+ return divide_by_reg_divisor(s) / 2;
310
+}
311
+
312
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
313
+{
314
+ return clock_get_hz(s->clock_in) >>
315
+ extract32(s->clk->regs[s->reg], s->offset, s->len);
316
+}
317
+
318
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
319
+{
320
+ switch (reg) {
321
+ case NPCM7XX_CLK_PLLCON0:
322
+ return NPCM7XX_CLOCK_PLL0;
323
+ case NPCM7XX_CLK_PLLCON1:
324
+ return NPCM7XX_CLOCK_PLL1;
325
+ case NPCM7XX_CLK_PLLCON2:
326
+ return NPCM7XX_CLOCK_PLL2;
327
+ case NPCM7XX_CLK_PLLCONG:
328
+ return NPCM7XX_CLOCK_PLLG;
329
+ default:
330
+ g_assert_not_reached();
331
+ }
332
+}
333
+
334
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
335
+{
336
+ int i;
337
+
338
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
339
+ npcm7xx_clk_update_pll(&clk->plls[i]);
340
+ }
341
+}
342
+
343
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
344
+{
345
+ int i;
346
+
347
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
348
+ npcm7xx_clk_update_sel(&clk->sels[i]);
349
+ }
350
+}
351
+
352
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
353
+{
354
+ int i;
355
+
356
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
357
+ npcm7xx_clk_update_divider(&clk->dividers[i]);
358
+ }
359
+}
360
+
361
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
362
+{
363
+ clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
364
+ npcm7xx_clk_update_all_plls(clk);
365
+ npcm7xx_clk_update_all_sels(clk);
366
+ npcm7xx_clk_update_all_dividers(clk);
367
+}
368
+
369
+/* Types of clock sources. */
370
+typedef enum ClockSrcType {
371
+ CLKSRC_REF,
372
+ CLKSRC_PLL,
373
+ CLKSRC_SEL,
374
+ CLKSRC_DIV,
375
+} ClockSrcType;
376
+
377
+typedef struct PLLInitInfo {
378
+ const char *name;
379
+ ClockSrcType src_type;
380
+ int src_index;
381
+ int reg;
382
+ const char *public_name;
383
+} PLLInitInfo;
384
+
385
+typedef struct SELInitInfo {
386
+ const char *name;
387
+ uint8_t input_size;
388
+ ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
389
+ int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
390
+ int offset;
391
+ int len;
392
+ const char *public_name;
393
+} SELInitInfo;
394
+
395
+typedef struct DividerInitInfo {
396
+ const char *name;
397
+ ClockSrcType src_type;
398
+ int src_index;
399
+ uint32_t (*divide)(NPCM7xxClockDividerState *s);
400
+ int reg; /* not used when type == CONSTANT */
401
+ int offset; /* not used when type == CONSTANT */
402
+ int len; /* not used when type == CONSTANT */
403
+ int divisor; /* used only when type == CONSTANT */
404
+ const char *public_name;
405
+} DividerInitInfo;
406
+
407
+static const PLLInitInfo pll_init_info_list[] = {
408
+ [NPCM7XX_CLOCK_PLL0] = {
409
+ .name = "pll0",
410
+ .src_type = CLKSRC_REF,
411
+ .reg = NPCM7XX_CLK_PLLCON0,
412
+ },
413
+ [NPCM7XX_CLOCK_PLL1] = {
414
+ .name = "pll1",
415
+ .src_type = CLKSRC_REF,
416
+ .reg = NPCM7XX_CLK_PLLCON1,
417
+ },
418
+ [NPCM7XX_CLOCK_PLL2] = {
419
+ .name = "pll2",
420
+ .src_type = CLKSRC_REF,
421
+ .reg = NPCM7XX_CLK_PLLCON2,
422
+ },
423
+ [NPCM7XX_CLOCK_PLLG] = {
424
+ .name = "pllg",
425
+ .src_type = CLKSRC_REF,
426
+ .reg = NPCM7XX_CLK_PLLCONG,
427
+ },
428
+};
429
+
430
+static const SELInitInfo sel_init_info_list[] = {
431
+ [NPCM7XX_CLOCK_PIXCKSEL] = {
432
+ .name = "pixcksel",
433
+ .input_size = 2,
434
+ .src_type = {CLKSRC_PLL, CLKSRC_REF},
435
+ .src_index = {NPCM7XX_CLOCK_PLLG, 0},
436
+ .offset = 5,
437
+ .len = 1,
438
+ .public_name = "pixel-clock",
439
+ },
440
+ [NPCM7XX_CLOCK_MCCKSEL] = {
441
+ .name = "mccksel",
442
+ .input_size = 4,
443
+ .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
444
+ /*MCBPCK, shouldn't be used in normal operation*/
445
+ CLKSRC_REF},
446
+ .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
447
+ .offset = 12,
448
+ .len = 2,
449
+ .public_name = "mc-phy-clock",
450
+ },
451
+ [NPCM7XX_CLOCK_CPUCKSEL] = {
452
+ .name = "cpucksel",
453
+ .input_size = 4,
454
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
455
+ /*SYSBPCK, shouldn't be used in normal operation*/
456
+ CLKSRC_REF},
457
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
458
+ .offset = 0,
459
+ .len = 2,
460
+ .public_name = "system-clock",
461
+ },
462
+ [NPCM7XX_CLOCK_CLKOUTSEL] = {
463
+ .name = "clkoutsel",
464
+ .input_size = 5,
465
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
466
+ CLKSRC_PLL, CLKSRC_DIV},
467
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
468
+ NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
469
+ .offset = 18,
470
+ .len = 3,
471
+ .public_name = "tock",
472
+ },
473
+ [NPCM7XX_CLOCK_UARTCKSEL] = {
474
+ .name = "uartcksel",
475
+ .input_size = 4,
476
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
477
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
478
+ NPCM7XX_CLOCK_PLL2D2},
479
+ .offset = 8,
480
+ .len = 2,
481
+ },
482
+ [NPCM7XX_CLOCK_TIMCKSEL] = {
483
+ .name = "timcksel",
484
+ .input_size = 4,
485
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
486
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
487
+ NPCM7XX_CLOCK_PLL2D2},
488
+ .offset = 14,
489
+ .len = 2,
490
+ },
491
+ [NPCM7XX_CLOCK_SDCKSEL] = {
492
+ .name = "sdcksel",
493
+ .input_size = 4,
494
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
495
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
496
+ NPCM7XX_CLOCK_PLL2D2},
497
+ .offset = 6,
498
+ .len = 2,
499
+ },
500
+ [NPCM7XX_CLOCK_GFXMSEL] = {
501
+ .name = "gfxmksel",
502
+ .input_size = 2,
503
+ .src_type = {CLKSRC_REF, CLKSRC_PLL},
504
+ .src_index = {0, NPCM7XX_CLOCK_PLL2},
505
+ .offset = 21,
506
+ .len = 1,
507
+ },
508
+ [NPCM7XX_CLOCK_SUCKSEL] = {
509
+ .name = "sucksel",
510
+ .input_size = 4,
511
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
512
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
513
+ NPCM7XX_CLOCK_PLL2D2},
514
+ .offset = 10,
515
+ .len = 2,
516
+ },
517
+};
518
+
519
+static const DividerInitInfo divider_init_info_list[] = {
520
+ [NPCM7XX_CLOCK_PLL1D2] = {
521
+ .name = "pll1d2",
522
+ .src_type = CLKSRC_PLL,
523
+ .src_index = NPCM7XX_CLOCK_PLL1,
524
+ .divide = divide_by_constant,
525
+ .divisor = 2,
526
+ },
527
+ [NPCM7XX_CLOCK_PLL2D2] = {
528
+ .name = "pll2d2",
529
+ .src_type = CLKSRC_PLL,
530
+ .src_index = NPCM7XX_CLOCK_PLL2,
531
+ .divide = divide_by_constant,
532
+ .divisor = 2,
533
+ },
534
+ [NPCM7XX_CLOCK_MC_DIVIDER] = {
535
+ .name = "mc-divider",
536
+ .src_type = CLKSRC_SEL,
537
+ .src_index = NPCM7XX_CLOCK_MCCKSEL,
538
+ .divide = divide_by_constant,
539
+ .divisor = 2,
540
+ .public_name = "mc-clock"
541
+ },
542
+ [NPCM7XX_CLOCK_AXI_DIVIDER] = {
543
+ .name = "axi-divider",
544
+ .src_type = CLKSRC_SEL,
545
+ .src_index = NPCM7XX_CLOCK_CPUCKSEL,
546
+ .divide = shift_by_reg_divisor,
547
+ .reg = NPCM7XX_CLK_CLKDIV1,
548
+ .offset = 0,
549
+ .len = 1,
550
+ .public_name = "clk2"
551
+ },
552
+ [NPCM7XX_CLOCK_AHB_DIVIDER] = {
553
+ .name = "ahb-divider",
554
+ .src_type = CLKSRC_DIV,
555
+ .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
556
+ .divide = divide_by_reg_divisor,
557
+ .reg = NPCM7XX_CLK_CLKDIV1,
558
+ .offset = 26,
559
+ .len = 2,
560
+ .public_name = "clk4"
561
+ },
562
+ [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
563
+ .name = "ahb3-divider",
564
+ .src_type = CLKSRC_DIV,
565
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
566
+ .divide = divide_by_reg_divisor,
567
+ .reg = NPCM7XX_CLK_CLKDIV1,
568
+ .offset = 6,
569
+ .len = 5,
570
+ .public_name = "ahb3-spi3-clock"
571
+ },
572
+ [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
573
+ .name = "spi0-divider",
574
+ .src_type = CLKSRC_DIV,
575
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
576
+ .divide = divide_by_reg_divisor,
577
+ .reg = NPCM7XX_CLK_CLKDIV3,
578
+ .offset = 6,
579
+ .len = 5,
580
+ .public_name = "spi0-clock",
581
+ },
582
+ [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
583
+ .name = "spix-divider",
584
+ .src_type = CLKSRC_DIV,
585
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
586
+ .divide = divide_by_reg_divisor,
587
+ .reg = NPCM7XX_CLK_CLKDIV3,
588
+ .offset = 1,
589
+ .len = 5,
590
+ .public_name = "spix-clock",
591
+ },
592
+ [NPCM7XX_CLOCK_APB1_DIVIDER] = {
593
+ .name = "apb1-divider",
594
+ .src_type = CLKSRC_DIV,
595
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
596
+ .divide = shift_by_reg_divisor,
597
+ .reg = NPCM7XX_CLK_CLKDIV2,
598
+ .offset = 24,
599
+ .len = 2,
600
+ .public_name = "apb1-clock",
601
+ },
602
+ [NPCM7XX_CLOCK_APB2_DIVIDER] = {
603
+ .name = "apb2-divider",
604
+ .src_type = CLKSRC_DIV,
605
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
606
+ .divide = shift_by_reg_divisor,
607
+ .reg = NPCM7XX_CLK_CLKDIV2,
608
+ .offset = 26,
609
+ .len = 2,
610
+ .public_name = "apb2-clock",
611
+ },
612
+ [NPCM7XX_CLOCK_APB3_DIVIDER] = {
613
+ .name = "apb3-divider",
614
+ .src_type = CLKSRC_DIV,
615
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
616
+ .divide = shift_by_reg_divisor,
617
+ .reg = NPCM7XX_CLK_CLKDIV2,
618
+ .offset = 28,
619
+ .len = 2,
620
+ .public_name = "apb3-clock",
621
+ },
622
+ [NPCM7XX_CLOCK_APB4_DIVIDER] = {
623
+ .name = "apb4-divider",
624
+ .src_type = CLKSRC_DIV,
625
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
626
+ .divide = shift_by_reg_divisor,
627
+ .reg = NPCM7XX_CLK_CLKDIV2,
628
+ .offset = 30,
629
+ .len = 2,
630
+ .public_name = "apb4-clock",
631
+ },
632
+ [NPCM7XX_CLOCK_APB5_DIVIDER] = {
633
+ .name = "apb5-divider",
634
+ .src_type = CLKSRC_DIV,
635
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
636
+ .divide = shift_by_reg_divisor,
637
+ .reg = NPCM7XX_CLK_CLKDIV2,
638
+ .offset = 22,
639
+ .len = 2,
640
+ .public_name = "apb5-clock",
641
+ },
642
+ [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
643
+ .name = "clkout-divider",
644
+ .src_type = CLKSRC_SEL,
645
+ .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
646
+ .divide = divide_by_reg_divisor,
647
+ .reg = NPCM7XX_CLK_CLKDIV2,
648
+ .offset = 16,
649
+ .len = 5,
650
+ .public_name = "clkout",
651
+ },
652
+ [NPCM7XX_CLOCK_UART_DIVIDER] = {
653
+ .name = "uart-divider",
654
+ .src_type = CLKSRC_SEL,
655
+ .src_index = NPCM7XX_CLOCK_UARTCKSEL,
656
+ .divide = divide_by_reg_divisor,
657
+ .reg = NPCM7XX_CLK_CLKDIV1,
658
+ .offset = 16,
659
+ .len = 5,
660
+ .public_name = "uart-clock",
661
+ },
662
+ [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
663
+ .name = "timer-divider",
664
+ .src_type = CLKSRC_SEL,
665
+ .src_index = NPCM7XX_CLOCK_TIMCKSEL,
666
+ .divide = divide_by_reg_divisor,
667
+ .reg = NPCM7XX_CLK_CLKDIV1,
668
+ .offset = 21,
669
+ .len = 5,
670
+ .public_name = "timer-clock",
671
+ },
672
+ [NPCM7XX_CLOCK_ADC_DIVIDER] = {
673
+ .name = "adc-divider",
674
+ .src_type = CLKSRC_DIV,
675
+ .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
676
+ .divide = shift_by_reg_divisor,
677
+ .reg = NPCM7XX_CLK_CLKDIV1,
678
+ .offset = 28,
679
+ .len = 3,
680
+ .public_name = "adc-clock",
681
+ },
682
+ [NPCM7XX_CLOCK_MMC_DIVIDER] = {
683
+ .name = "mmc-divider",
684
+ .src_type = CLKSRC_SEL,
685
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
686
+ .divide = divide_by_reg_divisor,
687
+ .reg = NPCM7XX_CLK_CLKDIV1,
688
+ .offset = 11,
689
+ .len = 5,
690
+ .public_name = "mmc-clock",
691
+ },
692
+ [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
693
+ .name = "sdhc-divider",
694
+ .src_type = CLKSRC_SEL,
695
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
696
+ .divide = divide_by_reg_divisor_times_2,
697
+ .reg = NPCM7XX_CLK_CLKDIV2,
698
+ .offset = 0,
699
+ .len = 4,
700
+ .public_name = "sdhc-clock",
701
+ },
702
+ [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
703
+ .name = "gfxm-divider",
704
+ .src_type = CLKSRC_SEL,
705
+ .src_index = NPCM7XX_CLOCK_GFXMSEL,
706
+ .divide = divide_by_constant,
707
+ .divisor = 3,
708
+ .public_name = "gfxm-clock",
709
+ },
710
+ [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
711
+ .name = "utmi-divider",
712
+ .src_type = CLKSRC_SEL,
713
+ .src_index = NPCM7XX_CLOCK_SUCKSEL,
714
+ .divide = divide_by_reg_divisor,
715
+ .reg = NPCM7XX_CLK_CLKDIV2,
716
+ .offset = 8,
717
+ .len = 5,
718
+ .public_name = "utmi-clock",
719
+ },
720
+};
721
+
722
+static void npcm7xx_clk_pll_init(Object *obj)
723
+{
724
+ NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
725
+
726
+ pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
727
+ npcm7xx_clk_update_pll, pll);
728
+ pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
729
+}
730
+
731
+static void npcm7xx_clk_sel_init(Object *obj)
732
+{
733
+ int i;
734
+ NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
735
+
736
+ for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
737
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
738
+ g_strdup_printf("clock-in[%d]", i),
739
+ npcm7xx_clk_update_sel, sel);
740
+ }
741
+ sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
742
+}
743
+static void npcm7xx_clk_divider_init(Object *obj)
744
+{
745
+ NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
746
+
747
+ div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
748
+ npcm7xx_clk_update_divider, div);
749
+ div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
750
+}
751
+
752
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
753
+ NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
754
+{
755
+ pll->name = init_info->name;
756
+ pll->clk = clk;
757
+ pll->reg = init_info->reg;
758
+ if (init_info->public_name != NULL) {
759
+ qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
760
+ init_info->public_name);
761
+ }
762
+}
763
+
764
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
765
+ NPCM7xxCLKState *clk, const SELInitInfo *init_info)
766
+{
767
+ int input_size = init_info->input_size;
768
+
769
+ sel->name = init_info->name;
770
+ sel->clk = clk;
771
+ sel->input_size = init_info->input_size;
772
+ g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
773
+ sel->offset = init_info->offset;
774
+ sel->len = init_info->len;
775
+ if (init_info->public_name != NULL) {
776
+ qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
777
+ init_info->public_name);
778
+ }
779
+}
780
+
781
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
782
+ NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
783
+{
784
+ div->name = init_info->name;
785
+ div->clk = clk;
786
+
787
+ div->divide = init_info->divide;
788
+ if (div->divide == divide_by_constant) {
789
+ div->divisor = init_info->divisor;
790
+ } else {
791
+ div->reg = init_info->reg;
792
+ div->offset = init_info->offset;
793
+ div->len = init_info->len;
794
+ }
795
+ if (init_info->public_name != NULL) {
796
+ qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
797
+ init_info->public_name);
798
+ }
799
+}
800
+
801
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
802
+ int index)
803
+{
804
+ switch (type) {
805
+ case CLKSRC_REF:
806
+ return clk->clkref;
807
+ case CLKSRC_PLL:
808
+ return clk->plls[index].clock_out;
809
+ case CLKSRC_SEL:
810
+ return clk->sels[index].clock_out;
811
+ case CLKSRC_DIV:
812
+ return clk->dividers[index].clock_out;
813
+ default:
814
+ g_assert_not_reached();
815
+ }
816
+}
817
+
818
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
819
+{
820
+ int i, j;
821
+ Clock *src;
822
+
823
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
824
+ src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
825
+ pll_init_info_list[i].src_index);
826
+ clock_set_source(clk->plls[i].clock_in, src);
827
+ }
828
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
829
+ for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
830
+ src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
831
+ sel_init_info_list[i].src_index[j]);
832
+ clock_set_source(clk->sels[i].clock_in[j], src);
833
+ }
834
+ }
835
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
836
+ src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
837
+ divider_init_info_list[i].src_index);
838
+ clock_set_source(clk->dividers[i].clock_in, src);
839
+ }
840
+}
841
+
842
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
99
{
843
{
100
BitBandState *s = BITBAND(obj);
844
uint32_t reg = offset / sizeof(uint32_t);
101
@@ -XXX,XX +XXX,XX @@ static void armv7m_bitband_init(void)
845
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
102
846
*
103
/* Board init. */
847
* The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
104
848
*/
105
+static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
849
- value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
106
+ 0x20000000, 0x40000000
850
+ value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
107
+};
851
break;
108
+
852
109
+static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
853
default:
110
+ 0x22000000, 0x42000000
854
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
111
+};
855
value |= (value & PLLCON_LOKS);
112
+
856
}
113
+static void armv7m_instance_init(Object *obj)
857
}
114
+{
858
+ /* Only update PLL when it is locked. */
115
+ ARMv7MState *s = ARMV7M(obj);
859
+ if (value & PLLCON_LOKI) {
860
+ npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
861
+ }
862
+ break;
863
+
864
+ case NPCM7XX_CLK_CLKSEL:
865
+ npcm7xx_clk_update_all_sels(s);
866
+ break;
867
+
868
+ case NPCM7XX_CLK_CLKDIV1:
869
+ case NPCM7XX_CLK_CLKDIV2:
870
+ case NPCM7XX_CLK_CLKDIV3:
871
+ npcm7xx_clk_update_all_dividers(s);
872
break;
873
874
case NPCM7XX_CLK_CNTR25M:
875
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
876
case RESET_TYPE_COLD:
877
memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
878
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
879
+ npcm7xx_clk_update_all_clocks(s);
880
return;
881
}
882
883
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
884
__func__, type);
885
}
886
887
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
888
+{
116
+ int i;
889
+ int i;
117
+
890
+
118
+ /* Can't init the cpu here, we don't yet know which model to use */
891
+ s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
119
+
892
+
120
+ object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
893
+ /* First pass: init all converter modules */
121
+ qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
894
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
122
+ object_property_add_alias(obj, "num-irq",
895
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
123
+ OBJECT(&s->nvic), "num-irq", &error_abort);
896
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
124
+
897
+ != NPCM7XX_CLOCK_NR_DIVIDERS);
125
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
898
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
126
+ object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
899
+ object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
127
+ qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
900
+ &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
128
+ }
901
+ npcm7xx_init_clock_pll(&s->plls[i], s,
129
+}
902
+ &pll_init_info_list[i]);
130
+
903
+ }
131
+static void armv7m_realize(DeviceState *dev, Error **errp)
904
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
132
+{
905
+ object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
133
+ ARMv7MState *s = ARMV7M(dev);
906
+ &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
134
+ Error *err = NULL;
907
+ npcm7xx_init_clock_sel(&s->sels[i], s,
908
+ &sel_init_info_list[i]);
909
+ }
910
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
911
+ object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
912
+ &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
913
+ npcm7xx_init_clock_divider(&s->dividers[i], s,
914
+ &divider_init_info_list[i]);
915
+ }
916
+
917
+ /* Second pass: connect converter modules */
918
+ npcm7xx_connect_clocks(s);
919
+
920
+ clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
921
+}
922
+
923
static void npcm7xx_clk_init(Object *obj)
924
{
925
NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
926
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
927
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
928
TYPE_NPCM7XX_CLK, 4 * KiB);
929
sysbus_init_mmio(&s->parent, &s->iomem);
930
- qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
931
- NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
932
}
933
934
-static const VMStateDescription vmstate_npcm7xx_clk = {
935
- .name = "npcm7xx-clk",
936
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
937
+{
938
+ if (version_id >= 1) {
939
+ NPCM7xxCLKState *clk = opaque;
940
+
941
+ npcm7xx_clk_update_all_clocks(clk);
942
+ }
943
+
944
+ return 0;
945
+}
946
+
947
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
948
+{
135
+ int i;
949
+ int i;
136
+ char **cpustr;
950
+ NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
137
+ ObjectClass *oc;
951
+
138
+ const char *typename;
952
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
139
+ CPUClass *cc;
953
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
140
+
954
+ npcm7xx_clk_init_clock_hierarchy(s);
141
+ cpustr = g_strsplit(s->cpu_model, ",", 2);
955
+
142
+
956
+ /* Realize child devices */
143
+ oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
957
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
144
+ if (!oc) {
958
+ if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
145
+ error_setg(errp, "Unknown CPU model %s", cpustr[0]);
146
+ g_strfreev(cpustr);
147
+ return;
148
+ }
149
+
150
+ cc = CPU_CLASS(oc);
151
+ typename = object_class_get_name(oc);
152
+ cc->parse_features(typename, cpustr[1], &err);
153
+ g_strfreev(cpustr);
154
+ if (err) {
155
+ error_propagate(errp, err);
156
+ return;
157
+ }
158
+
159
+ s->cpu = ARM_CPU(object_new(typename));
160
+ if (!s->cpu) {
161
+ error_setg(errp, "Unknown CPU model %s", s->cpu_model);
162
+ return;
163
+ }
164
+
165
+ object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
166
+ if (err != NULL) {
167
+ error_propagate(errp, err);
168
+ return;
169
+ }
170
+
171
+ /* Note that we must realize the NVIC after the CPU */
172
+ object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
173
+ if (err != NULL) {
174
+ error_propagate(errp, err);
175
+ return;
176
+ }
177
+
178
+ /* Alias the NVIC's input and output GPIOs as our own so the board
179
+ * code can wire them up. (We do this in realize because the
180
+ * NVIC doesn't create the input GPIO array until realize.)
181
+ */
182
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
183
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
184
+
185
+ /* Wire the NVIC up to the CPU */
186
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
187
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
188
+ s->cpu->env.nvic = &s->nvic;
189
+
190
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
191
+ Object *obj = OBJECT(&s->bitband[i]);
192
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
193
+
194
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
195
+ if (err != NULL) {
196
+ error_propagate(errp, err);
197
+ return;
959
+ return;
198
+ }
960
+ }
199
+ object_property_set_bool(obj, true, "realized", &err);
961
+ }
200
+ if (err != NULL) {
962
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
201
+ error_propagate(errp, err);
963
+ if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
202
+ return;
964
+ return;
203
+ }
965
+ }
204
+
966
+ }
205
+ sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
967
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
206
+ }
968
+ if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
207
+}
969
+ return;
208
+
970
+ }
209
+static Property armv7m_properties[] = {
971
+ }
210
+ DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
972
+}
211
+ DEFINE_PROP_END_OF_LIST(),
973
+
974
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
975
+ .name = "npcm7xx-clock-pll",
976
.version_id = 0,
977
.minimum_version_id = 0,
978
- .fields = (VMStateField[]) {
979
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
980
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
981
+ .fields = (VMStateField[]) {
982
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
983
VMSTATE_END_OF_LIST(),
984
},
985
};
986
987
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
988
+ .name = "npcm7xx-clock-sel",
989
+ .version_id = 0,
990
+ .minimum_version_id = 0,
991
+ .fields = (VMStateField[]) {
992
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
993
+ NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
994
+ VMSTATE_END_OF_LIST(),
995
+ },
212
+};
996
+};
213
+
997
+
214
+static void armv7m_class_init(ObjectClass *klass, void *data)
998
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
999
+ .name = "npcm7xx-clock-divider",
1000
+ .version_id = 0,
1001
+ .minimum_version_id = 0,
1002
+ .fields = (VMStateField[]) {
1003
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
1004
+ VMSTATE_END_OF_LIST(),
1005
+ },
1006
+};
1007
+
1008
+static const VMStateDescription vmstate_npcm7xx_clk = {
1009
+ .name = "npcm7xx-clk",
1010
+ .version_id = 1,
1011
+ .minimum_version_id = 1,
1012
+ .post_load = npcm7xx_clk_post_load,
1013
+ .fields = (VMStateField[]) {
1014
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
1015
+ VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
1016
+ VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
1017
+ VMSTATE_END_OF_LIST(),
1018
+ },
1019
+};
1020
+
1021
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
215
+{
1022
+{
216
+ DeviceClass *dc = DEVICE_CLASS(klass);
1023
+ DeviceClass *dc = DEVICE_CLASS(klass);
217
+
1024
+
218
+ dc->realize = armv7m_realize;
1025
+ dc->desc = "NPCM7xx Clock PLL Module";
219
+ dc->props = armv7m_properties;
1026
+ dc->vmsd = &vmstate_npcm7xx_clk_pll;
220
+}
1027
+}
221
+
1028
+
222
+static const TypeInfo armv7m_info = {
1029
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
223
+ .name = TYPE_ARMV7M,
1030
+{
224
+ .parent = TYPE_SYS_BUS_DEVICE,
1031
+ DeviceClass *dc = DEVICE_CLASS(klass);
225
+ .instance_size = sizeof(ARMv7MState),
1032
+
226
+ .instance_init = armv7m_instance_init,
1033
+ dc->desc = "NPCM7xx Clock SEL Module";
227
+ .class_init = armv7m_class_init,
1034
+ dc->vmsd = &vmstate_npcm7xx_clk_sel;
1035
+}
1036
+
1037
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
1038
+{
1039
+ DeviceClass *dc = DEVICE_CLASS(klass);
1040
+
1041
+ dc->desc = "NPCM7xx Clock Divider Module";
1042
+ dc->vmsd = &vmstate_npcm7xx_clk_divider;
1043
+}
1044
+
1045
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1046
{
1047
ResettableClass *rc = RESETTABLE_CLASS(klass);
1048
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1049
1050
dc->desc = "NPCM7xx Clock Control Registers";
1051
dc->vmsd = &vmstate_npcm7xx_clk;
1052
+ dc->realize = npcm7xx_clk_realize;
1053
rc->phases.enter = npcm7xx_clk_enter_reset;
1054
}
1055
1056
+static const TypeInfo npcm7xx_clk_pll_info = {
1057
+ .name = TYPE_NPCM7XX_CLOCK_PLL,
1058
+ .parent = TYPE_DEVICE,
1059
+ .instance_size = sizeof(NPCM7xxClockPLLState),
1060
+ .instance_init = npcm7xx_clk_pll_init,
1061
+ .class_init = npcm7xx_clk_pll_class_init,
228
+};
1062
+};
229
+
1063
+
230
static void armv7m_reset(void *opaque)
1064
+static const TypeInfo npcm7xx_clk_sel_info = {
1065
+ .name = TYPE_NPCM7XX_CLOCK_SEL,
1066
+ .parent = TYPE_DEVICE,
1067
+ .instance_size = sizeof(NPCM7xxClockSELState),
1068
+ .instance_init = npcm7xx_clk_sel_init,
1069
+ .class_init = npcm7xx_clk_sel_class_init,
1070
+};
1071
+
1072
+static const TypeInfo npcm7xx_clk_divider_info = {
1073
+ .name = TYPE_NPCM7XX_CLOCK_DIVIDER,
1074
+ .parent = TYPE_DEVICE,
1075
+ .instance_size = sizeof(NPCM7xxClockDividerState),
1076
+ .instance_init = npcm7xx_clk_divider_init,
1077
+ .class_init = npcm7xx_clk_divider_class_init,
1078
+};
1079
+
1080
static const TypeInfo npcm7xx_clk_info = {
1081
.name = TYPE_NPCM7XX_CLK,
1082
.parent = TYPE_SYS_BUS_DEVICE,
1083
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
1084
1085
static void npcm7xx_clk_register_type(void)
231
{
1086
{
232
ARMCPU *cpu = opaque;
1087
+ type_register_static(&npcm7xx_clk_pll_info);
233
@@ -XXX,XX +XXX,XX @@ static const TypeInfo bitband_info = {
1088
+ type_register_static(&npcm7xx_clk_sel_info);
234
static void armv7m_register_types(void)
1089
+ type_register_static(&npcm7xx_clk_divider_info);
235
{
1090
type_register_static(&npcm7xx_clk_info);
236
type_register_static(&bitband_info);
237
+ type_register_static(&armv7m_info);
238
}
1091
}
239
1092
type_init(npcm7xx_clk_register_type);
240
type_init(armv7m_register_types)
241
--
1093
--
242
2.7.4
1094
2.20.1
243
1095
244
1096
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
This actually implements pre_save and post_load methods for in-kernel
3
This patch makes NPCM7XX Timer to use a the timer clock generated by the
4
vGICv3.
4
CLK module instead of the magic number TIMER_REF_HZ.
5
5
6
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
9
Message-id: 20210108190945.949196-3-wuhaotsh@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
10
Message-id: 1487850673-26455-4-git-send-email-vijay.kilari@gmail.com
11
[PMM:
12
* use decimal, not 0bnnn
13
* fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1
14
* completely rearranged the get and put functions to read and write
15
the state in a natural order, rather than mixing distributor and
16
redistributor state together]
17
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
18
[Vijay:
19
* Update macro KVM_VGIC_ATTR
20
* Use 32 bit access for gicd and gicr
21
* GICD_IROUTER, GICD_TYPER, GICR_PROPBASER and GICR_PENDBASER reg
22
access are changed from 64-bit to 32-bit access
23
* Add ICC_SRE_EL1 save and restore
24
* Dropped translate_fn mechanism and coded functions to handle
25
save and restore of edge_trigger and priority
26
* Number of APnR register saved/restored based on number of
27
priority bits supported]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
---
12
---
30
hw/intc/gicv3_internal.h | 1 +
13
include/hw/misc/npcm7xx_clk.h | 6 -----
31
hw/intc/arm_gicv3_kvm.c | 573 +++++++++++++++++++++++++++++++++++++++++++++--
14
include/hw/timer/npcm7xx_timer.h | 1 +
32
2 files changed, 558 insertions(+), 16 deletions(-)
15
hw/arm/npcm7xx.c | 5 ++++
16
hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------
17
4 files changed, 24 insertions(+), 27 deletions(-)
33
18
34
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
19
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
35
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/intc/gicv3_internal.h
21
--- a/include/hw/misc/npcm7xx_clk.h
37
+++ b/hw/intc/gicv3_internal.h
22
+++ b/include/hw/misc/npcm7xx_clk.h
38
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
39
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
24
#include "hw/clock.h"
40
#define ICC_CTLR_EL1_PMHE (1U << 6)
25
#include "hw/sysbus.h"
41
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
26
42
+#define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
27
-/*
43
#define ICC_CTLR_EL1_IDBITS_SHIFT 11
28
- * The reference clock frequency for the timer modules, and the SECCNT and
44
#define ICC_CTLR_EL1_SEIS (1U << 14)
29
- * CNTR25M registers in this module, is always 25 MHz.
45
#define ICC_CTLR_EL1_A3V (1U << 15)
30
- */
46
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
31
-#define NPCM7XX_TIMER_REF_HZ (25000000)
32
-
33
/*
34
* Number of registers in our device state structure. Don't change this without
35
* incrementing the version_id in the vmstate.
36
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
47
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_kvm.c
38
--- a/include/hw/timer/npcm7xx_timer.h
49
+++ b/hw/intc/arm_gicv3_kvm.c
39
+++ b/include/hw/timer/npcm7xx_timer.h
40
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
41
42
uint32_t tisr;
43
44
+ Clock *clock;
45
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
46
NPCM7xxWatchdogTimer watchdog_timer;
47
};
48
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/npcm7xx.c
51
+++ b/hw/arm/npcm7xx.c
50
@@ -XXX,XX +XXX,XX @@
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/char/serial.h"
54
#include "hw/loader.h"
55
#include "hw/misc/unimp.h"
56
+#include "hw/qdev-clock.h"
57
#include "hw/qdev-properties.h"
51
#include "qapi/error.h"
58
#include "qapi/error.h"
52
#include "hw/intc/arm_gicv3_common.h"
59
#include "qemu/units.h"
53
#include "hw/sysbus.h"
60
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
54
+#include "qemu/error-report.h"
61
int first_irq;
55
#include "sysemu/kvm.h"
62
int j;
56
#include "kvm_arm.h"
63
57
+#include "gicv3_internal.h"
64
+ /* Connect the timer clock. */
58
#include "vgic_common.h"
65
+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
59
#include "migration/migration.h"
66
+ DEVICE(&s->clk), "timer-clock"));
60
67
+
68
sysbus_realize(sbd, &error_abort);
69
sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
70
71
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/timer/npcm7xx_timer.c
74
+++ b/hw/timer/npcm7xx_timer.c
61
@@ -XXX,XX +XXX,XX @@
75
@@ -XXX,XX +XXX,XX @@
62
#define KVM_ARM_GICV3_GET_CLASS(obj) \
76
#include "qemu/osdep.h"
63
OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
77
64
78
#include "hw/irq.h"
65
+#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
79
+#include "hw/qdev-clock.h"
66
+ (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
80
#include "hw/qdev-properties.h"
67
+ ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
81
-#include "hw/misc/npcm7xx_clk.h"
68
+ ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
82
#include "hw/timer/npcm7xx_timer.h"
69
+ ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
83
#include "migration/vmstate.h"
70
+ ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
84
#include "qemu/bitops.h"
71
+
85
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
72
+#define ICC_PMR_EL1 \
86
/* Convert a timer cycle count to a time interval in nanoseconds. */
73
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
87
static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
74
+#define ICC_BPR0_EL1 \
88
{
75
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
89
- int64_t ns = count;
76
+#define ICC_AP0R_EL1(n) \
90
+ int64_t ticks = count;
77
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
91
78
+#define ICC_AP1R_EL1(n) \
92
- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
79
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
93
- ns *= npcm7xx_tcsr_prescaler(t->tcsr);
80
+#define ICC_BPR1_EL1 \
94
+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
81
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
95
82
+#define ICC_CTLR_EL1 \
96
- return ns;
83
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
97
+ return clock_ticks_to_ns(t->ctrl->clock, ticks);
84
+#define ICC_SRE_EL1 \
85
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
86
+#define ICC_IGRPEN0_EL1 \
87
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
88
+#define ICC_IGRPEN1_EL1 \
89
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
90
+
91
typedef struct KVMARMGICv3Class {
92
ARMGICv3CommonClass parent_class;
93
DeviceRealize parent_realize;
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
95
kvm_arm_gic_set_irq(s->num_irq, irq, level);
96
}
98
}
97
99
98
+#define KVM_VGIC_ATTR(reg, typer) \
100
/* Convert a time interval in nanoseconds to a timer cycle count. */
99
+ ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
101
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
100
+
101
+static inline void kvm_gicd_access(GICv3State *s, int offset,
102
+ uint32_t *val, bool write)
103
+{
104
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
105
+ KVM_VGIC_ATTR(offset, 0),
106
+ val, write);
107
+}
108
+
109
+static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
110
+ uint32_t *val, bool write)
111
+{
112
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
113
+ KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
114
+ val, write);
115
+}
116
+
117
+static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
118
+ uint64_t *val, bool write)
119
+{
120
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
121
+ KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
122
+ val, write);
123
+}
124
+
125
+static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
126
+ uint32_t *val, bool write)
127
+{
128
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
129
+ KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
130
+ (VGIC_LEVEL_INFO_LINE_LEVEL <<
131
+ KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
132
+ val, write);
133
+}
134
+
135
+/* Loop through each distributor IRQ related register; since bits
136
+ * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
137
+ * is enabled, we skip those.
138
+ */
139
+#define for_each_dist_irq_reg(_irq, _max, _field_width) \
140
+ for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
141
+
142
+static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
143
+{
144
+ uint32_t reg, *field;
145
+ int irq;
146
+
147
+ field = (uint32_t *)bmp;
148
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
149
+ kvm_gicd_access(s, offset, &reg, false);
150
+ *field = reg;
151
+ offset += 4;
152
+ field++;
153
+ }
154
+}
155
+
156
+static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
157
+{
158
+ uint32_t reg, *field;
159
+ int irq;
160
+
161
+ field = (uint32_t *)bmp;
162
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
163
+ reg = *field;
164
+ kvm_gicd_access(s, offset, &reg, true);
165
+ offset += 4;
166
+ field++;
167
+ }
168
+}
169
+
170
+static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
171
+ uint32_t *bmp)
172
+{
173
+ uint32_t reg;
174
+ int irq;
175
+
176
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
177
+ kvm_gicd_access(s, offset, &reg, false);
178
+ reg = half_unshuffle32(reg >> 1);
179
+ if (irq % 32 != 0) {
180
+ reg = (reg << 16);
181
+ }
182
+ *gic_bmp_ptr32(bmp, irq) |= reg;
183
+ offset += 4;
184
+ }
185
+}
186
+
187
+static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
188
+ uint32_t *bmp)
189
+{
190
+ uint32_t reg;
191
+ int irq;
192
+
193
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
194
+ reg = *gic_bmp_ptr32(bmp, irq);
195
+ if (irq % 32 != 0) {
196
+ reg = (reg & 0xffff0000) >> 16;
197
+ } else {
198
+ reg = reg & 0xffff;
199
+ }
200
+ reg = half_shuffle32(reg) << 1;
201
+ kvm_gicd_access(s, offset, &reg, true);
202
+ offset += 4;
203
+ }
204
+}
205
+
206
+static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
207
+{
208
+ uint32_t reg;
209
+ int irq;
210
+
211
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
212
+ kvm_gic_line_level_access(s, irq, 0, &reg, false);
213
+ *gic_bmp_ptr32(bmp, irq) = reg;
214
+ }
215
+}
216
+
217
+static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
218
+{
219
+ uint32_t reg;
220
+ int irq;
221
+
222
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
223
+ reg = *gic_bmp_ptr32(bmp, irq);
224
+ kvm_gic_line_level_access(s, irq, 0, &reg, true);
225
+ }
226
+}
227
+
228
+/* Read a bitmap register group from the kernel VGIC. */
229
+static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
230
+{
231
+ uint32_t reg;
232
+ int irq;
233
+
234
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
235
+ kvm_gicd_access(s, offset, &reg, false);
236
+ *gic_bmp_ptr32(bmp, irq) = reg;
237
+ offset += 4;
238
+ }
239
+}
240
+
241
+static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
242
+ uint32_t clroffset, uint32_t *bmp)
243
+{
244
+ uint32_t reg;
245
+ int irq;
246
+
247
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
248
+ /* If this bitmap is a set/clear register pair, first write to the
249
+ * clear-reg to clear all bits before using the set-reg to write
250
+ * the 1 bits.
251
+ */
252
+ if (clroffset != 0) {
253
+ reg = 0;
254
+ kvm_gicd_access(s, clroffset, &reg, true);
255
+ }
256
+ reg = *gic_bmp_ptr32(bmp, irq);
257
+ kvm_gicd_access(s, offset, &reg, true);
258
+ offset += 4;
259
+ }
260
+}
261
+
262
+static void kvm_arm_gicv3_check(GICv3State *s)
263
+{
264
+ uint32_t reg;
265
+ uint32_t num_irq;
266
+
267
+ /* Sanity checking s->num_irq */
268
+ kvm_gicd_access(s, GICD_TYPER, &reg, false);
269
+ num_irq = ((reg & 0x1f) + 1) * 32;
270
+
271
+ if (num_irq < s->num_irq) {
272
+ error_report("Model requests %u IRQs, but kernel supports max %u",
273
+ s->num_irq, num_irq);
274
+ abort();
275
+ }
276
+}
277
+
278
static void kvm_arm_gicv3_put(GICv3State *s)
279
{
102
{
280
- /* TODO */
103
- int64_t count;
281
- DPRINTF("Cannot put kernel gic state, no kernel interface\n");
104
-
282
+ uint32_t regl, regh, reg;
105
- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
283
+ uint64_t reg64, redist_typer;
106
- count /= npcm7xx_tcsr_prescaler(t->tcsr);
284
+ int ncpu, i;
107
-
285
+
108
- return count;
286
+ kvm_arm_gicv3_check(s);
109
+ return ns / clock_ticks_to_ns(t->ctrl->clock,
287
+
110
+ npcm7xx_tcsr_prescaler(t->tcsr));
288
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
289
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
290
+ redist_typer = ((uint64_t)regh << 32) | regl;
291
+
292
+ reg = s->gicd_ctlr;
293
+ kvm_gicd_access(s, GICD_CTLR, &reg, true);
294
+
295
+ if (redist_typer & GICR_TYPER_PLPIS) {
296
+ /* Set base addresses before LPIs are enabled by GICR_CTLR write */
297
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
298
+ GICv3CPUState *c = &s->cpu[ncpu];
299
+
300
+ reg64 = c->gicr_propbaser;
301
+ regl = (uint32_t)reg64;
302
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, true);
303
+ regh = (uint32_t)(reg64 >> 32);
304
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
305
+
306
+ reg64 = c->gicr_pendbaser;
307
+ if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
308
+ /* Setting PTZ is advised if LPIs are disabled, to reduce
309
+ * GIC initialization time.
310
+ */
311
+ reg64 |= GICR_PENDBASER_PTZ;
312
+ }
313
+ regl = (uint32_t)reg64;
314
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
315
+ regh = (uint32_t)(reg64 >> 32);
316
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, true);
317
+ }
318
+ }
319
+
320
+ /* Redistributor state (one per CPU) */
321
+
322
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
323
+ GICv3CPUState *c = &s->cpu[ncpu];
324
+
325
+ reg = c->gicr_ctlr;
326
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, true);
327
+
328
+ reg = c->gicr_statusr[GICV3_NS];
329
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, true);
330
+
331
+ reg = c->gicr_waker;
332
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, true);
333
+
334
+ reg = c->gicr_igroupr0;
335
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, true);
336
+
337
+ reg = ~0;
338
+ kvm_gicr_access(s, GICR_ICENABLER0, ncpu, &reg, true);
339
+ reg = c->gicr_ienabler0;
340
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, true);
341
+
342
+ /* Restore config before pending so we treat level/edge correctly */
343
+ reg = half_shuffle32(c->edge_trigger >> 16) << 1;
344
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, true);
345
+
346
+ reg = c->level;
347
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, true);
348
+
349
+ reg = ~0;
350
+ kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true);
351
+ reg = c->gicr_ipendr0;
352
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true);
353
+
354
+ reg = ~0;
355
+ kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, &reg, true);
356
+ reg = c->gicr_iactiver0;
357
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true);
358
+
359
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
360
+ reg = c->gicr_ipriorityr[i] |
361
+ (c->gicr_ipriorityr[i + 1] << 8) |
362
+ (c->gicr_ipriorityr[i + 2] << 16) |
363
+ (c->gicr_ipriorityr[i + 3] << 24);
364
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, true);
365
+ }
366
+ }
367
+
368
+ /* Distributor state (shared between all CPUs */
369
+ reg = s->gicd_statusr[GICV3_NS];
370
+ kvm_gicd_access(s, GICD_STATUSR, &reg, true);
371
+
372
+ /* s->enable bitmap -> GICD_ISENABLERn */
373
+ kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
374
+
375
+ /* s->group bitmap -> GICD_IGROUPRn */
376
+ kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
377
+
378
+ /* Restore targets before pending to ensure the pending state is set on
379
+ * the appropriate CPU interfaces in the kernel
380
+ */
381
+
382
+ /* s->gicd_irouter[irq] -> GICD_IROUTERn
383
+ * We can't use kvm_dist_put() here because the registers are 64-bit
384
+ */
385
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
386
+ uint32_t offset;
387
+
388
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
389
+ reg = (uint32_t)s->gicd_irouter[i];
390
+ kvm_gicd_access(s, offset, &reg, true);
391
+
392
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
393
+ reg = (uint32_t)(s->gicd_irouter[i] >> 32);
394
+ kvm_gicd_access(s, offset, &reg, true);
395
+ }
396
+
397
+ /* s->trigger bitmap -> GICD_ICFGRn
398
+ * (restore configuration registers before pending IRQs so we treat
399
+ * level/edge correctly)
400
+ */
401
+ kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
402
+
403
+ /* s->level bitmap -> line_level */
404
+ kvm_gic_put_line_level_bmp(s, s->level);
405
+
406
+ /* s->pending bitmap -> GICD_ISPENDRn */
407
+ kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
408
+
409
+ /* s->active bitmap -> GICD_ISACTIVERn */
410
+ kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
411
+
412
+ /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
413
+ kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
414
+
415
+ /* CPU Interface state (one per CPU) */
416
+
417
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
418
+ GICv3CPUState *c = &s->cpu[ncpu];
419
+ int num_pri_bits;
420
+
421
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
422
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
423
+ &c->icc_ctlr_el1[GICV3_NS], true);
424
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
425
+ &c->icc_igrpen[GICV3_G0], true);
426
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
427
+ &c->icc_igrpen[GICV3_G1NS], true);
428
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
429
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
430
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
431
+
432
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
433
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
434
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
435
+
436
+ switch (num_pri_bits) {
437
+ case 7:
438
+ reg64 = c->icc_apr[GICV3_G0][3];
439
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, true);
440
+ reg64 = c->icc_apr[GICV3_G0][2];
441
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, true);
442
+ case 6:
443
+ reg64 = c->icc_apr[GICV3_G0][1];
444
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, true);
445
+ default:
446
+ reg64 = c->icc_apr[GICV3_G0][0];
447
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, true);
448
+ }
449
+
450
+ switch (num_pri_bits) {
451
+ case 7:
452
+ reg64 = c->icc_apr[GICV3_G1NS][3];
453
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true);
454
+ reg64 = c->icc_apr[GICV3_G1NS][2];
455
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true);
456
+ case 6:
457
+ reg64 = c->icc_apr[GICV3_G1NS][1];
458
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true);
459
+ default:
460
+ reg64 = c->icc_apr[GICV3_G1NS][0];
461
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true);
462
+ }
463
+ }
464
}
111
}
465
112
466
static void kvm_arm_gicv3_get(GICv3State *s)
113
static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
114
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
115
static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
116
int64_t cycles)
467
{
117
{
468
- /* TODO */
118
- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
469
- DPRINTF("Cannot get kernel gic state, no kernel interface\n");
119
- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
470
+ uint32_t regl, regh, reg;
120
+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
471
+ uint64_t reg64, redist_typer;
121
+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
472
+ int ncpu, i;
122
473
+
123
/*
474
+ kvm_arm_gicv3_check(s);
124
* The reset function always clears the current timer. The caller of the
475
+
125
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
476
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
126
*/
477
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
127
npcm7xx_timer_clear(&t->base_timer);
478
+ redist_typer = ((uint64_t)regh << 32) | regl;
128
479
+
129
- ns *= prescaler;
480
+ kvm_gicd_access(s, GICD_CTLR, &reg, false);
130
t->base_timer.remaining_ns = ns;
481
+ s->gicd_ctlr = reg;
482
+
483
+ /* Redistributor state (one per CPU) */
484
+
485
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
486
+ GICv3CPUState *c = &s->cpu[ncpu];
487
+
488
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, false);
489
+ c->gicr_ctlr = reg;
490
+
491
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, false);
492
+ c->gicr_statusr[GICV3_NS] = reg;
493
+
494
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, false);
495
+ c->gicr_waker = reg;
496
+
497
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, false);
498
+ c->gicr_igroupr0 = reg;
499
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, false);
500
+ c->gicr_ienabler0 = reg;
501
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, false);
502
+ c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
503
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, false);
504
+ c->level = reg;
505
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, false);
506
+ c->gicr_ipendr0 = reg;
507
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false);
508
+ c->gicr_iactiver0 = reg;
509
+
510
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
511
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false);
512
+ c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
513
+ c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
514
+ c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
515
+ c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
516
+ }
517
+ }
518
+
519
+ if (redist_typer & GICR_TYPER_PLPIS) {
520
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
521
+ GICv3CPUState *c = &s->cpu[ncpu];
522
+
523
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, false);
524
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, false);
525
+ c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
526
+
527
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, false);
528
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, false);
529
+ c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
530
+ }
531
+ }
532
+
533
+ /* Distributor state (shared between all CPUs */
534
+
535
+ kvm_gicd_access(s, GICD_STATUSR, &reg, false);
536
+ s->gicd_statusr[GICV3_NS] = reg;
537
+
538
+ /* GICD_IGROUPRn -> s->group bitmap */
539
+ kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
540
+
541
+ /* GICD_ISENABLERn -> s->enabled bitmap */
542
+ kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
543
+
544
+ /* Line level of irq */
545
+ kvm_gic_get_line_level_bmp(s, s->level);
546
+ /* GICD_ISPENDRn -> s->pending bitmap */
547
+ kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
548
+
549
+ /* GICD_ISACTIVERn -> s->active bitmap */
550
+ kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
551
+
552
+ /* GICD_ICFGRn -> s->trigger bitmap */
553
+ kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
554
+
555
+ /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
556
+ kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
557
+
558
+ /* GICD_IROUTERn -> s->gicd_irouter[irq] */
559
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
560
+ uint32_t offset;
561
+
562
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
563
+ kvm_gicd_access(s, offset, &regl, false);
564
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
565
+ kvm_gicd_access(s, offset, &regh, false);
566
+ s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
567
+ }
568
+
569
+ /*****************************************************************
570
+ * CPU Interface(s) State
571
+ */
572
+
573
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
574
+ GICv3CPUState *c = &s->cpu[ncpu];
575
+ int num_pri_bits;
576
+
577
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
578
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
579
+ &c->icc_ctlr_el1[GICV3_NS], false);
580
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
581
+ &c->icc_igrpen[GICV3_G0], false);
582
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
583
+ &c->icc_igrpen[GICV3_G1NS], false);
584
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
585
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
586
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
587
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
588
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
589
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
590
+
591
+ switch (num_pri_bits) {
592
+ case 7:
593
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, false);
594
+ c->icc_apr[GICV3_G0][3] = reg64;
595
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, false);
596
+ c->icc_apr[GICV3_G0][2] = reg64;
597
+ case 6:
598
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, false);
599
+ c->icc_apr[GICV3_G0][1] = reg64;
600
+ default:
601
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, false);
602
+ c->icc_apr[GICV3_G0][0] = reg64;
603
+ }
604
+
605
+ switch (num_pri_bits) {
606
+ case 7:
607
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false);
608
+ c->icc_apr[GICV3_G1NS][3] = reg64;
609
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false);
610
+ c->icc_apr[GICV3_G1NS][2] = reg64;
611
+ case 6:
612
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false);
613
+ c->icc_apr[GICV3_G1NS][1] = reg64;
614
+ default:
615
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);
616
+ c->icc_apr[GICV3_G1NS][0] = reg64;
617
+ }
618
+ }
619
}
131
}
620
132
621
static void kvm_arm_gicv3_reset(DeviceState *dev)
133
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
622
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
134
qemu_irq_lower(s->watchdog_timer.irq);
623
DPRINTF("Reset\n");
624
625
kgc->parent_reset(dev);
626
+
627
+ if (s->migration_blocker) {
628
+ DPRINTF("Cannot put kernel gic state, no kernel interface\n");
629
+ return;
630
+ }
631
+
632
kvm_arm_gicv3_put(s);
633
}
135
}
634
136
635
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
137
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
636
138
+static void npcm7xx_timer_init(Object *obj)
637
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
139
{
638
140
- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
639
- /* Block migration of a KVM GICv3 device: the API for saving and restoring
141
- SysBusDevice *sbd = &s->parent;
640
- * the state in the kernel is not yet finalised in the kernel or
142
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
641
- * implemented in QEMU.
143
+ DeviceState *dev = DEVICE(obj);
642
- */
144
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
643
- error_setg(&s->migration_blocker, "vGICv3 migration is not implemented");
145
int i;
644
- migrate_add_blocker(s->migration_blocker, &local_err);
146
NPCM7xxWatchdogTimer *w;
645
- if (local_err) {
147
646
- error_propagate(errp, local_err);
148
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
647
- error_free(s->migration_blocker);
149
npcm7xx_watchdog_timer_expired, w);
648
- return;
150
sysbus_init_irq(sbd, &w->irq);
649
- }
151
650
-
152
- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
651
/* Try to create the device via the device control API */
153
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
652
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
154
TYPE_NPCM7XX_TIMER, 4 * KiB);
653
if (s->dev_fd < 0) {
155
sysbus_init_mmio(sbd, &s->iomem);
654
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
156
qdev_init_gpio_out_named(dev, &w->reset_signal,
655
157
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
656
kvm_irqchip_commit_routes(kvm_state);
158
+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
657
}
658
+
659
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
660
+ GICD_CTLR)) {
661
+ error_setg(&s->migration_blocker, "This operating system kernel does "
662
+ "not support vGICv3 migration");
663
+ migrate_add_blocker(s->migration_blocker, &local_err);
664
+ if (local_err) {
665
+ error_propagate(errp, local_err);
666
+ error_free(s->migration_blocker);
667
+ return;
668
+ }
669
+ }
670
}
159
}
671
160
672
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
161
static const VMStateDescription vmstate_npcm7xx_base_timer = {
162
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
163
164
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
165
.name = "npcm7xx-timer-ctrl",
166
- .version_id = 1,
167
- .minimum_version_id = 1,
168
+ .version_id = 2,
169
+ .minimum_version_id = 2,
170
.fields = (VMStateField[]) {
171
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
172
+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
173
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
174
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
175
NPCM7xxTimer),
176
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
177
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
178
179
dc->desc = "NPCM7xx Timer Controller";
180
- dc->realize = npcm7xx_timer_realize;
181
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
182
rc->phases.enter = npcm7xx_timer_enter_reset;
183
rc->phases.hold = npcm7xx_timer_hold_reset;
184
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
185
.parent = TYPE_SYS_BUS_DEVICE,
186
.instance_size = sizeof(NPCM7xxTimerCtrlState),
187
.class_init = npcm7xx_timer_class_init,
188
+ .instance_init = npcm7xx_timer_init,
189
};
190
191
static void npcm7xx_timer_register_type(void)
673
--
192
--
674
2.7.4
193
2.20.1
675
194
676
195
diff view generated by jsdifflib
1
The SysTick timer isn't really part of the NVIC proper;
1
From: Hao Wu <wuhaotsh@google.com>
2
we just modelled it that way back when we couldn't
3
easily have devices that only occupied a small chunk
4
of a memory region. Split it out into its own device.
5
2
3
The ADC is part of NPCM7XX Module. Its behavior is controled by the
4
ADC_CON register. It converts one of the eight analog inputs into a
5
digital input and stores it in the ADC_DATA register when enabled.
6
7
Users can alter input value by using qom-set QMP command.
8
9
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
10
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
11
Signed-off-by: Hao Wu <wuhaotsh@google.com>
12
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
13
[PMM: Added missing hw/adc/trace.h file]
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
---
16
---
10
hw/timer/Makefile.objs | 1 +
17
docs/system/arm/nuvoton.rst | 2 +-
11
include/hw/arm/armv7m_nvic.h | 10 +-
18
meson.build | 1 +
12
include/hw/timer/armv7m_systick.h | 34 ++++++
19
hw/adc/trace.h | 1 +
13
hw/intc/armv7m_nvic.c | 160 ++++++-------------------
20
include/hw/adc/npcm7xx_adc.h | 69 ++++++
14
hw/timer/armv7m_systick.c | 240 ++++++++++++++++++++++++++++++++++++++
21
include/hw/arm/npcm7xx.h | 2 +
15
hw/timer/trace-events | 6 +
22
hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++
16
6 files changed, 318 insertions(+), 133 deletions(-)
23
hw/arm/npcm7xx.c | 24 ++-
17
create mode 100644 include/hw/timer/armv7m_systick.h
24
tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
18
create mode 100644 hw/timer/armv7m_systick.c
25
hw/adc/meson.build | 1 +
26
hw/adc/trace-events | 5 +
27
tests/qtest/meson.build | 3 +-
28
11 files changed, 783 insertions(+), 3 deletions(-)
29
create mode 100644 hw/adc/trace.h
30
create mode 100644 include/hw/adc/npcm7xx_adc.h
31
create mode 100644 hw/adc/npcm7xx_adc.c
32
create mode 100644 tests/qtest/npcm7xx_adc-test.c
33
create mode 100644 hw/adc/trace-events
19
34
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
35
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
21
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
37
--- a/docs/system/arm/nuvoton.rst
23
+++ b/hw/timer/Makefile.objs
38
+++ b/docs/system/arm/nuvoton.rst
24
@@ -XXX,XX +XXX,XX @@
39
@@ -XXX,XX +XXX,XX @@ Supported devices
25
common-obj-$(CONFIG_ARM_TIMER) += arm_timer.o
40
* Random Number Generator (RNG)
26
common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
41
* USB host (USBH)
27
+common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o
42
* GPIO controller
28
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
43
+ * Analog to Digital Converter (ADC)
29
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
44
30
common-obj-$(CONFIG_DS1338) += ds1338.o
45
Missing devices
31
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
46
---------------
47
@@ -XXX,XX +XXX,XX @@ Missing devices
48
* USB device (USBD)
49
* SMBus controller (SMBF)
50
* Peripheral SPI controller (PSPI)
51
- * Analog to Digital Converter (ADC)
52
* SD/MMC host
53
* PECI interface
54
* Pulse Width Modulation (PWM)
55
diff --git a/meson.build b/meson.build
32
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armv7m_nvic.h
57
--- a/meson.build
34
+++ b/include/hw/arm/armv7m_nvic.h
58
+++ b/meson.build
35
@@ -XXX,XX +XXX,XX @@
59
@@ -XXX,XX +XXX,XX @@ if have_system
36
60
'chardev',
37
#include "target/arm/cpu.h"
61
'hw/9pfs',
38
#include "hw/sysbus.h"
62
'hw/acpi',
39
+#include "hw/timer/armv7m_systick.h"
63
+ 'hw/adc',
40
64
'hw/alpha',
41
#define TYPE_NVIC "armv7m_nvic"
65
'hw/arm',
42
66
'hw/audio',
43
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
67
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
44
unsigned int vectpending; /* highest prio pending enabled exception */
45
int exception_prio; /* group prio of the highest prio active exception */
46
47
- struct {
48
- uint32_t control;
49
- uint32_t reload;
50
- int64_t tick;
51
- QEMUTimer *timer;
52
- } systick;
53
-
54
MemoryRegion sysregmem;
55
MemoryRegion container;
56
57
uint32_t num_irq;
58
qemu_irq excpout;
59
qemu_irq sysresetreq;
60
+
61
+ SysTickState systick;
62
} NVICState;
63
64
#endif
65
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
66
new file mode 100644
68
new file mode 100644
67
index XXXXXXX..XXXXXXX
69
index XXXXXXX..XXXXXXX
68
--- /dev/null
70
--- /dev/null
69
+++ b/include/hw/timer/armv7m_systick.h
71
+++ b/hw/adc/trace.h
70
@@ -XXX,XX +XXX,XX @@
72
@@ -0,0 +1 @@
71
+/*
73
+#include "trace/trace-hw_adc.h"
72
+ * ARMv7M SysTick timer
74
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
73
+ *
74
+ * Copyright (c) 2006-2007 CodeSourcery.
75
+ * Written by Paul Brook
76
+ * Copyright (c) 2017 Linaro Ltd
77
+ * Written by Peter Maydell
78
+ *
79
+ * This code is licensed under the GPL (version 2 or later).
80
+ */
81
+
82
+#ifndef HW_TIMER_ARMV7M_SYSTICK_H
83
+#define HW_TIMER_ARMV7M_SYSTICK_H
84
+
85
+#include "hw/sysbus.h"
86
+
87
+#define TYPE_SYSTICK "armv7m_systick"
88
+
89
+#define SYSTICK(obj) OBJECT_CHECK(SysTickState, (obj), TYPE_SYSTICK)
90
+
91
+typedef struct SysTickState {
92
+ /*< private >*/
93
+ SysBusDevice parent_obj;
94
+ /*< public >*/
95
+
96
+ uint32_t control;
97
+ uint32_t reload;
98
+ int64_t tick;
99
+ QEMUTimer *timer;
100
+ MemoryRegion iomem;
101
+ qemu_irq irq;
102
+} SysTickState;
103
+
104
+#endif
105
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/intc/armv7m_nvic.c
108
+++ b/hw/intc/armv7m_nvic.c
109
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
110
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
111
};
112
113
-/* qemu timers run at 1GHz. We want something closer to 1MHz. */
114
-#define SYSTICK_SCALE 1000ULL
115
-
116
-#define SYSTICK_ENABLE (1 << 0)
117
-#define SYSTICK_TICKINT (1 << 1)
118
-#define SYSTICK_CLKSOURCE (1 << 2)
119
-#define SYSTICK_COUNTFLAG (1 << 16)
120
-
121
-int system_clock_scale;
122
-
123
-/* Conversion factor from qemu timer to SysTick frequencies. */
124
-static inline int64_t systick_scale(NVICState *s)
125
-{
126
- if (s->systick.control & SYSTICK_CLKSOURCE)
127
- return system_clock_scale;
128
- else
129
- return 1000;
130
-}
131
-
132
-static void systick_reload(NVICState *s, int reset)
133
-{
134
- /* The Cortex-M3 Devices Generic User Guide says that "When the
135
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
136
- * SYST RVR register and then counts down". So, we need to check the
137
- * ENABLE bit before reloading the value.
138
- */
139
- if ((s->systick.control & SYSTICK_ENABLE) == 0) {
140
- return;
141
- }
142
-
143
- if (reset)
144
- s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
145
- s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
146
- timer_mod(s->systick.timer, s->systick.tick);
147
-}
148
-
149
-static void systick_timer_tick(void * opaque)
150
-{
151
- NVICState *s = (NVICState *)opaque;
152
- s->systick.control |= SYSTICK_COUNTFLAG;
153
- if (s->systick.control & SYSTICK_TICKINT) {
154
- /* Trigger the interrupt. */
155
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
156
- }
157
- if (s->systick.reload == 0) {
158
- s->systick.control &= ~SYSTICK_ENABLE;
159
- } else {
160
- systick_reload(s, 0);
161
- }
162
-}
163
-
164
-static void systick_reset(NVICState *s)
165
-{
166
- s->systick.control = 0;
167
- s->systick.reload = 0;
168
- s->systick.tick = 0;
169
- timer_del(s->systick.timer);
170
-}
171
-
172
static int nvic_pending_prio(NVICState *s)
173
{
174
/* return the priority of the current pending interrupt,
175
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
176
switch (offset) {
177
case 4: /* Interrupt Control Type. */
178
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
179
- case 0x10: /* SysTick Control and Status. */
180
- val = s->systick.control;
181
- s->systick.control &= ~SYSTICK_COUNTFLAG;
182
- return val;
183
- case 0x14: /* SysTick Reload Value. */
184
- return s->systick.reload;
185
- case 0x18: /* SysTick Current Value. */
186
- {
187
- int64_t t;
188
- if ((s->systick.control & SYSTICK_ENABLE) == 0)
189
- return 0;
190
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
191
- if (t >= s->systick.tick)
192
- return 0;
193
- val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
194
- /* The interrupt in triggered when the timer reaches zero.
195
- However the counter is not reloaded until the next clock
196
- tick. This is a hack to return zero during the first tick. */
197
- if (val > s->systick.reload)
198
- val = 0;
199
- return val;
200
- }
201
- case 0x1c: /* SysTick Calibration Value. */
202
- return 10000;
203
case 0xd00: /* CPUID Base. */
204
return cpu->midr;
205
case 0xd04: /* Interrupt Control State. */
206
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
207
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
208
{
209
ARMCPU *cpu = s->cpu;
210
- uint32_t oldval;
211
+
212
switch (offset) {
213
- case 0x10: /* SysTick Control and Status. */
214
- oldval = s->systick.control;
215
- s->systick.control &= 0xfffffff8;
216
- s->systick.control |= value & 7;
217
- if ((oldval ^ value) & SYSTICK_ENABLE) {
218
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
219
- if (value & SYSTICK_ENABLE) {
220
- if (s->systick.tick) {
221
- s->systick.tick += now;
222
- timer_mod(s->systick.timer, s->systick.tick);
223
- } else {
224
- systick_reload(s, 1);
225
- }
226
- } else {
227
- timer_del(s->systick.timer);
228
- s->systick.tick -= now;
229
- if (s->systick.tick < 0)
230
- s->systick.tick = 0;
231
- }
232
- } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
233
- /* This is a hack. Force the timer to be reloaded
234
- when the reference clock is changed. */
235
- systick_reload(s, 1);
236
- }
237
- break;
238
- case 0x14: /* SysTick Reload Value. */
239
- s->systick.reload = value;
240
- break;
241
- case 0x18: /* SysTick Current Value. Writes reload the timer. */
242
- systick_reload(s, 1);
243
- s->systick.control &= ~SYSTICK_COUNTFLAG;
244
- break;
245
case 0xd04: /* Interrupt Control State. */
246
if (value & (1 << 31)) {
247
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
248
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
249
250
static const VMStateDescription vmstate_nvic = {
251
.name = "armv7m_nvic",
252
- .version_id = 3,
253
- .minimum_version_id = 3,
254
+ .version_id = 4,
255
+ .minimum_version_id = 4,
256
.post_load = &nvic_post_load,
257
.fields = (VMStateField[]) {
258
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
259
vmstate_VecInfo, VecInfo),
260
- VMSTATE_UINT32(systick.control, NVICState),
261
- VMSTATE_UINT32(systick.reload, NVICState),
262
- VMSTATE_INT64(systick.tick, NVICState),
263
- VMSTATE_TIMER_PTR(systick.timer, NVICState),
264
VMSTATE_UINT32(prigroup, NVICState),
265
VMSTATE_END_OF_LIST()
266
}
267
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
268
269
s->exception_prio = NVIC_NOEXC_PRIO;
270
s->vectpending = 0;
271
+}
272
273
- systick_reset(s);
274
+static void nvic_systick_trigger(void *opaque, int n, int level)
275
+{
276
+ NVICState *s = opaque;
277
+
278
+ if (level) {
279
+ /* SysTick just asked us to pend its exception.
280
+ * (This is different from an external interrupt line's
281
+ * behaviour.)
282
+ */
283
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
284
+ }
285
}
286
287
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
288
{
289
NVICState *s = NVIC(dev);
290
+ SysBusDevice *systick_sbd;
291
+ Error *err = NULL;
292
293
s->cpu = ARM_CPU(qemu_get_cpu(0));
294
assert(s->cpu);
295
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
296
/* include space for internal exception vectors */
297
s->num_irq += NVIC_FIRST_IRQ;
298
299
+ object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
300
+ if (err != NULL) {
301
+ error_propagate(errp, err);
302
+ return;
303
+ }
304
+ systick_sbd = SYS_BUS_DEVICE(&s->systick);
305
+ sysbus_connect_irq(systick_sbd, 0,
306
+ qdev_get_gpio_in_named(dev, "systick-trigger", 0));
307
+
308
/* The NVIC and System Control Space (SCS) starts at 0xe000e000
309
* and looks like this:
310
* 0x004 - ICTR
311
- * 0x010 - 0x1c - systick
312
+ * 0x010 - 0xff - systick
313
* 0x100..0x7ec - NVIC
314
* 0x7f0..0xcff - Reserved
315
* 0xd00..0xd3c - SCS registers
316
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
317
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
318
"nvic_sysregs", 0x1000);
319
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
320
+ memory_region_add_subregion_overlap(&s->container, 0x10,
321
+ sysbus_mmio_get_region(systick_sbd, 0),
322
+ 1);
323
324
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
325
-
326
- s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
327
}
328
329
static void armv7m_nvic_instance_init(Object *obj)
330
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_instance_init(Object *obj)
331
NVICState *nvic = NVIC(obj);
332
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
333
334
+ object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
335
+ qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
336
+
337
sysbus_init_irq(sbd, &nvic->excpout);
338
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
339
+ qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
340
}
341
342
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
343
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
344
new file mode 100644
75
new file mode 100644
345
index XXXXXXX..XXXXXXX
76
index XXXXXXX..XXXXXXX
346
--- /dev/null
77
--- /dev/null
347
+++ b/hw/timer/armv7m_systick.c
78
+++ b/include/hw/adc/npcm7xx_adc.h
348
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
349
+/*
80
+/*
350
+ * ARMv7M SysTick timer
81
+ * Nuvoton NPCM7xx ADC Module
351
+ *
82
+ *
352
+ * Copyright (c) 2006-2007 CodeSourcery.
83
+ * Copyright 2020 Google LLC
353
+ * Written by Paul Brook
354
+ * Copyright (c) 2017 Linaro Ltd
355
+ * Written by Peter Maydell
356
+ *
84
+ *
357
+ * This code is licensed under the GPL (version 2 or later).
85
+ * This program is free software; you can redistribute it and/or modify it
86
+ * under the terms of the GNU General Public License as published by the
87
+ * Free Software Foundation; either version 2 of the License, or
88
+ * (at your option) any later version.
89
+ *
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
358
+ */
94
+ */
359
+
95
+#ifndef NPCM7XX_ADC_H
360
+#include "qemu/osdep.h"
96
+#define NPCM7XX_ADC_H
361
+#include "hw/timer/armv7m_systick.h"
97
+
362
+#include "qemu-common.h"
98
+#include "hw/clock.h"
99
+#include "hw/irq.h"
363
+#include "hw/sysbus.h"
100
+#include "hw/sysbus.h"
364
+#include "qemu/timer.h"
101
+#include "qemu/timer.h"
102
+
103
+#define NPCM7XX_ADC_NUM_INPUTS 8
104
+/**
105
+ * This value should not be changed unless write_adc_calibration function in
106
+ * hw/arm/npcm7xx.c is also changed.
107
+ */
108
+#define NPCM7XX_ADC_NUM_CALIB 2
109
+
110
+/**
111
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
112
+ * @parent: System bus device.
113
+ * @iomem: Memory region through which registers are accessed.
114
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
115
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
116
+ * @con: The Control Register.
117
+ * @data: The Data Buffer.
118
+ * @clock: The ADC Clock.
119
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
120
+ * @vref: The external reference voltage.
121
+ * @iref: The internal reference voltage, initialized at launch time.
122
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
123
+ */
124
+typedef struct {
125
+ SysBusDevice parent;
126
+
127
+ MemoryRegion iomem;
128
+
129
+ QEMUTimer conv_timer;
130
+
131
+ qemu_irq irq;
132
+ uint32_t con;
133
+ uint32_t data;
134
+ Clock *clock;
135
+
136
+ /* Voltages are in unit of uV. 1V = 1000000uV. */
137
+ uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
138
+ uint32_t vref;
139
+ uint32_t iref;
140
+
141
+ uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
142
+} NPCM7xxADCState;
143
+
144
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
145
+#define NPCM7XX_ADC(obj) \
146
+ OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
147
+
148
+#endif /* NPCM7XX_ADC_H */
149
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
150
index XXXXXXX..XXXXXXX 100644
151
--- a/include/hw/arm/npcm7xx.h
152
+++ b/include/hw/arm/npcm7xx.h
153
@@ -XXX,XX +XXX,XX @@
154
#define NPCM7XX_H
155
156
#include "hw/boards.h"
157
+#include "hw/adc/npcm7xx_adc.h"
158
#include "hw/cpu/a9mpcore.h"
159
#include "hw/gpio/npcm7xx_gpio.h"
160
#include "hw/mem/npcm7xx_mc.h"
161
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
162
NPCM7xxGCRState gcr;
163
NPCM7xxCLKState clk;
164
NPCM7xxTimerCtrlState tim[3];
165
+ NPCM7xxADCState adc;
166
NPCM7xxOTPState key_storage;
167
NPCM7xxOTPState fuse_array;
168
NPCM7xxMCState mc;
169
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
170
new file mode 100644
171
index XXXXXXX..XXXXXXX
172
--- /dev/null
173
+++ b/hw/adc/npcm7xx_adc.c
174
@@ -XXX,XX +XXX,XX @@
175
+/*
176
+ * Nuvoton NPCM7xx ADC Module
177
+ *
178
+ * Copyright 2020 Google LLC
179
+ *
180
+ * This program is free software; you can redistribute it and/or modify it
181
+ * under the terms of the GNU General Public License as published by the
182
+ * Free Software Foundation; either version 2 of the License, or
183
+ * (at your option) any later version.
184
+ *
185
+ * This program is distributed in the hope that it will be useful, but WITHOUT
186
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
188
+ * for more details.
189
+ */
190
+
191
+#include "qemu/osdep.h"
192
+#include "hw/adc/npcm7xx_adc.h"
193
+#include "hw/qdev-clock.h"
194
+#include "hw/qdev-properties.h"
195
+#include "hw/registerfields.h"
196
+#include "migration/vmstate.h"
365
+#include "qemu/log.h"
197
+#include "qemu/log.h"
198
+#include "qemu/module.h"
199
+#include "qemu/timer.h"
200
+#include "qemu/units.h"
366
+#include "trace.h"
201
+#include "trace.h"
367
+
202
+
368
+/* qemu timers run at 1GHz. We want something closer to 1MHz. */
203
+REG32(NPCM7XX_ADC_CON, 0x0)
369
+#define SYSTICK_SCALE 1000ULL
204
+REG32(NPCM7XX_ADC_DATA, 0x4)
370
+
205
+
371
+#define SYSTICK_ENABLE (1 << 0)
206
+/* Register field definitions. */
372
+#define SYSTICK_TICKINT (1 << 1)
207
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
373
+#define SYSTICK_CLKSOURCE (1 << 2)
208
+#define NPCM7XX_ADC_CON_INT_EN BIT(21)
374
+#define SYSTICK_COUNTFLAG (1 << 16)
209
+#define NPCM7XX_ADC_CON_REFSEL BIT(19)
375
+
210
+#define NPCM7XX_ADC_CON_INT BIT(18)
376
+int system_clock_scale;
211
+#define NPCM7XX_ADC_CON_EN BIT(17)
377
+
212
+#define NPCM7XX_ADC_CON_RST BIT(16)
378
+/* Conversion factor from qemu timer to SysTick frequencies. */
213
+#define NPCM7XX_ADC_CON_CONV BIT(14)
379
+static inline int64_t systick_scale(SysTickState *s)
214
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
380
+{
215
+
381
+ if (s->control & SYSTICK_CLKSOURCE) {
216
+#define NPCM7XX_ADC_MAX_RESULT 1023
382
+ return system_clock_scale;
217
+#define NPCM7XX_ADC_DEFAULT_IREF 2000000
383
+ } else {
218
+#define NPCM7XX_ADC_CONV_CYCLES 20
384
+ return 1000;
219
+#define NPCM7XX_ADC_RESET_CYCLES 10
385
+ }
220
+#define NPCM7XX_ADC_R0_INPUT 500000
386
+}
221
+#define NPCM7XX_ADC_R1_INPUT 1500000
387
+
222
+
388
+static void systick_reload(SysTickState *s, int reset)
223
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
389
+{
224
+{
390
+ /* The Cortex-M3 Devices Generic User Guide says that "When the
225
+ timer_del(&s->conv_timer);
391
+ * ENABLE bit is set to 1, the counter loads the RELOAD value from the
226
+ s->con = 0x000c0001;
392
+ * SYST RVR register and then counts down". So, we need to check the
227
+ s->data = 0x00000000;
393
+ * ENABLE bit before reloading the value.
228
+}
394
+ */
229
+
395
+ trace_systick_reload();
230
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
396
+
231
+{
397
+ if ((s->control & SYSTICK_ENABLE) == 0) {
232
+ uint32_t result;
233
+
234
+ result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
235
+ if (result > NPCM7XX_ADC_MAX_RESULT) {
236
+ result = NPCM7XX_ADC_MAX_RESULT;
237
+ }
238
+
239
+ return result;
240
+}
241
+
242
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
243
+{
244
+ return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
245
+}
246
+
247
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
248
+ uint32_t cycles, uint32_t prescaler)
249
+{
250
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
251
+ int64_t ticks = cycles;
252
+ int64_t ns;
253
+
254
+ ticks *= prescaler;
255
+ ns = clock_ticks_to_ns(clk, ticks);
256
+ ns += now;
257
+ timer_mod(timer, ns);
258
+}
259
+
260
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
261
+{
262
+ uint32_t prescaler = npcm7xx_adc_prescaler(s);
263
+
264
+ npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
265
+ prescaler);
266
+}
267
+
268
+static void npcm7xx_adc_convert_done(void *opaque)
269
+{
270
+ NPCM7xxADCState *s = opaque;
271
+ uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
272
+ uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
273
+ ? s->iref : s->vref;
274
+
275
+ if (input >= NPCM7XX_ADC_NUM_INPUTS) {
276
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
277
+ __func__, input);
398
+ return;
278
+ return;
399
+ }
279
+ }
400
+
280
+ s->data = npcm7xx_adc_convert(s->adci[input], ref);
401
+ if (reset) {
281
+ if (s->con & NPCM7XX_ADC_CON_INT_EN) {
402
+ s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
282
+ s->con |= NPCM7XX_ADC_CON_INT;
403
+ }
283
+ qemu_irq_raise(s->irq);
404
+ s->tick += (s->reload + 1) * systick_scale(s);
284
+ }
405
+ timer_mod(s->timer, s->tick);
285
+ s->con &= ~NPCM7XX_ADC_CON_CONV;
406
+}
286
+}
407
+
287
+
408
+static void systick_timer_tick(void *opaque)
288
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
409
+{
289
+{
410
+ SysTickState *s = (SysTickState *)opaque;
290
+ adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
411
+
291
+ adc->iref);
412
+ trace_systick_timer_tick();
292
+ adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
413
+
293
+ adc->iref);
414
+ s->control |= SYSTICK_COUNTFLAG;
294
+}
415
+ if (s->control & SYSTICK_TICKINT) {
295
+
416
+ /* Tell the NVIC to pend the SysTick exception */
296
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
417
+ qemu_irq_pulse(s->irq);
297
+{
418
+ }
298
+ uint32_t old_con = s->con;
419
+ if (s->reload == 0) {
299
+
420
+ s->control &= ~SYSTICK_ENABLE;
300
+ /* Write ADC_INT to 1 to clear it */
421
+ } else {
301
+ if (new_con & NPCM7XX_ADC_CON_INT) {
422
+ systick_reload(s, 0);
302
+ new_con &= ~NPCM7XX_ADC_CON_INT;
423
+ }
303
+ qemu_irq_lower(s->irq);
424
+}
304
+ } else if (old_con & NPCM7XX_ADC_CON_INT) {
425
+
305
+ new_con |= NPCM7XX_ADC_CON_INT;
426
+static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
306
+ }
427
+{
307
+
428
+ SysTickState *s = opaque;
308
+ s->con = new_con;
429
+ uint32_t val;
309
+
430
+
310
+ if (s->con & NPCM7XX_ADC_CON_RST) {
431
+ switch (addr) {
311
+ npcm7xx_adc_reset(s);
432
+ case 0x0: /* SysTick Control and Status. */
312
+ return;
433
+ val = s->control;
313
+ }
434
+ s->control &= ~SYSTICK_COUNTFLAG;
314
+
315
+ if ((s->con & NPCM7XX_ADC_CON_EN)) {
316
+ if (s->con & NPCM7XX_ADC_CON_CONV) {
317
+ if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
318
+ npcm7xx_adc_start_convert(s);
319
+ }
320
+ } else {
321
+ timer_del(&s->conv_timer);
322
+ }
323
+ }
324
+}
325
+
326
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
327
+{
328
+ uint64_t value = 0;
329
+ NPCM7xxADCState *s = opaque;
330
+
331
+ switch (offset) {
332
+ case A_NPCM7XX_ADC_CON:
333
+ value = s->con;
435
+ break;
334
+ break;
436
+ case 0x4: /* SysTick Reload Value. */
335
+
437
+ val = s->reload;
336
+ case A_NPCM7XX_ADC_DATA:
337
+ value = s->data;
438
+ break;
338
+ break;
439
+ case 0x8: /* SysTick Current Value. */
339
+
440
+ {
441
+ int64_t t;
442
+
443
+ if ((s->control & SYSTICK_ENABLE) == 0) {
444
+ val = 0;
445
+ break;
446
+ }
447
+ t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
448
+ if (t >= s->tick) {
449
+ val = 0;
450
+ break;
451
+ }
452
+ val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
453
+ /* The interrupt in triggered when the timer reaches zero.
454
+ However the counter is not reloaded until the next clock
455
+ tick. This is a hack to return zero during the first tick. */
456
+ if (val > s->reload) {
457
+ val = 0;
458
+ }
459
+ break;
460
+ }
461
+ case 0xc: /* SysTick Calibration Value. */
462
+ val = 10000;
463
+ break;
464
+ default:
465
+ val = 0;
466
+ qemu_log_mask(LOG_GUEST_ERROR,
467
+ "SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
468
+ break;
469
+ }
470
+
471
+ trace_systick_read(addr, val, size);
472
+ return val;
473
+}
474
+
475
+static void systick_write(void *opaque, hwaddr addr,
476
+ uint64_t value, unsigned size)
477
+{
478
+ SysTickState *s = opaque;
479
+
480
+ trace_systick_write(addr, value, size);
481
+
482
+ switch (addr) {
483
+ case 0x0: /* SysTick Control and Status. */
484
+ {
485
+ uint32_t oldval = s->control;
486
+
487
+ s->control &= 0xfffffff8;
488
+ s->control |= value & 7;
489
+ if ((oldval ^ value) & SYSTICK_ENABLE) {
490
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
491
+ if (value & SYSTICK_ENABLE) {
492
+ if (s->tick) {
493
+ s->tick += now;
494
+ timer_mod(s->timer, s->tick);
495
+ } else {
496
+ systick_reload(s, 1);
497
+ }
498
+ } else {
499
+ timer_del(s->timer);
500
+ s->tick -= now;
501
+ if (s->tick < 0) {
502
+ s->tick = 0;
503
+ }
504
+ }
505
+ } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
506
+ /* This is a hack. Force the timer to be reloaded
507
+ when the reference clock is changed. */
508
+ systick_reload(s, 1);
509
+ }
510
+ break;
511
+ }
512
+ case 0x4: /* SysTick Reload Value. */
513
+ s->reload = value;
514
+ break;
515
+ case 0x8: /* SysTick Current Value. Writes reload the timer. */
516
+ systick_reload(s, 1);
517
+ s->control &= ~SYSTICK_COUNTFLAG;
518
+ break;
519
+ default:
340
+ default:
520
+ qemu_log_mask(LOG_GUEST_ERROR,
341
+ qemu_log_mask(LOG_GUEST_ERROR,
521
+ "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
342
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
522
+ }
343
+ __func__, offset);
523
+}
344
+ break;
524
+
345
+ }
525
+static const MemoryRegionOps systick_ops = {
346
+
526
+ .read = systick_read,
347
+ trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
527
+ .write = systick_write,
348
+ return value;
528
+ .endianness = DEVICE_NATIVE_ENDIAN,
349
+}
529
+ .valid.min_access_size = 4,
350
+
530
+ .valid.max_access_size = 4,
351
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
352
+ unsigned size)
353
+{
354
+ NPCM7xxADCState *s = opaque;
355
+
356
+ trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
357
+ switch (offset) {
358
+ case A_NPCM7XX_ADC_CON:
359
+ npcm7xx_adc_write_con(s, v);
360
+ break;
361
+
362
+ case A_NPCM7XX_ADC_DATA:
363
+ qemu_log_mask(LOG_GUEST_ERROR,
364
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
365
+ __func__, offset);
366
+ break;
367
+
368
+ default:
369
+ qemu_log_mask(LOG_GUEST_ERROR,
370
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
371
+ __func__, offset);
372
+ break;
373
+ }
374
+
375
+}
376
+
377
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
378
+ .read = npcm7xx_adc_read,
379
+ .write = npcm7xx_adc_write,
380
+ .endianness = DEVICE_LITTLE_ENDIAN,
381
+ .valid = {
382
+ .min_access_size = 4,
383
+ .max_access_size = 4,
384
+ .unaligned = false,
385
+ },
531
+};
386
+};
532
+
387
+
533
+static void systick_reset(DeviceState *dev)
388
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
534
+{
389
+{
535
+ SysTickState *s = SYSTICK(dev);
390
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
536
+
391
+
537
+ s->control = 0;
392
+ npcm7xx_adc_reset(s);
538
+ s->reload = 0;
393
+}
539
+ s->tick = 0;
394
+
540
+ timer_del(s->timer);
395
+static void npcm7xx_adc_hold_reset(Object *obj)
541
+}
396
+{
542
+
397
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
543
+static void systick_instance_init(Object *obj)
398
+
544
+{
399
+ qemu_irq_lower(s->irq);
400
+}
401
+
402
+static void npcm7xx_adc_init(Object *obj)
403
+{
404
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
545
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
405
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
546
+ SysTickState *s = SYSTICK(obj);
406
+ int i;
547
+
407
+
548
+ memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
408
+ sysbus_init_irq(sbd, &s->irq);
409
+
410
+ timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
411
+ npcm7xx_adc_convert_done, s);
412
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
413
+ TYPE_NPCM7XX_ADC, 4 * KiB);
549
+ sysbus_init_mmio(sbd, &s->iomem);
414
+ sysbus_init_mmio(sbd, &s->iomem);
550
+ sysbus_init_irq(sbd, &s->irq);
415
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
551
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
416
+
552
+}
417
+ for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
553
+
418
+ object_property_add_uint32_ptr(obj, "adci[*]",
554
+static const VMStateDescription vmstate_systick = {
419
+ &s->adci[i], OBJ_PROP_FLAG_WRITE);
555
+ .name = "armv7m_systick",
420
+ }
556
+ .version_id = 1,
421
+ object_property_add_uint32_ptr(obj, "vref",
557
+ .minimum_version_id = 1,
422
+ &s->vref, OBJ_PROP_FLAG_WRITE);
423
+ npcm7xx_adc_calibrate(s);
424
+}
425
+
426
+static const VMStateDescription vmstate_npcm7xx_adc = {
427
+ .name = "npcm7xx-adc",
428
+ .version_id = 0,
429
+ .minimum_version_id = 0,
558
+ .fields = (VMStateField[]) {
430
+ .fields = (VMStateField[]) {
559
+ VMSTATE_UINT32(control, SysTickState),
431
+ VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
560
+ VMSTATE_UINT32(reload, SysTickState),
432
+ VMSTATE_UINT32(con, NPCM7xxADCState),
561
+ VMSTATE_INT64(tick, SysTickState),
433
+ VMSTATE_UINT32(data, NPCM7xxADCState),
562
+ VMSTATE_TIMER_PTR(timer, SysTickState),
434
+ VMSTATE_CLOCK(clock, NPCM7xxADCState),
563
+ VMSTATE_END_OF_LIST()
435
+ VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
564
+ }
436
+ VMSTATE_UINT32(vref, NPCM7xxADCState),
437
+ VMSTATE_UINT32(iref, NPCM7xxADCState),
438
+ VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
439
+ NPCM7XX_ADC_NUM_CALIB),
440
+ VMSTATE_END_OF_LIST(),
441
+ },
565
+};
442
+};
566
+
443
+
567
+static void systick_class_init(ObjectClass *klass, void *data)
444
+static Property npcm7xx_timer_properties[] = {
568
+{
445
+ DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
446
+ DEFINE_PROP_END_OF_LIST(),
447
+};
448
+
449
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
450
+{
451
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
569
+ DeviceClass *dc = DEVICE_CLASS(klass);
452
+ DeviceClass *dc = DEVICE_CLASS(klass);
570
+
453
+
571
+ dc->vmsd = &vmstate_systick;
454
+ dc->desc = "NPCM7xx ADC Module";
572
+ dc->reset = systick_reset;
455
+ dc->vmsd = &vmstate_npcm7xx_adc;
573
+}
456
+ rc->phases.enter = npcm7xx_adc_enter_reset;
574
+
457
+ rc->phases.hold = npcm7xx_adc_hold_reset;
575
+static const TypeInfo armv7m_systick_info = {
458
+
576
+ .name = TYPE_SYSTICK,
459
+ device_class_set_props(dc, npcm7xx_timer_properties);
577
+ .parent = TYPE_SYS_BUS_DEVICE,
460
+}
578
+ .instance_init = systick_instance_init,
461
+
579
+ .instance_size = sizeof(SysTickState),
462
+static const TypeInfo npcm7xx_adc_info = {
580
+ .class_init = systick_class_init,
463
+ .name = TYPE_NPCM7XX_ADC,
464
+ .parent = TYPE_SYS_BUS_DEVICE,
465
+ .instance_size = sizeof(NPCM7xxADCState),
466
+ .class_init = npcm7xx_adc_class_init,
467
+ .instance_init = npcm7xx_adc_init,
581
+};
468
+};
582
+
469
+
583
+static void armv7m_systick_register_types(void)
470
+static void npcm7xx_adc_register_types(void)
584
+{
471
+{
585
+ type_register_static(&armv7m_systick_info);
472
+ type_register_static(&npcm7xx_adc_info);
586
+}
473
+}
587
+
474
+
588
+type_init(armv7m_systick_register_types)
475
+type_init(npcm7xx_adc_register_types);
589
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
476
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
590
index XXXXXXX..XXXXXXX 100644
477
index XXXXXXX..XXXXXXX 100644
591
--- a/hw/timer/trace-events
478
--- a/hw/arm/npcm7xx.c
592
+++ b/hw/timer/trace-events
479
+++ b/hw/arm/npcm7xx.c
593
@@ -XXX,XX +XXX,XX @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
480
@@ -XXX,XX +XXX,XX @@
594
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
481
#define NPCM7XX_EHCI_BA (0xf0806000)
595
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
482
#define NPCM7XX_OHCI_BA (0xf0807000)
596
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
483
597
+
484
+/* ADC Module */
598
+# hw/timer/armv7m_systick.c
485
+#define NPCM7XX_ADC_BA (0xf000c000)
599
+systick_reload(void) "systick reload"
486
+
600
+systick_timer_tick(void) "systick reload"
487
/* Internal AHB SRAM */
601
+systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
488
#define NPCM7XX_RAM3_BA (0xc0008000)
602
+systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
489
#define NPCM7XX_RAM3_SZ (4 * KiB)
490
@@ -XXX,XX +XXX,XX @@
491
#define NPCM7XX_ROM_BA (0xffff0000)
492
#define NPCM7XX_ROM_SZ (64 * KiB)
493
494
+
495
/* Clock configuration values to be fixed up when bypassing bootloader */
496
497
/* Run PLL1 at 1600 MHz */
498
@@ -XXX,XX +XXX,XX @@
499
* interrupts.
500
*/
501
enum NPCM7xxInterrupt {
502
+ NPCM7XX_ADC_IRQ = 0,
503
NPCM7XX_UART0_IRQ = 2,
504
NPCM7XX_UART1_IRQ,
505
NPCM7XX_UART2_IRQ,
506
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
507
sizeof(value));
508
}
509
510
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
511
+{
512
+ /* Both ADC and the fuse array must have realized. */
513
+ QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
514
+ npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
515
+ NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
516
+}
517
+
518
static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
519
{
520
return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
521
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
522
TYPE_NPCM7XX_FUSE_ARRAY);
523
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
524
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
525
+ object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
526
527
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
528
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
529
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
530
sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
531
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
532
533
+ /* ADC Modules. Cannot fail. */
534
+ qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
535
+ DEVICE(&s->clk), "adc-clock"));
536
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
537
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
538
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
539
+ npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
540
+ npcm7xx_write_adc_calibration(s);
541
+
542
/* Timer Modules (TIM). Cannot fail. */
543
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
544
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
545
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
546
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
547
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
548
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
549
- create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
550
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
551
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
552
create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
553
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
554
new file mode 100644
555
index XXXXXXX..XXXXXXX
556
--- /dev/null
557
+++ b/tests/qtest/npcm7xx_adc-test.c
558
@@ -XXX,XX +XXX,XX @@
559
+/*
560
+ * QTests for Nuvoton NPCM7xx ADCModules.
561
+ *
562
+ * Copyright 2020 Google LLC
563
+ *
564
+ * This program is free software; you can redistribute it and/or modify it
565
+ * under the terms of the GNU General Public License as published by the
566
+ * Free Software Foundation; either version 2 of the License, or
567
+ * (at your option) any later version.
568
+ *
569
+ * This program is distributed in the hope that it will be useful, but WITHOUT
570
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
571
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
572
+ * for more details.
573
+ */
574
+
575
+#include "qemu/osdep.h"
576
+#include "qemu/bitops.h"
577
+#include "qemu/timer.h"
578
+#include "libqos/libqtest.h"
579
+#include "qapi/qmp/qdict.h"
580
+
581
+#define REF_HZ (25000000)
582
+
583
+#define CON_OFFSET 0x0
584
+#define DATA_OFFSET 0x4
585
+
586
+#define NUM_INPUTS 8
587
+#define DEFAULT_IREF 2000000
588
+#define CONV_CYCLES 20
589
+#define RESET_CYCLES 10
590
+#define R0_INPUT 500000
591
+#define R1_INPUT 1500000
592
+#define MAX_RESULT 1023
593
+
594
+#define DEFAULT_CLKDIV 5
595
+
596
+#define FUSE_ARRAY_BA 0xf018a000
597
+#define FCTL_OFFSET 0x14
598
+#define FST_OFFSET 0x0
599
+#define FADDR_OFFSET 0x4
600
+#define FDATA_OFFSET 0x8
601
+#define ADC_CALIB_ADDR 24
602
+#define FUSE_READ 0x2
603
+
604
+/* Register field definitions. */
605
+#define CON_MUX(rv) ((rv) << 24)
606
+#define CON_INT_EN BIT(21)
607
+#define CON_REFSEL BIT(19)
608
+#define CON_INT BIT(18)
609
+#define CON_EN BIT(17)
610
+#define CON_RST BIT(16)
611
+#define CON_CONV BIT(14)
612
+#define CON_DIV(rv) extract32(rv, 1, 8)
613
+
614
+#define FST_RDST BIT(1)
615
+#define FDATA_MASK 0xff
616
+
617
+#define MAX_ERROR 10000
618
+#define MIN_CALIB_INPUT 100000
619
+#define MAX_CALIB_INPUT 1800000
620
+
621
+static const uint32_t input_list[] = {
622
+ 100000,
623
+ 500000,
624
+ 1000000,
625
+ 1500000,
626
+ 1800000,
627
+ 2000000,
628
+};
629
+
630
+static const uint32_t vref_list[] = {
631
+ 2000000,
632
+ 2200000,
633
+ 2500000,
634
+};
635
+
636
+static const uint32_t iref_list[] = {
637
+ 1800000,
638
+ 1900000,
639
+ 2000000,
640
+ 2100000,
641
+ 2200000,
642
+};
643
+
644
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
645
+
646
+typedef struct ADC {
647
+ int irq;
648
+ uint64_t base_addr;
649
+} ADC;
650
+
651
+ADC adc = {
652
+ .irq = 0,
653
+ .base_addr = 0xf000c000
654
+};
655
+
656
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
657
+{
658
+ return qtest_readl(qts, adc->base_addr + CON_OFFSET);
659
+}
660
+
661
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
662
+{
663
+ qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
664
+}
665
+
666
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
667
+{
668
+ return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
669
+}
670
+
671
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
672
+{
673
+ return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
674
+ / (int32_t)(rv[1] - rv[0]);
675
+}
676
+
677
+static void adc_qom_set(QTestState *qts, const ADC *adc,
678
+ const char *name, uint32_t value)
679
+{
680
+ QDict *response;
681
+ const char *path = "/machine/soc/adc";
682
+
683
+ g_test_message("Setting properties %s of %s with value %u",
684
+ name, path, value);
685
+ response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
686
+ " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
687
+ path, name, value);
688
+ /* The qom set message returns successfully. */
689
+ g_assert_true(qdict_haskey(response, "return"));
690
+}
691
+
692
+static void adc_write_input(QTestState *qts, const ADC *adc,
693
+ uint32_t index, uint32_t value)
694
+{
695
+ char name[100];
696
+
697
+ sprintf(name, "adci[%u]", index);
698
+ adc_qom_set(qts, adc, name, value);
699
+}
700
+
701
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
702
+{
703
+ adc_qom_set(qts, adc, "vref", value);
704
+}
705
+
706
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
707
+{
708
+ uint32_t output;
709
+
710
+ g_assert_cmpuint(input, <=, ref);
711
+ output = (input * (MAX_RESULT + 1)) / ref;
712
+ if (output > MAX_RESULT) {
713
+ output = MAX_RESULT;
714
+ }
715
+
716
+ return output;
717
+}
718
+
719
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
720
+{
721
+ uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
722
+
723
+ return 2 * (div + 1);
724
+}
725
+
726
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
727
+ uint32_t clkdiv)
728
+{
729
+ return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
730
+}
731
+
732
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
733
+ uint32_t clkdiv)
734
+{
735
+ uint32_t prescaler = adc_prescaler(qts, adc);
736
+
737
+ /*
738
+ * ADC should takes roughly 20 cycles to convert one sample. So we assert it
739
+ * should take 10~30 cycles here.
740
+ */
741
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
742
+ clkdiv));
743
+ /* ADC is still converting. */
744
+ g_assert_true(adc_read_con(qts, adc) & CON_CONV);
745
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
746
+ /* ADC has finished conversion. */
747
+ g_assert_false(adc_read_con(qts, adc) & CON_CONV);
748
+}
749
+
750
+/* Check ADC can be reset to default value. */
751
+static void test_init(gconstpointer adc_p)
752
+{
753
+ const ADC *adc = adc_p;
754
+
755
+ QTestState *qts = qtest_init("-machine quanta-gsj");
756
+ adc_write_con(qts, adc, CON_REFSEL | CON_INT);
757
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
758
+ qtest_quit(qts);
759
+}
760
+
761
+/* Check ADC can convert from an internal reference. */
762
+static void test_convert_internal(gconstpointer adc_p)
763
+{
764
+ const ADC *adc = adc_p;
765
+ uint32_t index, input, output, expected_output;
766
+ QTestState *qts = qtest_init("-machine quanta-gsj");
767
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
768
+
769
+ for (index = 0; index < NUM_INPUTS; ++index) {
770
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
771
+ input = input_list[i];
772
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
773
+
774
+ adc_write_input(qts, adc, index, input);
775
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
776
+ CON_EN | CON_CONV);
777
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
778
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
779
+ CON_REFSEL | CON_EN);
780
+ g_assert_false(qtest_get_irq(qts, adc->irq));
781
+ output = adc_read_data(qts, adc);
782
+ g_assert_cmpuint(output, ==, expected_output);
783
+ }
784
+ }
785
+
786
+ qtest_quit(qts);
787
+}
788
+
789
+/* Check ADC can convert from an external reference. */
790
+static void test_convert_external(gconstpointer adc_p)
791
+{
792
+ const ADC *adc = adc_p;
793
+ uint32_t index, input, vref, output, expected_output;
794
+ QTestState *qts = qtest_init("-machine quanta-gsj");
795
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
796
+
797
+ for (index = 0; index < NUM_INPUTS; ++index) {
798
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
799
+ for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
800
+ input = input_list[i];
801
+ vref = vref_list[j];
802
+ expected_output = adc_calculate_output(input, vref);
803
+
804
+ adc_write_input(qts, adc, index, input);
805
+ adc_write_vref(qts, adc, vref);
806
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
807
+ CON_CONV);
808
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
809
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
810
+ CON_MUX(index) | CON_EN);
811
+ g_assert_false(qtest_get_irq(qts, adc->irq));
812
+ output = adc_read_data(qts, adc);
813
+ g_assert_cmpuint(output, ==, expected_output);
814
+ }
815
+ }
816
+ }
817
+
818
+ qtest_quit(qts);
819
+}
820
+
821
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
822
+static void test_interrupt(gconstpointer adc_p)
823
+{
824
+ const ADC *adc = adc_p;
825
+ uint32_t index, input, output, expected_output;
826
+ QTestState *qts = qtest_init("-machine quanta-gsj");
827
+
828
+ index = 1;
829
+ input = input_list[1];
830
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
831
+
832
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
833
+ adc_write_input(qts, adc, index, input);
834
+ g_assert_false(qtest_get_irq(qts, adc->irq));
835
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
836
+ | CON_EN | CON_CONV);
837
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
838
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
839
+ | CON_REFSEL | CON_INT | CON_EN);
840
+ g_assert_true(qtest_get_irq(qts, adc->irq));
841
+ output = adc_read_data(qts, adc);
842
+ g_assert_cmpuint(output, ==, expected_output);
843
+
844
+ qtest_quit(qts);
845
+}
846
+
847
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
848
+static void test_reset(gconstpointer adc_p)
849
+{
850
+ const ADC *adc = adc_p;
851
+ QTestState *qts = qtest_init("-machine quanta-gsj");
852
+
853
+ for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
854
+ uint32_t div = div_list[i];
855
+
856
+ adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
857
+ qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
858
+ adc_prescaler(qts, adc), DEFAULT_CLKDIV));
859
+ g_assert_false(adc_read_con(qts, adc) & CON_EN);
860
+ }
861
+ qtest_quit(qts);
862
+}
863
+
864
+/* Check ADC Calibration works as desired. */
865
+static void test_calibrate(gconstpointer adc_p)
866
+{
867
+ int i, j;
868
+ const ADC *adc = adc_p;
869
+
870
+ for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
871
+ uint32_t iref = iref_list[j];
872
+ uint32_t expected_rv[] = {
873
+ adc_calculate_output(R0_INPUT, iref),
874
+ adc_calculate_output(R1_INPUT, iref),
875
+ };
876
+ char buf[100];
877
+ QTestState *qts;
878
+
879
+ sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
880
+ qts = qtest_init(buf);
881
+
882
+ /* Check the converted value is correct using the calibration value. */
883
+ for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
884
+ uint32_t input;
885
+ uint32_t output;
886
+ uint32_t expected_output;
887
+ uint32_t calibrated_voltage;
888
+ uint32_t index = 0;
889
+
890
+ input = input_list[i];
891
+ /* Calibration only works for input range 0.1V ~ 1.8V. */
892
+ if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
893
+ continue;
894
+ }
895
+ expected_output = adc_calculate_output(input, iref);
896
+
897
+ adc_write_input(qts, adc, index, input);
898
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
899
+ CON_EN | CON_CONV);
900
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
901
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
902
+ CON_REFSEL | CON_MUX(index) | CON_EN);
903
+ output = adc_read_data(qts, adc);
904
+ g_assert_cmpuint(output, ==, expected_output);
905
+
906
+ calibrated_voltage = adc_calibrate(output, expected_rv);
907
+ g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
908
+ g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
909
+ }
910
+
911
+ qtest_quit(qts);
912
+ }
913
+}
914
+
915
+static void adc_add_test(const char *name, const ADC* wd,
916
+ GTestDataFunc fn)
917
+{
918
+ g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name);
919
+ qtest_add_data_func(full_name, wd, fn);
920
+}
921
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
922
+
923
+int main(int argc, char **argv)
924
+{
925
+ g_test_init(&argc, &argv, NULL);
926
+
927
+ add_test(init, &adc);
928
+ add_test(convert_internal, &adc);
929
+ add_test(convert_external, &adc);
930
+ add_test(interrupt, &adc);
931
+ add_test(reset, &adc);
932
+ add_test(calibrate, &adc);
933
+
934
+ return g_test_run();
935
+}
936
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
937
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/adc/meson.build
939
+++ b/hw/adc/meson.build
940
@@ -1 +1,2 @@
941
softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
942
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
943
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
944
new file mode 100644
945
index XXXXXXX..XXXXXXX
946
--- /dev/null
947
+++ b/hw/adc/trace-events
948
@@ -XXX,XX +XXX,XX @@
949
+# See docs/devel/tracing.txt for syntax documentation.
950
+
951
+# npcm7xx_adc.c
952
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
953
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
954
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
955
index XXXXXXX..XXXXXXX 100644
956
--- a/tests/qtest/meson.build
957
+++ b/tests/qtest/meson.build
958
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
959
['prom-env-test', 'boot-serial-test']
960
961
qtests_npcm7xx = \
962
- ['npcm7xx_gpio-test',
963
+ ['npcm7xx_adc-test',
964
+ 'npcm7xx_gpio-test',
965
'npcm7xx_rng-test',
966
'npcm7xx_timer-test',
967
'npcm7xx_watchdog_timer-test']
603
--
968
--
604
2.7.4
969
2.20.1
605
970
606
971
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
This adds the BCM2835 GPIO controller.
3
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
4
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
5
two outputs: frequency and duty_cycle. Both are computed using inputs
6
from software side.
4
7
5
It currently implements:
8
This module does not model detail pulse signals since it is expensive.
6
- The 54 GPIOs as outputs (qemu_irq)
9
It also does not model interrupts and watchdogs that are dependant on
7
- The SD controller selection via alternate function of GPIOs 48-53
10
the detail models. The interfaces for these are left in the module so
11
that anyone in need for these functionalities can implement on their
12
own.
8
13
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
14
The user can read the duty cycle and frequency using qom-get command.
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org
17
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
13
Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr
18
Signed-off-by: Hao Wu <wuhaotsh@google.com>
19
Message-id: 20210108190945.949196-5-wuhaotsh@google.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
22
---
17
hw/gpio/Makefile.objs | 1 +
23
docs/system/arm/nuvoton.rst | 2 +-
18
include/hw/gpio/bcm2835_gpio.h | 39 +++++
24
include/hw/arm/npcm7xx.h | 2 +
19
hw/gpio/bcm2835_gpio.c | 353 +++++++++++++++++++++++++++++++++++++++++
25
include/hw/misc/npcm7xx_pwm.h | 105 +++++++
20
3 files changed, 393 insertions(+)
26
hw/arm/npcm7xx.c | 26 +-
21
create mode 100644 include/hw/gpio/bcm2835_gpio.h
27
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++
22
create mode 100644 hw/gpio/bcm2835_gpio.c
28
hw/misc/meson.build | 1 +
29
hw/misc/trace-events | 6 +
30
7 files changed, 689 insertions(+), 3 deletions(-)
31
create mode 100644 include/hw/misc/npcm7xx_pwm.h
32
create mode 100644 hw/misc/npcm7xx_pwm.c
23
33
24
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
34
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
25
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/gpio/Makefile.objs
36
--- a/docs/system/arm/nuvoton.rst
27
+++ b/hw/gpio/Makefile.objs
37
+++ b/docs/system/arm/nuvoton.rst
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
38
@@ -XXX,XX +XXX,XX @@ Supported devices
29
39
* USB host (USBH)
30
obj-$(CONFIG_OMAP) += omap_gpio.o
40
* GPIO controller
31
obj-$(CONFIG_IMX) += imx_gpio.o
41
* Analog to Digital Converter (ADC)
32
+obj-$(CONFIG_RASPI) += bcm2835_gpio.o
42
+ * Pulse Width Modulation (PWM)
33
diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpio.h
43
44
Missing devices
45
---------------
46
@@ -XXX,XX +XXX,XX @@ Missing devices
47
* Peripheral SPI controller (PSPI)
48
* SD/MMC host
49
* PECI interface
50
- * Pulse Width Modulation (PWM)
51
* Tachometer
52
* PCI and PCIe root complex and bridges
53
* VDM and MCTP support
54
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
55
index XXXXXXX..XXXXXXX 100644
56
--- a/include/hw/arm/npcm7xx.h
57
+++ b/include/hw/arm/npcm7xx.h
58
@@ -XXX,XX +XXX,XX @@
59
#include "hw/mem/npcm7xx_mc.h"
60
#include "hw/misc/npcm7xx_clk.h"
61
#include "hw/misc/npcm7xx_gcr.h"
62
+#include "hw/misc/npcm7xx_pwm.h"
63
#include "hw/misc/npcm7xx_rng.h"
64
#include "hw/nvram/npcm7xx_otp.h"
65
#include "hw/timer/npcm7xx_timer.h"
66
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
67
NPCM7xxCLKState clk;
68
NPCM7xxTimerCtrlState tim[3];
69
NPCM7xxADCState adc;
70
+ NPCM7xxPWMState pwm[2];
71
NPCM7xxOTPState key_storage;
72
NPCM7xxOTPState fuse_array;
73
NPCM7xxMCState mc;
74
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
34
new file mode 100644
75
new file mode 100644
35
index XXXXXXX..XXXXXXX
76
index XXXXXXX..XXXXXXX
36
--- /dev/null
77
--- /dev/null
37
+++ b/include/hw/gpio/bcm2835_gpio.h
78
+++ b/include/hw/misc/npcm7xx_pwm.h
38
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
39
+/*
80
+/*
40
+ * Raspberry Pi (BCM2835) GPIO Controller
81
+ * Nuvoton NPCM7xx PWM Module
41
+ *
82
+ *
42
+ * Copyright (c) 2017 Antfield SAS
83
+ * Copyright 2020 Google LLC
43
+ *
84
+ *
44
+ * Authors:
85
+ * This program is free software; you can redistribute it and/or modify it
45
+ * Clement Deschamps <clement.deschamps@antfield.fr>
86
+ * under the terms of the GNU General Public License as published by the
46
+ * Luc Michel <luc.michel@antfield.fr>
87
+ * Free Software Foundation; either version 2 of the License, or
88
+ * (at your option) any later version.
47
+ *
89
+ *
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
49
+ * See the COPYING file in the top-level directory.
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
50
+ */
94
+ */
51
+
95
+#ifndef NPCM7XX_PWM_H
52
+#ifndef BCM2835_GPIO_H
96
+#define NPCM7XX_PWM_H
53
+#define BCM2835_GPIO_H
97
+
54
+
98
+#include "hw/clock.h"
55
+#include "hw/sd/sd.h"
99
+#include "hw/sysbus.h"
56
+
100
+#include "hw/irq.h"
57
+typedef struct BCM2835GpioState {
101
+
58
+ SysBusDevice parent_obj;
102
+/* Each PWM module holds 4 PWM channels. */
103
+#define NPCM7XX_PWM_PER_MODULE 4
104
+
105
+/*
106
+ * Number of registers in one pwm module. Don't change this without increasing
107
+ * the version_id in vmstate.
108
+ */
109
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
110
+
111
+/*
112
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
113
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
114
+ * value of 100,000 the duty cycle for that PWM is 10%.
115
+ */
116
+#define NPCM7XX_PWM_MAX_DUTY 1000000
117
+
118
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
119
+
120
+/**
121
+ * struct NPCM7xxPWM - The state of a single PWM channel.
122
+ * @module: The PWM module that contains this channel.
123
+ * @irq: GIC interrupt line to fire on expiration if enabled.
124
+ * @running: Whether this PWM channel is generating output.
125
+ * @inverted: Whether this PWM channel is inverted.
126
+ * @index: The index of this PWM channel.
127
+ * @cnr: The counter register.
128
+ * @cmr: The comparator register.
129
+ * @pdr: The data register.
130
+ * @pwdr: The watchdog register.
131
+ * @freq: The frequency of this PWM channel.
132
+ * @duty: The duty cycle of this PWM channel. One unit represents
133
+ * 1/NPCM7XX_MAX_DUTY cycles.
134
+ */
135
+typedef struct NPCM7xxPWM {
136
+ NPCM7xxPWMState *module;
137
+
138
+ qemu_irq irq;
139
+
140
+ bool running;
141
+ bool inverted;
142
+
143
+ uint8_t index;
144
+ uint32_t cnr;
145
+ uint32_t cmr;
146
+ uint32_t pdr;
147
+ uint32_t pwdr;
148
+
149
+ uint32_t freq;
150
+ uint32_t duty;
151
+} NPCM7xxPWM;
152
+
153
+/**
154
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
155
+ * @parent: System bus device.
156
+ * @iomem: Memory region through which registers are accessed.
157
+ * @clock: The PWM clock.
158
+ * @pwm: The PWM channels owned by this module.
159
+ * @ppr: The prescaler register.
160
+ * @csr: The clock selector register.
161
+ * @pcr: The control register.
162
+ * @pier: The interrupt enable register.
163
+ * @piir: The interrupt indication register.
164
+ */
165
+struct NPCM7xxPWMState {
166
+ SysBusDevice parent;
59
+
167
+
60
+ MemoryRegion iomem;
168
+ MemoryRegion iomem;
61
+
169
+
62
+ /* SDBus selector */
170
+ Clock *clock;
63
+ SDBus sdbus;
171
+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
64
+ SDBus *sdbus_sdhci;
172
+
65
+ SDBus *sdbus_sdhost;
173
+ uint32_t ppr;
66
+
174
+ uint32_t csr;
67
+ uint8_t fsel[54];
175
+ uint32_t pcr;
68
+ uint32_t lev0, lev1;
176
+ uint32_t pier;
69
+ uint8_t sd_fsel;
177
+ uint32_t piir;
70
+ qemu_irq out[54];
178
+};
71
+} BCM2835GpioState;
179
+
72
+
180
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
73
+#define TYPE_BCM2835_GPIO "bcm2835_gpio"
181
+#define NPCM7XX_PWM(obj) \
74
+#define BCM2835_GPIO(obj) \
182
+ OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
75
+ OBJECT_CHECK(BCM2835GpioState, (obj), TYPE_BCM2835_GPIO)
183
+
76
+
184
+#endif /* NPCM7XX_PWM_H */
77
+#endif
185
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
78
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/npcm7xx.c
188
+++ b/hw/arm/npcm7xx.c
189
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
190
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
191
NPCM7XX_EHCI_IRQ = 61,
192
NPCM7XX_OHCI_IRQ = 62,
193
+ NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
194
+ NPCM7XX_PWM1_IRQ, /* PWM module 1 */
195
NPCM7XX_GPIO0_IRQ = 116,
196
NPCM7XX_GPIO1_IRQ,
197
NPCM7XX_GPIO2_IRQ,
198
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
199
0xb8000000, /* CS3 */
200
};
201
202
+/* Register base address for each PWM Module */
203
+static const hwaddr npcm7xx_pwm_addr[] = {
204
+ 0xf0103000,
205
+ 0xf0104000,
206
+};
207
+
208
static const struct {
209
hwaddr regs_addr;
210
uint32_t unconnected_pins;
211
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
212
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
213
TYPE_NPCM7XX_FIU);
214
}
215
+
216
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
217
+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
218
+ }
219
}
220
221
static void npcm7xx_realize(DeviceState *dev, Error **errp)
222
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
223
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
224
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
225
226
+ /* PWM Modules. Cannot fail. */
227
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
228
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
229
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
230
+
231
+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
232
+ DEVICE(&s->clk), "apb3-clock"));
233
+ sysbus_realize(sbd, &error_abort);
234
+ sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
235
+ sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
236
+ }
237
+
238
/*
239
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
240
* specified, but this is a programming error.
241
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
242
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
243
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
244
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
245
- create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
246
- create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
247
create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
248
create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
249
create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
250
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
79
new file mode 100644
251
new file mode 100644
80
index XXXXXXX..XXXXXXX
252
index XXXXXXX..XXXXXXX
81
--- /dev/null
253
--- /dev/null
82
+++ b/hw/gpio/bcm2835_gpio.c
254
+++ b/hw/misc/npcm7xx_pwm.c
83
@@ -XXX,XX +XXX,XX @@
255
@@ -XXX,XX +XXX,XX @@
84
+/*
256
+/*
85
+ * Raspberry Pi (BCM2835) GPIO Controller
257
+ * Nuvoton NPCM7xx PWM Module
86
+ *
258
+ *
87
+ * Copyright (c) 2017 Antfield SAS
259
+ * Copyright 2020 Google LLC
88
+ *
260
+ *
89
+ * Authors:
261
+ * This program is free software; you can redistribute it and/or modify it
90
+ * Clement Deschamps <clement.deschamps@antfield.fr>
262
+ * under the terms of the GNU General Public License as published by the
91
+ * Luc Michel <luc.michel@antfield.fr>
263
+ * Free Software Foundation; either version 2 of the License, or
264
+ * (at your option) any later version.
92
+ *
265
+ *
93
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
266
+ * This program is distributed in the hope that it will be useful, but WITHOUT
94
+ * See the COPYING file in the top-level directory.
267
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
268
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
269
+ * for more details.
95
+ */
270
+ */
96
+
271
+
97
+#include "qemu/osdep.h"
272
+#include "qemu/osdep.h"
273
+#include "hw/irq.h"
274
+#include "hw/qdev-clock.h"
275
+#include "hw/qdev-properties.h"
276
+#include "hw/misc/npcm7xx_pwm.h"
277
+#include "hw/registerfields.h"
278
+#include "migration/vmstate.h"
279
+#include "qemu/bitops.h"
280
+#include "qemu/error-report.h"
98
+#include "qemu/log.h"
281
+#include "qemu/log.h"
99
+#include "qemu/timer.h"
282
+#include "qemu/module.h"
100
+#include "qapi/error.h"
283
+#include "qemu/units.h"
101
+#include "hw/sysbus.h"
284
+#include "trace.h"
102
+#include "hw/sd/sd.h"
285
+
103
+#include "hw/gpio/bcm2835_gpio.h"
286
+REG32(NPCM7XX_PWM_PPR, 0x00);
104
+
287
+REG32(NPCM7XX_PWM_CSR, 0x04);
105
+#define GPFSEL0 0x00
288
+REG32(NPCM7XX_PWM_PCR, 0x08);
106
+#define GPFSEL1 0x04
289
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
107
+#define GPFSEL2 0x08
290
+REG32(NPCM7XX_PWM_CMR0, 0x10);
108
+#define GPFSEL3 0x0C
291
+REG32(NPCM7XX_PWM_PDR0, 0x14);
109
+#define GPFSEL4 0x10
292
+REG32(NPCM7XX_PWM_CNR1, 0x18);
110
+#define GPFSEL5 0x14
293
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
111
+#define GPSET0 0x1C
294
+REG32(NPCM7XX_PWM_PDR1, 0x20);
112
+#define GPSET1 0x20
295
+REG32(NPCM7XX_PWM_CNR2, 0x24);
113
+#define GPCLR0 0x28
296
+REG32(NPCM7XX_PWM_CMR2, 0x28);
114
+#define GPCLR1 0x2C
297
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
115
+#define GPLEV0 0x34
298
+REG32(NPCM7XX_PWM_CNR3, 0x30);
116
+#define GPLEV1 0x38
299
+REG32(NPCM7XX_PWM_CMR3, 0x34);
117
+#define GPEDS0 0x40
300
+REG32(NPCM7XX_PWM_PDR3, 0x38);
118
+#define GPEDS1 0x44
301
+REG32(NPCM7XX_PWM_PIER, 0x3c);
119
+#define GPREN0 0x4C
302
+REG32(NPCM7XX_PWM_PIIR, 0x40);
120
+#define GPREN1 0x50
303
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
121
+#define GPFEN0 0x58
304
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
122
+#define GPFEN1 0x5C
305
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
123
+#define GPHEN0 0x64
306
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
124
+#define GPHEN1 0x68
307
+
125
+#define GPLEN0 0x70
308
+/* Register field definitions. */
126
+#define GPLEN1 0x74
309
+#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8)
127
+#define GPAREN0 0x7C
310
+#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3)
128
+#define GPAREN1 0x80
311
+#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4)
129
+#define GPAFEN0 0x88
312
+#define NPCM7XX_CH_EN BIT(0)
130
+#define GPAFEN1 0x8C
313
+#define NPCM7XX_CH_INV BIT(2)
131
+#define GPPUD 0x94
314
+#define NPCM7XX_CH_MOD BIT(3)
132
+#define GPPUDCLK0 0x98
315
+
133
+#define GPPUDCLK1 0x9C
316
+/* Offset of each PWM channel's prescaler in the PPR register. */
134
+
317
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
135
+static uint32_t gpfsel_get(BCM2835GpioState *s, uint8_t reg)
318
+/* Offset of each PWM channel's clock selector in the CSR register. */
319
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
320
+/* Offset of each PWM channel's control variable in the PCR register. */
321
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
322
+
323
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
324
+{
325
+ uint32_t ppr;
326
+ uint32_t csr;
327
+ uint32_t freq;
328
+
329
+ if (!p->running) {
330
+ return 0;
331
+ }
332
+
333
+ csr = NPCM7XX_CSR(p->module->csr, p->index);
334
+ ppr = NPCM7XX_PPR(p->module->ppr, p->index);
335
+ freq = clock_get_hz(p->module->clock);
336
+ freq /= ppr + 1;
337
+ /* csr can only be 0~4 */
338
+ if (csr > 4) {
339
+ qemu_log_mask(LOG_GUEST_ERROR,
340
+ "%s: invalid csr value %u\n",
341
+ __func__, csr);
342
+ csr = 4;
343
+ }
344
+ /* freq won't be changed if csr == 4. */
345
+ if (csr < 4) {
346
+ freq >>= csr + 1;
347
+ }
348
+
349
+ return freq / (p->cnr + 1);
350
+}
351
+
352
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
353
+{
354
+ uint64_t duty;
355
+
356
+ if (p->running) {
357
+ if (p->cnr == 0) {
358
+ duty = 0;
359
+ } else if (p->cmr >= p->cnr) {
360
+ duty = NPCM7XX_PWM_MAX_DUTY;
361
+ } else {
362
+ duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
363
+ }
364
+ } else {
365
+ duty = 0;
366
+ }
367
+
368
+ if (p->inverted) {
369
+ duty = NPCM7XX_PWM_MAX_DUTY - duty;
370
+ }
371
+
372
+ return duty;
373
+}
374
+
375
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
376
+{
377
+ uint32_t freq = npcm7xx_pwm_calculate_freq(p);
378
+
379
+ if (freq != p->freq) {
380
+ trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
381
+ p->index, p->freq, freq);
382
+ p->freq = freq;
383
+ }
384
+}
385
+
386
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
387
+{
388
+ uint32_t duty = npcm7xx_pwm_calculate_duty(p);
389
+
390
+ if (duty != p->duty) {
391
+ trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
392
+ p->index, p->duty, duty);
393
+ p->duty = duty;
394
+ }
395
+}
396
+
397
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
398
+{
399
+ npcm7xx_pwm_update_freq(p);
400
+ npcm7xx_pwm_update_duty(p);
401
+}
402
+
403
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
136
+{
404
+{
137
+ int i;
405
+ int i;
138
+ uint32_t value = 0;
406
+ uint32_t old_ppr = s->ppr;
139
+ for (i = 0; i < 10; i++) {
407
+
140
+ uint32_t index = 10 * reg + i;
408
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
141
+ if (index < sizeof(s->fsel)) {
409
+ s->ppr = new_ppr;
142
+ value |= (s->fsel[index] & 0x7) << (3 * i);
410
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
411
+ if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
412
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
143
+ }
413
+ }
144
+ }
414
+ }
415
+}
416
+
417
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
418
+{
419
+ int i;
420
+ uint32_t old_csr = s->csr;
421
+
422
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
423
+ s->csr = new_csr;
424
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
425
+ if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
426
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
427
+ }
428
+ }
429
+}
430
+
431
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
432
+{
433
+ int i;
434
+ bool inverted;
435
+ uint32_t pcr;
436
+ NPCM7xxPWM *p;
437
+
438
+ s->pcr = new_pcr;
439
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
440
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
441
+ p = &s->pwm[i];
442
+ pcr = NPCM7XX_CH(new_pcr, i);
443
+ inverted = pcr & NPCM7XX_CH_INV;
444
+
445
+ /*
446
+ * We only run a PWM channel with toggle mode. Single-shot mode does not
447
+ * generate frequency and duty-cycle values.
448
+ */
449
+ if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
450
+ if (p->running) {
451
+ /* Re-run this PWM channel if inverted changed. */
452
+ if (p->inverted ^ inverted) {
453
+ p->inverted = inverted;
454
+ npcm7xx_pwm_update_duty(p);
455
+ }
456
+ } else {
457
+ /* Run this PWM channel. */
458
+ p->running = true;
459
+ p->inverted = inverted;
460
+ npcm7xx_pwm_update_output(p);
461
+ }
462
+ } else {
463
+ /* Clear this PWM channel. */
464
+ p->running = false;
465
+ p->inverted = inverted;
466
+ npcm7xx_pwm_update_output(p);
467
+ }
468
+ }
469
+
470
+}
471
+
472
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
473
+{
474
+ switch (offset) {
475
+ case A_NPCM7XX_PWM_CNR0:
476
+ return 0;
477
+ case A_NPCM7XX_PWM_CNR1:
478
+ return 1;
479
+ case A_NPCM7XX_PWM_CNR2:
480
+ return 2;
481
+ case A_NPCM7XX_PWM_CNR3:
482
+ return 3;
483
+ default:
484
+ g_assert_not_reached();
485
+ }
486
+}
487
+
488
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
489
+{
490
+ switch (offset) {
491
+ case A_NPCM7XX_PWM_CMR0:
492
+ return 0;
493
+ case A_NPCM7XX_PWM_CMR1:
494
+ return 1;
495
+ case A_NPCM7XX_PWM_CMR2:
496
+ return 2;
497
+ case A_NPCM7XX_PWM_CMR3:
498
+ return 3;
499
+ default:
500
+ g_assert_not_reached();
501
+ }
502
+}
503
+
504
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
505
+{
506
+ switch (offset) {
507
+ case A_NPCM7XX_PWM_PDR0:
508
+ return 0;
509
+ case A_NPCM7XX_PWM_PDR1:
510
+ return 1;
511
+ case A_NPCM7XX_PWM_PDR2:
512
+ return 2;
513
+ case A_NPCM7XX_PWM_PDR3:
514
+ return 3;
515
+ default:
516
+ g_assert_not_reached();
517
+ }
518
+}
519
+
520
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
521
+{
522
+ switch (offset) {
523
+ case A_NPCM7XX_PWM_PWDR0:
524
+ return 0;
525
+ case A_NPCM7XX_PWM_PWDR1:
526
+ return 1;
527
+ case A_NPCM7XX_PWM_PWDR2:
528
+ return 2;
529
+ case A_NPCM7XX_PWM_PWDR3:
530
+ return 3;
531
+ default:
532
+ g_assert_not_reached();
533
+ }
534
+}
535
+
536
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
537
+{
538
+ NPCM7xxPWMState *s = opaque;
539
+ uint64_t value = 0;
540
+
541
+ switch (offset) {
542
+ case A_NPCM7XX_PWM_CNR0:
543
+ case A_NPCM7XX_PWM_CNR1:
544
+ case A_NPCM7XX_PWM_CNR2:
545
+ case A_NPCM7XX_PWM_CNR3:
546
+ value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
547
+ break;
548
+
549
+ case A_NPCM7XX_PWM_CMR0:
550
+ case A_NPCM7XX_PWM_CMR1:
551
+ case A_NPCM7XX_PWM_CMR2:
552
+ case A_NPCM7XX_PWM_CMR3:
553
+ value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
554
+ break;
555
+
556
+ case A_NPCM7XX_PWM_PDR0:
557
+ case A_NPCM7XX_PWM_PDR1:
558
+ case A_NPCM7XX_PWM_PDR2:
559
+ case A_NPCM7XX_PWM_PDR3:
560
+ value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
561
+ break;
562
+
563
+ case A_NPCM7XX_PWM_PWDR0:
564
+ case A_NPCM7XX_PWM_PWDR1:
565
+ case A_NPCM7XX_PWM_PWDR2:
566
+ case A_NPCM7XX_PWM_PWDR3:
567
+ value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
568
+ break;
569
+
570
+ case A_NPCM7XX_PWM_PPR:
571
+ value = s->ppr;
572
+ break;
573
+
574
+ case A_NPCM7XX_PWM_CSR:
575
+ value = s->csr;
576
+ break;
577
+
578
+ case A_NPCM7XX_PWM_PCR:
579
+ value = s->pcr;
580
+ break;
581
+
582
+ case A_NPCM7XX_PWM_PIER:
583
+ value = s->pier;
584
+ break;
585
+
586
+ case A_NPCM7XX_PWM_PIIR:
587
+ value = s->piir;
588
+ break;
589
+
590
+ default:
591
+ qemu_log_mask(LOG_GUEST_ERROR,
592
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
593
+ __func__, offset);
594
+ break;
595
+ }
596
+
597
+ trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
145
+ return value;
598
+ return value;
146
+}
599
+}
147
+
600
+
148
+static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value)
601
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
149
+{
602
+ uint64_t v, unsigned size)
603
+{
604
+ NPCM7xxPWMState *s = opaque;
605
+ NPCM7xxPWM *p;
606
+ uint32_t value = v;
607
+
608
+ trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
609
+ switch (offset) {
610
+ case A_NPCM7XX_PWM_CNR0:
611
+ case A_NPCM7XX_PWM_CNR1:
612
+ case A_NPCM7XX_PWM_CNR2:
613
+ case A_NPCM7XX_PWM_CNR3:
614
+ p = &s->pwm[npcm7xx_cnr_index(offset)];
615
+ p->cnr = value;
616
+ npcm7xx_pwm_update_output(p);
617
+ break;
618
+
619
+ case A_NPCM7XX_PWM_CMR0:
620
+ case A_NPCM7XX_PWM_CMR1:
621
+ case A_NPCM7XX_PWM_CMR2:
622
+ case A_NPCM7XX_PWM_CMR3:
623
+ p = &s->pwm[npcm7xx_cmr_index(offset)];
624
+ p->cmr = value;
625
+ npcm7xx_pwm_update_output(p);
626
+ break;
627
+
628
+ case A_NPCM7XX_PWM_PDR0:
629
+ case A_NPCM7XX_PWM_PDR1:
630
+ case A_NPCM7XX_PWM_PDR2:
631
+ case A_NPCM7XX_PWM_PDR3:
632
+ qemu_log_mask(LOG_GUEST_ERROR,
633
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
634
+ __func__, offset);
635
+ break;
636
+
637
+ case A_NPCM7XX_PWM_PWDR0:
638
+ case A_NPCM7XX_PWM_PWDR1:
639
+ case A_NPCM7XX_PWM_PWDR2:
640
+ case A_NPCM7XX_PWM_PWDR3:
641
+ qemu_log_mask(LOG_UNIMP,
642
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
643
+ __func__, offset);
644
+ break;
645
+
646
+ case A_NPCM7XX_PWM_PPR:
647
+ npcm7xx_pwm_write_ppr(s, value);
648
+ break;
649
+
650
+ case A_NPCM7XX_PWM_CSR:
651
+ npcm7xx_pwm_write_csr(s, value);
652
+ break;
653
+
654
+ case A_NPCM7XX_PWM_PCR:
655
+ npcm7xx_pwm_write_pcr(s, value);
656
+ break;
657
+
658
+ case A_NPCM7XX_PWM_PIER:
659
+ qemu_log_mask(LOG_UNIMP,
660
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
661
+ __func__, offset);
662
+ break;
663
+
664
+ case A_NPCM7XX_PWM_PIIR:
665
+ qemu_log_mask(LOG_UNIMP,
666
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
667
+ __func__, offset);
668
+ break;
669
+
670
+ default:
671
+ qemu_log_mask(LOG_GUEST_ERROR,
672
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
673
+ __func__, offset);
674
+ break;
675
+ }
676
+}
677
+
678
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
679
+ .read = npcm7xx_pwm_read,
680
+ .write = npcm7xx_pwm_write,
681
+ .endianness = DEVICE_LITTLE_ENDIAN,
682
+ .valid = {
683
+ .min_access_size = 4,
684
+ .max_access_size = 4,
685
+ .unaligned = false,
686
+ },
687
+};
688
+
689
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
690
+{
691
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
150
+ int i;
692
+ int i;
151
+ for (i = 0; i < 10; i++) {
693
+
152
+ uint32_t index = 10 * reg + i;
694
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
153
+ if (index < sizeof(s->fsel)) {
695
+ NPCM7xxPWM *p = &s->pwm[i];
154
+ int fsel = (value >> (3 * i)) & 0x7;
696
+
155
+ s->fsel[index] = fsel;
697
+ p->cnr = 0x00000000;
156
+ }
698
+ p->cmr = 0x00000000;
157
+ }
699
+ p->pdr = 0x00000000;
158
+
700
+ p->pwdr = 0x00000000;
159
+ /* SD controller selection (48-53) */
701
+ }
160
+ if (s->sd_fsel != 0
702
+
161
+ && (s->fsel[48] == 0) /* SD_CLK_R */
703
+ s->ppr = 0x00000000;
162
+ && (s->fsel[49] == 0) /* SD_CMD_R */
704
+ s->csr = 0x00000000;
163
+ && (s->fsel[50] == 0) /* SD_DATA0_R */
705
+ s->pcr = 0x00000000;
164
+ && (s->fsel[51] == 0) /* SD_DATA1_R */
706
+ s->pier = 0x00000000;
165
+ && (s->fsel[52] == 0) /* SD_DATA2_R */
707
+ s->piir = 0x00000000;
166
+ && (s->fsel[53] == 0) /* SD_DATA3_R */
708
+}
167
+ ) {
709
+
168
+ /* SDHCI controller selected */
710
+static void npcm7xx_pwm_hold_reset(Object *obj)
169
+ sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci);
711
+{
170
+ s->sd_fsel = 0;
712
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
171
+ } else if (s->sd_fsel != 4
172
+ && (s->fsel[48] == 4) /* SD_CLK_R */
173
+ && (s->fsel[49] == 4) /* SD_CMD_R */
174
+ && (s->fsel[50] == 4) /* SD_DATA0_R */
175
+ && (s->fsel[51] == 4) /* SD_DATA1_R */
176
+ && (s->fsel[52] == 4) /* SD_DATA2_R */
177
+ && (s->fsel[53] == 4) /* SD_DATA3_R */
178
+ ) {
179
+ /* SDHost controller selected */
180
+ sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost);
181
+ s->sd_fsel = 4;
182
+ }
183
+}
184
+
185
+static int gpfsel_is_out(BCM2835GpioState *s, int index)
186
+{
187
+ if (index >= 0 && index < 54) {
188
+ return s->fsel[index] == 1;
189
+ }
190
+ return 0;
191
+}
192
+
193
+static void gpset(BCM2835GpioState *s,
194
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
195
+{
196
+ uint32_t changes = val & ~*lev;
197
+ uint32_t cur = 1;
198
+
199
+ int i;
713
+ int i;
200
+ for (i = 0; i < count; i++) {
714
+
201
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
715
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
202
+ qemu_set_irq(s->out[start + i], 1);
716
+ qemu_irq_lower(s->pwm[i].irq);
203
+ }
717
+ }
204
+ cur <<= 1;
718
+}
205
+ }
719
+
206
+
720
+static void npcm7xx_pwm_init(Object *obj)
207
+ *lev |= val;
721
+{
208
+}
722
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
209
+
723
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
210
+static void gpclr(BCM2835GpioState *s,
211
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
212
+{
213
+ uint32_t changes = val & *lev;
214
+ uint32_t cur = 1;
215
+
216
+ int i;
724
+ int i;
217
+ for (i = 0; i < count; i++) {
725
+
218
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
726
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
219
+ qemu_set_irq(s->out[start + i], 0);
727
+ NPCM7xxPWM *p = &s->pwm[i];
220
+ }
728
+ p->module = s;
221
+ cur <<= 1;
729
+ p->index = i;
222
+ }
730
+ sysbus_init_irq(sbd, &p->irq);
223
+
731
+ }
224
+ *lev &= ~val;
732
+
225
+}
733
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
226
+
734
+ TYPE_NPCM7XX_PWM, 4 * KiB);
227
+static uint64_t bcm2835_gpio_read(void *opaque, hwaddr offset,
735
+ sysbus_init_mmio(sbd, &s->iomem);
228
+ unsigned size)
736
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
229
+{
737
+
230
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
738
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
231
+
739
+ object_property_add_uint32_ptr(obj, "freq[*]",
232
+ switch (offset) {
740
+ &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
233
+ case GPFSEL0:
741
+ object_property_add_uint32_ptr(obj, "duty[*]",
234
+ case GPFSEL1:
742
+ &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
235
+ case GPFSEL2:
743
+ }
236
+ case GPFSEL3:
744
+}
237
+ case GPFSEL4:
745
+
238
+ case GPFSEL5:
746
+static const VMStateDescription vmstate_npcm7xx_pwm = {
239
+ return gpfsel_get(s, offset / 4);
747
+ .name = "npcm7xx-pwm",
240
+ case GPSET0:
748
+ .version_id = 0,
241
+ case GPSET1:
749
+ .minimum_version_id = 0,
242
+ /* Write Only */
750
+ .fields = (VMStateField[]) {
243
+ return 0;
751
+ VMSTATE_BOOL(running, NPCM7xxPWM),
244
+ case GPCLR0:
752
+ VMSTATE_BOOL(inverted, NPCM7xxPWM),
245
+ case GPCLR1:
753
+ VMSTATE_UINT8(index, NPCM7xxPWM),
246
+ /* Write Only */
754
+ VMSTATE_UINT32(cnr, NPCM7xxPWM),
247
+ return 0;
755
+ VMSTATE_UINT32(cmr, NPCM7xxPWM),
248
+ case GPLEV0:
756
+ VMSTATE_UINT32(pdr, NPCM7xxPWM),
249
+ return s->lev0;
757
+ VMSTATE_UINT32(pwdr, NPCM7xxPWM),
250
+ case GPLEV1:
758
+ VMSTATE_UINT32(freq, NPCM7xxPWM),
251
+ return s->lev1;
759
+ VMSTATE_UINT32(duty, NPCM7xxPWM),
252
+ case GPEDS0:
760
+ VMSTATE_END_OF_LIST(),
253
+ case GPEDS1:
761
+ },
254
+ case GPREN0:
255
+ case GPREN1:
256
+ case GPFEN0:
257
+ case GPFEN1:
258
+ case GPHEN0:
259
+ case GPHEN1:
260
+ case GPLEN0:
261
+ case GPLEN1:
262
+ case GPAREN0:
263
+ case GPAREN1:
264
+ case GPAFEN0:
265
+ case GPAFEN1:
266
+ case GPPUD:
267
+ case GPPUDCLK0:
268
+ case GPPUDCLK1:
269
+ /* Not implemented */
270
+ return 0;
271
+ default:
272
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
273
+ __func__, offset);
274
+ break;
275
+ }
276
+
277
+ return 0;
278
+}
279
+
280
+static void bcm2835_gpio_write(void *opaque, hwaddr offset,
281
+ uint64_t value, unsigned size)
282
+{
283
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
284
+
285
+ switch (offset) {
286
+ case GPFSEL0:
287
+ case GPFSEL1:
288
+ case GPFSEL2:
289
+ case GPFSEL3:
290
+ case GPFSEL4:
291
+ case GPFSEL5:
292
+ gpfsel_set(s, offset / 4, value);
293
+ break;
294
+ case GPSET0:
295
+ gpset(s, value, 0, 32, &s->lev0);
296
+ break;
297
+ case GPSET1:
298
+ gpset(s, value, 32, 22, &s->lev1);
299
+ break;
300
+ case GPCLR0:
301
+ gpclr(s, value, 0, 32, &s->lev0);
302
+ break;
303
+ case GPCLR1:
304
+ gpclr(s, value, 32, 22, &s->lev1);
305
+ break;
306
+ case GPLEV0:
307
+ case GPLEV1:
308
+ /* Read Only */
309
+ break;
310
+ case GPEDS0:
311
+ case GPEDS1:
312
+ case GPREN0:
313
+ case GPREN1:
314
+ case GPFEN0:
315
+ case GPFEN1:
316
+ case GPHEN0:
317
+ case GPHEN1:
318
+ case GPLEN0:
319
+ case GPLEN1:
320
+ case GPAREN0:
321
+ case GPAREN1:
322
+ case GPAFEN0:
323
+ case GPAFEN1:
324
+ case GPPUD:
325
+ case GPPUDCLK0:
326
+ case GPPUDCLK1:
327
+ /* Not implemented */
328
+ break;
329
+ default:
330
+ goto err_out;
331
+ }
332
+ return;
333
+
334
+err_out:
335
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
336
+ __func__, offset);
337
+}
338
+
339
+static void bcm2835_gpio_reset(DeviceState *dev)
340
+{
341
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
342
+
343
+ int i;
344
+ for (i = 0; i < 6; i++) {
345
+ gpfsel_set(s, i, 0);
346
+ }
347
+
348
+ s->sd_fsel = 0;
349
+
350
+ /* SDHCI is selected by default */
351
+ sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci);
352
+
353
+ s->lev0 = 0;
354
+ s->lev1 = 0;
355
+}
356
+
357
+static const MemoryRegionOps bcm2835_gpio_ops = {
358
+ .read = bcm2835_gpio_read,
359
+ .write = bcm2835_gpio_write,
360
+ .endianness = DEVICE_NATIVE_ENDIAN,
361
+};
762
+};
362
+
763
+
363
+static const VMStateDescription vmstate_bcm2835_gpio = {
764
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
364
+ .name = "bcm2835_gpio",
765
+ .name = "npcm7xx-pwm-module",
365
+ .version_id = 1,
766
+ .version_id = 0,
366
+ .minimum_version_id = 1,
767
+ .minimum_version_id = 0,
367
+ .fields = (VMStateField[]) {
768
+ .fields = (VMStateField[]) {
368
+ VMSTATE_UINT8_ARRAY(fsel, BCM2835GpioState, 54),
769
+ VMSTATE_CLOCK(clock, NPCM7xxPWMState),
369
+ VMSTATE_UINT32(lev0, BCM2835GpioState),
770
+ VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
370
+ VMSTATE_UINT32(lev1, BCM2835GpioState),
771
+ NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
371
+ VMSTATE_UINT8(sd_fsel, BCM2835GpioState),
772
+ NPCM7xxPWM),
372
+ VMSTATE_END_OF_LIST()
773
+ VMSTATE_UINT32(ppr, NPCM7xxPWMState),
373
+ }
774
+ VMSTATE_UINT32(csr, NPCM7xxPWMState),
775
+ VMSTATE_UINT32(pcr, NPCM7xxPWMState),
776
+ VMSTATE_UINT32(pier, NPCM7xxPWMState),
777
+ VMSTATE_UINT32(piir, NPCM7xxPWMState),
778
+ VMSTATE_END_OF_LIST(),
779
+ },
374
+};
780
+};
375
+
781
+
376
+static void bcm2835_gpio_init(Object *obj)
782
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
377
+{
783
+{
378
+ BCM2835GpioState *s = BCM2835_GPIO(obj);
784
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
379
+ DeviceState *dev = DEVICE(obj);
380
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
381
+
382
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
383
+ TYPE_SD_BUS, DEVICE(s), "sd-bus");
384
+
385
+ memory_region_init_io(&s->iomem, obj,
386
+ &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
387
+ sysbus_init_mmio(sbd, &s->iomem);
388
+ qdev_init_gpio_out(dev, s->out, 54);
389
+}
390
+
391
+static void bcm2835_gpio_realize(DeviceState *dev, Error **errp)
392
+{
393
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
394
+ Object *obj;
395
+ Error *err = NULL;
396
+
397
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhci", &err);
398
+ if (obj == NULL) {
399
+ error_setg(errp, "%s: required sdhci link not found: %s",
400
+ __func__, error_get_pretty(err));
401
+ return;
402
+ }
403
+ s->sdbus_sdhci = SD_BUS(obj);
404
+
405
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhost", &err);
406
+ if (obj == NULL) {
407
+ error_setg(errp, "%s: required sdhost link not found: %s",
408
+ __func__, error_get_pretty(err));
409
+ return;
410
+ }
411
+ s->sdbus_sdhost = SD_BUS(obj);
412
+}
413
+
414
+static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
415
+{
416
+ DeviceClass *dc = DEVICE_CLASS(klass);
785
+ DeviceClass *dc = DEVICE_CLASS(klass);
417
+
786
+
418
+ dc->vmsd = &vmstate_bcm2835_gpio;
787
+ dc->desc = "NPCM7xx PWM Controller";
419
+ dc->realize = &bcm2835_gpio_realize;
788
+ dc->vmsd = &vmstate_npcm7xx_pwm_module;
420
+ dc->reset = &bcm2835_gpio_reset;
789
+ rc->phases.enter = npcm7xx_pwm_enter_reset;
421
+}
790
+ rc->phases.hold = npcm7xx_pwm_hold_reset;
422
+
791
+}
423
+static const TypeInfo bcm2835_gpio_info = {
792
+
424
+ .name = TYPE_BCM2835_GPIO,
793
+static const TypeInfo npcm7xx_pwm_info = {
425
+ .parent = TYPE_SYS_BUS_DEVICE,
794
+ .name = TYPE_NPCM7XX_PWM,
426
+ .instance_size = sizeof(BCM2835GpioState),
795
+ .parent = TYPE_SYS_BUS_DEVICE,
427
+ .instance_init = bcm2835_gpio_init,
796
+ .instance_size = sizeof(NPCM7xxPWMState),
428
+ .class_init = bcm2835_gpio_class_init,
797
+ .class_init = npcm7xx_pwm_class_init,
798
+ .instance_init = npcm7xx_pwm_init,
429
+};
799
+};
430
+
800
+
431
+static void bcm2835_gpio_register_types(void)
801
+static void npcm7xx_pwm_register_type(void)
432
+{
802
+{
433
+ type_register_static(&bcm2835_gpio_info);
803
+ type_register_static(&npcm7xx_pwm_info);
434
+}
804
+}
435
+
805
+type_init(npcm7xx_pwm_register_type);
436
+type_init(bcm2835_gpio_register_types)
806
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
807
index XXXXXXX..XXXXXXX 100644
808
--- a/hw/misc/meson.build
809
+++ b/hw/misc/meson.build
810
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
811
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
812
'npcm7xx_clk.c',
813
'npcm7xx_gcr.c',
814
+ 'npcm7xx_pwm.c',
815
'npcm7xx_rng.c',
816
))
817
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
818
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
819
index XXXXXXX..XXXXXXX 100644
820
--- a/hw/misc/trace-events
821
+++ b/hw/misc/trace-events
822
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
823
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
824
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
825
826
+# npcm7xx_pwm.c
827
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
828
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
829
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
830
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
831
+
832
# stm32f4xx_syscfg.c
833
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
834
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
437
--
835
--
438
2.7.4
836
2.20.1
439
837
440
838
diff view generated by jsdifflib
1
Move the NVICState struct definition into a header, so we can
1
From: Hao Wu <wuhaotsh@google.com>
2
embed it into other QOM objects like SoCs.
3
2
3
We add a qtest for the PWM in the previous patch. It proves it works as
4
expected.
5
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
8
---
12
---
9
include/hw/arm/armv7m_nvic.h | 66 ++++++++++++++++++++++++++++++++++++++++++++
13
tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
10
hw/intc/armv7m_nvic.c | 49 +-------------------------------
14
tests/qtest/meson.build | 1 +
11
2 files changed, 67 insertions(+), 48 deletions(-)
15
2 files changed, 491 insertions(+)
12
create mode 100644 include/hw/arm/armv7m_nvic.h
16
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
13
17
14
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
18
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
15
new file mode 100644
19
new file mode 100644
16
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
17
--- /dev/null
21
--- /dev/null
18
+++ b/include/hw/arm/armv7m_nvic.h
22
+++ b/tests/qtest/npcm7xx_pwm-test.c
19
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
20
+/*
24
+/*
21
+ * ARMv7M NVIC object
25
+ * QTests for Nuvoton NPCM7xx PWM Modules.
22
+ *
26
+ *
23
+ * Copyright (c) 2017 Linaro Ltd
27
+ * Copyright 2020 Google LLC
24
+ * Written by Peter Maydell <peter.maydell@linaro.org>
25
+ *
28
+ *
26
+ * This code is licensed under the GPL version 2 or later.
29
+ * This program is free software; you can redistribute it and/or modify it
30
+ * under the terms of the GNU General Public License as published by the
31
+ * Free Software Foundation; either version 2 of the License, or
32
+ * (at your option) any later version.
33
+ *
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37
+ * for more details.
27
+ */
38
+ */
28
+
39
+
29
+#ifndef HW_ARM_ARMV7M_NVIC_H
40
+#include "qemu/osdep.h"
30
+#define HW_ARM_ARMV7M_NVIC_H
41
+#include "qemu/bitops.h"
31
+
42
+#include "libqos/libqtest.h"
32
+#include "target/arm/cpu.h"
43
+#include "qapi/qmp/qdict.h"
33
+#include "hw/sysbus.h"
44
+#include "qapi/qmp/qnum.h"
34
+
45
+
35
+#define TYPE_NVIC "armv7m_nvic"
46
+#define REF_HZ 25000000
36
+
47
+
37
+#define NVIC(obj) \
48
+/* Register field definitions. */
38
+ OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
49
+#define CH_EN BIT(0)
39
+
50
+#define CH_INV BIT(2)
40
+/* Highest permitted number of exceptions (architectural limit) */
51
+#define CH_MOD BIT(3)
41
+#define NVIC_MAX_VECTORS 512
52
+
42
+
53
+/* Registers shared between all PWMs in a module */
43
+typedef struct VecInfo {
54
+#define PPR 0x00
44
+ /* Exception priorities can range from -3 to 255; only the unmodifiable
55
+#define CSR 0x04
45
+ * priority values for RESET, NMI and HardFault can be negative.
56
+#define PCR 0x08
46
+ */
57
+#define PIER 0x3c
47
+ int16_t prio;
58
+#define PIIR 0x40
48
+ uint8_t enabled;
59
+
49
+ uint8_t pending;
60
+/* CLK module related */
50
+ uint8_t active;
61
+#define CLK_BA 0xf0801000
51
+ uint8_t level; /* exceptions <=15 never set level */
62
+#define CLKSEL 0x04
52
+} VecInfo;
63
+#define CLKDIV1 0x08
53
+
64
+#define CLKDIV2 0x2c
54
+typedef struct NVICState {
65
+#define PLLCON0 0x0c
55
+ /*< private >*/
66
+#define PLLCON1 0x10
56
+ SysBusDevice parent_obj;
67
+#define PLL_INDV(rv) extract32((rv), 0, 6)
57
+ /*< public >*/
68
+#define PLL_FBDV(rv) extract32((rv), 16, 12)
58
+
69
+#define PLL_OTDV1(rv) extract32((rv), 8, 3)
59
+ ARMCPU *cpu;
70
+#define PLL_OTDV2(rv) extract32((rv), 13, 3)
60
+
71
+#define APB3CKDIV(rv) extract32((rv), 28, 2)
61
+ VecInfo vectors[NVIC_MAX_VECTORS];
72
+#define CLK2CKDIV(rv) extract32((rv), 0, 1)
62
+ uint32_t prigroup;
73
+#define CLK4CKDIV(rv) extract32((rv), 26, 2)
63
+
74
+#define CPUCKSEL(rv) extract32((rv), 0, 2)
64
+ /* vectpending and exception_prio are both cached state that can
75
+
65
+ * be recalculated from the vectors[] array and the prigroup field.
76
+#define MAX_DUTY 1000000
66
+ */
77
+
67
+ unsigned int vectpending; /* highest prio pending enabled exception */
78
+typedef struct PWMModule {
68
+ int exception_prio; /* group prio of the highest prio active exception */
79
+ int irq;
69
+
80
+ uint64_t base_addr;
70
+ struct {
81
+} PWMModule;
71
+ uint32_t control;
82
+
72
+ uint32_t reload;
83
+typedef struct PWM {
73
+ int64_t tick;
84
+ uint32_t cnr_offset;
74
+ QEMUTimer *timer;
85
+ uint32_t cmr_offset;
75
+ } systick;
86
+ uint32_t pdr_offset;
76
+
87
+ uint32_t pwdr_offset;
77
+ MemoryRegion sysregmem;
88
+} PWM;
78
+ MemoryRegion container;
89
+
79
+
90
+typedef struct TestData {
80
+ uint32_t num_irq;
91
+ const PWMModule *module;
81
+ qemu_irq excpout;
92
+ const PWM *pwm;
82
+ qemu_irq sysresetreq;
93
+} TestData;
83
+} NVICState;
94
+
84
+
95
+static const PWMModule pwm_module_list[] = {
85
+#endif
96
+ {
86
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
97
+ .irq = 93,
98
+ .base_addr = 0xf0103000
99
+ },
100
+ {
101
+ .irq = 94,
102
+ .base_addr = 0xf0104000
103
+ }
104
+};
105
+
106
+static const PWM pwm_list[] = {
107
+ {
108
+ .cnr_offset = 0x0c,
109
+ .cmr_offset = 0x10,
110
+ .pdr_offset = 0x14,
111
+ .pwdr_offset = 0x44,
112
+ },
113
+ {
114
+ .cnr_offset = 0x18,
115
+ .cmr_offset = 0x1c,
116
+ .pdr_offset = 0x20,
117
+ .pwdr_offset = 0x48,
118
+ },
119
+ {
120
+ .cnr_offset = 0x24,
121
+ .cmr_offset = 0x28,
122
+ .pdr_offset = 0x2c,
123
+ .pwdr_offset = 0x4c,
124
+ },
125
+ {
126
+ .cnr_offset = 0x30,
127
+ .cmr_offset = 0x34,
128
+ .pdr_offset = 0x38,
129
+ .pwdr_offset = 0x50,
130
+ },
131
+};
132
+
133
+static const int ppr_base[] = { 0, 0, 8, 8 };
134
+static const int csr_base[] = { 0, 4, 8, 12 };
135
+static const int pcr_base[] = { 0, 8, 12, 16 };
136
+
137
+static const uint32_t ppr_list[] = {
138
+ 0,
139
+ 1,
140
+ 10,
141
+ 100,
142
+ 255, /* Max possible value. */
143
+};
144
+
145
+static const uint32_t csr_list[] = {
146
+ 0,
147
+ 1,
148
+ 2,
149
+ 3,
150
+ 4, /* Max possible value. */
151
+};
152
+
153
+static const uint32_t cnr_list[] = {
154
+ 0,
155
+ 1,
156
+ 50,
157
+ 100,
158
+ 150,
159
+ 200,
160
+ 1000,
161
+ 10000,
162
+ 65535, /* Max possible value. */
163
+};
164
+
165
+static const uint32_t cmr_list[] = {
166
+ 0,
167
+ 1,
168
+ 10,
169
+ 50,
170
+ 100,
171
+ 150,
172
+ 200,
173
+ 1000,
174
+ 10000,
175
+ 65535, /* Max possible value. */
176
+};
177
+
178
+/* Returns the index of the PWM module. */
179
+static int pwm_module_index(const PWMModule *module)
180
+{
181
+ ptrdiff_t diff = module - pwm_module_list;
182
+
183
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
184
+
185
+ return diff;
186
+}
187
+
188
+/* Returns the index of the PWM entry. */
189
+static int pwm_index(const PWM *pwm)
190
+{
191
+ ptrdiff_t diff = pwm - pwm_list;
192
+
193
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
194
+
195
+ return diff;
196
+}
197
+
198
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
199
+{
200
+ QDict *response;
201
+
202
+ g_test_message("Getting properties %s from %s", name, path);
203
+ response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
204
+ " 'arguments': { 'path': %s, 'property': %s}}",
205
+ path, name);
206
+ /* The qom set message returns successfully. */
207
+ g_assert_true(qdict_haskey(response, "return"));
208
+ return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
209
+}
210
+
211
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
212
+{
213
+ char path[100];
214
+ char name[100];
215
+
216
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
217
+ sprintf(name, "freq[%d]", pwm_index);
218
+
219
+ return pwm_qom_get(qts, path, name);
220
+}
221
+
222
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
223
+{
224
+ char path[100];
225
+ char name[100];
226
+
227
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
228
+ sprintf(name, "duty[%d]", pwm_index);
229
+
230
+ return pwm_qom_get(qts, path, name);
231
+}
232
+
233
+static uint32_t get_pll(uint32_t con)
234
+{
235
+ return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
236
+ * PLL_OTDV2(con));
237
+}
238
+
239
+static uint64_t read_pclk(QTestState *qts)
240
+{
241
+ uint64_t freq = REF_HZ;
242
+ uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
243
+ uint32_t pllcon;
244
+ uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
245
+ uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
246
+
247
+ switch (CPUCKSEL(clksel)) {
248
+ case 0:
249
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
250
+ freq = get_pll(pllcon);
251
+ break;
252
+ case 1:
253
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
254
+ freq = get_pll(pllcon);
255
+ break;
256
+ case 2:
257
+ break;
258
+ case 3:
259
+ break;
260
+ default:
261
+ g_assert_not_reached();
262
+ }
263
+
264
+ freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
265
+
266
+ return freq;
267
+}
268
+
269
+static uint32_t pwm_selector(uint32_t csr)
270
+{
271
+ switch (csr) {
272
+ case 0:
273
+ return 2;
274
+ case 1:
275
+ return 4;
276
+ case 2:
277
+ return 8;
278
+ case 3:
279
+ return 16;
280
+ case 4:
281
+ return 1;
282
+ default:
283
+ g_assert_not_reached();
284
+ }
285
+}
286
+
287
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
288
+ uint32_t cnr)
289
+{
290
+ return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
291
+}
292
+
293
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
294
+{
295
+ uint64_t duty;
296
+
297
+ if (cnr == 0) {
298
+ /* PWM is stopped. */
299
+ duty = 0;
300
+ } else if (cmr >= cnr) {
301
+ duty = MAX_DUTY;
302
+ } else {
303
+ duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
304
+ }
305
+
306
+ if (inverted) {
307
+ duty = MAX_DUTY - duty;
308
+ }
309
+
310
+ return duty;
311
+}
312
+
313
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
314
+{
315
+ return qtest_readl(qts, td->module->base_addr + offset);
316
+}
317
+
318
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
319
+ uint32_t value)
320
+{
321
+ qtest_writel(qts, td->module->base_addr + offset, value);
322
+}
323
+
324
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
325
+{
326
+ return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
327
+}
328
+
329
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
330
+{
331
+ pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
332
+}
333
+
334
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
335
+{
336
+ return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
337
+}
338
+
339
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
340
+{
341
+ pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
342
+}
343
+
344
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
345
+{
346
+ return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
347
+}
348
+
349
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
350
+{
351
+ pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
352
+}
353
+
354
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
355
+{
356
+ return pwm_read(qts, td, td->pwm->cnr_offset);
357
+}
358
+
359
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
360
+{
361
+ pwm_write(qts, td, td->pwm->cnr_offset, value);
362
+}
363
+
364
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
365
+{
366
+ return pwm_read(qts, td, td->pwm->cmr_offset);
367
+}
368
+
369
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
370
+{
371
+ pwm_write(qts, td, td->pwm->cmr_offset, value);
372
+}
373
+
374
+/* Check pwm registers can be reset to default value */
375
+static void test_init(gconstpointer test_data)
376
+{
377
+ const TestData *td = test_data;
378
+ QTestState *qts = qtest_init("-machine quanta-gsj");
379
+ int module = pwm_module_index(td->module);
380
+ int pwm = pwm_index(td->pwm);
381
+
382
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
383
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
384
+
385
+ qtest_quit(qts);
386
+}
387
+
388
+/* One-shot mode should not change frequency and duty cycle. */
389
+static void test_oneshot(gconstpointer test_data)
390
+{
391
+ const TestData *td = test_data;
392
+ QTestState *qts = qtest_init("-machine quanta-gsj");
393
+ int module = pwm_module_index(td->module);
394
+ int pwm = pwm_index(td->pwm);
395
+ uint32_t ppr, csr, pcr;
396
+ int i, j;
397
+
398
+ pcr = CH_EN;
399
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
400
+ ppr = ppr_list[i];
401
+ pwm_write_ppr(qts, td, ppr);
402
+
403
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
404
+ csr = csr_list[j];
405
+ pwm_write_csr(qts, td, csr);
406
+ pwm_write_pcr(qts, td, pcr);
407
+
408
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
409
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
410
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
411
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
412
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
413
+ }
414
+ }
415
+
416
+ qtest_quit(qts);
417
+}
418
+
419
+/* In toggle mode, the PWM generates correct outputs. */
420
+static void test_toggle(gconstpointer test_data)
421
+{
422
+ const TestData *td = test_data;
423
+ QTestState *qts = qtest_init("-machine quanta-gsj");
424
+ int module = pwm_module_index(td->module);
425
+ int pwm = pwm_index(td->pwm);
426
+ uint32_t ppr, csr, pcr, cnr, cmr;
427
+ int i, j, k, l;
428
+ uint64_t expected_freq, expected_duty;
429
+
430
+ pcr = CH_EN | CH_MOD;
431
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
432
+ ppr = ppr_list[i];
433
+ pwm_write_ppr(qts, td, ppr);
434
+
435
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
436
+ csr = csr_list[j];
437
+ pwm_write_csr(qts, td, csr);
438
+
439
+ for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
440
+ cnr = cnr_list[k];
441
+ pwm_write_cnr(qts, td, cnr);
442
+
443
+ for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
444
+ cmr = cmr_list[l];
445
+ pwm_write_cmr(qts, td, cmr);
446
+ expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
447
+ expected_duty = pwm_compute_duty(cnr, cmr, false);
448
+
449
+ pwm_write_pcr(qts, td, pcr);
450
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
451
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
452
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
453
+ g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
454
+ g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
455
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
456
+ ==, expected_duty);
457
+ if (expected_duty != 0 && expected_duty != 100) {
458
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
459
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
460
+ ==, expected_freq);
461
+ }
462
+
463
+ /* Test inverted mode */
464
+ expected_duty = pwm_compute_duty(cnr, cmr, true);
465
+ pwm_write_pcr(qts, td, pcr | CH_INV);
466
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
467
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
468
+ ==, expected_duty);
469
+ if (expected_duty != 0 && expected_duty != 100) {
470
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
471
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
472
+ ==, expected_freq);
473
+ }
474
+
475
+ }
476
+ }
477
+ }
478
+ }
479
+
480
+ qtest_quit(qts);
481
+}
482
+
483
+static void pwm_add_test(const char *name, const TestData* td,
484
+ GTestDataFunc fn)
485
+{
486
+ g_autofree char *full_name = g_strdup_printf(
487
+ "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
488
+ pwm_index(td->pwm), name);
489
+ qtest_add_data_func(full_name, td, fn);
490
+}
491
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
492
+
493
+int main(int argc, char **argv)
494
+{
495
+ TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
496
+
497
+ g_test_init(&argc, &argv, NULL);
498
+
499
+ for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
500
+ for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
501
+ TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
502
+
503
+ td->module = &pwm_module_list[i];
504
+ td->pwm = &pwm_list[j];
505
+
506
+ add_test(init, td);
507
+ add_test(oneshot, td);
508
+ add_test(toggle, td);
509
+ }
510
+ }
511
+
512
+ return g_test_run();
513
+}
514
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
87
index XXXXXXX..XXXXXXX 100644
515
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/intc/armv7m_nvic.c
516
--- a/tests/qtest/meson.build
89
+++ b/hw/intc/armv7m_nvic.c
517
+++ b/tests/qtest/meson.build
90
@@ -XXX,XX +XXX,XX @@
518
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
91
#include "hw/sysbus.h"
519
qtests_npcm7xx = \
92
#include "qemu/timer.h"
520
['npcm7xx_adc-test',
93
#include "hw/arm/arm.h"
521
'npcm7xx_gpio-test',
94
+#include "hw/arm/armv7m_nvic.h"
522
+ 'npcm7xx_pwm-test',
95
#include "target/arm/cpu.h"
523
'npcm7xx_rng-test',
96
#include "exec/address-spaces.h"
524
'npcm7xx_timer-test',
97
#include "qemu/log.h"
525
'npcm7xx_watchdog_timer-test']
98
@@ -XXX,XX +XXX,XX @@
99
* "exception" more or less interchangeably.
100
*/
101
#define NVIC_FIRST_IRQ 16
102
-#define NVIC_MAX_VECTORS 512
103
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
104
105
/* Effective running priority of the CPU when no exception is active
106
@@ -XXX,XX +XXX,XX @@
107
*/
108
#define NVIC_NOEXC_PRIO 0x100
109
110
-typedef struct VecInfo {
111
- /* Exception priorities can range from -3 to 255; only the unmodifiable
112
- * priority values for RESET, NMI and HardFault can be negative.
113
- */
114
- int16_t prio;
115
- uint8_t enabled;
116
- uint8_t pending;
117
- uint8_t active;
118
- uint8_t level; /* exceptions <=15 never set level */
119
-} VecInfo;
120
-
121
-typedef struct NVICState {
122
- /*< private >*/
123
- SysBusDevice parent_obj;
124
- /*< public >*/
125
-
126
- ARMCPU *cpu;
127
-
128
- VecInfo vectors[NVIC_MAX_VECTORS];
129
- uint32_t prigroup;
130
-
131
- /* vectpending and exception_prio are both cached state that can
132
- * be recalculated from the vectors[] array and the prigroup field.
133
- */
134
- unsigned int vectpending; /* highest prio pending enabled exception */
135
- int exception_prio; /* group prio of the highest prio active exception */
136
-
137
- struct {
138
- uint32_t control;
139
- uint32_t reload;
140
- int64_t tick;
141
- QEMUTimer *timer;
142
- } systick;
143
-
144
- MemoryRegion sysregmem;
145
- MemoryRegion container;
146
-
147
- uint32_t num_irq;
148
- qemu_irq excpout;
149
- qemu_irq sysresetreq;
150
-} NVICState;
151
-
152
-#define TYPE_NVIC "armv7m_nvic"
153
-
154
-#define NVIC(obj) \
155
- OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
156
-
157
static const uint8_t nvic_id[] = {
158
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
159
};
160
--
526
--
161
2.7.4
527
2.20.1
162
528
163
529
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform.
3
A device shouldn't access its parent object which is QOM internal.
4
Instead it should use type cast for this purporse. This patch fixes this
5
issue for all NPCM7XX Devices.
4
6
5
For supporting the SD controller selection (alternate function of GPIOs
7
Signed-off-by: Hao Wu <wuhaotsh@google.com>
6
48-53), the bcm2835_gpio now exposes an sdbus.
7
It also has a link to both the sdbus of sdhci and sdhost controllers,
8
and the card is reparented from one bus to another when the alternate
9
function of GPIOs 48-53 is modified.
10
11
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
14
Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org
15
Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/arm/bcm2835_peripherals.h | 4 ++++
12
hw/arm/npcm7xx_boards.c | 2 +-
20
hw/arm/bcm2835_peripherals.c | 43 ++++++++++++++++++++++++++++++++++--
13
hw/mem/npcm7xx_mc.c | 2 +-
21
2 files changed, 45 insertions(+), 2 deletions(-)
14
hw/misc/npcm7xx_clk.c | 2 +-
15
hw/misc/npcm7xx_gcr.c | 2 +-
16
hw/misc/npcm7xx_rng.c | 2 +-
17
hw/nvram/npcm7xx_otp.c | 2 +-
18
hw/ssi/npcm7xx_fiu.c | 2 +-
19
7 files changed, 7 insertions(+), 7 deletions(-)
22
20
23
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
21
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
24
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/bcm2835_peripherals.h
23
--- a/hw/arm/npcm7xx_boards.c
26
+++ b/include/hw/arm/bcm2835_peripherals.h
24
+++ b/hw/arm/npcm7xx_boards.c
27
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
28
#include "hw/misc/bcm2835_rng.h"
26
uint32_t hw_straps)
29
#include "hw/misc/bcm2835_mbox.h"
27
{
30
#include "hw/sd/sdhci.h"
28
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
31
+#include "hw/sd/bcm2835_sdhost.h"
29
- MachineClass *mc = &nmc->parent;
32
+#include "hw/gpio/bcm2835_gpio.h"
30
+ MachineClass *mc = MACHINE_CLASS(nmc);
33
31
Object *obj;
34
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
32
35
#define BCM2835_PERIPHERALS(obj) \
33
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
36
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
34
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
37
BCM2835RngState rng;
38
BCM2835MboxState mboxes;
39
SDHCIState sdhci;
40
+ BCM2835SDHostState sdhost;
41
+ BCM2835GpioState gpio;
42
} BCM2835PeripheralState;
43
44
#endif /* BCM2835_PERIPHERALS_H */
45
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
46
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/bcm2835_peripherals.c
36
--- a/hw/mem/npcm7xx_mc.c
48
+++ b/hw/arm/bcm2835_peripherals.c
37
+++ b/hw/mem/npcm7xx_mc.c
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
38
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
50
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
39
51
qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
40
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
52
41
NPCM7XX_MC_REGS_SIZE);
53
+ /* SDHOST */
42
- sysbus_init_mmio(&s->parent, &s->mmio);
54
+ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
43
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
55
+ object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
56
+ qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
57
+
58
/* DMA Channels */
59
object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
60
object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
61
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
62
63
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
64
OBJECT(&s->gpu_bus_mr), &error_abort);
65
+
66
+ /* GPIO */
67
+ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
68
+ object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
69
+ qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
70
+
71
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
72
+ OBJECT(&s->sdhci.sdbus), &error_abort);
73
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
74
+ OBJECT(&s->sdhost.sdbus), &error_abort);
75
}
44
}
76
45
77
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
46
static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
78
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
47
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
79
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
48
index XXXXXXX..XXXXXXX 100644
80
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
49
--- a/hw/misc/npcm7xx_clk.c
81
INTERRUPT_ARASANSDIO));
50
+++ b/hw/misc/npcm7xx_clk.c
82
- object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "sd-bus",
51
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
83
- &err);
52
84
+
53
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
85
+ /* SDHOST */
54
TYPE_NPCM7XX_CLK, 4 * KiB);
86
+ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
55
- sysbus_init_mmio(&s->parent, &s->iomem);
87
if (err) {
56
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
88
error_propagate(errp, err);
89
return;
90
}
91
92
+ memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
93
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
95
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
96
+ INTERRUPT_SDIO));
97
+
98
/* DMA Channels */
99
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
100
if (err) {
101
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
102
BCM2835_IC_GPU_IRQ,
103
INTERRUPT_DMA0 + n));
104
}
105
+
106
+ /* GPIO */
107
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
108
+ if (err) {
109
+ error_propagate(errp, err);
110
+ return;
111
+ }
112
+
113
+ memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
114
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
115
+
116
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
117
+ &err);
118
+ if (err) {
119
+ error_propagate(errp, err);
120
+ return;
121
+ }
122
}
57
}
123
58
124
static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
59
static int npcm7xx_clk_post_load(void *opaque, int version_id)
60
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/misc/npcm7xx_gcr.c
63
+++ b/hw/misc/npcm7xx_gcr.c
64
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
65
66
memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
67
TYPE_NPCM7XX_GCR, 4 * KiB);
68
- sysbus_init_mmio(&s->parent, &s->iomem);
69
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
70
}
71
72
static const VMStateDescription vmstate_npcm7xx_gcr = {
73
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/misc/npcm7xx_rng.c
76
+++ b/hw/misc/npcm7xx_rng.c
77
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
78
79
memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
80
NPCM7XX_RNG_REGS_SIZE);
81
- sysbus_init_mmio(&s->parent, &s->iomem);
82
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
83
}
84
85
static const VMStateDescription vmstate_npcm7xx_rng = {
86
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/nvram/npcm7xx_otp.c
89
+++ b/hw/nvram/npcm7xx_otp.c
90
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
91
{
92
NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
93
NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
94
- SysBusDevice *sbd = &s->parent;
95
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
96
97
memset(s->array, 0, sizeof(s->array));
98
99
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/ssi/npcm7xx_fiu.c
102
+++ b/hw/ssi/npcm7xx_fiu.c
103
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
104
static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
105
{
106
NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
107
- SysBusDevice *sbd = &s->parent;
108
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
109
int i;
110
111
if (s->cs_count <= 0) {
125
--
112
--
126
2.7.4
113
2.20.1
127
114
128
115
diff view generated by jsdifflib
1
Make the ARMv7M object take a memory region link which it uses
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
to wire up the bitband rather than having them always put
3
themselves in the system address space.
4
2
3
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
4
[-Wdeprecated-declarations]
5
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
6
^
7
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
8
'openFile:' has been explicitly marked deprecated here
9
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
10
^
11
12
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
8
---
16
---
9
include/hw/arm/armv7m.h | 10 ++++++++++
17
ui/cocoa.m | 5 ++++-
10
hw/arm/armv7m.c | 23 ++++++++++++++++++++++-
18
1 file changed, 4 insertions(+), 1 deletion(-)
11
2 files changed, 32 insertions(+), 1 deletion(-)
12
19
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/armv7m.h
22
--- a/ui/cocoa.m
16
+++ b/include/hw/arm/armv7m.h
23
+++ b/ui/cocoa.m
17
@@ -XXX,XX +XXX,XX @@ typedef struct {
24
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
18
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
25
/* Where to look for local files */
19
* + Property "cpu-model": CPU model to instantiate
26
NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
20
* + Property "num-irq": number of external IRQ lines
27
NSString *full_file_path;
21
+ * + Property "memory": MemoryRegion defining the physical address space
28
+ NSURL *full_file_url;
22
+ * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
29
23
+ * devices will be automatically layered on top of this view.)
30
/* iterate thru the possible paths until the file is found */
24
*/
31
int index;
25
typedef struct ARMv7MState {
32
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
26
/*< private >*/
33
full_file_path = [full_file_path stringByDeletingLastPathComponent];
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
34
full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
28
BitBandState bitband[ARMV7M_NUM_BITBANDS];
35
path_array[index], filename];
29
ARMCPU *cpu;
36
- if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
30
37
+ full_file_url = [NSURL fileURLWithPath: full_file_path
31
+ /* MemoryRegion we pass to the CPU, with our devices layered on
38
+ isDirectory: false];
32
+ * top of the ones the board provides in board_memory.
39
+ if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
33
+ */
34
+ MemoryRegion container;
35
+
36
/* Properties */
37
char *cpu_model;
38
+ /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
39
+ MemoryRegion *board_memory;
40
} ARMv7MState;
41
42
#endif
43
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/armv7m.c
46
+++ b/hw/arm/armv7m.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "elf.h"
49
#include "sysemu/qtest.h"
50
#include "qemu/error-report.h"
51
+#include "exec/address-spaces.h"
52
53
/* Bitbanded IO. Each word corresponds to a single bit. */
54
55
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
56
57
/* Can't init the cpu here, we don't yet know which model to use */
58
59
+ object_property_add_link(obj, "memory",
60
+ TYPE_MEMORY_REGION,
61
+ (Object **)&s->board_memory,
62
+ qdev_prop_allow_set_link_before_realize,
63
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
64
+ &error_abort);
65
+ memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
66
+
67
object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
68
qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
69
object_property_add_alias(obj, "num-irq",
70
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
71
const char *typename;
72
CPUClass *cc;
73
74
+ if (!s->board_memory) {
75
+ error_setg(errp, "memory property was not set");
76
+ return;
77
+ }
78
+
79
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
80
+
81
cpustr = g_strsplit(s->cpu_model, ",", 2);
82
83
oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
84
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
85
return;
86
}
87
88
+ object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
89
+ &error_abort);
90
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
91
if (err != NULL) {
92
error_propagate(errp, err);
93
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
94
return;
40
return;
95
}
41
}
96
97
- sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
98
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
99
+ sysbus_mmio_get_region(sbd, 0));
100
}
42
}
101
}
102
103
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
104
armv7m = qdev_create(NULL, "armv7m");
105
qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
106
qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
107
+ object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
108
+ "memory", &error_abort);
109
/* This will exit with an error if the user passed us a bad cpu_model */
110
qdev_init_nofail(armv7m);
111
112
--
43
--
113
2.7.4
44
2.20.1
114
45
115
46
diff view generated by jsdifflib