1
Second lot of ARM changes to sneak in before freeze:
1
First pullreq for 6.0: mostly my v8.1M work, plus some other
2
* fixed version of the raspi2 sd controller patches
2
bits and pieces. (I still have a lot of stuff in my to-review
3
* GICv3 save/restore
3
folder, which I may or may not get to before the Christmas break...)
4
* v7M QOMify
5
6
I've also included the Linux header update patches stolen
7
from Paolo's pullreq since it hasn't quite hit master yet.
8
4
9
thanks
5
thanks
10
-- PMM
6
-- PMM
11
7
12
The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:
8
The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
13
9
14
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging (2017-02-28 14:50:17 +0000)
10
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
15
11
16
are available in the git repository at:
12
are available in the Git repository at:
17
13
18
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228-1
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
19
15
20
for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:
16
for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
21
17
22
bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +0000)
18
hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
23
19
24
----------------------------------------------------------------
20
----------------------------------------------------------------
25
target-arm queue:
21
target-arm queue:
26
* raspi2: add gpio controller and sdhost controller, with
22
* hw/arm/smmuv3: Fix up L1STD_SPAN decoding
27
the wiring so the guest can switch which controller the
23
* xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
28
SD card is attached to
24
* sbsa-ref: allow to use Cortex-A53/57/72 cpus
29
(this is sufficient to get raspbian kernels to boot)
25
* Various minor code cleanups
30
* GICv3: support state save/restore from KVM
26
* hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
31
* update Linux headers to 4.11
27
* Implement more pieces of ARMv8.1M support
32
* refactor and QOMify the ARMv7M container object
33
28
34
----------------------------------------------------------------
29
----------------------------------------------------------------
35
Clement Deschamps (3):
30
Alex Chen (4):
36
hw/sd: add card-reparenting function
31
i.MX25: Fix bad printf format specifiers
37
bcm2835_gpio: add bcm2835 gpio controller
32
i.MX31: Fix bad printf format specifiers
38
bcm2835: add sdhost and gpio controllers
33
i.MX6: Fix bad printf format specifiers
34
i.MX6ul: Fix bad printf format specifiers
39
35
40
Paolo Bonzini (2):
36
Havard Skinnemoen (1):
41
update-linux-headers: update for 4.11
37
tests/qtest/npcm7xx_rng-test: dump random data on failure
42
update Linux headers to 4.11
43
38
44
Peter Maydell (12):
39
Kunkun Jiang (1):
45
armv7m: Abstract out the "load kernel" code
40
hw/arm/smmuv3: Fix up L1STD_SPAN decoding
46
armv7m: Move NVICState struct definition into header
47
armv7m: QOMify the armv7m container
48
armv7m: Use QOMified armv7m object in armv7m_init()
49
armv7m: Make ARMv7M object take memory region link
50
armv7m: Make NVIC expose a memory region rather than mapping itself
51
armv7m: Make bitband device take the address space to access
52
armv7m: Don't put core v7M devices under CONFIG_STELLARIS
53
armv7m: Split systick out from NVIC
54
stm32f205: Create armv7m object without using armv7m_init()
55
stm32f205: Rename 'nvic' local to 'armv7m'
56
qdev: Have qdev_set_parent_bus() handle devices already on a bus
57
41
58
Vijaya Kumar K (4):
42
Marcin Juszkiewicz (1):
59
hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
43
sbsa-ref: allow to use Cortex-A53/57/72 cpus
60
hw/intc/arm_gicv3_kvm: Implement get/put functions
61
target-arm: Add GICv3CPUState in CPUARMState struct
62
hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
63
44
64
hw/gpio/Makefile.objs | 1 +
45
Peter Maydell (25):
65
hw/intc/Makefile.objs | 2 +-
46
hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
66
hw/timer/Makefile.objs | 1 +
47
target/arm: Implement v8.1M PXN extension
67
hw/intc/gicv3_internal.h | 3 +
48
target/arm: Don't clobber ID_PFR1.Security on M-profile cores
68
include/hw/arm/arm.h | 12 +
49
target/arm: Implement VSCCLRM insn
69
include/hw/arm/armv7m.h | 63 +++
50
target/arm: Implement CLRM instruction
70
include/hw/arm/armv7m_nvic.h | 62 ++
51
target/arm: Enforce M-profile VMRS/VMSR register restrictions
71
include/hw/arm/bcm2835_peripherals.h | 4 +
52
target/arm: Refactor M-profile VMSR/VMRS handling
72
include/hw/arm/stm32f205_soc.h | 4 +-
53
target/arm: Move general-use constant expanders up in translate.c
73
include/hw/gpio/bcm2835_gpio.h | 39 ++
54
target/arm: Implement VLDR/VSTR system register
74
include/hw/intc/arm_gicv3_common.h | 1 +
55
target/arm: Implement M-profile FPSCR_nzcvqc
75
include/hw/sd/sd.h | 11 +
56
target/arm: Use new FPCR_NZCV_MASK constant
76
include/hw/timer/armv7m_systick.h | 34 ++
57
target/arm: Factor out preserve-fp-state from full_vfp_access_check()
77
include/standard-headers/asm-x86/hyperv.h | 8 +
58
target/arm: Implement FPCXT_S fp system register
78
include/standard-headers/linux/input-event-codes.h | 2 +-
59
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
79
include/standard-headers/linux/pci_regs.h | 25 +
60
target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
80
include/standard-headers/linux/virtio_ids.h | 1 +
61
target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
81
linux-headers/asm-arm/kvm.h | 15 +
62
target/arm: Implement v8.1M REVIDR register
82
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++
63
target/arm: Implement new v8.1M NOCP check for exception return
83
linux-headers/asm-arm/unistd-eabi.h | 5 +
64
target/arm: Implement new v8.1M VLLDM and VLSTM encodings
84
linux-headers/asm-arm/unistd-oabi.h | 17 +
65
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
85
linux-headers/asm-arm/unistd.h | 419 +-------------
66
target/arm: Implement CCR_S.TRD behaviour for SG insns
86
linux-headers/asm-arm64/kvm.h | 13 +
67
hw/intc/armv7m_nvic: Fix "return from inactive handler" check
87
linux-headers/asm-powerpc/kvm.h | 27 +
68
target/arm: Implement M-profile "minimal RAS implementation"
88
linux-headers/asm-powerpc/unistd.h | 1 +
69
hw/intc/armv7m_nvic: Implement read/write for RAS register block
89
linux-headers/asm-x86/kvm_para.h | 13 +-
70
hw/arm/armv7m: Correct typo in QOM object name
90
linux-headers/linux/kvm.h | 24 +-
91
linux-headers/linux/kvm_para.h | 2 +
92
linux-headers/linux/userfaultfd.h | 67 ++-
93
linux-headers/linux/vfio.h | 10 +
94
target/arm/cpu.h | 2 +
95
hw/arm/armv7m.c | 379 ++++++++-----
96
hw/arm/bcm2835_peripherals.c | 43 +-
97
hw/arm/netduino2.c | 7 +-
98
hw/arm/stm32f205_soc.c | 28 +-
99
hw/core/qdev.c | 14 +
100
hw/gpio/bcm2835_gpio.c | 353 ++++++++++++
101
hw/intc/arm_gicv3_common.c | 38 ++
102
hw/intc/arm_gicv3_cpuif.c | 8 +
103
hw/intc/arm_gicv3_kvm.c | 629 ++++++++++++++++++++-
104
hw/intc/armv7m_nvic.c | 214 ++-----
105
hw/sd/core.c | 27 +
106
hw/timer/armv7m_systick.c | 240 ++++++++
107
default-configs/arm-softmmu.mak | 2 +
108
hw/timer/trace-events | 6 +
109
scripts/update-linux-headers.sh | 13 +-
110
46 files changed, 2479 insertions(+), 767 deletions(-)
111
create mode 100644 include/hw/arm/armv7m.h
112
create mode 100644 include/hw/arm/armv7m_nvic.h
113
create mode 100644 include/hw/gpio/bcm2835_gpio.h
114
create mode 100644 include/hw/timer/armv7m_systick.h
115
create mode 100644 linux-headers/asm-arm/unistd-common.h
116
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
117
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
118
create mode 100644 hw/gpio/bcm2835_gpio.c
119
create mode 100644 hw/timer/armv7m_systick.c
120
71
72
Vikram Garhwal (4):
73
hw/net/can: Introduce Xilinx ZynqMP CAN controller
74
xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
75
tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
76
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
77
78
meson.build | 1 +
79
hw/arm/smmuv3-internal.h | 2 +-
80
hw/net/can/trace.h | 1 +
81
include/hw/arm/xlnx-zynqmp.h | 8 +
82
include/hw/intc/armv7m_nvic.h | 2 +
83
include/hw/net/xlnx-zynqmp-can.h | 78 +++
84
target/arm/cpu.h | 46 ++
85
target/arm/m-nocp.decode | 10 +-
86
target/arm/t32.decode | 10 +-
87
target/arm/vfp.decode | 14 +
88
hw/arm/armv7m.c | 4 +-
89
hw/arm/sbsa-ref.c | 23 +-
90
hw/arm/xlnx-zcu102.c | 20 +
91
hw/arm/xlnx-zynqmp.c | 34 ++
92
hw/intc/armv7m_nvic.c | 246 ++++++--
93
hw/misc/imx25_ccm.c | 12 +-
94
hw/misc/imx31_ccm.c | 14 +-
95
hw/misc/imx6_ccm.c | 20 +-
96
hw/misc/imx6_src.c | 2 +-
97
hw/misc/imx6ul_ccm.c | 4 +-
98
hw/misc/imx_ccm.c | 4 +-
99
hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++++++++++
100
target/arm/cpu.c | 5 +-
101
target/arm/helper.c | 7 +-
102
target/arm/m_helper.c | 130 ++++-
103
target/arm/translate.c | 105 +++-
104
tests/qtest/npcm7xx_rng-test.c | 12 +
105
tests/qtest/xlnx-can-test.c | 360 ++++++++++++
106
MAINTAINERS | 8 +
107
hw/Kconfig | 1 +
108
hw/net/can/meson.build | 1 +
109
hw/net/can/trace-events | 9 +
110
target/arm/translate-vfp.c.inc | 511 ++++++++++++++++-
111
tests/qtest/meson.build | 1 +
112
34 files changed, 2713 insertions(+), 153 deletions(-)
113
create mode 100644 hw/net/can/trace.h
114
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
115
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
116
create mode 100644 tests/qtest/xlnx-can-test.c
117
create mode 100644 hw/net/can/trace-events
118
diff view generated by jsdifflib
New patch
1
From: Kunkun Jiang <jiangkunkun@huawei.com>
1
2
3
Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table
4
Descriptor is 5 bits([4:0]).
5
6
Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback)
7
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
8
Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Acked-by: Eric Auger <eric.auger@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/smmuv3-internal.h | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/smmuv3-internal.h
19
+++ b/hw/arm/smmuv3-internal.h
20
@@ -XXX,XX +XXX,XX @@ static inline uint64_t l1std_l2ptr(STEDesc *desc)
21
return hi << 32 | lo;
22
}
23
24
-#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
25
+#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
26
27
#endif
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
2
2
3
This adds the BCM2835 GPIO controller.
3
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
4
implementation. Bus connection and socketCAN connection for each CAN module
5
can be set through command lines.
4
6
5
It currently implements:
7
Example for using single CAN:
6
- The 54 GPIOs as outputs (qemu_irq)
8
-object can-bus,id=canbus0 \
7
- The SD controller selection via alternate function of GPIOs 48-53
9
-machine xlnx-zcu102.canbus0=canbus0 \
10
-object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0
8
11
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
12
Example for connecting both CAN to same virtual CAN on host machine:
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
-object can-bus,id=canbus0 -object can-bus,id=canbus1 \
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
-machine xlnx-zcu102.canbus0=canbus0 \
12
Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org
15
-machine xlnx-zcu102.canbus1=canbus1 \
13
Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr
16
-object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \
17
-object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1
18
19
To create virtual CAN on the host machine, please check the QEMU CAN docs:
20
https://github.com/qemu/qemu/blob/master/docs/can.txt
21
22
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
23
Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
26
---
17
hw/gpio/Makefile.objs | 1 +
27
meson.build | 1 +
18
include/hw/gpio/bcm2835_gpio.h | 39 +++++
28
hw/net/can/trace.h | 1 +
19
hw/gpio/bcm2835_gpio.c | 353 +++++++++++++++++++++++++++++++++++++++++
29
include/hw/net/xlnx-zynqmp-can.h | 78 ++
20
3 files changed, 393 insertions(+)
30
hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++
21
create mode 100644 include/hw/gpio/bcm2835_gpio.h
31
hw/Kconfig | 1 +
22
create mode 100644 hw/gpio/bcm2835_gpio.c
32
hw/net/can/meson.build | 1 +
33
hw/net/can/trace-events | 9 +
34
7 files changed, 1252 insertions(+)
35
create mode 100644 hw/net/can/trace.h
36
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
37
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
38
create mode 100644 hw/net/can/trace-events
23
39
24
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
40
diff --git a/meson.build b/meson.build
25
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/gpio/Makefile.objs
42
--- a/meson.build
27
+++ b/hw/gpio/Makefile.objs
43
+++ b/meson.build
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
44
@@ -XXX,XX +XXX,XX @@ if have_system
29
45
'hw/misc',
30
obj-$(CONFIG_OMAP) += omap_gpio.o
46
'hw/misc/macio',
31
obj-$(CONFIG_IMX) += imx_gpio.o
47
'hw/net',
32
+obj-$(CONFIG_RASPI) += bcm2835_gpio.o
48
+ 'hw/net/can',
33
diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpio.h
49
'hw/nvram',
50
'hw/pci',
51
'hw/pci-host',
52
diff --git a/hw/net/can/trace.h b/hw/net/can/trace.h
34
new file mode 100644
53
new file mode 100644
35
index XXXXXXX..XXXXXXX
54
index XXXXXXX..XXXXXXX
36
--- /dev/null
55
--- /dev/null
37
+++ b/include/hw/gpio/bcm2835_gpio.h
56
+++ b/hw/net/can/trace.h
38
@@ -XXX,XX +XXX,XX @@
57
@@ -0,0 +1 @@
39
+/*
58
+#include "trace/trace-hw_net_can.h"
40
+ * Raspberry Pi (BCM2835) GPIO Controller
59
diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h
41
+ *
42
+ * Copyright (c) 2017 Antfield SAS
43
+ *
44
+ * Authors:
45
+ * Clement Deschamps <clement.deschamps@antfield.fr>
46
+ * Luc Michel <luc.michel@antfield.fr>
47
+ *
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
49
+ * See the COPYING file in the top-level directory.
50
+ */
51
+
52
+#ifndef BCM2835_GPIO_H
53
+#define BCM2835_GPIO_H
54
+
55
+#include "hw/sd/sd.h"
56
+
57
+typedef struct BCM2835GpioState {
58
+ SysBusDevice parent_obj;
59
+
60
+ MemoryRegion iomem;
61
+
62
+ /* SDBus selector */
63
+ SDBus sdbus;
64
+ SDBus *sdbus_sdhci;
65
+ SDBus *sdbus_sdhost;
66
+
67
+ uint8_t fsel[54];
68
+ uint32_t lev0, lev1;
69
+ uint8_t sd_fsel;
70
+ qemu_irq out[54];
71
+} BCM2835GpioState;
72
+
73
+#define TYPE_BCM2835_GPIO "bcm2835_gpio"
74
+#define BCM2835_GPIO(obj) \
75
+ OBJECT_CHECK(BCM2835GpioState, (obj), TYPE_BCM2835_GPIO)
76
+
77
+#endif
78
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
79
new file mode 100644
60
new file mode 100644
80
index XXXXXXX..XXXXXXX
61
index XXXXXXX..XXXXXXX
81
--- /dev/null
62
--- /dev/null
82
+++ b/hw/gpio/bcm2835_gpio.c
63
+++ b/include/hw/net/xlnx-zynqmp-can.h
83
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
84
+/*
65
+/*
85
+ * Raspberry Pi (BCM2835) GPIO Controller
66
+ * QEMU model of the Xilinx ZynqMP CAN controller.
86
+ *
67
+ *
87
+ * Copyright (c) 2017 Antfield SAS
68
+ * Copyright (c) 2020 Xilinx Inc.
88
+ *
69
+ *
89
+ * Authors:
70
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
90
+ * Clement Deschamps <clement.deschamps@antfield.fr>
91
+ * Luc Michel <luc.michel@antfield.fr>
92
+ *
71
+ *
93
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
72
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
94
+ * See the COPYING file in the top-level directory.
73
+ * Pavel Pisa.
74
+ *
75
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
76
+ * of this software and associated documentation files (the "Software"), to deal
77
+ * in the Software without restriction, including without limitation the rights
78
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
79
+ * copies of the Software, and to permit persons to whom the Software is
80
+ * furnished to do so, subject to the following conditions:
81
+ *
82
+ * The above copyright notice and this permission notice shall be included in
83
+ * all copies or substantial portions of the Software.
84
+ *
85
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
86
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
87
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
88
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
89
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
90
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
91
+ * THE SOFTWARE.
95
+ */
92
+ */
96
+
93
+
94
+#ifndef XLNX_ZYNQMP_CAN_H
95
+#define XLNX_ZYNQMP_CAN_H
96
+
97
+#include "hw/register.h"
98
+#include "net/can_emu.h"
99
+#include "net/can_host.h"
100
+#include "qemu/fifo32.h"
101
+#include "hw/ptimer.h"
102
+#include "hw/qdev-clock.h"
103
+
104
+#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can"
105
+
106
+#define XLNX_ZYNQMP_CAN(obj) \
107
+ OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN)
108
+
109
+#define MAX_CAN_CTRLS 2
110
+#define XLNX_ZYNQMP_CAN_R_MAX (0x84 / 4)
111
+#define MAILBOX_CAPACITY 64
112
+#define CAN_TIMER_MAX 0XFFFFUL
113
+#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000)
114
+
115
+/* Each CAN_FRAME will have 4 * 32bit size. */
116
+#define CAN_FRAME_SIZE 4
117
+#define RXFIFO_SIZE (MAILBOX_CAPACITY * CAN_FRAME_SIZE)
118
+
119
+typedef struct XlnxZynqMPCANState {
120
+ SysBusDevice parent_obj;
121
+ MemoryRegion iomem;
122
+
123
+ qemu_irq irq;
124
+
125
+ CanBusClientState bus_client;
126
+ CanBusState *canbus;
127
+
128
+ struct {
129
+ uint32_t ext_clk_freq;
130
+ } cfg;
131
+
132
+ RegisterInfo reg_info[XLNX_ZYNQMP_CAN_R_MAX];
133
+ uint32_t regs[XLNX_ZYNQMP_CAN_R_MAX];
134
+
135
+ Fifo32 rx_fifo;
136
+ Fifo32 tx_fifo;
137
+ Fifo32 txhpb_fifo;
138
+
139
+ ptimer_state *can_timer;
140
+} XlnxZynqMPCANState;
141
+
142
+#endif
143
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
144
new file mode 100644
145
index XXXXXXX..XXXXXXX
146
--- /dev/null
147
+++ b/hw/net/can/xlnx-zynqmp-can.c
148
@@ -XXX,XX +XXX,XX @@
149
+/*
150
+ * QEMU model of the Xilinx ZynqMP CAN controller.
151
+ * This implementation is based on the following datasheet:
152
+ * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
153
+ *
154
+ * Copyright (c) 2020 Xilinx Inc.
155
+ *
156
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
157
+ *
158
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
159
+ * Pavel Pisa
160
+ *
161
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
162
+ * of this software and associated documentation files (the "Software"), to deal
163
+ * in the Software without restriction, including without limitation the rights
164
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
165
+ * copies of the Software, and to permit persons to whom the Software is
166
+ * furnished to do so, subject to the following conditions:
167
+ *
168
+ * The above copyright notice and this permission notice shall be included in
169
+ * all copies or substantial portions of the Software.
170
+ *
171
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
172
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
173
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
174
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
175
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
176
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
177
+ * THE SOFTWARE.
178
+ */
179
+
97
+#include "qemu/osdep.h"
180
+#include "qemu/osdep.h"
181
+#include "hw/sysbus.h"
182
+#include "hw/register.h"
183
+#include "hw/irq.h"
184
+#include "qapi/error.h"
185
+#include "qemu/bitops.h"
98
+#include "qemu/log.h"
186
+#include "qemu/log.h"
99
+#include "qemu/timer.h"
187
+#include "qemu/cutils.h"
100
+#include "qapi/error.h"
188
+#include "sysemu/sysemu.h"
101
+#include "hw/sysbus.h"
189
+#include "migration/vmstate.h"
102
+#include "hw/sd/sd.h"
190
+#include "hw/qdev-properties.h"
103
+#include "hw/gpio/bcm2835_gpio.h"
191
+#include "net/can_emu.h"
104
+
192
+#include "net/can_host.h"
105
+#define GPFSEL0 0x00
193
+#include "qemu/event_notifier.h"
106
+#define GPFSEL1 0x04
194
+#include "qom/object_interfaces.h"
107
+#define GPFSEL2 0x08
195
+#include "hw/net/xlnx-zynqmp-can.h"
108
+#define GPFSEL3 0x0C
196
+#include "trace.h"
109
+#define GPFSEL4 0x10
197
+
110
+#define GPFSEL5 0x14
198
+#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG
111
+#define GPSET0 0x1C
199
+#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0
112
+#define GPSET1 0x20
200
+#endif
113
+#define GPCLR0 0x28
201
+
114
+#define GPCLR1 0x2C
202
+#define MAX_DLC 8
115
+#define GPLEV0 0x34
203
+#undef ERROR
116
+#define GPLEV1 0x38
204
+
117
+#define GPEDS0 0x40
205
+REG32(SOFTWARE_RESET_REGISTER, 0x0)
118
+#define GPEDS1 0x44
206
+ FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
119
+#define GPREN0 0x4C
207
+ FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
120
+#define GPREN1 0x50
208
+REG32(MODE_SELECT_REGISTER, 0x4)
121
+#define GPFEN0 0x58
209
+ FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
122
+#define GPFEN1 0x5C
210
+ FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
123
+#define GPHEN0 0x64
211
+ FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
124
+#define GPHEN1 0x68
212
+REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
125
+#define GPLEN0 0x70
213
+ FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
126
+#define GPLEN1 0x74
214
+REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
127
+#define GPAREN0 0x7C
215
+ FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2)
128
+#define GPAREN1 0x80
216
+ FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3)
129
+#define GPAFEN0 0x88
217
+ FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4)
130
+#define GPAFEN1 0x8C
218
+REG32(ERROR_COUNTER_REGISTER, 0x10)
131
+#define GPPUD 0x94
219
+ FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
132
+#define GPPUDCLK0 0x98
220
+ FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
133
+#define GPPUDCLK1 0x9C
221
+REG32(ERROR_STATUS_REGISTER, 0x14)
134
+
222
+ FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
135
+static uint32_t gpfsel_get(BCM2835GpioState *s, uint8_t reg)
223
+ FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
136
+{
224
+ FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
225
+ FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
226
+ FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
227
+REG32(STATUS_REGISTER, 0x18)
228
+ FIELD(STATUS_REGISTER, SNOOP, 12, 1)
229
+ FIELD(STATUS_REGISTER, ACFBSY, 11, 1)
230
+ FIELD(STATUS_REGISTER, TXFLL, 10, 1)
231
+ FIELD(STATUS_REGISTER, TXBFLL, 9, 1)
232
+ FIELD(STATUS_REGISTER, ESTAT, 7, 2)
233
+ FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
234
+ FIELD(STATUS_REGISTER, BBSY, 5, 1)
235
+ FIELD(STATUS_REGISTER, BIDLE, 4, 1)
236
+ FIELD(STATUS_REGISTER, NORMAL, 3, 1)
237
+ FIELD(STATUS_REGISTER, SLEEP, 2, 1)
238
+ FIELD(STATUS_REGISTER, LBACK, 1, 1)
239
+ FIELD(STATUS_REGISTER, CONFIG, 0, 1)
240
+REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
241
+ FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1)
242
+ FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1)
243
+ FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
244
+ FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
245
+ FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
246
+ FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
247
+ FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1)
248
+ FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1)
249
+ FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1)
250
+ FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1)
251
+ FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
252
+ FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1)
253
+ FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1)
254
+ FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
255
+ FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
256
+REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
257
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1)
258
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1)
259
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
260
+ FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
261
+ FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
262
+ FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
263
+ FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
264
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1)
265
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1)
266
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1)
267
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
268
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1)
269
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1)
270
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
271
+ FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1)
272
+REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
273
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1)
274
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1)
275
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
276
+ FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
277
+ FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
278
+ FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
279
+ FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
280
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1)
281
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1)
282
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1)
283
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
284
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1)
285
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1)
286
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
287
+ FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1)
288
+REG32(TIMESTAMP_REGISTER, 0x28)
289
+ FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
290
+REG32(WIR, 0x2c)
291
+ FIELD(WIR, EW, 8, 8)
292
+ FIELD(WIR, FW, 0, 8)
293
+REG32(TXFIFO_ID, 0x30)
294
+ FIELD(TXFIFO_ID, IDH, 21, 11)
295
+ FIELD(TXFIFO_ID, SRRRTR, 20, 1)
296
+ FIELD(TXFIFO_ID, IDE, 19, 1)
297
+ FIELD(TXFIFO_ID, IDL, 1, 18)
298
+ FIELD(TXFIFO_ID, RTR, 0, 1)
299
+REG32(TXFIFO_DLC, 0x34)
300
+ FIELD(TXFIFO_DLC, DLC, 28, 4)
301
+REG32(TXFIFO_DATA1, 0x38)
302
+ FIELD(TXFIFO_DATA1, DB0, 24, 8)
303
+ FIELD(TXFIFO_DATA1, DB1, 16, 8)
304
+ FIELD(TXFIFO_DATA1, DB2, 8, 8)
305
+ FIELD(TXFIFO_DATA1, DB3, 0, 8)
306
+REG32(TXFIFO_DATA2, 0x3c)
307
+ FIELD(TXFIFO_DATA2, DB4, 24, 8)
308
+ FIELD(TXFIFO_DATA2, DB5, 16, 8)
309
+ FIELD(TXFIFO_DATA2, DB6, 8, 8)
310
+ FIELD(TXFIFO_DATA2, DB7, 0, 8)
311
+REG32(TXHPB_ID, 0x40)
312
+ FIELD(TXHPB_ID, IDH, 21, 11)
313
+ FIELD(TXHPB_ID, SRRRTR, 20, 1)
314
+ FIELD(TXHPB_ID, IDE, 19, 1)
315
+ FIELD(TXHPB_ID, IDL, 1, 18)
316
+ FIELD(TXHPB_ID, RTR, 0, 1)
317
+REG32(TXHPB_DLC, 0x44)
318
+ FIELD(TXHPB_DLC, DLC, 28, 4)
319
+REG32(TXHPB_DATA1, 0x48)
320
+ FIELD(TXHPB_DATA1, DB0, 24, 8)
321
+ FIELD(TXHPB_DATA1, DB1, 16, 8)
322
+ FIELD(TXHPB_DATA1, DB2, 8, 8)
323
+ FIELD(TXHPB_DATA1, DB3, 0, 8)
324
+REG32(TXHPB_DATA2, 0x4c)
325
+ FIELD(TXHPB_DATA2, DB4, 24, 8)
326
+ FIELD(TXHPB_DATA2, DB5, 16, 8)
327
+ FIELD(TXHPB_DATA2, DB6, 8, 8)
328
+ FIELD(TXHPB_DATA2, DB7, 0, 8)
329
+REG32(RXFIFO_ID, 0x50)
330
+ FIELD(RXFIFO_ID, IDH, 21, 11)
331
+ FIELD(RXFIFO_ID, SRRRTR, 20, 1)
332
+ FIELD(RXFIFO_ID, IDE, 19, 1)
333
+ FIELD(RXFIFO_ID, IDL, 1, 18)
334
+ FIELD(RXFIFO_ID, RTR, 0, 1)
335
+REG32(RXFIFO_DLC, 0x54)
336
+ FIELD(RXFIFO_DLC, DLC, 28, 4)
337
+ FIELD(RXFIFO_DLC, RXT, 0, 16)
338
+REG32(RXFIFO_DATA1, 0x58)
339
+ FIELD(RXFIFO_DATA1, DB0, 24, 8)
340
+ FIELD(RXFIFO_DATA1, DB1, 16, 8)
341
+ FIELD(RXFIFO_DATA1, DB2, 8, 8)
342
+ FIELD(RXFIFO_DATA1, DB3, 0, 8)
343
+REG32(RXFIFO_DATA2, 0x5c)
344
+ FIELD(RXFIFO_DATA2, DB4, 24, 8)
345
+ FIELD(RXFIFO_DATA2, DB5, 16, 8)
346
+ FIELD(RXFIFO_DATA2, DB6, 8, 8)
347
+ FIELD(RXFIFO_DATA2, DB7, 0, 8)
348
+REG32(AFR, 0x60)
349
+ FIELD(AFR, UAF4, 3, 1)
350
+ FIELD(AFR, UAF3, 2, 1)
351
+ FIELD(AFR, UAF2, 1, 1)
352
+ FIELD(AFR, UAF1, 0, 1)
353
+REG32(AFMR1, 0x64)
354
+ FIELD(AFMR1, AMIDH, 21, 11)
355
+ FIELD(AFMR1, AMSRR, 20, 1)
356
+ FIELD(AFMR1, AMIDE, 19, 1)
357
+ FIELD(AFMR1, AMIDL, 1, 18)
358
+ FIELD(AFMR1, AMRTR, 0, 1)
359
+REG32(AFIR1, 0x68)
360
+ FIELD(AFIR1, AIIDH, 21, 11)
361
+ FIELD(AFIR1, AISRR, 20, 1)
362
+ FIELD(AFIR1, AIIDE, 19, 1)
363
+ FIELD(AFIR1, AIIDL, 1, 18)
364
+ FIELD(AFIR1, AIRTR, 0, 1)
365
+REG32(AFMR2, 0x6c)
366
+ FIELD(AFMR2, AMIDH, 21, 11)
367
+ FIELD(AFMR2, AMSRR, 20, 1)
368
+ FIELD(AFMR2, AMIDE, 19, 1)
369
+ FIELD(AFMR2, AMIDL, 1, 18)
370
+ FIELD(AFMR2, AMRTR, 0, 1)
371
+REG32(AFIR2, 0x70)
372
+ FIELD(AFIR2, AIIDH, 21, 11)
373
+ FIELD(AFIR2, AISRR, 20, 1)
374
+ FIELD(AFIR2, AIIDE, 19, 1)
375
+ FIELD(AFIR2, AIIDL, 1, 18)
376
+ FIELD(AFIR2, AIRTR, 0, 1)
377
+REG32(AFMR3, 0x74)
378
+ FIELD(AFMR3, AMIDH, 21, 11)
379
+ FIELD(AFMR3, AMSRR, 20, 1)
380
+ FIELD(AFMR3, AMIDE, 19, 1)
381
+ FIELD(AFMR3, AMIDL, 1, 18)
382
+ FIELD(AFMR3, AMRTR, 0, 1)
383
+REG32(AFIR3, 0x78)
384
+ FIELD(AFIR3, AIIDH, 21, 11)
385
+ FIELD(AFIR3, AISRR, 20, 1)
386
+ FIELD(AFIR3, AIIDE, 19, 1)
387
+ FIELD(AFIR3, AIIDL, 1, 18)
388
+ FIELD(AFIR3, AIRTR, 0, 1)
389
+REG32(AFMR4, 0x7c)
390
+ FIELD(AFMR4, AMIDH, 21, 11)
391
+ FIELD(AFMR4, AMSRR, 20, 1)
392
+ FIELD(AFMR4, AMIDE, 19, 1)
393
+ FIELD(AFMR4, AMIDL, 1, 18)
394
+ FIELD(AFMR4, AMRTR, 0, 1)
395
+REG32(AFIR4, 0x80)
396
+ FIELD(AFIR4, AIIDH, 21, 11)
397
+ FIELD(AFIR4, AISRR, 20, 1)
398
+ FIELD(AFIR4, AIIDE, 19, 1)
399
+ FIELD(AFIR4, AIIDL, 1, 18)
400
+ FIELD(AFIR4, AIRTR, 0, 1)
401
+
402
+static void can_update_irq(XlnxZynqMPCANState *s)
403
+{
404
+ uint32_t irq;
405
+
406
+ /* Watermark register interrupts. */
407
+ if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) >
408
+ ARRAY_FIELD_EX32(s->regs, WIR, EW)) {
409
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1);
410
+ }
411
+
412
+ if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) >
413
+ ARRAY_FIELD_EX32(s->regs, WIR, FW)) {
414
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
415
+ }
416
+
417
+ /* RX Interrupts. */
418
+ if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) {
419
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1);
420
+ }
421
+
422
+ /* TX interrupts. */
423
+ if (fifo32_is_empty(&s->tx_fifo)) {
424
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1);
425
+ }
426
+
427
+ if (fifo32_is_full(&s->tx_fifo)) {
428
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1);
429
+ }
430
+
431
+ if (fifo32_is_full(&s->txhpb_fifo)) {
432
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1);
433
+ }
434
+
435
+ irq = s->regs[R_INTERRUPT_STATUS_REGISTER];
436
+ irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER];
437
+
438
+ trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER],
439
+ s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
440
+ qemu_set_irq(s->irq, irq);
441
+}
442
+
443
+static void can_ier_post_write(RegisterInfo *reg, uint64_t val)
444
+{
445
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
446
+
447
+ can_update_irq(s);
448
+}
449
+
450
+static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val)
451
+{
452
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
453
+
454
+ s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
455
+ can_update_irq(s);
456
+
457
+ return 0;
458
+}
459
+
460
+static void can_config_reset(XlnxZynqMPCANState *s)
461
+{
462
+ /* Reset all the configuration registers. */
463
+ register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]);
464
+ register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]);
465
+ register_reset(
466
+ &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]);
467
+ register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]);
468
+ register_reset(&s->reg_info[R_STATUS_REGISTER]);
469
+ register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]);
470
+ register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]);
471
+ register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]);
472
+ register_reset(&s->reg_info[R_WIR]);
473
+}
474
+
475
+static void can_config_mode(XlnxZynqMPCANState *s)
476
+{
477
+ register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
478
+ register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
479
+
480
+ /* Put XlnxZynqMPCAN in configuration mode. */
481
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
482
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
483
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
484
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
485
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0);
486
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0);
487
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
488
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
489
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
490
+
491
+ can_update_irq(s);
492
+}
493
+
494
+static void update_status_register_mode_bits(XlnxZynqMPCANState *s)
495
+{
496
+ bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
497
+ bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
498
+ /* Wake up interrupt bit. */
499
+ bool wakeup_irq_val = sleep_status && (sleep_mode == 0);
500
+ /* Sleep interrupt bit. */
501
+ bool sleep_irq_val = sleep_mode && (sleep_status == 0);
502
+
503
+ /* Clear previous core mode status bits. */
504
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
505
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
506
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
507
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
508
+
509
+ /* set current mode bit and generate irqs accordingly. */
510
+ if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
511
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
512
+ } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
513
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
514
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
515
+ sleep_irq_val);
516
+ } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
517
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
518
+ } else {
519
+ /*
520
+ * If all bits are zero then XlnxZynqMPCAN is set in normal mode.
521
+ */
522
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
523
+ /* Set wakeup interrupt bit. */
524
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
525
+ wakeup_irq_val);
526
+ }
527
+
528
+ can_update_irq(s);
529
+}
530
+
531
+static void can_exit_sleep_mode(XlnxZynqMPCANState *s)
532
+{
533
+ ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
534
+ update_status_register_mode_bits(s);
535
+}
536
+
537
+static void generate_frame(qemu_can_frame *frame, uint32_t *data)
538
+{
539
+ frame->can_id = data[0];
540
+ frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC);
541
+
542
+ frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3);
543
+ frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2);
544
+ frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1);
545
+ frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0);
546
+
547
+ frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7);
548
+ frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6);
549
+ frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5);
550
+ frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4);
551
+}
552
+
553
+static bool tx_ready_check(XlnxZynqMPCANState *s)
554
+{
555
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
556
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
557
+
558
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
559
+ " data while controller is in reset mode.\n",
560
+ path);
561
+ return false;
562
+ }
563
+
564
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
565
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
566
+
567
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
568
+ " data while controller is in configuration mode. Reset"
569
+ " the core so operations can start fresh.\n",
570
+ path);
571
+ return false;
572
+ }
573
+
574
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
575
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
576
+
577
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
578
+ " data while controller is in SNOOP MODE.\n",
579
+ path);
580
+ return false;
581
+ }
582
+
583
+ return true;
584
+}
585
+
586
+static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo)
587
+{
588
+ qemu_can_frame frame;
589
+ uint32_t data[CAN_FRAME_SIZE];
137
+ int i;
590
+ int i;
138
+ uint32_t value = 0;
591
+ bool can_tx = tx_ready_check(s);
139
+ for (i = 0; i < 10; i++) {
592
+
140
+ uint32_t index = 10 * reg + i;
593
+ if (!can_tx) {
141
+ if (index < sizeof(s->fsel)) {
594
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
142
+ value |= (s->fsel[index] & 0x7) << (3 * i);
595
+
596
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is not enabled for data"
597
+ " transfer.\n", path);
598
+ can_update_irq(s);
599
+ return;
600
+ }
601
+
602
+ while (!fifo32_is_empty(fifo)) {
603
+ for (i = 0; i < CAN_FRAME_SIZE; i++) {
604
+ data[i] = fifo32_pop(fifo);
143
+ }
605
+ }
144
+ }
606
+
145
+ return value;
607
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
146
+}
608
+ /*
147
+
609
+ * Controller is in loopback. In Loopback mode, the CAN core
148
+static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value)
610
+ * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus.
149
+{
611
+ * Any message transmitted is looped back to the RX line and
150
+ int i;
612
+ * acknowledged. The XlnxZynqMPCAN core receives any message
151
+ for (i = 0; i < 10; i++) {
613
+ * that it transmits.
152
+ uint32_t index = 10 * reg + i;
614
+ */
153
+ if (index < sizeof(s->fsel)) {
615
+ if (fifo32_is_full(&s->rx_fifo)) {
154
+ int fsel = (value >> (3 * i)) & 0x7;
616
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
155
+ s->fsel[index] = fsel;
617
+ } else {
618
+ for (i = 0; i < CAN_FRAME_SIZE; i++) {
619
+ fifo32_push(&s->rx_fifo, data[i]);
620
+ }
621
+
622
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
623
+ }
624
+ } else {
625
+ /* Normal mode Tx. */
626
+ generate_frame(&frame, data);
627
+
628
+ trace_xlnx_can_tx_data(frame.can_id, frame.can_dlc,
629
+ frame.data[0], frame.data[1],
630
+ frame.data[2], frame.data[3],
631
+ frame.data[4], frame.data[5],
632
+ frame.data[6], frame.data[7]);
633
+ can_bus_client_send(&s->bus_client, &frame, 1);
156
+ }
634
+ }
157
+ }
635
+ }
158
+
636
+
159
+ /* SD controller selection (48-53) */
637
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
160
+ if (s->sd_fsel != 0
638
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0);
161
+ && (s->fsel[48] == 0) /* SD_CLK_R */
639
+
162
+ && (s->fsel[49] == 0) /* SD_CMD_R */
640
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
163
+ && (s->fsel[50] == 0) /* SD_DATA0_R */
641
+ can_exit_sleep_mode(s);
164
+ && (s->fsel[51] == 0) /* SD_DATA1_R */
642
+ }
165
+ && (s->fsel[52] == 0) /* SD_DATA2_R */
643
+
166
+ && (s->fsel[53] == 0) /* SD_DATA3_R */
644
+ can_update_irq(s);
167
+ ) {
645
+}
168
+ /* SDHCI controller selected */
646
+
169
+ sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci);
647
+static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val)
170
+ s->sd_fsel = 0;
648
+{
171
+ } else if (s->sd_fsel != 4
649
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
172
+ && (s->fsel[48] == 4) /* SD_CLK_R */
650
+
173
+ && (s->fsel[49] == 4) /* SD_CMD_R */
651
+ ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
174
+ && (s->fsel[50] == 4) /* SD_DATA0_R */
652
+ FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
175
+ && (s->fsel[51] == 4) /* SD_DATA1_R */
653
+
176
+ && (s->fsel[52] == 4) /* SD_DATA2_R */
654
+ if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
177
+ && (s->fsel[53] == 4) /* SD_DATA3_R */
655
+ trace_xlnx_can_reset(val);
178
+ ) {
656
+
179
+ /* SDHost controller selected */
657
+ /* First, core will do software reset then will enter in config mode. */
180
+ sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost);
658
+ can_config_reset(s);
181
+ s->sd_fsel = 4;
659
+ }
182
+ }
660
+
183
+}
661
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
184
+
662
+ can_config_mode(s);
185
+static int gpfsel_is_out(BCM2835GpioState *s, int index)
663
+ } else {
186
+{
664
+ /*
187
+ if (index >= 0 && index < 54) {
665
+ * Leave config mode. Now XlnxZynqMPCAN core will enter normal,
188
+ return s->fsel[index] == 1;
666
+ * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP
189
+ }
667
+ * register states.
668
+ */
669
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
670
+
671
+ ptimer_transaction_begin(s->can_timer);
672
+ ptimer_set_count(s->can_timer, 0);
673
+ ptimer_transaction_commit(s->can_timer);
674
+
675
+ /* XlnxZynqMPCAN is out of config mode. It will send pending data. */
676
+ transfer_fifo(s, &s->txhpb_fifo);
677
+ transfer_fifo(s, &s->tx_fifo);
678
+ }
679
+
680
+ update_status_register_mode_bits(s);
681
+
682
+ return s->regs[R_SOFTWARE_RESET_REGISTER];
683
+}
684
+
685
+static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val)
686
+{
687
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
688
+ uint8_t multi_mode;
689
+
690
+ /*
691
+ * Multiple mode set check. This is done to make sure user doesn't set
692
+ * multiple modes.
693
+ */
694
+ multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
695
+ FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
696
+ FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
697
+
698
+ if (multi_mode > 1) {
699
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
700
+
701
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config"
702
+ " several modes simultaneously. One mode will be selected"
703
+ " according to their priority: LBACK > SLEEP > SNOOP.\n",
704
+ path);
705
+ }
706
+
707
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
708
+ /* We are in configuration mode, any mode can be selected. */
709
+ s->regs[R_MODE_SELECT_REGISTER] = val;
710
+ } else {
711
+ bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
712
+
713
+ ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
714
+
715
+ if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
716
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
717
+
718
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
719
+ " LBACK mode without setting CEN bit as 0.\n",
720
+ path);
721
+ } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
722
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
723
+
724
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
725
+ " SNOOP mode without setting CEN bit as 0.\n",
726
+ path);
727
+ }
728
+
729
+ update_status_register_mode_bits(s);
730
+ }
731
+
732
+ return s->regs[R_MODE_SELECT_REGISTER];
733
+}
734
+
735
+static uint64_t can_brpr_pre_write(RegisterInfo *reg, uint64_t val)
736
+{
737
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
738
+
739
+ /* Only allow writes when in config mode. */
740
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
741
+ return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER];
742
+ }
743
+
744
+ return val;
745
+}
746
+
747
+static uint64_t can_btr_pre_write(RegisterInfo *reg, uint64_t val)
748
+{
749
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
750
+
751
+ /* Only allow writes when in config mode. */
752
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
753
+ return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER];
754
+ }
755
+
756
+ return val;
757
+}
758
+
759
+static uint64_t can_tcr_pre_write(RegisterInfo *reg, uint64_t val)
760
+{
761
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
762
+
763
+ if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
764
+ ptimer_transaction_begin(s->can_timer);
765
+ ptimer_set_count(s->can_timer, 0);
766
+ ptimer_transaction_commit(s->can_timer);
767
+ }
768
+
190
+ return 0;
769
+ return 0;
191
+}
770
+}
192
+
771
+
193
+static void gpset(BCM2835GpioState *s,
772
+static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
194
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
773
+{
195
+{
774
+ bool filter_pass = false;
196
+ uint32_t changes = val & ~*lev;
775
+ uint16_t timestamp = 0;
197
+ uint32_t cur = 1;
776
+
198
+
777
+ /* If no filter is enabled. Message will be stored in FIFO. */
199
+ int i;
778
+ if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) |
200
+ for (i = 0; i < count; i++) {
779
+ (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) |
201
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
780
+ (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) |
202
+ qemu_set_irq(s->out[start + i], 1);
781
+ (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) {
782
+ filter_pass = true;
783
+ }
784
+
785
+ /*
786
+ * Messages that pass any of the acceptance filters will be stored in
787
+ * the RX FIFO.
788
+ */
789
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) {
790
+ uint32_t id_masked = s->regs[R_AFMR1] & frame->can_id;
791
+ uint32_t filter_id_masked = s->regs[R_AFMR1] & s->regs[R_AFIR1];
792
+
793
+ if (filter_id_masked == id_masked) {
794
+ filter_pass = true;
203
+ }
795
+ }
204
+ cur <<= 1;
796
+ }
205
+ }
797
+
206
+
798
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) {
207
+ *lev |= val;
799
+ uint32_t id_masked = s->regs[R_AFMR2] & frame->can_id;
208
+}
800
+ uint32_t filter_id_masked = s->regs[R_AFMR2] & s->regs[R_AFIR2];
209
+
801
+
210
+static void gpclr(BCM2835GpioState *s,
802
+ if (filter_id_masked == id_masked) {
211
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
803
+ filter_pass = true;
212
+{
213
+ uint32_t changes = val & *lev;
214
+ uint32_t cur = 1;
215
+
216
+ int i;
217
+ for (i = 0; i < count; i++) {
218
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
219
+ qemu_set_irq(s->out[start + i], 0);
220
+ }
804
+ }
221
+ cur <<= 1;
805
+ }
222
+ }
806
+
223
+
807
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) {
224
+ *lev &= ~val;
808
+ uint32_t id_masked = s->regs[R_AFMR3] & frame->can_id;
225
+}
809
+ uint32_t filter_id_masked = s->regs[R_AFMR3] & s->regs[R_AFIR3];
226
+
810
+
227
+static uint64_t bcm2835_gpio_read(void *opaque, hwaddr offset,
811
+ if (filter_id_masked == id_masked) {
228
+ unsigned size)
812
+ filter_pass = true;
229
+{
813
+ }
230
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
814
+ }
231
+
815
+
232
+ switch (offset) {
816
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
233
+ case GPFSEL0:
817
+ uint32_t id_masked = s->regs[R_AFMR4] & frame->can_id;
234
+ case GPFSEL1:
818
+ uint32_t filter_id_masked = s->regs[R_AFMR4] & s->regs[R_AFIR4];
235
+ case GPFSEL2:
819
+
236
+ case GPFSEL3:
820
+ if (filter_id_masked == id_masked) {
237
+ case GPFSEL4:
821
+ filter_pass = true;
238
+ case GPFSEL5:
822
+ }
239
+ return gpfsel_get(s, offset / 4);
823
+ }
240
+ case GPSET0:
824
+
241
+ case GPSET1:
825
+ if (!filter_pass) {
242
+ /* Write Only */
826
+ trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc);
827
+ return;
828
+ }
829
+
830
+ /* Store the message in fifo if it passed through any of the filters. */
831
+ if (filter_pass && frame->can_dlc <= MAX_DLC) {
832
+
833
+ if (fifo32_is_full(&s->rx_fifo)) {
834
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
835
+ } else {
836
+ timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer);
837
+
838
+ fifo32_push(&s->rx_fifo, frame->can_id);
839
+
840
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT,
841
+ R_RXFIFO_DLC_DLC_LENGTH,
842
+ frame->can_dlc) |
843
+ deposit32(0, R_RXFIFO_DLC_RXT_SHIFT,
844
+ R_RXFIFO_DLC_RXT_LENGTH,
845
+ timestamp));
846
+
847
+ /* First 32 bit of the data. */
848
+ fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
849
+ R_TXFIFO_DATA1_DB3_LENGTH,
850
+ frame->data[0]) |
851
+ deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
852
+ R_TXFIFO_DATA1_DB2_LENGTH,
853
+ frame->data[1]) |
854
+ deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
855
+ R_TXFIFO_DATA1_DB1_LENGTH,
856
+ frame->data[2]) |
857
+ deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
858
+ R_TXFIFO_DATA1_DB0_LENGTH,
859
+ frame->data[3]));
860
+ /* Last 32 bit of the data. */
861
+ fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
862
+ R_TXFIFO_DATA2_DB7_LENGTH,
863
+ frame->data[4]) |
864
+ deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
865
+ R_TXFIFO_DATA2_DB6_LENGTH,
866
+ frame->data[5]) |
867
+ deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
868
+ R_TXFIFO_DATA2_DB5_LENGTH,
869
+ frame->data[6]) |
870
+ deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
871
+ R_TXFIFO_DATA2_DB4_LENGTH,
872
+ frame->data[7]));
873
+
874
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
875
+ trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc,
876
+ frame->data[0], frame->data[1],
877
+ frame->data[2], frame->data[3],
878
+ frame->data[4], frame->data[5],
879
+ frame->data[6], frame->data[7]);
880
+ }
881
+
882
+ can_update_irq(s);
883
+ }
884
+}
885
+
886
+static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val)
887
+{
888
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
889
+
890
+ if (!fifo32_is_empty(&s->rx_fifo)) {
891
+ val = fifo32_pop(&s->rx_fifo);
892
+ } else {
893
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1);
894
+ }
895
+
896
+ can_update_irq(s);
897
+ return val;
898
+}
899
+
900
+static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val)
901
+{
902
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
903
+
904
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) &&
905
+ ARRAY_FIELD_EX32(s->regs, AFR, UAF2) &&
906
+ ARRAY_FIELD_EX32(s->regs, AFR, UAF3) &&
907
+ ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
908
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1);
909
+ } else {
910
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0);
911
+ }
912
+}
913
+
914
+static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val)
915
+{
916
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
917
+ uint32_t reg_idx = (reg->access->addr) / 4;
918
+ uint32_t filter_number = (reg_idx - R_AFMR1) / 2;
919
+
920
+ /* modify an acceptance filter, the corresponding UAF bit should be '0'. */
921
+ if (!(s->regs[R_AFR] & (1 << filter_number))) {
922
+ s->regs[reg_idx] = val;
923
+
924
+ trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_idx]);
925
+ } else {
926
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
927
+
928
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
929
+ " mask is not set as corresponding UAF bit is not 0.\n",
930
+ path, filter_number + 1);
931
+ }
932
+
933
+ return s->regs[reg_idx];
934
+}
935
+
936
+static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val)
937
+{
938
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
939
+ uint32_t reg_idx = (reg->access->addr) / 4;
940
+ uint32_t filter_number = (reg_idx - R_AFIR1) / 2;
941
+
942
+ if (!(s->regs[R_AFR] & (1 << filter_number))) {
943
+ s->regs[reg_idx] = val;
944
+
945
+ trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]);
946
+ } else {
947
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
948
+
949
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
950
+ " id is not set as corresponding UAF bit is not 0.\n",
951
+ path, filter_number + 1);
952
+ }
953
+
954
+ return s->regs[reg_idx];
955
+}
956
+
957
+static void can_tx_post_write(RegisterInfo *reg, uint64_t val)
958
+{
959
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
960
+
961
+ bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2;
962
+
963
+ bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) ||
964
+ (reg->access->addr == A_TXHPB_DATA2);
965
+
966
+ Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo;
967
+
968
+ if (!fifo32_is_full(f)) {
969
+ fifo32_push(f, val);
970
+ } else {
971
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
972
+
973
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path);
974
+ }
975
+
976
+ /* Initiate the message send if TX register is written. */
977
+ if (initiate_transfer &&
978
+ ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
979
+ transfer_fifo(s, f);
980
+ }
981
+
982
+ can_update_irq(s);
983
+}
984
+
985
+static const RegisterAccessInfo can_regs_info[] = {
986
+ { .name = "SOFTWARE_RESET_REGISTER",
987
+ .addr = A_SOFTWARE_RESET_REGISTER,
988
+ .rsvd = 0xfffffffc,
989
+ .pre_write = can_srr_pre_write,
990
+ },{ .name = "MODE_SELECT_REGISTER",
991
+ .addr = A_MODE_SELECT_REGISTER,
992
+ .rsvd = 0xfffffff8,
993
+ .pre_write = can_msr_pre_write,
994
+ },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
995
+ .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
996
+ .rsvd = 0xffffff00,
997
+ .pre_write = can_brpr_pre_write,
998
+ },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
999
+ .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
1000
+ .rsvd = 0xfffffe00,
1001
+ .pre_write = can_btr_pre_write,
1002
+ },{ .name = "ERROR_COUNTER_REGISTER",
1003
+ .addr = A_ERROR_COUNTER_REGISTER,
1004
+ .rsvd = 0xffff0000,
1005
+ .ro = 0xffffffff,
1006
+ },{ .name = "ERROR_STATUS_REGISTER",
1007
+ .addr = A_ERROR_STATUS_REGISTER,
1008
+ .rsvd = 0xffffffe0,
1009
+ .w1c = 0x1f,
1010
+ },{ .name = "STATUS_REGISTER", .addr = A_STATUS_REGISTER,
1011
+ .reset = 0x1,
1012
+ .rsvd = 0xffffe000,
1013
+ .ro = 0x1fff,
1014
+ },{ .name = "INTERRUPT_STATUS_REGISTER",
1015
+ .addr = A_INTERRUPT_STATUS_REGISTER,
1016
+ .reset = 0x6000,
1017
+ .rsvd = 0xffff8000,
1018
+ .ro = 0x7fff,
1019
+ },{ .name = "INTERRUPT_ENABLE_REGISTER",
1020
+ .addr = A_INTERRUPT_ENABLE_REGISTER,
1021
+ .rsvd = 0xffff8000,
1022
+ .post_write = can_ier_post_write,
1023
+ },{ .name = "INTERRUPT_CLEAR_REGISTER",
1024
+ .addr = A_INTERRUPT_CLEAR_REGISTER,
1025
+ .rsvd = 0xffff8000,
1026
+ .pre_write = can_icr_pre_write,
1027
+ },{ .name = "TIMESTAMP_REGISTER",
1028
+ .addr = A_TIMESTAMP_REGISTER,
1029
+ .rsvd = 0xfffffffe,
1030
+ .pre_write = can_tcr_pre_write,
1031
+ },{ .name = "WIR", .addr = A_WIR,
1032
+ .reset = 0x3f3f,
1033
+ .rsvd = 0xffff0000,
1034
+ },{ .name = "TXFIFO_ID", .addr = A_TXFIFO_ID,
1035
+ .post_write = can_tx_post_write,
1036
+ },{ .name = "TXFIFO_DLC", .addr = A_TXFIFO_DLC,
1037
+ .rsvd = 0xfffffff,
1038
+ .post_write = can_tx_post_write,
1039
+ },{ .name = "TXFIFO_DATA1", .addr = A_TXFIFO_DATA1,
1040
+ .post_write = can_tx_post_write,
1041
+ },{ .name = "TXFIFO_DATA2", .addr = A_TXFIFO_DATA2,
1042
+ .post_write = can_tx_post_write,
1043
+ },{ .name = "TXHPB_ID", .addr = A_TXHPB_ID,
1044
+ .post_write = can_tx_post_write,
1045
+ },{ .name = "TXHPB_DLC", .addr = A_TXHPB_DLC,
1046
+ .rsvd = 0xfffffff,
1047
+ .post_write = can_tx_post_write,
1048
+ },{ .name = "TXHPB_DATA1", .addr = A_TXHPB_DATA1,
1049
+ .post_write = can_tx_post_write,
1050
+ },{ .name = "TXHPB_DATA2", .addr = A_TXHPB_DATA2,
1051
+ .post_write = can_tx_post_write,
1052
+ },{ .name = "RXFIFO_ID", .addr = A_RXFIFO_ID,
1053
+ .ro = 0xffffffff,
1054
+ .post_read = can_rxfifo_pre_read,
1055
+ },{ .name = "RXFIFO_DLC", .addr = A_RXFIFO_DLC,
1056
+ .rsvd = 0xfff0000,
1057
+ .post_read = can_rxfifo_pre_read,
1058
+ },{ .name = "RXFIFO_DATA1", .addr = A_RXFIFO_DATA1,
1059
+ .post_read = can_rxfifo_pre_read,
1060
+ },{ .name = "RXFIFO_DATA2", .addr = A_RXFIFO_DATA2,
1061
+ .post_read = can_rxfifo_pre_read,
1062
+ },{ .name = "AFR", .addr = A_AFR,
1063
+ .rsvd = 0xfffffff0,
1064
+ .post_write = can_filter_enable_post_write,
1065
+ },{ .name = "AFMR1", .addr = A_AFMR1,
1066
+ .pre_write = can_filter_mask_pre_write,
1067
+ },{ .name = "AFIR1", .addr = A_AFIR1,
1068
+ .pre_write = can_filter_id_pre_write,
1069
+ },{ .name = "AFMR2", .addr = A_AFMR2,
1070
+ .pre_write = can_filter_mask_pre_write,
1071
+ },{ .name = "AFIR2", .addr = A_AFIR2,
1072
+ .pre_write = can_filter_id_pre_write,
1073
+ },{ .name = "AFMR3", .addr = A_AFMR3,
1074
+ .pre_write = can_filter_mask_pre_write,
1075
+ },{ .name = "AFIR3", .addr = A_AFIR3,
1076
+ .pre_write = can_filter_id_pre_write,
1077
+ },{ .name = "AFMR4", .addr = A_AFMR4,
1078
+ .pre_write = can_filter_mask_pre_write,
1079
+ },{ .name = "AFIR4", .addr = A_AFIR4,
1080
+ .pre_write = can_filter_id_pre_write,
1081
+ }
1082
+};
1083
+
1084
+static void xlnx_zynqmp_can_ptimer_cb(void *opaque)
1085
+{
1086
+ /* No action required on the timer rollover. */
1087
+}
1088
+
1089
+static const MemoryRegionOps can_ops = {
1090
+ .read = register_read_memory,
1091
+ .write = register_write_memory,
1092
+ .endianness = DEVICE_LITTLE_ENDIAN,
1093
+ .valid = {
1094
+ .min_access_size = 4,
1095
+ .max_access_size = 4,
1096
+ },
1097
+};
1098
+
1099
+static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type)
1100
+{
1101
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
1102
+ unsigned int i;
1103
+
1104
+ for (i = R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) {
1105
+ register_reset(&s->reg_info[i]);
1106
+ }
1107
+
1108
+ ptimer_transaction_begin(s->can_timer);
1109
+ ptimer_set_count(s->can_timer, 0);
1110
+ ptimer_transaction_commit(s->can_timer);
1111
+}
1112
+
1113
+static void xlnx_zynqmp_can_reset_hold(Object *obj)
1114
+{
1115
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
1116
+ unsigned int i;
1117
+
1118
+ for (i = 0; i < R_RXFIFO_ID; ++i) {
1119
+ register_reset(&s->reg_info[i]);
1120
+ }
1121
+
1122
+ /*
1123
+ * Reset FIFOs when CAN model is reset. This will clear the fifo writes
1124
+ * done by post_write which gets called from register_reset function,
1125
+ * post_write handle will not be able to trigger tx because CAN will be
1126
+ * disabled when software_reset_register is cleared first.
1127
+ */
1128
+ fifo32_reset(&s->rx_fifo);
1129
+ fifo32_reset(&s->tx_fifo);
1130
+ fifo32_reset(&s->txhpb_fifo);
1131
+}
1132
+
1133
+static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client)
1134
+{
1135
+ XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
1136
+ bus_client);
1137
+
1138
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
1139
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1140
+
1141
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in reset state.\n",
1142
+ path);
1143
+ return false;
1144
+ }
1145
+
1146
+ if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) {
1147
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1148
+
1149
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is disabled. Incoming"
1150
+ " messages will be discarded.\n", path);
1151
+ return false;
1152
+ }
1153
+
1154
+ return true;
1155
+}
1156
+
1157
+static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client,
1158
+ const qemu_can_frame *buf, size_t buf_size) {
1159
+ XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
1160
+ bus_client);
1161
+ const qemu_can_frame *frame = buf;
1162
+
1163
+ if (buf_size <= 0) {
1164
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1165
+
1166
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Error in the data received.\n",
1167
+ path);
243
+ return 0;
1168
+ return 0;
244
+ case GPCLR0:
1169
+ }
245
+ case GPCLR1:
1170
+
246
+ /* Write Only */
1171
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
247
+ return 0;
1172
+ /* Snoop Mode: Just keep the data. no response back. */
248
+ case GPLEV0:
1173
+ update_rx_fifo(s, frame);
249
+ return s->lev0;
1174
+ } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
250
+ case GPLEV1:
1175
+ /*
251
+ return s->lev1;
1176
+ * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it to wake
252
+ case GPEDS0:
1177
+ * up state.
253
+ case GPEDS1:
1178
+ */
254
+ case GPREN0:
1179
+ can_exit_sleep_mode(s);
255
+ case GPREN1:
1180
+ update_rx_fifo(s, frame);
256
+ case GPFEN0:
1181
+ } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) {
257
+ case GPFEN1:
1182
+ update_rx_fifo(s, frame);
258
+ case GPHEN0:
1183
+ } else {
259
+ case GPHEN1:
1184
+ /*
260
+ case GPLEN0:
1185
+ * XlnxZynqMPCAN will not participate in normal bus communication
261
+ case GPLEN1:
1186
+ * and will not receive any messages transmitted by other CAN nodes.
262
+ case GPAREN0:
1187
+ */
263
+ case GPAREN1:
1188
+ trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]);
264
+ case GPAFEN0:
1189
+ }
265
+ case GPAFEN1:
1190
+
266
+ case GPPUD:
1191
+ return 1;
267
+ case GPPUDCLK0:
1192
+}
268
+ case GPPUDCLK1:
1193
+
269
+ /* Not implemented */
1194
+static CanBusClientInfo can_xilinx_bus_client_info = {
270
+ return 0;
1195
+ .can_receive = xlnx_zynqmp_can_can_receive,
271
+ default:
1196
+ .receive = xlnx_zynqmp_can_receive,
272
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
1197
+};
273
+ __func__, offset);
1198
+
274
+ break;
1199
+static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s,
275
+ }
1200
+ CanBusState *bus)
276
+
1201
+{
1202
+ s->bus_client.info = &can_xilinx_bus_client_info;
1203
+
1204
+ if (can_bus_insert_client(bus, &s->bus_client) < 0) {
1205
+ return -1;
1206
+ }
277
+ return 0;
1207
+ return 0;
278
+}
1208
+}
279
+
1209
+
280
+static void bcm2835_gpio_write(void *opaque, hwaddr offset,
1210
+static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp)
281
+ uint64_t value, unsigned size)
1211
+{
282
+{
1212
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(dev);
283
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
1213
+
284
+
1214
+ if (s->canbus) {
285
+ switch (offset) {
1215
+ if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) {
286
+ case GPFSEL0:
1216
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
287
+ case GPFSEL1:
1217
+
288
+ case GPFSEL2:
1218
+ error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus"
289
+ case GPFSEL3:
1219
+ " failed.", path);
290
+ case GPFSEL4:
1220
+ return;
291
+ case GPFSEL5:
1221
+ }
292
+ gpfsel_set(s, offset / 4, value);
1222
+ }
293
+ break;
1223
+
294
+ case GPSET0:
1224
+ /* Create RX FIFO, TXFIFO, TXHPB storage. */
295
+ gpset(s, value, 0, 32, &s->lev0);
1225
+ fifo32_create(&s->rx_fifo, RXFIFO_SIZE);
296
+ break;
1226
+ fifo32_create(&s->tx_fifo, RXFIFO_SIZE);
297
+ case GPSET1:
1227
+ fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE);
298
+ gpset(s, value, 32, 22, &s->lev1);
1228
+
299
+ break;
1229
+ /* Allocate a new timer. */
300
+ case GPCLR0:
1230
+ s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s,
301
+ gpclr(s, value, 0, 32, &s->lev0);
1231
+ PTIMER_POLICY_DEFAULT);
302
+ break;
1232
+
303
+ case GPCLR1:
1233
+ ptimer_transaction_begin(s->can_timer);
304
+ gpclr(s, value, 32, 22, &s->lev1);
1234
+
305
+ break;
1235
+ ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq);
306
+ case GPLEV0:
1236
+ ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1);
307
+ case GPLEV1:
1237
+ ptimer_run(s->can_timer, 0);
308
+ /* Read Only */
1238
+ ptimer_transaction_commit(s->can_timer);
309
+ break;
1239
+}
310
+ case GPEDS0:
1240
+
311
+ case GPEDS1:
1241
+static void xlnx_zynqmp_can_init(Object *obj)
312
+ case GPREN0:
1242
+{
313
+ case GPREN1:
1243
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
314
+ case GPFEN0:
1244
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
315
+ case GPFEN1:
1245
+
316
+ case GPHEN0:
1246
+ RegisterInfoArray *reg_array;
317
+ case GPHEN1:
1247
+
318
+ case GPLEN0:
1248
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN,
319
+ case GPLEN1:
1249
+ XLNX_ZYNQMP_CAN_R_MAX * 4);
320
+ case GPAREN0:
1250
+ reg_array = register_init_block32(DEVICE(obj), can_regs_info,
321
+ case GPAREN1:
1251
+ ARRAY_SIZE(can_regs_info),
322
+ case GPAFEN0:
1252
+ s->reg_info, s->regs,
323
+ case GPAFEN1:
1253
+ &can_ops,
324
+ case GPPUD:
1254
+ XLNX_ZYNQMP_CAN_ERR_DEBUG,
325
+ case GPPUDCLK0:
1255
+ XLNX_ZYNQMP_CAN_R_MAX * 4);
326
+ case GPPUDCLK1:
1256
+
327
+ /* Not implemented */
1257
+ memory_region_add_subregion(&s->iomem, 0x00, &reg_array->mem);
328
+ break;
1258
+ sysbus_init_mmio(sbd, &s->iomem);
329
+ default:
1259
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
330
+ goto err_out;
1260
+}
331
+ }
1261
+
332
+ return;
1262
+static const VMStateDescription vmstate_can = {
333
+
1263
+ .name = TYPE_XLNX_ZYNQMP_CAN,
334
+err_out:
335
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
336
+ __func__, offset);
337
+}
338
+
339
+static void bcm2835_gpio_reset(DeviceState *dev)
340
+{
341
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
342
+
343
+ int i;
344
+ for (i = 0; i < 6; i++) {
345
+ gpfsel_set(s, i, 0);
346
+ }
347
+
348
+ s->sd_fsel = 0;
349
+
350
+ /* SDHCI is selected by default */
351
+ sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci);
352
+
353
+ s->lev0 = 0;
354
+ s->lev1 = 0;
355
+}
356
+
357
+static const MemoryRegionOps bcm2835_gpio_ops = {
358
+ .read = bcm2835_gpio_read,
359
+ .write = bcm2835_gpio_write,
360
+ .endianness = DEVICE_NATIVE_ENDIAN,
361
+};
362
+
363
+static const VMStateDescription vmstate_bcm2835_gpio = {
364
+ .name = "bcm2835_gpio",
365
+ .version_id = 1,
1264
+ .version_id = 1,
366
+ .minimum_version_id = 1,
1265
+ .minimum_version_id = 1,
367
+ .fields = (VMStateField[]) {
1266
+ .fields = (VMStateField[]) {
368
+ VMSTATE_UINT8_ARRAY(fsel, BCM2835GpioState, 54),
1267
+ VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState),
369
+ VMSTATE_UINT32(lev0, BCM2835GpioState),
1268
+ VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState),
370
+ VMSTATE_UINT32(lev1, BCM2835GpioState),
1269
+ VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState),
371
+ VMSTATE_UINT8(sd_fsel, BCM2835GpioState),
1270
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_MAX),
372
+ VMSTATE_END_OF_LIST()
1271
+ VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState),
1272
+ VMSTATE_END_OF_LIST(),
373
+ }
1273
+ }
374
+};
1274
+};
375
+
1275
+
376
+static void bcm2835_gpio_init(Object *obj)
1276
+static Property xlnx_zynqmp_can_properties[] = {
377
+{
1277
+ DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_freq,
378
+ BCM2835GpioState *s = BCM2835_GPIO(obj);
1278
+ CAN_DEFAULT_CLOCK),
379
+ DeviceState *dev = DEVICE(obj);
1279
+ DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS,
380
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1280
+ CanBusState *),
381
+
1281
+ DEFINE_PROP_END_OF_LIST(),
382
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
1282
+};
383
+ TYPE_SD_BUS, DEVICE(s), "sd-bus");
1283
+
384
+
1284
+static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data)
385
+ memory_region_init_io(&s->iomem, obj,
386
+ &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
387
+ sysbus_init_mmio(sbd, &s->iomem);
388
+ qdev_init_gpio_out(dev, s->out, 54);
389
+}
390
+
391
+static void bcm2835_gpio_realize(DeviceState *dev, Error **errp)
392
+{
393
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
394
+ Object *obj;
395
+ Error *err = NULL;
396
+
397
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhci", &err);
398
+ if (obj == NULL) {
399
+ error_setg(errp, "%s: required sdhci link not found: %s",
400
+ __func__, error_get_pretty(err));
401
+ return;
402
+ }
403
+ s->sdbus_sdhci = SD_BUS(obj);
404
+
405
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhost", &err);
406
+ if (obj == NULL) {
407
+ error_setg(errp, "%s: required sdhost link not found: %s",
408
+ __func__, error_get_pretty(err));
409
+ return;
410
+ }
411
+ s->sdbus_sdhost = SD_BUS(obj);
412
+}
413
+
414
+static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
415
+{
1285
+{
416
+ DeviceClass *dc = DEVICE_CLASS(klass);
1286
+ DeviceClass *dc = DEVICE_CLASS(klass);
417
+
1287
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
418
+ dc->vmsd = &vmstate_bcm2835_gpio;
1288
+
419
+ dc->realize = &bcm2835_gpio_realize;
1289
+ rc->phases.enter = xlnx_zynqmp_can_reset_init;
420
+ dc->reset = &bcm2835_gpio_reset;
1290
+ rc->phases.hold = xlnx_zynqmp_can_reset_hold;
421
+}
1291
+ dc->realize = xlnx_zynqmp_can_realize;
422
+
1292
+ device_class_set_props(dc, xlnx_zynqmp_can_properties);
423
+static const TypeInfo bcm2835_gpio_info = {
1293
+ dc->vmsd = &vmstate_can;
424
+ .name = TYPE_BCM2835_GPIO,
1294
+}
1295
+
1296
+static const TypeInfo can_info = {
1297
+ .name = TYPE_XLNX_ZYNQMP_CAN,
425
+ .parent = TYPE_SYS_BUS_DEVICE,
1298
+ .parent = TYPE_SYS_BUS_DEVICE,
426
+ .instance_size = sizeof(BCM2835GpioState),
1299
+ .instance_size = sizeof(XlnxZynqMPCANState),
427
+ .instance_init = bcm2835_gpio_init,
1300
+ .class_init = xlnx_zynqmp_can_class_init,
428
+ .class_init = bcm2835_gpio_class_init,
1301
+ .instance_init = xlnx_zynqmp_can_init,
429
+};
1302
+};
430
+
1303
+
431
+static void bcm2835_gpio_register_types(void)
1304
+static void can_register_types(void)
432
+{
1305
+{
433
+ type_register_static(&bcm2835_gpio_info);
1306
+ type_register_static(&can_info);
434
+}
1307
+}
435
+
1308
+
436
+type_init(bcm2835_gpio_register_types)
1309
+type_init(can_register_types)
1310
diff --git a/hw/Kconfig b/hw/Kconfig
1311
index XXXXXXX..XXXXXXX 100644
1312
--- a/hw/Kconfig
1313
+++ b/hw/Kconfig
1314
@@ -XXX,XX +XXX,XX @@ config XILINX_AXI
1315
config XLNX_ZYNQMP
1316
bool
1317
select REGISTER
1318
+ select CAN_BUS
1319
diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build
1320
index XXXXXXX..XXXXXXX 100644
1321
--- a/hw/net/can/meson.build
1322
+++ b/hw/net/can/meson.build
1323
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
1324
softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
1325
softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'))
1326
softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.c'))
1327
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c'))
1328
diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events
1329
new file mode 100644
1330
index XXXXXXX..XXXXXXX
1331
--- /dev/null
1332
+++ b/hw/net/can/trace-events
1333
@@ -XXX,XX +XXX,XX @@
1334
+# xlnx-zynqmp-can.c
1335
+xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
1336
+xlnx_can_reset(uint32_t val) "Resetting controller with value = 0x%08x"
1337
+xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08x DLC: 0x%02x"
1338
+xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d ID: 0x%08x"
1339
+xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x"
1340
+xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
1341
+xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
1342
+xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x"
437
--
1343
--
438
2.7.4
1344
2.20.1
439
1345
440
1346
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
2
2
3
virtio_mmio.h would be deleted; I am leaving it in though it was a
3
Connect CAN0 and CAN1 on the ZynqMP.
4
mistake to add it.
5
4
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
5
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
8
Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
include/standard-headers/asm-x86/hyperv.h | 8 +
11
include/hw/arm/xlnx-zynqmp.h | 8 ++++++++
10
include/standard-headers/linux/input-event-codes.h | 2 +-
12
hw/arm/xlnx-zcu102.c | 20 ++++++++++++++++++++
11
include/standard-headers/linux/pci_regs.h | 25 ++
13
hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++
12
include/standard-headers/linux/virtio_ids.h | 1 +
14
3 files changed, 62 insertions(+)
13
linux-headers/asm-arm/kvm.h | 15 +
14
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++++++++
15
linux-headers/asm-arm/unistd-eabi.h | 5 +
16
linux-headers/asm-arm/unistd-oabi.h | 17 +
17
linux-headers/asm-arm/unistd.h | 419 +--------------------
18
linux-headers/asm-arm64/kvm.h | 13 +
19
linux-headers/asm-powerpc/kvm.h | 27 ++
20
linux-headers/asm-powerpc/unistd.h | 1 +
21
linux-headers/asm-x86/kvm_para.h | 13 +-
22
linux-headers/linux/kvm.h | 24 +-
23
linux-headers/linux/kvm_para.h | 2 +
24
linux-headers/linux/userfaultfd.h | 67 +++-
25
linux-headers/linux/vfio.h | 10 +
26
17 files changed, 577 insertions(+), 429 deletions(-)
27
create mode 100644 linux-headers/asm-arm/unistd-common.h
28
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
29
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
30
15
31
diff --git a/include/standard-headers/asm-x86/hyperv.h b/include/standard-headers/asm-x86/hyperv.h
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
32
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
33
--- a/include/standard-headers/asm-x86/hyperv.h
18
--- a/include/hw/arm/xlnx-zynqmp.h
34
+++ b/include/standard-headers/asm-x86/hyperv.h
19
+++ b/include/hw/arm/xlnx-zynqmp.h
35
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
36
*/
21
#include "hw/intc/arm_gic.h"
37
#define HV_X64_MSR_STAT_PAGES_AVAILABLE        (1 << 8)
22
#include "hw/net/cadence_gem.h"
38
23
#include "hw/char/cadence_uart.h"
39
+/* Crash MSR available */
24
+#include "hw/net/xlnx-zynqmp-can.h"
40
+#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
25
#include "hw/ide/ahci.h"
26
#include "hw/sd/sdhci.h"
27
#include "hw/ssi/xilinx_spips.h"
28
@@ -XXX,XX +XXX,XX @@
29
#include "hw/cpu/cluster.h"
30
#include "target/arm/cpu.h"
31
#include "qom/object.h"
32
+#include "net/can_emu.h"
33
34
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
35
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
36
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
37
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
38
#define XLNX_ZYNQMP_NUM_GEMS 4
39
#define XLNX_ZYNQMP_NUM_UARTS 2
40
+#define XLNX_ZYNQMP_NUM_CAN 2
41
+#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
42
#define XLNX_ZYNQMP_NUM_SDHCI 2
43
#define XLNX_ZYNQMP_NUM_SPIS 2
44
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
45
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
46
47
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
48
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
49
+ XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
50
SysbusAHCIState sata;
51
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
52
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
53
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
54
bool virt;
55
/* Has the RPU subsystem? */
56
bool has_rpu;
41
+
57
+
42
/*
58
+ /* CAN bus. */
43
* Feature identification: EBX indicates which flags were specified at
59
+ CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
44
* partition creation. The format is the same as the partition creation
60
};
61
62
#endif
63
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/xlnx-zcu102.c
66
+++ b/hw/arm/xlnx-zcu102.c
45
@@ -XXX,XX +XXX,XX @@
67
@@ -XXX,XX +XXX,XX @@
46
*/
68
#include "sysemu/qtest.h"
47
#define HV_X64_RELAXED_TIMING_RECOMMENDED    (1 << 5)
69
#include "sysemu/device_tree.h"
48
70
#include "qom/object.h"
49
+/*
71
+#include "net/can_emu.h"
50
+ * Crash notification flag.
72
51
+ */
73
struct XlnxZCU102 {
52
+#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
74
MachineState parent_obj;
75
@@ -XXX,XX +XXX,XX @@ struct XlnxZCU102 {
76
bool secure;
77
bool virt;
78
79
+ CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
53
+
80
+
54
/* MSR used to identify the guest OS. */
81
struct arm_boot_info binfo;
55
#define HV_X64_MSR_GUEST_OS_ID            0x40000000
82
};
56
83
57
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
84
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
85
object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
86
&error_fatal);
87
88
+ for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
89
+ gchar *bus_name = g_strdup_printf("canbus%d", i);
90
+
91
+ object_property_set_link(OBJECT(&s->soc), bus_name,
92
+ OBJECT(s->canbus[i]), &error_fatal);
93
+ g_free(bus_name);
94
+ }
95
+
96
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
97
98
/* Create and plug in the SD cards */
99
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
100
s->secure = false;
101
/* Default to virt (EL2) being disabled */
102
s->virt = false;
103
+ object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
104
+ (Object **)&s->canbus[0],
105
+ object_property_allow_set_link,
106
+ 0);
107
+
108
+ object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
109
+ (Object **)&s->canbus[1],
110
+ object_property_allow_set_link,
111
+ 0);
112
}
113
114
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
115
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
58
index XXXXXXX..XXXXXXX 100644
116
index XXXXXXX..XXXXXXX 100644
59
--- a/include/standard-headers/linux/input-event-codes.h
117
--- a/hw/arm/xlnx-zynqmp.c
60
+++ b/include/standard-headers/linux/input-event-codes.h
118
+++ b/hw/arm/xlnx-zynqmp.c
61
@@ -XXX,XX +XXX,XX @@
119
@@ -XXX,XX +XXX,XX @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
62
* Control a data application associated with the currently viewed channel,
120
21, 22,
63
* e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
64
*/
65
-#define KEY_DATA            0x275
66
+#define KEY_DATA            0x277
67
68
#define BTN_TRIGGER_HAPPY        0x2c0
69
#define BTN_TRIGGER_HAPPY1        0x2c0
70
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/standard-headers/linux/pci_regs.h
73
+++ b/include/standard-headers/linux/pci_regs.h
74
@@ -XXX,XX +XXX,XX @@
75
#define LINUX_PCI_REGS_H
76
77
/*
78
+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
79
+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
80
+ * configuration space.
81
+ */
82
+#define PCI_CFG_SPACE_SIZE    256
83
+#define PCI_CFG_SPACE_EXP_SIZE    4096
84
+
85
+/*
86
* Under PCI, each device has 256 bytes of configuration address space,
87
* of which the first 64 bytes are standardized as follows:
88
*/
89
@@ -XXX,XX +XXX,XX @@
90
#define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
91
#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
92
#define PCI_EXT_CAP_ID_DPC    0x1D    /* Downstream Port Containment */
93
+#define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
94
#define PCI_EXT_CAP_ID_PTM    0x1F    /* Precision Time Measurement */
95
#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PTM
96
97
@@ -XXX,XX +XXX,XX @@
98
#define PCI_EXP_DPC_STATUS        8    /* DPC Status */
99
#define PCI_EXP_DPC_STATUS_TRIGGER    0x01    /* Trigger Status */
100
#define PCI_EXP_DPC_STATUS_INTERRUPT    0x08    /* Interrupt Status */
101
+#define PCI_EXP_DPC_RP_BUSY        0x10    /* Root Port Busy */
102
103
#define PCI_EXP_DPC_SOURCE_ID        10    /* DPC Source Identifier */
104
105
@@ -XXX,XX +XXX,XX @@
106
#define PCI_PTM_CTRL_ENABLE        0x00000001 /* PTM enable */
107
#define PCI_PTM_CTRL_ROOT        0x00000002 /* Root select */
108
109
+/* L1 PM Substates */
110
+#define PCI_L1SS_CAP         4    /* capability register */
111
+#define PCI_L1SS_CAP_PCIPM_L1_2     1    /* PCI PM L1.2 Support */
112
+#define PCI_L1SS_CAP_PCIPM_L1_1     2    /* PCI PM L1.1 Support */
113
+#define PCI_L1SS_CAP_ASPM_L1_2         4    /* ASPM L1.2 Support */
114
+#define PCI_L1SS_CAP_ASPM_L1_1         8    /* ASPM L1.1 Support */
115
+#define PCI_L1SS_CAP_L1_PM_SS        16    /* L1 PM Substates Support */
116
+#define PCI_L1SS_CTL1         8    /* Control Register 1 */
117
+#define PCI_L1SS_CTL1_PCIPM_L1_2    1    /* PCI PM L1.2 Enable */
118
+#define PCI_L1SS_CTL1_PCIPM_L1_1    2    /* PCI PM L1.1 Support */
119
+#define PCI_L1SS_CTL1_ASPM_L1_2    4    /* ASPM L1.2 Support */
120
+#define PCI_L1SS_CTL1_ASPM_L1_1    8    /* ASPM L1.1 Support */
121
+#define PCI_L1SS_CTL1_L1SS_MASK    0x0000000F
122
+#define PCI_L1SS_CTL2         0xC    /* Control Register 2 */
123
+
124
#endif /* LINUX_PCI_REGS_H */
125
diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h
126
index XXXXXXX..XXXXXXX 100644
127
--- a/include/standard-headers/linux/virtio_ids.h
128
+++ b/include/standard-headers/linux/virtio_ids.h
129
@@ -XXX,XX +XXX,XX @@
130
#define VIRTIO_ID_INPUT 18 /* virtio input */
131
#define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */
132
#define VIRTIO_ID_CRYPTO 20 /* virtio crypto */
133
+
134
#endif /* _LINUX_VIRTIO_IDS_H */
135
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-headers/asm-arm/kvm.h
138
+++ b/linux-headers/asm-arm/kvm.h
139
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
140
/* Supported VGICv3 address types */
141
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
142
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
143
+#define KVM_VGIC_ITS_ADDR_TYPE        4
144
145
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
146
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
147
+#define KVM_VGIC_V3_ITS_SIZE        (2 * SZ_64K)
148
149
#define KVM_ARM_VCPU_POWER_OFF        0 /* CPU is started in OFF state */
150
#define KVM_ARM_VCPU_PSCI_0_2        1 /* CPU uses PSCI v0.2 */
151
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
152
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
153
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
154
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
155
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
156
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
157
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
158
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
159
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
160
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
161
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
162
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
163
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
164
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
165
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
166
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
167
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
168
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
169
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
170
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
171
+
172
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
173
174
/* KVM_IRQ_LINE irq field index values */
175
diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h
176
new file mode 100644
177
index XXXXXXX..XXXXXXX
178
--- /dev/null
179
+++ b/linux-headers/asm-arm/unistd-common.h
180
@@ -XXX,XX +XXX,XX @@
181
+#ifndef _ASM_ARM_UNISTD_COMMON_H
182
+#define _ASM_ARM_UNISTD_COMMON_H 1
183
+
184
+#define __NR_restart_syscall (__NR_SYSCALL_BASE + 0)
185
+#define __NR_exit (__NR_SYSCALL_BASE + 1)
186
+#define __NR_fork (__NR_SYSCALL_BASE + 2)
187
+#define __NR_read (__NR_SYSCALL_BASE + 3)
188
+#define __NR_write (__NR_SYSCALL_BASE + 4)
189
+#define __NR_open (__NR_SYSCALL_BASE + 5)
190
+#define __NR_close (__NR_SYSCALL_BASE + 6)
191
+#define __NR_creat (__NR_SYSCALL_BASE + 8)
192
+#define __NR_link (__NR_SYSCALL_BASE + 9)
193
+#define __NR_unlink (__NR_SYSCALL_BASE + 10)
194
+#define __NR_execve (__NR_SYSCALL_BASE + 11)
195
+#define __NR_chdir (__NR_SYSCALL_BASE + 12)
196
+#define __NR_mknod (__NR_SYSCALL_BASE + 14)
197
+#define __NR_chmod (__NR_SYSCALL_BASE + 15)
198
+#define __NR_lchown (__NR_SYSCALL_BASE + 16)
199
+#define __NR_lseek (__NR_SYSCALL_BASE + 19)
200
+#define __NR_getpid (__NR_SYSCALL_BASE + 20)
201
+#define __NR_mount (__NR_SYSCALL_BASE + 21)
202
+#define __NR_setuid (__NR_SYSCALL_BASE + 23)
203
+#define __NR_getuid (__NR_SYSCALL_BASE + 24)
204
+#define __NR_ptrace (__NR_SYSCALL_BASE + 26)
205
+#define __NR_pause (__NR_SYSCALL_BASE + 29)
206
+#define __NR_access (__NR_SYSCALL_BASE + 33)
207
+#define __NR_nice (__NR_SYSCALL_BASE + 34)
208
+#define __NR_sync (__NR_SYSCALL_BASE + 36)
209
+#define __NR_kill (__NR_SYSCALL_BASE + 37)
210
+#define __NR_rename (__NR_SYSCALL_BASE + 38)
211
+#define __NR_mkdir (__NR_SYSCALL_BASE + 39)
212
+#define __NR_rmdir (__NR_SYSCALL_BASE + 40)
213
+#define __NR_dup (__NR_SYSCALL_BASE + 41)
214
+#define __NR_pipe (__NR_SYSCALL_BASE + 42)
215
+#define __NR_times (__NR_SYSCALL_BASE + 43)
216
+#define __NR_brk (__NR_SYSCALL_BASE + 45)
217
+#define __NR_setgid (__NR_SYSCALL_BASE + 46)
218
+#define __NR_getgid (__NR_SYSCALL_BASE + 47)
219
+#define __NR_geteuid (__NR_SYSCALL_BASE + 49)
220
+#define __NR_getegid (__NR_SYSCALL_BASE + 50)
221
+#define __NR_acct (__NR_SYSCALL_BASE + 51)
222
+#define __NR_umount2 (__NR_SYSCALL_BASE + 52)
223
+#define __NR_ioctl (__NR_SYSCALL_BASE + 54)
224
+#define __NR_fcntl (__NR_SYSCALL_BASE + 55)
225
+#define __NR_setpgid (__NR_SYSCALL_BASE + 57)
226
+#define __NR_umask (__NR_SYSCALL_BASE + 60)
227
+#define __NR_chroot (__NR_SYSCALL_BASE + 61)
228
+#define __NR_ustat (__NR_SYSCALL_BASE + 62)
229
+#define __NR_dup2 (__NR_SYSCALL_BASE + 63)
230
+#define __NR_getppid (__NR_SYSCALL_BASE + 64)
231
+#define __NR_getpgrp (__NR_SYSCALL_BASE + 65)
232
+#define __NR_setsid (__NR_SYSCALL_BASE + 66)
233
+#define __NR_sigaction (__NR_SYSCALL_BASE + 67)
234
+#define __NR_setreuid (__NR_SYSCALL_BASE + 70)
235
+#define __NR_setregid (__NR_SYSCALL_BASE + 71)
236
+#define __NR_sigsuspend (__NR_SYSCALL_BASE + 72)
237
+#define __NR_sigpending (__NR_SYSCALL_BASE + 73)
238
+#define __NR_sethostname (__NR_SYSCALL_BASE + 74)
239
+#define __NR_setrlimit (__NR_SYSCALL_BASE + 75)
240
+#define __NR_getrusage (__NR_SYSCALL_BASE + 77)
241
+#define __NR_gettimeofday (__NR_SYSCALL_BASE + 78)
242
+#define __NR_settimeofday (__NR_SYSCALL_BASE + 79)
243
+#define __NR_getgroups (__NR_SYSCALL_BASE + 80)
244
+#define __NR_setgroups (__NR_SYSCALL_BASE + 81)
245
+#define __NR_symlink (__NR_SYSCALL_BASE + 83)
246
+#define __NR_readlink (__NR_SYSCALL_BASE + 85)
247
+#define __NR_uselib (__NR_SYSCALL_BASE + 86)
248
+#define __NR_swapon (__NR_SYSCALL_BASE + 87)
249
+#define __NR_reboot (__NR_SYSCALL_BASE + 88)
250
+#define __NR_munmap (__NR_SYSCALL_BASE + 91)
251
+#define __NR_truncate (__NR_SYSCALL_BASE + 92)
252
+#define __NR_ftruncate (__NR_SYSCALL_BASE + 93)
253
+#define __NR_fchmod (__NR_SYSCALL_BASE + 94)
254
+#define __NR_fchown (__NR_SYSCALL_BASE + 95)
255
+#define __NR_getpriority (__NR_SYSCALL_BASE + 96)
256
+#define __NR_setpriority (__NR_SYSCALL_BASE + 97)
257
+#define __NR_statfs (__NR_SYSCALL_BASE + 99)
258
+#define __NR_fstatfs (__NR_SYSCALL_BASE + 100)
259
+#define __NR_syslog (__NR_SYSCALL_BASE + 103)
260
+#define __NR_setitimer (__NR_SYSCALL_BASE + 104)
261
+#define __NR_getitimer (__NR_SYSCALL_BASE + 105)
262
+#define __NR_stat (__NR_SYSCALL_BASE + 106)
263
+#define __NR_lstat (__NR_SYSCALL_BASE + 107)
264
+#define __NR_fstat (__NR_SYSCALL_BASE + 108)
265
+#define __NR_vhangup (__NR_SYSCALL_BASE + 111)
266
+#define __NR_wait4 (__NR_SYSCALL_BASE + 114)
267
+#define __NR_swapoff (__NR_SYSCALL_BASE + 115)
268
+#define __NR_sysinfo (__NR_SYSCALL_BASE + 116)
269
+#define __NR_fsync (__NR_SYSCALL_BASE + 118)
270
+#define __NR_sigreturn (__NR_SYSCALL_BASE + 119)
271
+#define __NR_clone (__NR_SYSCALL_BASE + 120)
272
+#define __NR_setdomainname (__NR_SYSCALL_BASE + 121)
273
+#define __NR_uname (__NR_SYSCALL_BASE + 122)
274
+#define __NR_adjtimex (__NR_SYSCALL_BASE + 124)
275
+#define __NR_mprotect (__NR_SYSCALL_BASE + 125)
276
+#define __NR_sigprocmask (__NR_SYSCALL_BASE + 126)
277
+#define __NR_init_module (__NR_SYSCALL_BASE + 128)
278
+#define __NR_delete_module (__NR_SYSCALL_BASE + 129)
279
+#define __NR_quotactl (__NR_SYSCALL_BASE + 131)
280
+#define __NR_getpgid (__NR_SYSCALL_BASE + 132)
281
+#define __NR_fchdir (__NR_SYSCALL_BASE + 133)
282
+#define __NR_bdflush (__NR_SYSCALL_BASE + 134)
283
+#define __NR_sysfs (__NR_SYSCALL_BASE + 135)
284
+#define __NR_personality (__NR_SYSCALL_BASE + 136)
285
+#define __NR_setfsuid (__NR_SYSCALL_BASE + 138)
286
+#define __NR_setfsgid (__NR_SYSCALL_BASE + 139)
287
+#define __NR__llseek (__NR_SYSCALL_BASE + 140)
288
+#define __NR_getdents (__NR_SYSCALL_BASE + 141)
289
+#define __NR__newselect (__NR_SYSCALL_BASE + 142)
290
+#define __NR_flock (__NR_SYSCALL_BASE + 143)
291
+#define __NR_msync (__NR_SYSCALL_BASE + 144)
292
+#define __NR_readv (__NR_SYSCALL_BASE + 145)
293
+#define __NR_writev (__NR_SYSCALL_BASE + 146)
294
+#define __NR_getsid (__NR_SYSCALL_BASE + 147)
295
+#define __NR_fdatasync (__NR_SYSCALL_BASE + 148)
296
+#define __NR__sysctl (__NR_SYSCALL_BASE + 149)
297
+#define __NR_mlock (__NR_SYSCALL_BASE + 150)
298
+#define __NR_munlock (__NR_SYSCALL_BASE + 151)
299
+#define __NR_mlockall (__NR_SYSCALL_BASE + 152)
300
+#define __NR_munlockall (__NR_SYSCALL_BASE + 153)
301
+#define __NR_sched_setparam (__NR_SYSCALL_BASE + 154)
302
+#define __NR_sched_getparam (__NR_SYSCALL_BASE + 155)
303
+#define __NR_sched_setscheduler (__NR_SYSCALL_BASE + 156)
304
+#define __NR_sched_getscheduler (__NR_SYSCALL_BASE + 157)
305
+#define __NR_sched_yield (__NR_SYSCALL_BASE + 158)
306
+#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE + 159)
307
+#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE + 160)
308
+#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE + 161)
309
+#define __NR_nanosleep (__NR_SYSCALL_BASE + 162)
310
+#define __NR_mremap (__NR_SYSCALL_BASE + 163)
311
+#define __NR_setresuid (__NR_SYSCALL_BASE + 164)
312
+#define __NR_getresuid (__NR_SYSCALL_BASE + 165)
313
+#define __NR_poll (__NR_SYSCALL_BASE + 168)
314
+#define __NR_nfsservctl (__NR_SYSCALL_BASE + 169)
315
+#define __NR_setresgid (__NR_SYSCALL_BASE + 170)
316
+#define __NR_getresgid (__NR_SYSCALL_BASE + 171)
317
+#define __NR_prctl (__NR_SYSCALL_BASE + 172)
318
+#define __NR_rt_sigreturn (__NR_SYSCALL_BASE + 173)
319
+#define __NR_rt_sigaction (__NR_SYSCALL_BASE + 174)
320
+#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE + 175)
321
+#define __NR_rt_sigpending (__NR_SYSCALL_BASE + 176)
322
+#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE + 177)
323
+#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE + 178)
324
+#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE + 179)
325
+#define __NR_pread64 (__NR_SYSCALL_BASE + 180)
326
+#define __NR_pwrite64 (__NR_SYSCALL_BASE + 181)
327
+#define __NR_chown (__NR_SYSCALL_BASE + 182)
328
+#define __NR_getcwd (__NR_SYSCALL_BASE + 183)
329
+#define __NR_capget (__NR_SYSCALL_BASE + 184)
330
+#define __NR_capset (__NR_SYSCALL_BASE + 185)
331
+#define __NR_sigaltstack (__NR_SYSCALL_BASE + 186)
332
+#define __NR_sendfile (__NR_SYSCALL_BASE + 187)
333
+#define __NR_vfork (__NR_SYSCALL_BASE + 190)
334
+#define __NR_ugetrlimit (__NR_SYSCALL_BASE + 191)
335
+#define __NR_mmap2 (__NR_SYSCALL_BASE + 192)
336
+#define __NR_truncate64 (__NR_SYSCALL_BASE + 193)
337
+#define __NR_ftruncate64 (__NR_SYSCALL_BASE + 194)
338
+#define __NR_stat64 (__NR_SYSCALL_BASE + 195)
339
+#define __NR_lstat64 (__NR_SYSCALL_BASE + 196)
340
+#define __NR_fstat64 (__NR_SYSCALL_BASE + 197)
341
+#define __NR_lchown32 (__NR_SYSCALL_BASE + 198)
342
+#define __NR_getuid32 (__NR_SYSCALL_BASE + 199)
343
+#define __NR_getgid32 (__NR_SYSCALL_BASE + 200)
344
+#define __NR_geteuid32 (__NR_SYSCALL_BASE + 201)
345
+#define __NR_getegid32 (__NR_SYSCALL_BASE + 202)
346
+#define __NR_setreuid32 (__NR_SYSCALL_BASE + 203)
347
+#define __NR_setregid32 (__NR_SYSCALL_BASE + 204)
348
+#define __NR_getgroups32 (__NR_SYSCALL_BASE + 205)
349
+#define __NR_setgroups32 (__NR_SYSCALL_BASE + 206)
350
+#define __NR_fchown32 (__NR_SYSCALL_BASE + 207)
351
+#define __NR_setresuid32 (__NR_SYSCALL_BASE + 208)
352
+#define __NR_getresuid32 (__NR_SYSCALL_BASE + 209)
353
+#define __NR_setresgid32 (__NR_SYSCALL_BASE + 210)
354
+#define __NR_getresgid32 (__NR_SYSCALL_BASE + 211)
355
+#define __NR_chown32 (__NR_SYSCALL_BASE + 212)
356
+#define __NR_setuid32 (__NR_SYSCALL_BASE + 213)
357
+#define __NR_setgid32 (__NR_SYSCALL_BASE + 214)
358
+#define __NR_setfsuid32 (__NR_SYSCALL_BASE + 215)
359
+#define __NR_setfsgid32 (__NR_SYSCALL_BASE + 216)
360
+#define __NR_getdents64 (__NR_SYSCALL_BASE + 217)
361
+#define __NR_pivot_root (__NR_SYSCALL_BASE + 218)
362
+#define __NR_mincore (__NR_SYSCALL_BASE + 219)
363
+#define __NR_madvise (__NR_SYSCALL_BASE + 220)
364
+#define __NR_fcntl64 (__NR_SYSCALL_BASE + 221)
365
+#define __NR_gettid (__NR_SYSCALL_BASE + 224)
366
+#define __NR_readahead (__NR_SYSCALL_BASE + 225)
367
+#define __NR_setxattr (__NR_SYSCALL_BASE + 226)
368
+#define __NR_lsetxattr (__NR_SYSCALL_BASE + 227)
369
+#define __NR_fsetxattr (__NR_SYSCALL_BASE + 228)
370
+#define __NR_getxattr (__NR_SYSCALL_BASE + 229)
371
+#define __NR_lgetxattr (__NR_SYSCALL_BASE + 230)
372
+#define __NR_fgetxattr (__NR_SYSCALL_BASE + 231)
373
+#define __NR_listxattr (__NR_SYSCALL_BASE + 232)
374
+#define __NR_llistxattr (__NR_SYSCALL_BASE + 233)
375
+#define __NR_flistxattr (__NR_SYSCALL_BASE + 234)
376
+#define __NR_removexattr (__NR_SYSCALL_BASE + 235)
377
+#define __NR_lremovexattr (__NR_SYSCALL_BASE + 236)
378
+#define __NR_fremovexattr (__NR_SYSCALL_BASE + 237)
379
+#define __NR_tkill (__NR_SYSCALL_BASE + 238)
380
+#define __NR_sendfile64 (__NR_SYSCALL_BASE + 239)
381
+#define __NR_futex (__NR_SYSCALL_BASE + 240)
382
+#define __NR_sched_setaffinity (__NR_SYSCALL_BASE + 241)
383
+#define __NR_sched_getaffinity (__NR_SYSCALL_BASE + 242)
384
+#define __NR_io_setup (__NR_SYSCALL_BASE + 243)
385
+#define __NR_io_destroy (__NR_SYSCALL_BASE + 244)
386
+#define __NR_io_getevents (__NR_SYSCALL_BASE + 245)
387
+#define __NR_io_submit (__NR_SYSCALL_BASE + 246)
388
+#define __NR_io_cancel (__NR_SYSCALL_BASE + 247)
389
+#define __NR_exit_group (__NR_SYSCALL_BASE + 248)
390
+#define __NR_lookup_dcookie (__NR_SYSCALL_BASE + 249)
391
+#define __NR_epoll_create (__NR_SYSCALL_BASE + 250)
392
+#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 251)
393
+#define __NR_epoll_wait (__NR_SYSCALL_BASE + 252)
394
+#define __NR_remap_file_pages (__NR_SYSCALL_BASE + 253)
395
+#define __NR_set_tid_address (__NR_SYSCALL_BASE + 256)
396
+#define __NR_timer_create (__NR_SYSCALL_BASE + 257)
397
+#define __NR_timer_settime (__NR_SYSCALL_BASE + 258)
398
+#define __NR_timer_gettime (__NR_SYSCALL_BASE + 259)
399
+#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 260)
400
+#define __NR_timer_delete (__NR_SYSCALL_BASE + 261)
401
+#define __NR_clock_settime (__NR_SYSCALL_BASE + 262)
402
+#define __NR_clock_gettime (__NR_SYSCALL_BASE + 263)
403
+#define __NR_clock_getres (__NR_SYSCALL_BASE + 264)
404
+#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 265)
405
+#define __NR_statfs64 (__NR_SYSCALL_BASE + 266)
406
+#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 267)
407
+#define __NR_tgkill (__NR_SYSCALL_BASE + 268)
408
+#define __NR_utimes (__NR_SYSCALL_BASE + 269)
409
+#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE + 270)
410
+#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE + 271)
411
+#define __NR_pciconfig_read (__NR_SYSCALL_BASE + 272)
412
+#define __NR_pciconfig_write (__NR_SYSCALL_BASE + 273)
413
+#define __NR_mq_open (__NR_SYSCALL_BASE + 274)
414
+#define __NR_mq_unlink (__NR_SYSCALL_BASE + 275)
415
+#define __NR_mq_timedsend (__NR_SYSCALL_BASE + 276)
416
+#define __NR_mq_timedreceive (__NR_SYSCALL_BASE + 277)
417
+#define __NR_mq_notify (__NR_SYSCALL_BASE + 278)
418
+#define __NR_mq_getsetattr (__NR_SYSCALL_BASE + 279)
419
+#define __NR_waitid (__NR_SYSCALL_BASE + 280)
420
+#define __NR_socket (__NR_SYSCALL_BASE + 281)
421
+#define __NR_bind (__NR_SYSCALL_BASE + 282)
422
+#define __NR_connect (__NR_SYSCALL_BASE + 283)
423
+#define __NR_listen (__NR_SYSCALL_BASE + 284)
424
+#define __NR_accept (__NR_SYSCALL_BASE + 285)
425
+#define __NR_getsockname (__NR_SYSCALL_BASE + 286)
426
+#define __NR_getpeername (__NR_SYSCALL_BASE + 287)
427
+#define __NR_socketpair (__NR_SYSCALL_BASE + 288)
428
+#define __NR_send (__NR_SYSCALL_BASE + 289)
429
+#define __NR_sendto (__NR_SYSCALL_BASE + 290)
430
+#define __NR_recv (__NR_SYSCALL_BASE + 291)
431
+#define __NR_recvfrom (__NR_SYSCALL_BASE + 292)
432
+#define __NR_shutdown (__NR_SYSCALL_BASE + 293)
433
+#define __NR_setsockopt (__NR_SYSCALL_BASE + 294)
434
+#define __NR_getsockopt (__NR_SYSCALL_BASE + 295)
435
+#define __NR_sendmsg (__NR_SYSCALL_BASE + 296)
436
+#define __NR_recvmsg (__NR_SYSCALL_BASE + 297)
437
+#define __NR_semop (__NR_SYSCALL_BASE + 298)
438
+#define __NR_semget (__NR_SYSCALL_BASE + 299)
439
+#define __NR_semctl (__NR_SYSCALL_BASE + 300)
440
+#define __NR_msgsnd (__NR_SYSCALL_BASE + 301)
441
+#define __NR_msgrcv (__NR_SYSCALL_BASE + 302)
442
+#define __NR_msgget (__NR_SYSCALL_BASE + 303)
443
+#define __NR_msgctl (__NR_SYSCALL_BASE + 304)
444
+#define __NR_shmat (__NR_SYSCALL_BASE + 305)
445
+#define __NR_shmdt (__NR_SYSCALL_BASE + 306)
446
+#define __NR_shmget (__NR_SYSCALL_BASE + 307)
447
+#define __NR_shmctl (__NR_SYSCALL_BASE + 308)
448
+#define __NR_add_key (__NR_SYSCALL_BASE + 309)
449
+#define __NR_request_key (__NR_SYSCALL_BASE + 310)
450
+#define __NR_keyctl (__NR_SYSCALL_BASE + 311)
451
+#define __NR_semtimedop (__NR_SYSCALL_BASE + 312)
452
+#define __NR_vserver (__NR_SYSCALL_BASE + 313)
453
+#define __NR_ioprio_set (__NR_SYSCALL_BASE + 314)
454
+#define __NR_ioprio_get (__NR_SYSCALL_BASE + 315)
455
+#define __NR_inotify_init (__NR_SYSCALL_BASE + 316)
456
+#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 317)
457
+#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 318)
458
+#define __NR_mbind (__NR_SYSCALL_BASE + 319)
459
+#define __NR_get_mempolicy (__NR_SYSCALL_BASE + 320)
460
+#define __NR_set_mempolicy (__NR_SYSCALL_BASE + 321)
461
+#define __NR_openat (__NR_SYSCALL_BASE + 322)
462
+#define __NR_mkdirat (__NR_SYSCALL_BASE + 323)
463
+#define __NR_mknodat (__NR_SYSCALL_BASE + 324)
464
+#define __NR_fchownat (__NR_SYSCALL_BASE + 325)
465
+#define __NR_futimesat (__NR_SYSCALL_BASE + 326)
466
+#define __NR_fstatat64 (__NR_SYSCALL_BASE + 327)
467
+#define __NR_unlinkat (__NR_SYSCALL_BASE + 328)
468
+#define __NR_renameat (__NR_SYSCALL_BASE + 329)
469
+#define __NR_linkat (__NR_SYSCALL_BASE + 330)
470
+#define __NR_symlinkat (__NR_SYSCALL_BASE + 331)
471
+#define __NR_readlinkat (__NR_SYSCALL_BASE + 332)
472
+#define __NR_fchmodat (__NR_SYSCALL_BASE + 333)
473
+#define __NR_faccessat (__NR_SYSCALL_BASE + 334)
474
+#define __NR_pselect6 (__NR_SYSCALL_BASE + 335)
475
+#define __NR_ppoll (__NR_SYSCALL_BASE + 336)
476
+#define __NR_unshare (__NR_SYSCALL_BASE + 337)
477
+#define __NR_set_robust_list (__NR_SYSCALL_BASE + 338)
478
+#define __NR_get_robust_list (__NR_SYSCALL_BASE + 339)
479
+#define __NR_splice (__NR_SYSCALL_BASE + 340)
480
+#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE + 341)
481
+#define __NR_tee (__NR_SYSCALL_BASE + 342)
482
+#define __NR_vmsplice (__NR_SYSCALL_BASE + 343)
483
+#define __NR_move_pages (__NR_SYSCALL_BASE + 344)
484
+#define __NR_getcpu (__NR_SYSCALL_BASE + 345)
485
+#define __NR_epoll_pwait (__NR_SYSCALL_BASE + 346)
486
+#define __NR_kexec_load (__NR_SYSCALL_BASE + 347)
487
+#define __NR_utimensat (__NR_SYSCALL_BASE + 348)
488
+#define __NR_signalfd (__NR_SYSCALL_BASE + 349)
489
+#define __NR_timerfd_create (__NR_SYSCALL_BASE + 350)
490
+#define __NR_eventfd (__NR_SYSCALL_BASE + 351)
491
+#define __NR_fallocate (__NR_SYSCALL_BASE + 352)
492
+#define __NR_timerfd_settime (__NR_SYSCALL_BASE + 353)
493
+#define __NR_timerfd_gettime (__NR_SYSCALL_BASE + 354)
494
+#define __NR_signalfd4 (__NR_SYSCALL_BASE + 355)
495
+#define __NR_eventfd2 (__NR_SYSCALL_BASE + 356)
496
+#define __NR_epoll_create1 (__NR_SYSCALL_BASE + 357)
497
+#define __NR_dup3 (__NR_SYSCALL_BASE + 358)
498
+#define __NR_pipe2 (__NR_SYSCALL_BASE + 359)
499
+#define __NR_inotify_init1 (__NR_SYSCALL_BASE + 360)
500
+#define __NR_preadv (__NR_SYSCALL_BASE + 361)
501
+#define __NR_pwritev (__NR_SYSCALL_BASE + 362)
502
+#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE + 363)
503
+#define __NR_perf_event_open (__NR_SYSCALL_BASE + 364)
504
+#define __NR_recvmmsg (__NR_SYSCALL_BASE + 365)
505
+#define __NR_accept4 (__NR_SYSCALL_BASE + 366)
506
+#define __NR_fanotify_init (__NR_SYSCALL_BASE + 367)
507
+#define __NR_fanotify_mark (__NR_SYSCALL_BASE + 368)
508
+#define __NR_prlimit64 (__NR_SYSCALL_BASE + 369)
509
+#define __NR_name_to_handle_at (__NR_SYSCALL_BASE + 370)
510
+#define __NR_open_by_handle_at (__NR_SYSCALL_BASE + 371)
511
+#define __NR_clock_adjtime (__NR_SYSCALL_BASE + 372)
512
+#define __NR_syncfs (__NR_SYSCALL_BASE + 373)
513
+#define __NR_sendmmsg (__NR_SYSCALL_BASE + 374)
514
+#define __NR_setns (__NR_SYSCALL_BASE + 375)
515
+#define __NR_process_vm_readv (__NR_SYSCALL_BASE + 376)
516
+#define __NR_process_vm_writev (__NR_SYSCALL_BASE + 377)
517
+#define __NR_kcmp (__NR_SYSCALL_BASE + 378)
518
+#define __NR_finit_module (__NR_SYSCALL_BASE + 379)
519
+#define __NR_sched_setattr (__NR_SYSCALL_BASE + 380)
520
+#define __NR_sched_getattr (__NR_SYSCALL_BASE + 381)
521
+#define __NR_renameat2 (__NR_SYSCALL_BASE + 382)
522
+#define __NR_seccomp (__NR_SYSCALL_BASE + 383)
523
+#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
524
+#define __NR_memfd_create (__NR_SYSCALL_BASE + 385)
525
+#define __NR_bpf (__NR_SYSCALL_BASE + 386)
526
+#define __NR_execveat (__NR_SYSCALL_BASE + 387)
527
+#define __NR_userfaultfd (__NR_SYSCALL_BASE + 388)
528
+#define __NR_membarrier (__NR_SYSCALL_BASE + 389)
529
+#define __NR_mlock2 (__NR_SYSCALL_BASE + 390)
530
+#define __NR_copy_file_range (__NR_SYSCALL_BASE + 391)
531
+#define __NR_preadv2 (__NR_SYSCALL_BASE + 392)
532
+#define __NR_pwritev2 (__NR_SYSCALL_BASE + 393)
533
+#define __NR_pkey_mprotect (__NR_SYSCALL_BASE + 394)
534
+#define __NR_pkey_alloc (__NR_SYSCALL_BASE + 395)
535
+#define __NR_pkey_free (__NR_SYSCALL_BASE + 396)
536
+
537
+#endif /* _ASM_ARM_UNISTD_COMMON_H */
538
diff --git a/linux-headers/asm-arm/unistd-eabi.h b/linux-headers/asm-arm/unistd-eabi.h
539
new file mode 100644
540
index XXXXXXX..XXXXXXX
541
--- /dev/null
542
+++ b/linux-headers/asm-arm/unistd-eabi.h
543
@@ -XXX,XX +XXX,XX @@
544
+#ifndef _ASM_ARM_UNISTD_EABI_H
545
+#define _ASM_ARM_UNISTD_EABI_H 1
546
+
547
+
548
+#endif /* _ASM_ARM_UNISTD_EABI_H */
549
diff --git a/linux-headers/asm-arm/unistd-oabi.h b/linux-headers/asm-arm/unistd-oabi.h
550
new file mode 100644
551
index XXXXXXX..XXXXXXX
552
--- /dev/null
553
+++ b/linux-headers/asm-arm/unistd-oabi.h
554
@@ -XXX,XX +XXX,XX @@
555
+#ifndef _ASM_ARM_UNISTD_OABI_H
556
+#define _ASM_ARM_UNISTD_OABI_H 1
557
+
558
+#define __NR_time (__NR_SYSCALL_BASE + 13)
559
+#define __NR_umount (__NR_SYSCALL_BASE + 22)
560
+#define __NR_stime (__NR_SYSCALL_BASE + 25)
561
+#define __NR_alarm (__NR_SYSCALL_BASE + 27)
562
+#define __NR_utime (__NR_SYSCALL_BASE + 30)
563
+#define __NR_getrlimit (__NR_SYSCALL_BASE + 76)
564
+#define __NR_select (__NR_SYSCALL_BASE + 82)
565
+#define __NR_readdir (__NR_SYSCALL_BASE + 89)
566
+#define __NR_mmap (__NR_SYSCALL_BASE + 90)
567
+#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
568
+#define __NR_syscall (__NR_SYSCALL_BASE + 113)
569
+#define __NR_ipc (__NR_SYSCALL_BASE + 117)
570
+
571
+#endif /* _ASM_ARM_UNISTD_OABI_H */
572
diff --git a/linux-headers/asm-arm/unistd.h b/linux-headers/asm-arm/unistd.h
573
index XXXXXXX..XXXXXXX 100644
574
--- a/linux-headers/asm-arm/unistd.h
575
+++ b/linux-headers/asm-arm/unistd.h
576
@@ -XXX,XX +XXX,XX @@
577
578
#if defined(__thumb__) || defined(__ARM_EABI__)
579
#define __NR_SYSCALL_BASE    0
580
+#include <asm/unistd-eabi.h>
581
#else
582
#define __NR_SYSCALL_BASE    __NR_OABI_SYSCALL_BASE
583
+#include <asm/unistd-oabi.h>
584
#endif
585
586
-/*
587
- * This file contains the system call numbers.
588
- */
589
-
590
-#define __NR_restart_syscall        (__NR_SYSCALL_BASE+ 0)
591
-#define __NR_exit            (__NR_SYSCALL_BASE+ 1)
592
-#define __NR_fork            (__NR_SYSCALL_BASE+ 2)
593
-#define __NR_read            (__NR_SYSCALL_BASE+ 3)
594
-#define __NR_write            (__NR_SYSCALL_BASE+ 4)
595
-#define __NR_open            (__NR_SYSCALL_BASE+ 5)
596
-#define __NR_close            (__NR_SYSCALL_BASE+ 6)
597
-                    /* 7 was sys_waitpid */
598
-#define __NR_creat            (__NR_SYSCALL_BASE+ 8)
599
-#define __NR_link            (__NR_SYSCALL_BASE+ 9)
600
-#define __NR_unlink            (__NR_SYSCALL_BASE+ 10)
601
-#define __NR_execve            (__NR_SYSCALL_BASE+ 11)
602
-#define __NR_chdir            (__NR_SYSCALL_BASE+ 12)
603
-#define __NR_time            (__NR_SYSCALL_BASE+ 13)
604
-#define __NR_mknod            (__NR_SYSCALL_BASE+ 14)
605
-#define __NR_chmod            (__NR_SYSCALL_BASE+ 15)
606
-#define __NR_lchown            (__NR_SYSCALL_BASE+ 16)
607
-                    /* 17 was sys_break */
608
-                    /* 18 was sys_stat */
609
-#define __NR_lseek            (__NR_SYSCALL_BASE+ 19)
610
-#define __NR_getpid            (__NR_SYSCALL_BASE+ 20)
611
-#define __NR_mount            (__NR_SYSCALL_BASE+ 21)
612
-#define __NR_umount            (__NR_SYSCALL_BASE+ 22)
613
-#define __NR_setuid            (__NR_SYSCALL_BASE+ 23)
614
-#define __NR_getuid            (__NR_SYSCALL_BASE+ 24)
615
-#define __NR_stime            (__NR_SYSCALL_BASE+ 25)
616
-#define __NR_ptrace            (__NR_SYSCALL_BASE+ 26)
617
-#define __NR_alarm            (__NR_SYSCALL_BASE+ 27)
618
-                    /* 28 was sys_fstat */
619
-#define __NR_pause            (__NR_SYSCALL_BASE+ 29)
620
-#define __NR_utime            (__NR_SYSCALL_BASE+ 30)
621
-                    /* 31 was sys_stty */
622
-                    /* 32 was sys_gtty */
623
-#define __NR_access            (__NR_SYSCALL_BASE+ 33)
624
-#define __NR_nice            (__NR_SYSCALL_BASE+ 34)
625
-                    /* 35 was sys_ftime */
626
-#define __NR_sync            (__NR_SYSCALL_BASE+ 36)
627
-#define __NR_kill            (__NR_SYSCALL_BASE+ 37)
628
-#define __NR_rename            (__NR_SYSCALL_BASE+ 38)
629
-#define __NR_mkdir            (__NR_SYSCALL_BASE+ 39)
630
-#define __NR_rmdir            (__NR_SYSCALL_BASE+ 40)
631
-#define __NR_dup            (__NR_SYSCALL_BASE+ 41)
632
-#define __NR_pipe            (__NR_SYSCALL_BASE+ 42)
633
-#define __NR_times            (__NR_SYSCALL_BASE+ 43)
634
-                    /* 44 was sys_prof */
635
-#define __NR_brk            (__NR_SYSCALL_BASE+ 45)
636
-#define __NR_setgid            (__NR_SYSCALL_BASE+ 46)
637
-#define __NR_getgid            (__NR_SYSCALL_BASE+ 47)
638
-                    /* 48 was sys_signal */
639
-#define __NR_geteuid            (__NR_SYSCALL_BASE+ 49)
640
-#define __NR_getegid            (__NR_SYSCALL_BASE+ 50)
641
-#define __NR_acct            (__NR_SYSCALL_BASE+ 51)
642
-#define __NR_umount2            (__NR_SYSCALL_BASE+ 52)
643
-                    /* 53 was sys_lock */
644
-#define __NR_ioctl            (__NR_SYSCALL_BASE+ 54)
645
-#define __NR_fcntl            (__NR_SYSCALL_BASE+ 55)
646
-                    /* 56 was sys_mpx */
647
-#define __NR_setpgid            (__NR_SYSCALL_BASE+ 57)
648
-                    /* 58 was sys_ulimit */
649
-                    /* 59 was sys_olduname */
650
-#define __NR_umask            (__NR_SYSCALL_BASE+ 60)
651
-#define __NR_chroot            (__NR_SYSCALL_BASE+ 61)
652
-#define __NR_ustat            (__NR_SYSCALL_BASE+ 62)
653
-#define __NR_dup2            (__NR_SYSCALL_BASE+ 63)
654
-#define __NR_getppid            (__NR_SYSCALL_BASE+ 64)
655
-#define __NR_getpgrp            (__NR_SYSCALL_BASE+ 65)
656
-#define __NR_setsid            (__NR_SYSCALL_BASE+ 66)
657
-#define __NR_sigaction            (__NR_SYSCALL_BASE+ 67)
658
-                    /* 68 was sys_sgetmask */
659
-                    /* 69 was sys_ssetmask */
660
-#define __NR_setreuid            (__NR_SYSCALL_BASE+ 70)
661
-#define __NR_setregid            (__NR_SYSCALL_BASE+ 71)
662
-#define __NR_sigsuspend            (__NR_SYSCALL_BASE+ 72)
663
-#define __NR_sigpending            (__NR_SYSCALL_BASE+ 73)
664
-#define __NR_sethostname        (__NR_SYSCALL_BASE+ 74)
665
-#define __NR_setrlimit            (__NR_SYSCALL_BASE+ 75)
666
-#define __NR_getrlimit            (__NR_SYSCALL_BASE+ 76)    /* Back compat 2GB limited rlimit */
667
-#define __NR_getrusage            (__NR_SYSCALL_BASE+ 77)
668
-#define __NR_gettimeofday        (__NR_SYSCALL_BASE+ 78)
669
-#define __NR_settimeofday        (__NR_SYSCALL_BASE+ 79)
670
-#define __NR_getgroups            (__NR_SYSCALL_BASE+ 80)
671
-#define __NR_setgroups            (__NR_SYSCALL_BASE+ 81)
672
-#define __NR_select            (__NR_SYSCALL_BASE+ 82)
673
-#define __NR_symlink            (__NR_SYSCALL_BASE+ 83)
674
-                    /* 84 was sys_lstat */
675
-#define __NR_readlink            (__NR_SYSCALL_BASE+ 85)
676
-#define __NR_uselib            (__NR_SYSCALL_BASE+ 86)
677
-#define __NR_swapon            (__NR_SYSCALL_BASE+ 87)
678
-#define __NR_reboot            (__NR_SYSCALL_BASE+ 88)
679
-#define __NR_readdir            (__NR_SYSCALL_BASE+ 89)
680
-#define __NR_mmap            (__NR_SYSCALL_BASE+ 90)
681
-#define __NR_munmap            (__NR_SYSCALL_BASE+ 91)
682
-#define __NR_truncate            (__NR_SYSCALL_BASE+ 92)
683
-#define __NR_ftruncate            (__NR_SYSCALL_BASE+ 93)
684
-#define __NR_fchmod            (__NR_SYSCALL_BASE+ 94)
685
-#define __NR_fchown            (__NR_SYSCALL_BASE+ 95)
686
-#define __NR_getpriority        (__NR_SYSCALL_BASE+ 96)
687
-#define __NR_setpriority        (__NR_SYSCALL_BASE+ 97)
688
-                    /* 98 was sys_profil */
689
-#define __NR_statfs            (__NR_SYSCALL_BASE+ 99)
690
-#define __NR_fstatfs            (__NR_SYSCALL_BASE+100)
691
-                    /* 101 was sys_ioperm */
692
-#define __NR_socketcall            (__NR_SYSCALL_BASE+102)
693
-#define __NR_syslog            (__NR_SYSCALL_BASE+103)
694
-#define __NR_setitimer            (__NR_SYSCALL_BASE+104)
695
-#define __NR_getitimer            (__NR_SYSCALL_BASE+105)
696
-#define __NR_stat            (__NR_SYSCALL_BASE+106)
697
-#define __NR_lstat            (__NR_SYSCALL_BASE+107)
698
-#define __NR_fstat            (__NR_SYSCALL_BASE+108)
699
-                    /* 109 was sys_uname */
700
-                    /* 110 was sys_iopl */
701
-#define __NR_vhangup            (__NR_SYSCALL_BASE+111)
702
-                    /* 112 was sys_idle */
703
-#define __NR_syscall            (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
704
-#define __NR_wait4            (__NR_SYSCALL_BASE+114)
705
-#define __NR_swapoff            (__NR_SYSCALL_BASE+115)
706
-#define __NR_sysinfo            (__NR_SYSCALL_BASE+116)
707
-#define __NR_ipc            (__NR_SYSCALL_BASE+117)
708
-#define __NR_fsync            (__NR_SYSCALL_BASE+118)
709
-#define __NR_sigreturn            (__NR_SYSCALL_BASE+119)
710
-#define __NR_clone            (__NR_SYSCALL_BASE+120)
711
-#define __NR_setdomainname        (__NR_SYSCALL_BASE+121)
712
-#define __NR_uname            (__NR_SYSCALL_BASE+122)
713
-                    /* 123 was sys_modify_ldt */
714
-#define __NR_adjtimex            (__NR_SYSCALL_BASE+124)
715
-#define __NR_mprotect            (__NR_SYSCALL_BASE+125)
716
-#define __NR_sigprocmask        (__NR_SYSCALL_BASE+126)
717
-                    /* 127 was sys_create_module */
718
-#define __NR_init_module        (__NR_SYSCALL_BASE+128)
719
-#define __NR_delete_module        (__NR_SYSCALL_BASE+129)
720
-                    /* 130 was sys_get_kernel_syms */
721
-#define __NR_quotactl            (__NR_SYSCALL_BASE+131)
722
-#define __NR_getpgid            (__NR_SYSCALL_BASE+132)
723
-#define __NR_fchdir            (__NR_SYSCALL_BASE+133)
724
-#define __NR_bdflush            (__NR_SYSCALL_BASE+134)
725
-#define __NR_sysfs            (__NR_SYSCALL_BASE+135)
726
-#define __NR_personality        (__NR_SYSCALL_BASE+136)
727
-                    /* 137 was sys_afs_syscall */
728
-#define __NR_setfsuid            (__NR_SYSCALL_BASE+138)
729
-#define __NR_setfsgid            (__NR_SYSCALL_BASE+139)
730
-#define __NR__llseek            (__NR_SYSCALL_BASE+140)
731
-#define __NR_getdents            (__NR_SYSCALL_BASE+141)
732
-#define __NR__newselect            (__NR_SYSCALL_BASE+142)
733
-#define __NR_flock            (__NR_SYSCALL_BASE+143)
734
-#define __NR_msync            (__NR_SYSCALL_BASE+144)
735
-#define __NR_readv            (__NR_SYSCALL_BASE+145)
736
-#define __NR_writev            (__NR_SYSCALL_BASE+146)
737
-#define __NR_getsid            (__NR_SYSCALL_BASE+147)
738
-#define __NR_fdatasync            (__NR_SYSCALL_BASE+148)
739
-#define __NR__sysctl            (__NR_SYSCALL_BASE+149)
740
-#define __NR_mlock            (__NR_SYSCALL_BASE+150)
741
-#define __NR_munlock            (__NR_SYSCALL_BASE+151)
742
-#define __NR_mlockall            (__NR_SYSCALL_BASE+152)
743
-#define __NR_munlockall            (__NR_SYSCALL_BASE+153)
744
-#define __NR_sched_setparam        (__NR_SYSCALL_BASE+154)
745
-#define __NR_sched_getparam        (__NR_SYSCALL_BASE+155)
746
-#define __NR_sched_setscheduler        (__NR_SYSCALL_BASE+156)
747
-#define __NR_sched_getscheduler        (__NR_SYSCALL_BASE+157)
748
-#define __NR_sched_yield        (__NR_SYSCALL_BASE+158)
749
-#define __NR_sched_get_priority_max    (__NR_SYSCALL_BASE+159)
750
-#define __NR_sched_get_priority_min    (__NR_SYSCALL_BASE+160)
751
-#define __NR_sched_rr_get_interval    (__NR_SYSCALL_BASE+161)
752
-#define __NR_nanosleep            (__NR_SYSCALL_BASE+162)
753
-#define __NR_mremap            (__NR_SYSCALL_BASE+163)
754
-#define __NR_setresuid            (__NR_SYSCALL_BASE+164)
755
-#define __NR_getresuid            (__NR_SYSCALL_BASE+165)
756
-                    /* 166 was sys_vm86 */
757
-                    /* 167 was sys_query_module */
758
-#define __NR_poll            (__NR_SYSCALL_BASE+168)
759
-#define __NR_nfsservctl            (__NR_SYSCALL_BASE+169)
760
-#define __NR_setresgid            (__NR_SYSCALL_BASE+170)
761
-#define __NR_getresgid            (__NR_SYSCALL_BASE+171)
762
-#define __NR_prctl            (__NR_SYSCALL_BASE+172)
763
-#define __NR_rt_sigreturn        (__NR_SYSCALL_BASE+173)
764
-#define __NR_rt_sigaction        (__NR_SYSCALL_BASE+174)
765
-#define __NR_rt_sigprocmask        (__NR_SYSCALL_BASE+175)
766
-#define __NR_rt_sigpending        (__NR_SYSCALL_BASE+176)
767
-#define __NR_rt_sigtimedwait        (__NR_SYSCALL_BASE+177)
768
-#define __NR_rt_sigqueueinfo        (__NR_SYSCALL_BASE+178)
769
-#define __NR_rt_sigsuspend        (__NR_SYSCALL_BASE+179)
770
-#define __NR_pread64            (__NR_SYSCALL_BASE+180)
771
-#define __NR_pwrite64            (__NR_SYSCALL_BASE+181)
772
-#define __NR_chown            (__NR_SYSCALL_BASE+182)
773
-#define __NR_getcwd            (__NR_SYSCALL_BASE+183)
774
-#define __NR_capget            (__NR_SYSCALL_BASE+184)
775
-#define __NR_capset            (__NR_SYSCALL_BASE+185)
776
-#define __NR_sigaltstack        (__NR_SYSCALL_BASE+186)
777
-#define __NR_sendfile            (__NR_SYSCALL_BASE+187)
778
-                    /* 188 reserved */
779
-                    /* 189 reserved */
780
-#define __NR_vfork            (__NR_SYSCALL_BASE+190)
781
-#define __NR_ugetrlimit            (__NR_SYSCALL_BASE+191)    /* SuS compliant getrlimit */
782
-#define __NR_mmap2            (__NR_SYSCALL_BASE+192)
783
-#define __NR_truncate64            (__NR_SYSCALL_BASE+193)
784
-#define __NR_ftruncate64        (__NR_SYSCALL_BASE+194)
785
-#define __NR_stat64            (__NR_SYSCALL_BASE+195)
786
-#define __NR_lstat64            (__NR_SYSCALL_BASE+196)
787
-#define __NR_fstat64            (__NR_SYSCALL_BASE+197)
788
-#define __NR_lchown32            (__NR_SYSCALL_BASE+198)
789
-#define __NR_getuid32            (__NR_SYSCALL_BASE+199)
790
-#define __NR_getgid32            (__NR_SYSCALL_BASE+200)
791
-#define __NR_geteuid32            (__NR_SYSCALL_BASE+201)
792
-#define __NR_getegid32            (__NR_SYSCALL_BASE+202)
793
-#define __NR_setreuid32            (__NR_SYSCALL_BASE+203)
794
-#define __NR_setregid32            (__NR_SYSCALL_BASE+204)
795
-#define __NR_getgroups32        (__NR_SYSCALL_BASE+205)
796
-#define __NR_setgroups32        (__NR_SYSCALL_BASE+206)
797
-#define __NR_fchown32            (__NR_SYSCALL_BASE+207)
798
-#define __NR_setresuid32        (__NR_SYSCALL_BASE+208)
799
-#define __NR_getresuid32        (__NR_SYSCALL_BASE+209)
800
-#define __NR_setresgid32        (__NR_SYSCALL_BASE+210)
801
-#define __NR_getresgid32        (__NR_SYSCALL_BASE+211)
802
-#define __NR_chown32            (__NR_SYSCALL_BASE+212)
803
-#define __NR_setuid32            (__NR_SYSCALL_BASE+213)
804
-#define __NR_setgid32            (__NR_SYSCALL_BASE+214)
805
-#define __NR_setfsuid32            (__NR_SYSCALL_BASE+215)
806
-#define __NR_setfsgid32            (__NR_SYSCALL_BASE+216)
807
-#define __NR_getdents64            (__NR_SYSCALL_BASE+217)
808
-#define __NR_pivot_root            (__NR_SYSCALL_BASE+218)
809
-#define __NR_mincore            (__NR_SYSCALL_BASE+219)
810
-#define __NR_madvise            (__NR_SYSCALL_BASE+220)
811
-#define __NR_fcntl64            (__NR_SYSCALL_BASE+221)
812
-                    /* 222 for tux */
813
-                    /* 223 is unused */
814
-#define __NR_gettid            (__NR_SYSCALL_BASE+224)
815
-#define __NR_readahead            (__NR_SYSCALL_BASE+225)
816
-#define __NR_setxattr            (__NR_SYSCALL_BASE+226)
817
-#define __NR_lsetxattr            (__NR_SYSCALL_BASE+227)
818
-#define __NR_fsetxattr            (__NR_SYSCALL_BASE+228)
819
-#define __NR_getxattr            (__NR_SYSCALL_BASE+229)
820
-#define __NR_lgetxattr            (__NR_SYSCALL_BASE+230)
821
-#define __NR_fgetxattr            (__NR_SYSCALL_BASE+231)
822
-#define __NR_listxattr            (__NR_SYSCALL_BASE+232)
823
-#define __NR_llistxattr            (__NR_SYSCALL_BASE+233)
824
-#define __NR_flistxattr            (__NR_SYSCALL_BASE+234)
825
-#define __NR_removexattr        (__NR_SYSCALL_BASE+235)
826
-#define __NR_lremovexattr        (__NR_SYSCALL_BASE+236)
827
-#define __NR_fremovexattr        (__NR_SYSCALL_BASE+237)
828
-#define __NR_tkill            (__NR_SYSCALL_BASE+238)
829
-#define __NR_sendfile64            (__NR_SYSCALL_BASE+239)
830
-#define __NR_futex            (__NR_SYSCALL_BASE+240)
831
-#define __NR_sched_setaffinity        (__NR_SYSCALL_BASE+241)
832
-#define __NR_sched_getaffinity        (__NR_SYSCALL_BASE+242)
833
-#define __NR_io_setup            (__NR_SYSCALL_BASE+243)
834
-#define __NR_io_destroy            (__NR_SYSCALL_BASE+244)
835
-#define __NR_io_getevents        (__NR_SYSCALL_BASE+245)
836
-#define __NR_io_submit            (__NR_SYSCALL_BASE+246)
837
-#define __NR_io_cancel            (__NR_SYSCALL_BASE+247)
838
-#define __NR_exit_group            (__NR_SYSCALL_BASE+248)
839
-#define __NR_lookup_dcookie        (__NR_SYSCALL_BASE+249)
840
-#define __NR_epoll_create        (__NR_SYSCALL_BASE+250)
841
-#define __NR_epoll_ctl            (__NR_SYSCALL_BASE+251)
842
-#define __NR_epoll_wait            (__NR_SYSCALL_BASE+252)
843
-#define __NR_remap_file_pages        (__NR_SYSCALL_BASE+253)
844
-                    /* 254 for set_thread_area */
845
-                    /* 255 for get_thread_area */
846
-#define __NR_set_tid_address        (__NR_SYSCALL_BASE+256)
847
-#define __NR_timer_create        (__NR_SYSCALL_BASE+257)
848
-#define __NR_timer_settime        (__NR_SYSCALL_BASE+258)
849
-#define __NR_timer_gettime        (__NR_SYSCALL_BASE+259)
850
-#define __NR_timer_getoverrun        (__NR_SYSCALL_BASE+260)
851
-#define __NR_timer_delete        (__NR_SYSCALL_BASE+261)
852
-#define __NR_clock_settime        (__NR_SYSCALL_BASE+262)
853
-#define __NR_clock_gettime        (__NR_SYSCALL_BASE+263)
854
-#define __NR_clock_getres        (__NR_SYSCALL_BASE+264)
855
-#define __NR_clock_nanosleep        (__NR_SYSCALL_BASE+265)
856
-#define __NR_statfs64            (__NR_SYSCALL_BASE+266)
857
-#define __NR_fstatfs64            (__NR_SYSCALL_BASE+267)
858
-#define __NR_tgkill            (__NR_SYSCALL_BASE+268)
859
-#define __NR_utimes            (__NR_SYSCALL_BASE+269)
860
-#define __NR_arm_fadvise64_64        (__NR_SYSCALL_BASE+270)
861
-#define __NR_pciconfig_iobase        (__NR_SYSCALL_BASE+271)
862
-#define __NR_pciconfig_read        (__NR_SYSCALL_BASE+272)
863
-#define __NR_pciconfig_write        (__NR_SYSCALL_BASE+273)
864
-#define __NR_mq_open            (__NR_SYSCALL_BASE+274)
865
-#define __NR_mq_unlink            (__NR_SYSCALL_BASE+275)
866
-#define __NR_mq_timedsend        (__NR_SYSCALL_BASE+276)
867
-#define __NR_mq_timedreceive        (__NR_SYSCALL_BASE+277)
868
-#define __NR_mq_notify            (__NR_SYSCALL_BASE+278)
869
-#define __NR_mq_getsetattr        (__NR_SYSCALL_BASE+279)
870
-#define __NR_waitid            (__NR_SYSCALL_BASE+280)
871
-#define __NR_socket            (__NR_SYSCALL_BASE+281)
872
-#define __NR_bind            (__NR_SYSCALL_BASE+282)
873
-#define __NR_connect            (__NR_SYSCALL_BASE+283)
874
-#define __NR_listen            (__NR_SYSCALL_BASE+284)
875
-#define __NR_accept            (__NR_SYSCALL_BASE+285)
876
-#define __NR_getsockname        (__NR_SYSCALL_BASE+286)
877
-#define __NR_getpeername        (__NR_SYSCALL_BASE+287)
878
-#define __NR_socketpair            (__NR_SYSCALL_BASE+288)
879
-#define __NR_send            (__NR_SYSCALL_BASE+289)
880
-#define __NR_sendto            (__NR_SYSCALL_BASE+290)
881
-#define __NR_recv            (__NR_SYSCALL_BASE+291)
882
-#define __NR_recvfrom            (__NR_SYSCALL_BASE+292)
883
-#define __NR_shutdown            (__NR_SYSCALL_BASE+293)
884
-#define __NR_setsockopt            (__NR_SYSCALL_BASE+294)
885
-#define __NR_getsockopt            (__NR_SYSCALL_BASE+295)
886
-#define __NR_sendmsg            (__NR_SYSCALL_BASE+296)
887
-#define __NR_recvmsg            (__NR_SYSCALL_BASE+297)
888
-#define __NR_semop            (__NR_SYSCALL_BASE+298)
889
-#define __NR_semget            (__NR_SYSCALL_BASE+299)
890
-#define __NR_semctl            (__NR_SYSCALL_BASE+300)
891
-#define __NR_msgsnd            (__NR_SYSCALL_BASE+301)
892
-#define __NR_msgrcv            (__NR_SYSCALL_BASE+302)
893
-#define __NR_msgget            (__NR_SYSCALL_BASE+303)
894
-#define __NR_msgctl            (__NR_SYSCALL_BASE+304)
895
-#define __NR_shmat            (__NR_SYSCALL_BASE+305)
896
-#define __NR_shmdt            (__NR_SYSCALL_BASE+306)
897
-#define __NR_shmget            (__NR_SYSCALL_BASE+307)
898
-#define __NR_shmctl            (__NR_SYSCALL_BASE+308)
899
-#define __NR_add_key            (__NR_SYSCALL_BASE+309)
900
-#define __NR_request_key        (__NR_SYSCALL_BASE+310)
901
-#define __NR_keyctl            (__NR_SYSCALL_BASE+311)
902
-#define __NR_semtimedop            (__NR_SYSCALL_BASE+312)
903
-#define __NR_vserver            (__NR_SYSCALL_BASE+313)
904
-#define __NR_ioprio_set            (__NR_SYSCALL_BASE+314)
905
-#define __NR_ioprio_get            (__NR_SYSCALL_BASE+315)
906
-#define __NR_inotify_init        (__NR_SYSCALL_BASE+316)
907
-#define __NR_inotify_add_watch        (__NR_SYSCALL_BASE+317)
908
-#define __NR_inotify_rm_watch        (__NR_SYSCALL_BASE+318)
909
-#define __NR_mbind            (__NR_SYSCALL_BASE+319)
910
-#define __NR_get_mempolicy        (__NR_SYSCALL_BASE+320)
911
-#define __NR_set_mempolicy        (__NR_SYSCALL_BASE+321)
912
-#define __NR_openat            (__NR_SYSCALL_BASE+322)
913
-#define __NR_mkdirat            (__NR_SYSCALL_BASE+323)
914
-#define __NR_mknodat            (__NR_SYSCALL_BASE+324)
915
-#define __NR_fchownat            (__NR_SYSCALL_BASE+325)
916
-#define __NR_futimesat            (__NR_SYSCALL_BASE+326)
917
-#define __NR_fstatat64            (__NR_SYSCALL_BASE+327)
918
-#define __NR_unlinkat            (__NR_SYSCALL_BASE+328)
919
-#define __NR_renameat            (__NR_SYSCALL_BASE+329)
920
-#define __NR_linkat            (__NR_SYSCALL_BASE+330)
921
-#define __NR_symlinkat            (__NR_SYSCALL_BASE+331)
922
-#define __NR_readlinkat            (__NR_SYSCALL_BASE+332)
923
-#define __NR_fchmodat            (__NR_SYSCALL_BASE+333)
924
-#define __NR_faccessat            (__NR_SYSCALL_BASE+334)
925
-#define __NR_pselect6            (__NR_SYSCALL_BASE+335)
926
-#define __NR_ppoll            (__NR_SYSCALL_BASE+336)
927
-#define __NR_unshare            (__NR_SYSCALL_BASE+337)
928
-#define __NR_set_robust_list        (__NR_SYSCALL_BASE+338)
929
-#define __NR_get_robust_list        (__NR_SYSCALL_BASE+339)
930
-#define __NR_splice            (__NR_SYSCALL_BASE+340)
931
-#define __NR_arm_sync_file_range    (__NR_SYSCALL_BASE+341)
932
+#include <asm/unistd-common.h>
933
#define __NR_sync_file_range2        __NR_arm_sync_file_range
934
-#define __NR_tee            (__NR_SYSCALL_BASE+342)
935
-#define __NR_vmsplice            (__NR_SYSCALL_BASE+343)
936
-#define __NR_move_pages            (__NR_SYSCALL_BASE+344)
937
-#define __NR_getcpu            (__NR_SYSCALL_BASE+345)
938
-#define __NR_epoll_pwait        (__NR_SYSCALL_BASE+346)
939
-#define __NR_kexec_load            (__NR_SYSCALL_BASE+347)
940
-#define __NR_utimensat            (__NR_SYSCALL_BASE+348)
941
-#define __NR_signalfd            (__NR_SYSCALL_BASE+349)
942
-#define __NR_timerfd_create        (__NR_SYSCALL_BASE+350)
943
-#define __NR_eventfd            (__NR_SYSCALL_BASE+351)
944
-#define __NR_fallocate            (__NR_SYSCALL_BASE+352)
945
-#define __NR_timerfd_settime        (__NR_SYSCALL_BASE+353)
946
-#define __NR_timerfd_gettime        (__NR_SYSCALL_BASE+354)
947
-#define __NR_signalfd4            (__NR_SYSCALL_BASE+355)
948
-#define __NR_eventfd2            (__NR_SYSCALL_BASE+356)
949
-#define __NR_epoll_create1        (__NR_SYSCALL_BASE+357)
950
-#define __NR_dup3            (__NR_SYSCALL_BASE+358)
951
-#define __NR_pipe2            (__NR_SYSCALL_BASE+359)
952
-#define __NR_inotify_init1        (__NR_SYSCALL_BASE+360)
953
-#define __NR_preadv            (__NR_SYSCALL_BASE+361)
954
-#define __NR_pwritev            (__NR_SYSCALL_BASE+362)
955
-#define __NR_rt_tgsigqueueinfo        (__NR_SYSCALL_BASE+363)
956
-#define __NR_perf_event_open        (__NR_SYSCALL_BASE+364)
957
-#define __NR_recvmmsg            (__NR_SYSCALL_BASE+365)
958
-#define __NR_accept4            (__NR_SYSCALL_BASE+366)
959
-#define __NR_fanotify_init        (__NR_SYSCALL_BASE+367)
960
-#define __NR_fanotify_mark        (__NR_SYSCALL_BASE+368)
961
-#define __NR_prlimit64            (__NR_SYSCALL_BASE+369)
962
-#define __NR_name_to_handle_at        (__NR_SYSCALL_BASE+370)
963
-#define __NR_open_by_handle_at        (__NR_SYSCALL_BASE+371)
964
-#define __NR_clock_adjtime        (__NR_SYSCALL_BASE+372)
965
-#define __NR_syncfs            (__NR_SYSCALL_BASE+373)
966
-#define __NR_sendmmsg            (__NR_SYSCALL_BASE+374)
967
-#define __NR_setns            (__NR_SYSCALL_BASE+375)
968
-#define __NR_process_vm_readv        (__NR_SYSCALL_BASE+376)
969
-#define __NR_process_vm_writev        (__NR_SYSCALL_BASE+377)
970
-#define __NR_kcmp            (__NR_SYSCALL_BASE+378)
971
-#define __NR_finit_module        (__NR_SYSCALL_BASE+379)
972
-#define __NR_sched_setattr        (__NR_SYSCALL_BASE+380)
973
-#define __NR_sched_getattr        (__NR_SYSCALL_BASE+381)
974
-#define __NR_renameat2            (__NR_SYSCALL_BASE+382)
975
-#define __NR_seccomp            (__NR_SYSCALL_BASE+383)
976
-#define __NR_getrandom            (__NR_SYSCALL_BASE+384)
977
-#define __NR_memfd_create        (__NR_SYSCALL_BASE+385)
978
-#define __NR_bpf            (__NR_SYSCALL_BASE+386)
979
-#define __NR_execveat            (__NR_SYSCALL_BASE+387)
980
-#define __NR_userfaultfd        (__NR_SYSCALL_BASE+388)
981
-#define __NR_membarrier            (__NR_SYSCALL_BASE+389)
982
-#define __NR_mlock2            (__NR_SYSCALL_BASE+390)
983
-#define __NR_copy_file_range        (__NR_SYSCALL_BASE+391)
984
-#define __NR_preadv2            (__NR_SYSCALL_BASE+392)
985
-#define __NR_pwritev2            (__NR_SYSCALL_BASE+393)
986
987
/*
988
* The following SWIs are ARM private.
989
@@ -XXX,XX +XXX,XX @@
990
#define __ARM_NR_usr32            (__ARM_NR_BASE+4)
991
#define __ARM_NR_set_tls        (__ARM_NR_BASE+5)
992
993
-/*
994
- * The following syscalls are obsolete and no longer available for EABI.
995
- */
996
-#if defined(__ARM_EABI__)
997
-#undef __NR_time
998
-#undef __NR_umount
999
-#undef __NR_stime
1000
-#undef __NR_alarm
1001
-#undef __NR_utime
1002
-#undef __NR_getrlimit
1003
-#undef __NR_select
1004
-#undef __NR_readdir
1005
-#undef __NR_mmap
1006
-#undef __NR_socketcall
1007
-#undef __NR_syscall
1008
-#undef __NR_ipc
1009
-#endif
1010
-
1011
#endif /* __ASM_ARM_UNISTD_H */
1012
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
1013
index XXXXXXX..XXXXXXX 100644
1014
--- a/linux-headers/asm-arm64/kvm.h
1015
+++ b/linux-headers/asm-arm64/kvm.h
1016
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
1017
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
1018
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
1019
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
1020
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
1021
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
1022
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
1023
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
1024
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
1025
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
1026
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
1027
#define KVM_DEV_ARM_VGIC_GRP_CTRL    4
1028
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
1029
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
1030
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
1031
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
1032
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
1033
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
1034
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK    0x3ff
1035
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
1036
+
1037
#define KVM_DEV_ARM_VGIC_CTRL_INIT    0
1038
1039
/* Device Control API on vcpu fd */
1040
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
1041
index XXXXXXX..XXXXXXX 100644
1042
--- a/linux-headers/asm-powerpc/kvm.h
1043
+++ b/linux-headers/asm-powerpc/kvm.h
1044
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1045
    __u16    n_invalid;
1046
};
121
};
1047
122
1048
+/* For KVM_PPC_CONFIGURE_V3_MMU */
123
+static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
1049
+struct kvm_ppc_mmuv3_cfg {
124
+ 0xFF060000, 0xFF070000,
1050
+    __u64    flags;
1051
+    __u64    process_table;    /* second doubleword of partition table entry */
1052
+};
125
+};
1053
+
126
+
1054
+/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
127
+static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
1055
+#define KVM_PPC_MMUV3_RADIX    1    /* 1 = radix mode, 0 = HPT */
128
+ 23, 24,
1056
+#define KVM_PPC_MMUV3_GTSE    2    /* global translation shootdown enb. */
1057
+
1058
+/* For KVM_PPC_GET_RMMU_INFO */
1059
+struct kvm_ppc_rmmu_info {
1060
+    struct kvm_ppc_radix_geom {
1061
+        __u8    page_shift;
1062
+        __u8    level_bits[4];
1063
+        __u8    pad[3];
1064
+    }    geometries[8];
1065
+    __u32    ap_encodings[8];
1066
+};
129
+};
1067
+
130
+
1068
/* Per-vcpu XICS interrupt controller state */
131
static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
1069
#define KVM_REG_PPC_ICP_STATE    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
132
0xFF160000, 0xFF170000,
1070
133
};
1071
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
134
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
1072
#define KVM_REG_PPC_SPRG9    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
135
TYPE_CADENCE_UART);
1073
#define KVM_REG_PPC_DBSR    (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
136
}
1074
137
1075
+/* POWER9 registers */
138
+ for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
1076
+#define KVM_REG_PPC_TIDR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
139
+ object_initialize_child(obj, "can[*]", &s->can[i],
1077
+#define KVM_REG_PPC_PSSCR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
140
+ TYPE_XLNX_ZYNQMP_CAN);
141
+ }
1078
+
142
+
1079
/* Transactional Memory checkpointed state:
143
object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
1080
* This is all GPRs, all VSX regs and a subset of SPRs
144
1081
*/
145
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
1082
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
146
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
1083
#define KVM_REG_PPC_TM_VSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
147
gic_spi[uart_intr[i]]);
1084
#define KVM_REG_PPC_TM_DSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
148
}
1085
#define KVM_REG_PPC_TM_TAR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
149
1086
+#define KVM_REG_PPC_TM_XER    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
150
+ for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
1087
151
+ object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
1088
/* PPC64 eXternal Interrupt Controller Specification */
152
+ XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
1089
#define KVM_DEV_XICS_GRP_SOURCES    1    /* 64-bit source attributes */
1090
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1091
#define KVM_XICS_LEVEL_SENSITIVE    (1ULL << 40)
1092
#define KVM_XICS_MASKED        (1ULL << 41)
1093
#define KVM_XICS_PENDING        (1ULL << 42)
1094
+#define KVM_XICS_PRESENTED        (1ULL << 43)
1095
+#define KVM_XICS_QUEUED        (1ULL << 44)
1096
1097
#endif /* __LINUX_KVM_POWERPC_H */
1098
diff --git a/linux-headers/asm-powerpc/unistd.h b/linux-headers/asm-powerpc/unistd.h
1099
index XXXXXXX..XXXXXXX 100644
1100
--- a/linux-headers/asm-powerpc/unistd.h
1101
+++ b/linux-headers/asm-powerpc/unistd.h
1102
@@ -XXX,XX +XXX,XX @@
1103
#define __NR_copy_file_range    379
1104
#define __NR_preadv2        380
1105
#define __NR_pwritev2        381
1106
+#define __NR_kexec_file_load    382
1107
1108
#endif /* _ASM_POWERPC_UNISTD_H_ */
1109
diff --git a/linux-headers/asm-x86/kvm_para.h b/linux-headers/asm-x86/kvm_para.h
1110
index XXXXXXX..XXXXXXX 100644
1111
--- a/linux-headers/asm-x86/kvm_para.h
1112
+++ b/linux-headers/asm-x86/kvm_para.h
1113
@@ -XXX,XX +XXX,XX @@ struct kvm_steal_time {
1114
    __u64 steal;
1115
    __u32 version;
1116
    __u32 flags;
1117
-    __u32 pad[12];
1118
+    __u8 preempted;
1119
+    __u8 u8_pad[3];
1120
+    __u32 pad[11];
1121
+};
1122
+
153
+
1123
+#define KVM_CLOCK_PAIRING_WALLCLOCK 0
154
+ object_property_set_link(OBJECT(&s->can[i]), "canbus",
1124
+struct kvm_clock_pairing {
155
+ OBJECT(s->canbus[i]), &error_fatal);
1125
+    __s64 sec;
156
+
1126
+    __s64 nsec;
157
+ sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
1127
+    __u64 tsc;
158
+ if (err) {
1128
+    __u32 flags;
159
+ error_propagate(errp, err);
1129
+    __u32 pad[9];
160
+ return;
161
+ }
162
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
163
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
164
+ gic_spi[can_intr[i]]);
165
+ }
166
+
167
object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
168
&error_abort);
169
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
170
@@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = {
171
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
172
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
173
MemoryRegion *),
174
+ DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
175
+ CanBusState *),
176
+ DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
177
+ CanBusState *),
178
DEFINE_PROP_END_OF_LIST()
1130
};
179
};
1131
180
1132
#define KVM_STEAL_ALIGNMENT_BITS 5
1133
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/linux-headers/linux/kvm.h
1136
+++ b/linux-headers/linux/kvm.h
1137
@@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit {
1138
struct kvm_run {
1139
    /* in */
1140
    __u8 request_interrupt_window;
1141
-    __u8 padding1[7];
1142
+    __u8 immediate_exit;
1143
+    __u8 padding1[6];
1144
1145
    /* out */
1146
    __u32 exit_reason;
1147
@@ -XXX,XX +XXX,XX @@ struct kvm_enable_cap {
1148
};
1149
1150
/* for KVM_PPC_GET_PVINFO */
1151
+
1152
+#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1153
+
1154
struct kvm_ppc_pvinfo {
1155
    /* out */
1156
    __u32 flags;
1157
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1158
    struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
1159
};
1160
1161
-#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1162
+/* for KVM_PPC_RESIZE_HPT_{PREPARE,COMMIT} */
1163
+struct kvm_ppc_resize_hpt {
1164
+    __u64 flags;
1165
+    __u32 shift;
1166
+    __u32 pad;
1167
+};
1168
1169
#define KVMIO 0xAE
1170
1171
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1172
#define KVM_CAP_S390_USER_INSTR0 130
1173
#define KVM_CAP_MSI_DEVID 131
1174
#define KVM_CAP_PPC_HTM 132
1175
+#define KVM_CAP_SPAPR_RESIZE_HPT 133
1176
+#define KVM_CAP_PPC_MMU_RADIX 134
1177
+#define KVM_CAP_PPC_MMU_HASH_V3 135
1178
+#define KVM_CAP_IMMEDIATE_EXIT 136
1179
1180
#ifdef KVM_CAP_IRQ_ROUTING
1181
1182
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
1183
#define KVM_ARM_SET_DEVICE_ADDR     _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
1184
/* Available with KVM_CAP_PPC_RTAS */
1185
#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
1186
+/* Available with KVM_CAP_SPAPR_RESIZE_HPT */
1187
+#define KVM_PPC_RESIZE_HPT_PREPARE _IOR(KVMIO, 0xad, struct kvm_ppc_resize_hpt)
1188
+#define KVM_PPC_RESIZE_HPT_COMMIT _IOR(KVMIO, 0xae, struct kvm_ppc_resize_hpt)
1189
+/* Available with KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3 */
1190
+#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
1191
+/* Available with KVM_CAP_PPC_RADIX_MMU */
1192
+#define KVM_PPC_GET_RMMU_INFO     _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
1193
1194
/* ioctl for vm fd */
1195
#define KVM_CREATE_DEVICE     _IOWR(KVMIO, 0xe0, struct kvm_create_device)
1196
diff --git a/linux-headers/linux/kvm_para.h b/linux-headers/linux/kvm_para.h
1197
index XXXXXXX..XXXXXXX 100644
1198
--- a/linux-headers/linux/kvm_para.h
1199
+++ b/linux-headers/linux/kvm_para.h
1200
@@ -XXX,XX +XXX,XX @@
1201
#define KVM_EFAULT        EFAULT
1202
#define KVM_E2BIG        E2BIG
1203
#define KVM_EPERM        EPERM
1204
+#define KVM_EOPNOTSUPP        95
1205
1206
#define KVM_HC_VAPIC_POLL_IRQ        1
1207
#define KVM_HC_MMU_OP            2
1208
@@ -XXX,XX +XXX,XX @@
1209
#define KVM_HC_MIPS_GET_CLOCK_FREQ    6
1210
#define KVM_HC_MIPS_EXIT_VM        7
1211
#define KVM_HC_MIPS_CONSOLE_OUTPUT    8
1212
+#define KVM_HC_CLOCK_PAIRING        9
1213
1214
/*
1215
* hypercalls use architecture specific
1216
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
1217
index XXXXXXX..XXXXXXX 100644
1218
--- a/linux-headers/linux/userfaultfd.h
1219
+++ b/linux-headers/linux/userfaultfd.h
1220
@@ -XXX,XX +XXX,XX @@
1221
1222
#include <linux/types.h>
1223
1224
-#define UFFD_API ((__u64)0xAA)
1225
/*
1226
- * After implementing the respective features it will become:
1227
- * #define UFFD_API_FEATURES (UFFD_FEATURE_PAGEFAULT_FLAG_WP | \
1228
- *             UFFD_FEATURE_EVENT_FORK)
1229
+ * If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and
1230
+ * UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In
1231
+ * userfaultfd.h we assumed the kernel was reading (instead _IOC_READ
1232
+ * means the userland is reading).
1233
*/
1234
-#define UFFD_API_FEATURES (0)
1235
+#define UFFD_API ((__u64)0xAA)
1236
+#define UFFD_API_FEATURES (UFFD_FEATURE_EVENT_FORK |        \
1237
+             UFFD_FEATURE_EVENT_REMAP |        \
1238
+             UFFD_FEATURE_EVENT_MADVDONTNEED |    \
1239
+             UFFD_FEATURE_MISSING_HUGETLBFS |    \
1240
+             UFFD_FEATURE_MISSING_SHMEM)
1241
#define UFFD_API_IOCTLS                \
1242
    ((__u64)1 << _UFFDIO_REGISTER |        \
1243
     (__u64)1 << _UFFDIO_UNREGISTER |    \
1244
@@ -XXX,XX +XXX,XX @@
1245
    ((__u64)1 << _UFFDIO_WAKE |        \
1246
     (__u64)1 << _UFFDIO_COPY |        \
1247
     (__u64)1 << _UFFDIO_ZEROPAGE)
1248
+#define UFFD_API_RANGE_IOCTLS_BASIC        \
1249
+    ((__u64)1 << _UFFDIO_WAKE |        \
1250
+     (__u64)1 << _UFFDIO_COPY)
1251
1252
/*
1253
* Valid ioctl command number range with this API is from 0x00 to
1254
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1255
        } pagefault;
1256
1257
        struct {
1258
+            __u32    ufd;
1259
+        } fork;
1260
+
1261
+        struct {
1262
+            __u64    from;
1263
+            __u64    to;
1264
+            __u64    len;
1265
+        } remap;
1266
+
1267
+        struct {
1268
+            __u64    start;
1269
+            __u64    end;
1270
+        } madv_dn;
1271
+
1272
+        struct {
1273
            /* unused reserved fields */
1274
            __u64    reserved1;
1275
            __u64    reserved2;
1276
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1277
* Start at 0x12 and not at 0 to be more strict against bugs.
1278
*/
1279
#define UFFD_EVENT_PAGEFAULT    0x12
1280
-#if 0 /* not available yet */
1281
#define UFFD_EVENT_FORK        0x13
1282
-#endif
1283
+#define UFFD_EVENT_REMAP    0x14
1284
+#define UFFD_EVENT_MADVDONTNEED    0x15
1285
1286
/* flags for UFFD_EVENT_PAGEFAULT */
1287
#define UFFD_PAGEFAULT_FLAG_WRITE    (1<<0)    /* If this was a write fault */
1288
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
1289
     * Note: UFFD_EVENT_PAGEFAULT and UFFD_PAGEFAULT_FLAG_WRITE
1290
     * are to be considered implicitly always enabled in all kernels as
1291
     * long as the uffdio_api.api requested matches UFFD_API.
1292
+     *
1293
+     * UFFD_FEATURE_MISSING_HUGETLBFS means an UFFDIO_REGISTER
1294
+     * with UFFDIO_REGISTER_MODE_MISSING mode will succeed on
1295
+     * hugetlbfs virtual memory ranges. Adding or not adding
1296
+     * UFFD_FEATURE_MISSING_HUGETLBFS to uffdio_api.features has
1297
+     * no real functional effect after UFFDIO_API returns, but
1298
+     * it's only useful for an initial feature set probe at
1299
+     * UFFDIO_API time. There are two ways to use it:
1300
+     *
1301
+     * 1) by adding UFFD_FEATURE_MISSING_HUGETLBFS to the
1302
+     * uffdio_api.features before calling UFFDIO_API, an error
1303
+     * will be returned by UFFDIO_API on a kernel without
1304
+     * hugetlbfs missing support
1305
+     *
1306
+     * 2) the UFFD_FEATURE_MISSING_HUGETLBFS can not be added in
1307
+     * uffdio_api.features and instead it will be set by the
1308
+     * kernel in the uffdio_api.features if the kernel supports
1309
+     * it, so userland can later check if the feature flag is
1310
+     * present in uffdio_api.features after UFFDIO_API
1311
+     * succeeded.
1312
+     *
1313
+     * UFFD_FEATURE_MISSING_SHMEM works the same as
1314
+     * UFFD_FEATURE_MISSING_HUGETLBFS, but it applies to shmem
1315
+     * (i.e. tmpfs and other shmem based APIs).
1316
     */
1317
-#if 0 /* not available yet */
1318
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
1319
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
1320
-#endif
1321
+#define UFFD_FEATURE_EVENT_REMAP        (1<<2)
1322
+#define UFFD_FEATURE_EVENT_MADVDONTNEED        (1<<3)
1323
+#define UFFD_FEATURE_MISSING_HUGETLBFS        (1<<4)
1324
+#define UFFD_FEATURE_MISSING_SHMEM        (1<<5)
1325
    __u64 features;
1326
1327
    __u64 ioctls;
1328
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
1329
index XXXXXXX..XXXXXXX 100644
1330
--- a/linux-headers/linux/vfio.h
1331
+++ b/linux-headers/linux/vfio.h
1332
@@ -XXX,XX +XXX,XX @@ struct vfio_device_info {
1333
};
1334
#define VFIO_DEVICE_GET_INFO        _IO(VFIO_TYPE, VFIO_BASE + 7)
1335
1336
+/*
1337
+ * Vendor driver using Mediated device framework should provide device_api
1338
+ * attribute in supported type attribute groups. Device API string should be one
1339
+ * of the following corresponding to device flags in vfio_device_info structure.
1340
+ */
1341
+
1342
+#define VFIO_DEVICE_API_PCI_STRING        "vfio-pci"
1343
+#define VFIO_DEVICE_API_PLATFORM_STRING        "vfio-platform"
1344
+#define VFIO_DEVICE_API_AMBA_STRING        "vfio-amba"
1345
+
1346
/**
1347
* VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8,
1348
*                 struct vfio_region_info)
1349
--
181
--
1350
2.7.4
182
2.20.1
1351
183
1352
184
diff view generated by jsdifflib
New patch
1
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
2
3
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
4
Tests the CAN controller in loopback, sleep and snoop mode.
5
Tests filtering of incoming CAN messages.
6
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
9
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
10
Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
tests/qtest/xlnx-can-test.c | 360 ++++++++++++++++++++++++++++++++++++
14
tests/qtest/meson.build | 1 +
15
2 files changed, 361 insertions(+)
16
create mode 100644 tests/qtest/xlnx-can-test.c
17
18
diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/tests/qtest/xlnx-can-test.c
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * QTests for the Xilinx ZynqMP CAN controller.
26
+ *
27
+ * Copyright (c) 2020 Xilinx Inc.
28
+ *
29
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
30
+ *
31
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
32
+ * of this software and associated documentation files (the "Software"), to deal
33
+ * in the Software without restriction, including without limitation the rights
34
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
35
+ * copies of the Software, and to permit persons to whom the Software is
36
+ * furnished to do so, subject to the following conditions:
37
+ *
38
+ * The above copyright notice and this permission notice shall be included in
39
+ * all copies or substantial portions of the Software.
40
+ *
41
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
42
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
44
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
46
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
47
+ * THE SOFTWARE.
48
+ */
49
+
50
+#include "qemu/osdep.h"
51
+#include "libqos/libqtest.h"
52
+
53
+/* Base address. */
54
+#define CAN0_BASE_ADDR 0xFF060000
55
+#define CAN1_BASE_ADDR 0xFF070000
56
+
57
+/* Register addresses. */
58
+#define R_SRR_OFFSET 0x00
59
+#define R_MSR_OFFSET 0x04
60
+#define R_SR_OFFSET 0x18
61
+#define R_ISR_OFFSET 0x1C
62
+#define R_ICR_OFFSET 0x24
63
+#define R_TXID_OFFSET 0x30
64
+#define R_TXDLC_OFFSET 0x34
65
+#define R_TXDATA1_OFFSET 0x38
66
+#define R_TXDATA2_OFFSET 0x3C
67
+#define R_RXID_OFFSET 0x50
68
+#define R_RXDLC_OFFSET 0x54
69
+#define R_RXDATA1_OFFSET 0x58
70
+#define R_RXDATA2_OFFSET 0x5C
71
+#define R_AFR 0x60
72
+#define R_AFMR1 0x64
73
+#define R_AFIR1 0x68
74
+#define R_AFMR2 0x6C
75
+#define R_AFIR2 0x70
76
+#define R_AFMR3 0x74
77
+#define R_AFIR3 0x78
78
+#define R_AFMR4 0x7C
79
+#define R_AFIR4 0x80
80
+
81
+/* CAN modes. */
82
+#define CONFIG_MODE 0x00
83
+#define NORMAL_MODE 0x00
84
+#define LOOPBACK_MODE 0x02
85
+#define SNOOP_MODE 0x04
86
+#define SLEEP_MODE 0x01
87
+#define ENABLE_CAN (1 << 1)
88
+#define STATUS_NORMAL_MODE (1 << 3)
89
+#define STATUS_LOOPBACK_MODE (1 << 1)
90
+#define STATUS_SNOOP_MODE (1 << 12)
91
+#define STATUS_SLEEP_MODE (1 << 2)
92
+#define ISR_TXOK (1 << 1)
93
+#define ISR_RXOK (1 << 4)
94
+
95
+static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
96
+ uint8_t can_timestamp)
97
+{
98
+ uint16_t size = 0;
99
+ uint8_t len = 4;
100
+
101
+ while (size < len) {
102
+ if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET) {
103
+ g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp);
104
+ } else {
105
+ g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
106
+ }
107
+
108
+ size++;
109
+ }
110
+}
111
+
112
+static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
113
+{
114
+ uint32_t int_status;
115
+
116
+ /* Read the interrupt on CAN rx. */
117
+ int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
118
+
119
+ g_assert_cmpint(int_status, ==, ISR_RXOK);
120
+
121
+ /* Read the RX register data for CAN. */
122
+ buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET);
123
+ buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET);
124
+ buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET);
125
+ buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET);
126
+
127
+ /* Clear the RX interrupt. */
128
+ qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
129
+}
130
+
131
+static void send_data(QTestState *qts, uint64_t can_base_addr,
132
+ const uint32_t *buf_tx)
133
+{
134
+ uint32_t int_status;
135
+
136
+ /* Write the TX register data for CAN. */
137
+ qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
138
+ qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);
139
+ qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);
140
+ qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);
141
+
142
+ /* Read the interrupt on CAN for tx. */
143
+ int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK;
144
+
145
+ g_assert_cmpint(int_status, ==, ISR_TXOK);
146
+
147
+ /* Clear the interrupt for tx. */
148
+ qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);
149
+}
150
+
151
+/*
152
+ * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
153
+ * initiate the data transfer to can-bus, CAN1 receives the data. Test compares
154
+ * the data sent from CAN0 with received on CAN1.
155
+ */
156
+static void test_can_bus(void)
157
+{
158
+ const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
159
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
160
+ uint32_t status = 0;
161
+ uint8_t can_timestamp = 1;
162
+
163
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
164
+ " -object can-bus,id=canbus0"
165
+ " -machine xlnx-zcu102.canbus0=canbus0"
166
+ " -machine xlnx-zcu102.canbus1=canbus0"
167
+ );
168
+
169
+ /* Configure the CAN0 and CAN1. */
170
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
171
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
172
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
173
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
174
+
175
+ /* Check here if CAN0 and CAN1 are in normal mode. */
176
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
177
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
178
+
179
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
180
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
181
+
182
+ send_data(qts, CAN0_BASE_ADDR, buf_tx);
183
+
184
+ read_data(qts, CAN1_BASE_ADDR, buf_rx);
185
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
186
+
187
+ qtest_quit(qts);
188
+}
189
+
190
+/*
191
+ * This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
192
+ * each CAN0 and CAN1 are compared with RX register data for respective CAN.
193
+ */
194
+static void test_can_loopback(void)
195
+{
196
+ uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
197
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
198
+ uint32_t status = 0;
199
+
200
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
201
+ " -object can-bus,id=canbus0"
202
+ " -machine xlnx-zcu102.canbus0=canbus0"
203
+ " -machine xlnx-zcu102.canbus1=canbus0"
204
+ );
205
+
206
+ /* Configure the CAN0 in loopback mode. */
207
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
208
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
209
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
210
+
211
+ /* Check here if CAN0 is set in loopback mode. */
212
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
213
+
214
+ g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
215
+
216
+ send_data(qts, CAN0_BASE_ADDR, buf_tx);
217
+ read_data(qts, CAN0_BASE_ADDR, buf_rx);
218
+ match_rx_tx_data(buf_tx, buf_rx, 0);
219
+
220
+ /* Configure the CAN1 in loopback mode. */
221
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
222
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
223
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
224
+
225
+ /* Check here if CAN1 is set in loopback mode. */
226
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
227
+
228
+ g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
229
+
230
+ send_data(qts, CAN1_BASE_ADDR, buf_tx);
231
+ read_data(qts, CAN1_BASE_ADDR, buf_rx);
232
+ match_rx_tx_data(buf_tx, buf_rx, 0);
233
+
234
+ qtest_quit(qts);
235
+}
236
+
237
+/*
238
+ * Enable filters for CAN1. This will filter incoming messages with ID. In this
239
+ * test message will pass through filter 2.
240
+ */
241
+static void test_can_filter(void)
242
+{
243
+ uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
244
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
245
+ uint32_t status = 0;
246
+ uint8_t can_timestamp = 1;
247
+
248
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
249
+ " -object can-bus,id=canbus0"
250
+ " -machine xlnx-zcu102.canbus0=canbus0"
251
+ " -machine xlnx-zcu102.canbus1=canbus0"
252
+ );
253
+
254
+ /* Configure the CAN0 and CAN1. */
255
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
256
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
257
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
258
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
259
+
260
+ /* Check here if CAN0 and CAN1 are in normal mode. */
261
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
262
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
263
+
264
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
265
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
266
+
267
+ /* Set filter for CAN1 for incoming messages. */
268
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0);
269
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7);
270
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F);
271
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431);
272
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14);
273
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234);
274
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431);
275
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF);
276
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234);
277
+
278
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
279
+
280
+ send_data(qts, CAN0_BASE_ADDR, buf_tx);
281
+
282
+ read_data(qts, CAN1_BASE_ADDR, buf_rx);
283
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
284
+
285
+ qtest_quit(qts);
286
+}
287
+
288
+/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */
289
+static void test_can_sleepmode(void)
290
+{
291
+ uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
292
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
293
+ uint32_t status = 0;
294
+ uint8_t can_timestamp = 1;
295
+
296
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
297
+ " -object can-bus,id=canbus0"
298
+ " -machine xlnx-zcu102.canbus0=canbus0"
299
+ " -machine xlnx-zcu102.canbus1=canbus0"
300
+ );
301
+
302
+ /* Configure the CAN0. */
303
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
304
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE);
305
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
306
+
307
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
308
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
309
+
310
+ /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */
311
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
312
+ g_assert_cmpint(status, ==, STATUS_SLEEP_MODE);
313
+
314
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
315
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
316
+
317
+ send_data(qts, CAN1_BASE_ADDR, buf_tx);
318
+
319
+ /*
320
+ * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode.
321
+ * Check the CAN0 status now. It should exit the sleep mode and receive the
322
+ * incoming data.
323
+ */
324
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
325
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
326
+
327
+ read_data(qts, CAN0_BASE_ADDR, buf_rx);
328
+
329
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
330
+
331
+ qtest_quit(qts);
332
+}
333
+
334
+/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */
335
+static void test_can_snoopmode(void)
336
+{
337
+ uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
338
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
339
+ uint32_t status = 0;
340
+ uint8_t can_timestamp = 1;
341
+
342
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
343
+ " -object can-bus,id=canbus0"
344
+ " -machine xlnx-zcu102.canbus0=canbus0"
345
+ " -machine xlnx-zcu102.canbus1=canbus0"
346
+ );
347
+
348
+ /* Configure the CAN0. */
349
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
350
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE);
351
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
352
+
353
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
354
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
355
+
356
+ /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */
357
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
358
+ g_assert_cmpint(status, ==, STATUS_SNOOP_MODE);
359
+
360
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
361
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
362
+
363
+ send_data(qts, CAN1_BASE_ADDR, buf_tx);
364
+
365
+ read_data(qts, CAN0_BASE_ADDR, buf_rx);
366
+
367
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
368
+
369
+ qtest_quit(qts);
370
+}
371
+
372
+int main(int argc, char **argv)
373
+{
374
+ g_test_init(&argc, &argv, NULL);
375
+
376
+ qtest_add_func("/net/can/can_bus", test_can_bus);
377
+ qtest_add_func("/net/can/can_loopback", test_can_loopback);
378
+ qtest_add_func("/net/can/can_filter", test_can_filter);
379
+ qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode);
380
+ qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode);
381
+
382
+ return g_test_run();
383
+}
384
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
385
index XXXXXXX..XXXXXXX 100644
386
--- a/tests/qtest/meson.build
387
+++ b/tests/qtest/meson.build
388
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
389
['arm-cpu-features',
390
'numa-test',
391
'boot-serial-test',
392
+ 'xlnx-can-test',
393
'migration-test']
394
395
qtests_s390x = \
396
--
397
2.20.1
398
399
diff view generated by jsdifflib
New patch
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
1
2
3
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
4
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
6
Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
MAINTAINERS | 8 ++++++++
10
1 file changed, 8 insertions(+)
11
12
diff --git a/MAINTAINERS b/MAINTAINERS
13
index XXXXXXX..XXXXXXX 100644
14
--- a/MAINTAINERS
15
+++ b/MAINTAINERS
16
@@ -XXX,XX +XXX,XX @@ F: hw/net/opencores_eth.c
17
18
Devices
19
-------
20
+Xilinx CAN
21
+M: Vikram Garhwal <fnu.vikram@xilinx.com>
22
+M: Francisco Iglesias <francisco.iglesias@xilinx.com>
23
+S: Maintained
24
+F: hw/net/can/xlnx-*
25
+F: include/hw/net/xlnx-*
26
+F: tests/qtest/xlnx-can-test*
27
+
28
EDU
29
M: Jiri Slaby <jslaby@suse.cz>
30
S: Maintained
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
To Save and Restore ICC_SRE_EL1 register introduce vmstate
3
Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable
4
subsection and load only if non-zero.
4
it for QEMU as well. A53 was already enabled there.
5
Also initialize icc_sre_el1 with to 0x7 in pre_load
6
function.
7
5
8
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
6
1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117
7
8
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
include/hw/intc/arm_gicv3_common.h | 1 +
14
hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++---
15
hw/intc/arm_gicv3_common.c | 36 ++++++++++++++++++++++++++++++++++++
15
1 file changed, 20 insertions(+), 3 deletions(-)
16
2 files changed, 37 insertions(+)
17
16
18
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/arm_gicv3_common.h
19
--- a/hw/arm/sbsa-ref.c
21
+++ b/include/hw/intc/arm_gicv3_common.h
20
+++ b/hw/arm/sbsa-ref.c
22
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
21
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
23
uint8_t gicr_ipriorityr[GIC_INTERNAL];
22
[SBSA_GWDT] = 16,
24
25
/* CPU interface */
26
+ uint64_t icc_sre_el1;
27
uint64_t icc_ctlr_el1[2];
28
uint64_t icc_pmr_el1;
29
uint64_t icc_bpr[3];
30
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_common.c
33
+++ b/hw/intc/arm_gicv3_common.c
34
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu_virt = {
35
}
36
};
23
};
37
24
38
+static int icc_sre_el1_reg_pre_load(void *opaque)
25
+static const char * const valid_cpus[] = {
26
+ ARM_CPU_TYPE_NAME("cortex-a53"),
27
+ ARM_CPU_TYPE_NAME("cortex-a57"),
28
+ ARM_CPU_TYPE_NAME("cortex-a72"),
29
+};
30
+
31
+static bool cpu_type_valid(const char *cpu)
39
+{
32
+{
40
+ GICv3CPUState *cs = opaque;
33
+ int i;
41
+
34
+
42
+ /*
35
+ for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
43
+ * If the sre_el1 subsection is not transferred this
36
+ if (strcmp(cpu, valid_cpus[i]) == 0) {
44
+ * means SRE_EL1 is 0x7 (which might not be the same as
37
+ return true;
45
+ * our reset value).
38
+ }
46
+ */
39
+ }
47
+ cs->icc_sre_el1 = 0x7;
40
+ return false;
48
+ return 0;
49
+}
41
+}
50
+
42
+
51
+static bool icc_sre_el1_reg_needed(void *opaque)
43
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
52
+{
44
{
53
+ GICv3CPUState *cs = opaque;
45
uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
54
+
46
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
55
+ return cs->icc_sre_el1 != 7;
47
const CPUArchIdList *possible_cpus;
56
+}
48
int n, sbsa_max_cpus;
57
+
49
58
+const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
50
- if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
59
+ .name = "arm_gicv3_cpu/sre_el1",
51
- error_report("sbsa-ref: CPU type other than the built-in "
60
+ .version_id = 1,
52
- "cortex-a57 not supported");
61
+ .minimum_version_id = 1,
53
+ if (!cpu_type_valid(machine->cpu_type)) {
62
+ .pre_load = icc_sre_el1_reg_pre_load,
54
+ error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
63
+ .needed = icc_sre_el1_reg_needed,
55
exit(1);
64
+ .fields = (VMStateField[]) {
65
+ VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
66
+ VMSTATE_END_OF_LIST()
67
+ }
68
+};
69
+
70
static const VMStateDescription vmstate_gicv3_cpu = {
71
.name = "arm_gicv3_cpu",
72
.version_id = 1,
73
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
74
.subsections = (const VMStateDescription * []) {
75
&vmstate_gicv3_cpu_virt,
76
NULL
77
+ },
78
+ .subsections = (const VMStateDescription * []) {
79
+ &vmstate_gicv3_cpu_sre_el1,
80
+ NULL
81
}
56
}
82
};
83
57
84
--
58
--
85
2.7.4
59
2.20.1
86
60
87
61
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
This actually implements pre_save and post_load methods for in-kernel
3
Dump the collected random data after a randomness test failure.
4
vGICv3.
5
4
6
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
5
Note that this relies on the test having called
6
g_test_set_nonfatal_assertions() so we don't abort immediately on the
7
assertion failure.
8
9
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: minor commit message tweak]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
10
Message-id: 1487850673-26455-4-git-send-email-vijay.kilari@gmail.com
11
[PMM:
12
* use decimal, not 0bnnn
13
* fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1
14
* completely rearranged the get and put functions to read and write
15
the state in a natural order, rather than mixing distributor and
16
redistributor state together]
17
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
18
[Vijay:
19
* Update macro KVM_VGIC_ATTR
20
* Use 32 bit access for gicd and gicr
21
* GICD_IROUTER, GICD_TYPER, GICR_PROPBASER and GICR_PENDBASER reg
22
access are changed from 64-bit to 32-bit access
23
* Add ICC_SRE_EL1 save and restore
24
* Dropped translate_fn mechanism and coded functions to handle
25
save and restore of edge_trigger and priority
26
* Number of APnR register saved/restored based on number of
27
priority bits supported]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
---
13
---
30
hw/intc/gicv3_internal.h | 1 +
14
tests/qtest/npcm7xx_rng-test.c | 12 ++++++++++++
31
hw/intc/arm_gicv3_kvm.c | 573 +++++++++++++++++++++++++++++++++++++++++++++--
15
1 file changed, 12 insertions(+)
32
2 files changed, 558 insertions(+), 16 deletions(-)
33
16
34
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
17
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
35
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/intc/gicv3_internal.h
19
--- a/tests/qtest/npcm7xx_rng-test.c
37
+++ b/hw/intc/gicv3_internal.h
20
+++ b/tests/qtest/npcm7xx_rng-test.c
38
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
39
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
22
40
#define ICC_CTLR_EL1_PMHE (1U << 6)
23
#include "libqtest-single.h"
41
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
24
#include "qemu/bitops.h"
42
+#define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
25
+#include "qemu-common.h"
43
#define ICC_CTLR_EL1_IDBITS_SHIFT 11
26
44
#define ICC_CTLR_EL1_SEIS (1U << 14)
27
#define RNG_BASE_ADDR 0xf000b000
45
#define ICC_CTLR_EL1_A3V (1U << 15)
28
46
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_kvm.c
49
+++ b/hw/intc/arm_gicv3_kvm.c
50
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@
51
#include "qapi/error.h"
30
/* Number of bits to collect for randomness tests. */
52
#include "hw/intc/arm_gicv3_common.h"
31
#define TEST_INPUT_BITS (128)
53
#include "hw/sysbus.h"
32
54
+#include "qemu/error-report.h"
33
+static void dump_buf_if_failed(const uint8_t *buf, size_t size)
55
#include "sysemu/kvm.h"
56
#include "kvm_arm.h"
57
+#include "gicv3_internal.h"
58
#include "vgic_common.h"
59
#include "migration/migration.h"
60
61
@@ -XXX,XX +XXX,XX @@
62
#define KVM_ARM_GICV3_GET_CLASS(obj) \
63
OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
64
65
+#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
66
+ (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
67
+ ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
68
+ ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
69
+ ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
70
+ ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
71
+
72
+#define ICC_PMR_EL1 \
73
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
74
+#define ICC_BPR0_EL1 \
75
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
76
+#define ICC_AP0R_EL1(n) \
77
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
78
+#define ICC_AP1R_EL1(n) \
79
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
80
+#define ICC_BPR1_EL1 \
81
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
82
+#define ICC_CTLR_EL1 \
83
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
84
+#define ICC_SRE_EL1 \
85
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
86
+#define ICC_IGRPEN0_EL1 \
87
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
88
+#define ICC_IGRPEN1_EL1 \
89
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
90
+
91
typedef struct KVMARMGICv3Class {
92
ARMGICv3CommonClass parent_class;
93
DeviceRealize parent_realize;
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
95
kvm_arm_gic_set_irq(s->num_irq, irq, level);
96
}
97
98
+#define KVM_VGIC_ATTR(reg, typer) \
99
+ ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
100
+
101
+static inline void kvm_gicd_access(GICv3State *s, int offset,
102
+ uint32_t *val, bool write)
103
+{
34
+{
104
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
35
+ if (g_test_failed()) {
105
+ KVM_VGIC_ATTR(offset, 0),
36
+ qemu_hexdump(stderr, "", buf, size);
106
+ val, write);
107
+}
108
+
109
+static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
110
+ uint32_t *val, bool write)
111
+{
112
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
113
+ KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
114
+ val, write);
115
+}
116
+
117
+static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
118
+ uint64_t *val, bool write)
119
+{
120
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
121
+ KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
122
+ val, write);
123
+}
124
+
125
+static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
126
+ uint32_t *val, bool write)
127
+{
128
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
129
+ KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
130
+ (VGIC_LEVEL_INFO_LINE_LEVEL <<
131
+ KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
132
+ val, write);
133
+}
134
+
135
+/* Loop through each distributor IRQ related register; since bits
136
+ * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
137
+ * is enabled, we skip those.
138
+ */
139
+#define for_each_dist_irq_reg(_irq, _max, _field_width) \
140
+ for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
141
+
142
+static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
143
+{
144
+ uint32_t reg, *field;
145
+ int irq;
146
+
147
+ field = (uint32_t *)bmp;
148
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
149
+ kvm_gicd_access(s, offset, &reg, false);
150
+ *field = reg;
151
+ offset += 4;
152
+ field++;
153
+ }
37
+ }
154
+}
38
+}
155
+
39
+
156
+static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
40
static void rng_writeb(unsigned int offset, uint8_t value)
157
+{
158
+ uint32_t reg, *field;
159
+ int irq;
160
+
161
+ field = (uint32_t *)bmp;
162
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
163
+ reg = *field;
164
+ kvm_gicd_access(s, offset, &reg, true);
165
+ offset += 4;
166
+ field++;
167
+ }
168
+}
169
+
170
+static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
171
+ uint32_t *bmp)
172
+{
173
+ uint32_t reg;
174
+ int irq;
175
+
176
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
177
+ kvm_gicd_access(s, offset, &reg, false);
178
+ reg = half_unshuffle32(reg >> 1);
179
+ if (irq % 32 != 0) {
180
+ reg = (reg << 16);
181
+ }
182
+ *gic_bmp_ptr32(bmp, irq) |= reg;
183
+ offset += 4;
184
+ }
185
+}
186
+
187
+static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
188
+ uint32_t *bmp)
189
+{
190
+ uint32_t reg;
191
+ int irq;
192
+
193
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
194
+ reg = *gic_bmp_ptr32(bmp, irq);
195
+ if (irq % 32 != 0) {
196
+ reg = (reg & 0xffff0000) >> 16;
197
+ } else {
198
+ reg = reg & 0xffff;
199
+ }
200
+ reg = half_shuffle32(reg) << 1;
201
+ kvm_gicd_access(s, offset, &reg, true);
202
+ offset += 4;
203
+ }
204
+}
205
+
206
+static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
207
+{
208
+ uint32_t reg;
209
+ int irq;
210
+
211
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
212
+ kvm_gic_line_level_access(s, irq, 0, &reg, false);
213
+ *gic_bmp_ptr32(bmp, irq) = reg;
214
+ }
215
+}
216
+
217
+static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
218
+{
219
+ uint32_t reg;
220
+ int irq;
221
+
222
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
223
+ reg = *gic_bmp_ptr32(bmp, irq);
224
+ kvm_gic_line_level_access(s, irq, 0, &reg, true);
225
+ }
226
+}
227
+
228
+/* Read a bitmap register group from the kernel VGIC. */
229
+static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
230
+{
231
+ uint32_t reg;
232
+ int irq;
233
+
234
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
235
+ kvm_gicd_access(s, offset, &reg, false);
236
+ *gic_bmp_ptr32(bmp, irq) = reg;
237
+ offset += 4;
238
+ }
239
+}
240
+
241
+static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
242
+ uint32_t clroffset, uint32_t *bmp)
243
+{
244
+ uint32_t reg;
245
+ int irq;
246
+
247
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
248
+ /* If this bitmap is a set/clear register pair, first write to the
249
+ * clear-reg to clear all bits before using the set-reg to write
250
+ * the 1 bits.
251
+ */
252
+ if (clroffset != 0) {
253
+ reg = 0;
254
+ kvm_gicd_access(s, clroffset, &reg, true);
255
+ }
256
+ reg = *gic_bmp_ptr32(bmp, irq);
257
+ kvm_gicd_access(s, offset, &reg, true);
258
+ offset += 4;
259
+ }
260
+}
261
+
262
+static void kvm_arm_gicv3_check(GICv3State *s)
263
+{
264
+ uint32_t reg;
265
+ uint32_t num_irq;
266
+
267
+ /* Sanity checking s->num_irq */
268
+ kvm_gicd_access(s, GICD_TYPER, &reg, false);
269
+ num_irq = ((reg & 0x1f) + 1) * 32;
270
+
271
+ if (num_irq < s->num_irq) {
272
+ error_report("Model requests %u IRQs, but kernel supports max %u",
273
+ s->num_irq, num_irq);
274
+ abort();
275
+ }
276
+}
277
+
278
static void kvm_arm_gicv3_put(GICv3State *s)
279
{
41
{
280
- /* TODO */
42
writeb(RNG_BASE_ADDR + offset, value);
281
- DPRINTF("Cannot put kernel gic state, no kernel interface\n");
43
@@ -XXX,XX +XXX,XX @@ static void test_continuous_monobit(void)
282
+ uint32_t regl, regh, reg;
44
}
283
+ uint64_t reg64, redist_typer;
45
284
+ int ncpu, i;
46
g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
285
+
47
+ dump_buf_if_failed(buf, sizeof(buf));
286
+ kvm_arm_gicv3_check(s);
287
+
288
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
289
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
290
+ redist_typer = ((uint64_t)regh << 32) | regl;
291
+
292
+ reg = s->gicd_ctlr;
293
+ kvm_gicd_access(s, GICD_CTLR, &reg, true);
294
+
295
+ if (redist_typer & GICR_TYPER_PLPIS) {
296
+ /* Set base addresses before LPIs are enabled by GICR_CTLR write */
297
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
298
+ GICv3CPUState *c = &s->cpu[ncpu];
299
+
300
+ reg64 = c->gicr_propbaser;
301
+ regl = (uint32_t)reg64;
302
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, true);
303
+ regh = (uint32_t)(reg64 >> 32);
304
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
305
+
306
+ reg64 = c->gicr_pendbaser;
307
+ if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
308
+ /* Setting PTZ is advised if LPIs are disabled, to reduce
309
+ * GIC initialization time.
310
+ */
311
+ reg64 |= GICR_PENDBASER_PTZ;
312
+ }
313
+ regl = (uint32_t)reg64;
314
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
315
+ regh = (uint32_t)(reg64 >> 32);
316
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, true);
317
+ }
318
+ }
319
+
320
+ /* Redistributor state (one per CPU) */
321
+
322
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
323
+ GICv3CPUState *c = &s->cpu[ncpu];
324
+
325
+ reg = c->gicr_ctlr;
326
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, true);
327
+
328
+ reg = c->gicr_statusr[GICV3_NS];
329
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, true);
330
+
331
+ reg = c->gicr_waker;
332
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, true);
333
+
334
+ reg = c->gicr_igroupr0;
335
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, true);
336
+
337
+ reg = ~0;
338
+ kvm_gicr_access(s, GICR_ICENABLER0, ncpu, &reg, true);
339
+ reg = c->gicr_ienabler0;
340
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, true);
341
+
342
+ /* Restore config before pending so we treat level/edge correctly */
343
+ reg = half_shuffle32(c->edge_trigger >> 16) << 1;
344
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, true);
345
+
346
+ reg = c->level;
347
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, true);
348
+
349
+ reg = ~0;
350
+ kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true);
351
+ reg = c->gicr_ipendr0;
352
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true);
353
+
354
+ reg = ~0;
355
+ kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, &reg, true);
356
+ reg = c->gicr_iactiver0;
357
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true);
358
+
359
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
360
+ reg = c->gicr_ipriorityr[i] |
361
+ (c->gicr_ipriorityr[i + 1] << 8) |
362
+ (c->gicr_ipriorityr[i + 2] << 16) |
363
+ (c->gicr_ipriorityr[i + 3] << 24);
364
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, true);
365
+ }
366
+ }
367
+
368
+ /* Distributor state (shared between all CPUs */
369
+ reg = s->gicd_statusr[GICV3_NS];
370
+ kvm_gicd_access(s, GICD_STATUSR, &reg, true);
371
+
372
+ /* s->enable bitmap -> GICD_ISENABLERn */
373
+ kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
374
+
375
+ /* s->group bitmap -> GICD_IGROUPRn */
376
+ kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
377
+
378
+ /* Restore targets before pending to ensure the pending state is set on
379
+ * the appropriate CPU interfaces in the kernel
380
+ */
381
+
382
+ /* s->gicd_irouter[irq] -> GICD_IROUTERn
383
+ * We can't use kvm_dist_put() here because the registers are 64-bit
384
+ */
385
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
386
+ uint32_t offset;
387
+
388
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
389
+ reg = (uint32_t)s->gicd_irouter[i];
390
+ kvm_gicd_access(s, offset, &reg, true);
391
+
392
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
393
+ reg = (uint32_t)(s->gicd_irouter[i] >> 32);
394
+ kvm_gicd_access(s, offset, &reg, true);
395
+ }
396
+
397
+ /* s->trigger bitmap -> GICD_ICFGRn
398
+ * (restore configuration registers before pending IRQs so we treat
399
+ * level/edge correctly)
400
+ */
401
+ kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
402
+
403
+ /* s->level bitmap -> line_level */
404
+ kvm_gic_put_line_level_bmp(s, s->level);
405
+
406
+ /* s->pending bitmap -> GICD_ISPENDRn */
407
+ kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
408
+
409
+ /* s->active bitmap -> GICD_ISACTIVERn */
410
+ kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
411
+
412
+ /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
413
+ kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
414
+
415
+ /* CPU Interface state (one per CPU) */
416
+
417
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
418
+ GICv3CPUState *c = &s->cpu[ncpu];
419
+ int num_pri_bits;
420
+
421
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
422
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
423
+ &c->icc_ctlr_el1[GICV3_NS], true);
424
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
425
+ &c->icc_igrpen[GICV3_G0], true);
426
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
427
+ &c->icc_igrpen[GICV3_G1NS], true);
428
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
429
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
430
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
431
+
432
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
433
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
434
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
435
+
436
+ switch (num_pri_bits) {
437
+ case 7:
438
+ reg64 = c->icc_apr[GICV3_G0][3];
439
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, true);
440
+ reg64 = c->icc_apr[GICV3_G0][2];
441
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, true);
442
+ case 6:
443
+ reg64 = c->icc_apr[GICV3_G0][1];
444
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, true);
445
+ default:
446
+ reg64 = c->icc_apr[GICV3_G0][0];
447
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, true);
448
+ }
449
+
450
+ switch (num_pri_bits) {
451
+ case 7:
452
+ reg64 = c->icc_apr[GICV3_G1NS][3];
453
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true);
454
+ reg64 = c->icc_apr[GICV3_G1NS][2];
455
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true);
456
+ case 6:
457
+ reg64 = c->icc_apr[GICV3_G1NS][1];
458
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true);
459
+ default:
460
+ reg64 = c->icc_apr[GICV3_G1NS][0];
461
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true);
462
+ }
463
+ }
464
}
48
}
465
49
466
static void kvm_arm_gicv3_get(GICv3State *s)
50
/*
467
{
51
@@ -XXX,XX +XXX,XX @@ static void test_continuous_runs(void)
468
- /* TODO */
52
}
469
- DPRINTF("Cannot get kernel gic state, no kernel interface\n");
53
470
+ uint32_t regl, regh, reg;
54
g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
471
+ uint64_t reg64, redist_typer;
55
+ dump_buf_if_failed(buf.c, sizeof(buf));
472
+ int ncpu, i;
473
+
474
+ kvm_arm_gicv3_check(s);
475
+
476
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
477
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
478
+ redist_typer = ((uint64_t)regh << 32) | regl;
479
+
480
+ kvm_gicd_access(s, GICD_CTLR, &reg, false);
481
+ s->gicd_ctlr = reg;
482
+
483
+ /* Redistributor state (one per CPU) */
484
+
485
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
486
+ GICv3CPUState *c = &s->cpu[ncpu];
487
+
488
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, false);
489
+ c->gicr_ctlr = reg;
490
+
491
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, false);
492
+ c->gicr_statusr[GICV3_NS] = reg;
493
+
494
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, false);
495
+ c->gicr_waker = reg;
496
+
497
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, false);
498
+ c->gicr_igroupr0 = reg;
499
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, false);
500
+ c->gicr_ienabler0 = reg;
501
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, false);
502
+ c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
503
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, false);
504
+ c->level = reg;
505
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, false);
506
+ c->gicr_ipendr0 = reg;
507
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false);
508
+ c->gicr_iactiver0 = reg;
509
+
510
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
511
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false);
512
+ c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
513
+ c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
514
+ c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
515
+ c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
516
+ }
517
+ }
518
+
519
+ if (redist_typer & GICR_TYPER_PLPIS) {
520
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
521
+ GICv3CPUState *c = &s->cpu[ncpu];
522
+
523
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, false);
524
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, false);
525
+ c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
526
+
527
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, false);
528
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, false);
529
+ c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
530
+ }
531
+ }
532
+
533
+ /* Distributor state (shared between all CPUs */
534
+
535
+ kvm_gicd_access(s, GICD_STATUSR, &reg, false);
536
+ s->gicd_statusr[GICV3_NS] = reg;
537
+
538
+ /* GICD_IGROUPRn -> s->group bitmap */
539
+ kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
540
+
541
+ /* GICD_ISENABLERn -> s->enabled bitmap */
542
+ kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
543
+
544
+ /* Line level of irq */
545
+ kvm_gic_get_line_level_bmp(s, s->level);
546
+ /* GICD_ISPENDRn -> s->pending bitmap */
547
+ kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
548
+
549
+ /* GICD_ISACTIVERn -> s->active bitmap */
550
+ kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
551
+
552
+ /* GICD_ICFGRn -> s->trigger bitmap */
553
+ kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
554
+
555
+ /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
556
+ kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
557
+
558
+ /* GICD_IROUTERn -> s->gicd_irouter[irq] */
559
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
560
+ uint32_t offset;
561
+
562
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
563
+ kvm_gicd_access(s, offset, &regl, false);
564
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
565
+ kvm_gicd_access(s, offset, &regh, false);
566
+ s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
567
+ }
568
+
569
+ /*****************************************************************
570
+ * CPU Interface(s) State
571
+ */
572
+
573
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
574
+ GICv3CPUState *c = &s->cpu[ncpu];
575
+ int num_pri_bits;
576
+
577
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
578
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
579
+ &c->icc_ctlr_el1[GICV3_NS], false);
580
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
581
+ &c->icc_igrpen[GICV3_G0], false);
582
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
583
+ &c->icc_igrpen[GICV3_G1NS], false);
584
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
585
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
586
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
587
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
588
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
589
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
590
+
591
+ switch (num_pri_bits) {
592
+ case 7:
593
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, false);
594
+ c->icc_apr[GICV3_G0][3] = reg64;
595
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, false);
596
+ c->icc_apr[GICV3_G0][2] = reg64;
597
+ case 6:
598
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, false);
599
+ c->icc_apr[GICV3_G0][1] = reg64;
600
+ default:
601
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, false);
602
+ c->icc_apr[GICV3_G0][0] = reg64;
603
+ }
604
+
605
+ switch (num_pri_bits) {
606
+ case 7:
607
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false);
608
+ c->icc_apr[GICV3_G1NS][3] = reg64;
609
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false);
610
+ c->icc_apr[GICV3_G1NS][2] = reg64;
611
+ case 6:
612
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false);
613
+ c->icc_apr[GICV3_G1NS][1] = reg64;
614
+ default:
615
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);
616
+ c->icc_apr[GICV3_G1NS][0] = reg64;
617
+ }
618
+ }
619
}
56
}
620
57
621
static void kvm_arm_gicv3_reset(DeviceState *dev)
58
/*
622
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
59
@@ -XXX,XX +XXX,XX @@ static void test_first_byte_monobit(void)
623
DPRINTF("Reset\n");
60
}
624
61
625
kgc->parent_reset(dev);
62
g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
626
+
63
+ dump_buf_if_failed(buf, sizeof(buf));
627
+ if (s->migration_blocker) {
628
+ DPRINTF("Cannot put kernel gic state, no kernel interface\n");
629
+ return;
630
+ }
631
+
632
kvm_arm_gicv3_put(s);
633
}
64
}
634
65
635
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
66
/*
636
67
@@ -XXX,XX +XXX,XX @@ static void test_first_byte_runs(void)
637
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
638
639
- /* Block migration of a KVM GICv3 device: the API for saving and restoring
640
- * the state in the kernel is not yet finalised in the kernel or
641
- * implemented in QEMU.
642
- */
643
- error_setg(&s->migration_blocker, "vGICv3 migration is not implemented");
644
- migrate_add_blocker(s->migration_blocker, &local_err);
645
- if (local_err) {
646
- error_propagate(errp, local_err);
647
- error_free(s->migration_blocker);
648
- return;
649
- }
650
-
651
/* Try to create the device via the device control API */
652
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
653
if (s->dev_fd < 0) {
654
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
655
656
kvm_irqchip_commit_routes(kvm_state);
657
}
68
}
658
+
69
659
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
70
g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
660
+ GICD_CTLR)) {
71
+ dump_buf_if_failed(buf.c, sizeof(buf));
661
+ error_setg(&s->migration_blocker, "This operating system kernel does "
662
+ "not support vGICv3 migration");
663
+ migrate_add_blocker(s->migration_blocker, &local_err);
664
+ if (local_err) {
665
+ error_propagate(errp, local_err);
666
+ error_free(s->migration_blocker);
667
+ return;
668
+ }
669
+ }
670
}
72
}
671
73
672
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
74
int main(int argc, char **argv)
673
--
75
--
674
2.7.4
76
2.20.1
675
77
676
78
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Alex Chen <alex.chen@huawei.com>
2
2
3
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform.
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
4
5
5
For supporting the SD controller selection (alternate function of GPIOs
6
Reported-by: Euler Robot <euler.robot@huawei.com>
6
48-53), the bcm2835_gpio now exposes an sdbus.
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
7
It also has a link to both the sdbus of sdhci and sdhost controllers,
8
Message-id: 20201126111109.112238-2-alex.chen@huawei.com
8
and the card is reparented from one bus to another when the alternate
9
function of GPIOs 48-53 is modified.
10
11
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org
15
Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/arm/bcm2835_peripherals.h | 4 ++++
12
hw/misc/imx25_ccm.c | 12 ++++++------
20
hw/arm/bcm2835_peripherals.c | 43 ++++++++++++++++++++++++++++++++++--
13
1 file changed, 6 insertions(+), 6 deletions(-)
21
2 files changed, 45 insertions(+), 2 deletions(-)
22
14
23
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
15
diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/bcm2835_peripherals.h
17
--- a/hw/misc/imx25_ccm.c
26
+++ b/include/hw/arm/bcm2835_peripherals.h
18
+++ b/hw/misc/imx25_ccm.c
27
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static const char *imx25_ccm_reg_name(uint32_t reg)
28
#include "hw/misc/bcm2835_rng.h"
20
case IMX25_CCM_LPIMR1_REG:
29
#include "hw/misc/bcm2835_mbox.h"
21
return "lpimr1";
30
#include "hw/sd/sdhci.h"
22
default:
31
+#include "hw/sd/bcm2835_sdhost.h"
23
- sprintf(unknown, "[%d ?]", reg);
32
+#include "hw/gpio/bcm2835_gpio.h"
24
+ sprintf(unknown, "[%u ?]", reg);
33
25
return unknown;
34
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
26
}
35
#define BCM2835_PERIPHERALS(obj) \
36
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
37
BCM2835RngState rng;
38
BCM2835MboxState mboxes;
39
SDHCIState sdhci;
40
+ BCM2835SDHostState sdhost;
41
+ BCM2835GpioState gpio;
42
} BCM2835PeripheralState;
43
44
#endif /* BCM2835_PERIPHERALS_H */
45
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/bcm2835_peripherals.c
48
+++ b/hw/arm/bcm2835_peripherals.c
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
50
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
51
qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
52
53
+ /* SDHOST */
54
+ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
55
+ object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
56
+ qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
57
+
58
/* DMA Channels */
59
object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
60
object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
61
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
62
63
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
64
OBJECT(&s->gpu_bus_mr), &error_abort);
65
+
66
+ /* GPIO */
67
+ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
68
+ object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
69
+ qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
70
+
71
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
72
+ OBJECT(&s->sdhci.sdbus), &error_abort);
73
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
74
+ OBJECT(&s->sdhost.sdbus), &error_abort);
75
}
27
}
76
28
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
77
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
29
freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
78
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
79
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
80
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
81
INTERRUPT_ARASANSDIO));
82
- object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "sd-bus",
83
- &err);
84
+
85
+ /* SDHOST */
86
+ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
87
if (err) {
88
error_propagate(errp, err);
89
return;
90
}
30
}
91
31
92
+ memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
32
- DPRINTF("freq = %d\n", freq);
93
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
33
+ DPRINTF("freq = %u\n", freq);
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
34
95
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
35
return freq;
96
+ INTERRUPT_SDIO));
36
}
97
+
37
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
98
/* DMA Channels */
38
99
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
39
freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
100
if (err) {
40
101
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
41
- DPRINTF("freq = %d\n", freq);
102
BCM2835_IC_GPU_IRQ,
42
+ DPRINTF("freq = %u\n", freq);
103
INTERRUPT_DMA0 + n));
43
44
return freq;
45
}
46
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
47
freq = imx25_ccm_get_mcu_clk(dev)
48
/ (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
49
50
- DPRINTF("freq = %d\n", freq);
51
+ DPRINTF("freq = %u\n", freq);
52
53
return freq;
54
}
55
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
56
57
freq = imx25_ccm_get_ahb_clk(dev) / 2;
58
59
- DPRINTF("freq = %d\n", freq);
60
+ DPRINTF("freq = %u\n", freq);
61
62
return freq;
63
}
64
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
65
break;
104
}
66
}
105
+
67
106
+ /* GPIO */
68
- DPRINTF("Clock = %d) = %d\n", clock, freq);
107
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
69
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
108
+ if (err) {
70
109
+ error_propagate(errp, err);
71
return freq;
110
+ return;
111
+ }
112
+
113
+ memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
114
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
115
+
116
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
117
+ &err);
118
+ if (err) {
119
+ error_propagate(errp, err);
120
+ return;
121
+ }
122
}
72
}
123
124
static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
125
--
73
--
126
2.7.4
74
2.20.1
127
75
128
76
diff view generated by jsdifflib
New patch
1
From: Alex Chen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201126111109.112238-3-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/imx31_ccm.c | 14 +++++++-------
13
hw/misc/imx_ccm.c | 4 ++--
14
2 files changed, 9 insertions(+), 9 deletions(-)
15
16
diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/imx31_ccm.c
19
+++ b/hw/misc/imx31_ccm.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx31_ccm_reg_name(uint32_t reg)
21
case IMX31_CCM_PDR2_REG:
22
return "PDR2";
23
default:
24
- sprintf(unknown, "[%d ?]", reg);
25
+ sprintf(unknown, "[%u ?]", reg);
26
return unknown;
27
}
28
}
29
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
30
freq = CKIH_FREQ;
31
}
32
33
- DPRINTF("freq = %d\n", freq);
34
+ DPRINTF("freq = %u\n", freq);
35
36
return freq;
37
}
38
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
39
freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
40
imx31_ccm_get_pll_ref_clk(dev));
41
42
- DPRINTF("freq = %d\n", freq);
43
+ DPRINTF("freq = %u\n", freq);
44
45
return freq;
46
}
47
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
48
freq = imx31_ccm_get_mpll_clk(dev);
49
}
50
51
- DPRINTF("freq = %d\n", freq);
52
+ DPRINTF("freq = %u\n", freq);
53
54
return freq;
55
}
56
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
57
freq = imx31_ccm_get_mcu_main_clk(dev)
58
/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
59
60
- DPRINTF("freq = %d\n", freq);
61
+ DPRINTF("freq = %u\n", freq);
62
63
return freq;
64
}
65
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
66
freq = imx31_ccm_get_hclk_clk(dev)
67
/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
68
69
- DPRINTF("freq = %d\n", freq);
70
+ DPRINTF("freq = %u\n", freq);
71
72
return freq;
73
}
74
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
75
break;
76
}
77
78
- DPRINTF("Clock = %d) = %d\n", clock, freq);
79
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
80
81
return freq;
82
}
83
diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/misc/imx_ccm.c
86
+++ b/hw/misc/imx_ccm.c
87
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
88
freq = klass->get_clock_frequency(dev, clock);
89
}
90
91
- DPRINTF("(clock = %d) = %d\n", clock, freq);
92
+ DPRINTF("(clock = %d) = %u\n", clock, freq);
93
94
return freq;
95
}
96
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq)
97
freq = ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
98
(mfd * pd)) << 10;
99
100
- DPRINTF("(pllreg = 0x%08x, base_freq = %d) = %d\n", pllreg, base_freq,
101
+ DPRINTF("(pllreg = 0x%08x, base_freq = %u) = %d\n", pllreg, base_freq,
102
freq);
103
104
return freq;
105
--
106
2.20.1
107
108
diff view generated by jsdifflib
New patch
1
From: Alex Chen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201126111109.112238-4-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/imx6_ccm.c | 20 ++++++++++----------
13
hw/misc/imx6_src.c | 2 +-
14
2 files changed, 11 insertions(+), 11 deletions(-)
15
16
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/imx6_ccm.c
19
+++ b/hw/misc/imx6_ccm.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx6_ccm_reg_name(uint32_t reg)
21
case CCM_CMEOR:
22
return "CMEOR";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
27
}
28
}
29
@@ -XXX,XX +XXX,XX @@ static const char *imx6_analog_reg_name(uint32_t reg)
30
case USB_ANALOG_DIGPROG:
31
return "USB_ANALOG_DIGPROG";
32
default:
33
- sprintf(unknown, "%d ?", reg);
34
+ sprintf(unknown, "%u ?", reg);
35
return unknown;
36
}
37
}
38
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev)
39
freq *= 20;
40
}
41
42
- DPRINTF("freq = %d\n", (uint32_t)freq);
43
+ DPRINTF("freq = %u\n", (uint32_t)freq);
44
45
return freq;
46
}
47
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev)
48
freq = imx6_analog_get_pll2_clk(dev) * 18
49
/ EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC);
50
51
- DPRINTF("freq = %d\n", (uint32_t)freq);
52
+ DPRINTF("freq = %u\n", (uint32_t)freq);
53
54
return freq;
55
}
56
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev)
57
freq = imx6_analog_get_pll2_clk(dev) * 18
58
/ EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC);
59
60
- DPRINTF("freq = %d\n", (uint32_t)freq);
61
+ DPRINTF("freq = %u\n", (uint32_t)freq);
62
63
return freq;
64
}
65
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev)
66
break;
67
}
68
69
- DPRINTF("freq = %d\n", (uint32_t)freq);
70
+ DPRINTF("freq = %u\n", (uint32_t)freq);
71
72
return freq;
73
}
74
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev)
75
freq = imx6_analog_get_periph_clk(dev)
76
/ (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF));
77
78
- DPRINTF("freq = %d\n", (uint32_t)freq);
79
+ DPRINTF("freq = %u\n", (uint32_t)freq);
80
81
return freq;
82
}
83
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev)
84
freq = imx6_ccm_get_ahb_clk(dev)
85
/ (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF));
86
87
- DPRINTF("freq = %d\n", (uint32_t)freq);
88
+ DPRINTF("freq = %u\n", (uint32_t)freq);
89
90
return freq;
91
}
92
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev)
93
freq = imx6_ccm_get_ipg_clk(dev)
94
/ (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF));
95
96
- DPRINTF("freq = %d\n", (uint32_t)freq);
97
+ DPRINTF("freq = %u\n", (uint32_t)freq);
98
99
return freq;
100
}
101
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
102
break;
103
}
104
105
- DPRINTF("Clock = %d) = %d\n", clock, freq);
106
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
107
108
return freq;
109
}
110
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/hw/misc/imx6_src.c
113
+++ b/hw/misc/imx6_src.c
114
@@ -XXX,XX +XXX,XX @@ static const char *imx6_src_reg_name(uint32_t reg)
115
case SRC_GPR10:
116
return "SRC_GPR10";
117
default:
118
- sprintf(unknown, "%d ?", reg);
119
+ sprintf(unknown, "%u ?", reg);
120
return unknown;
121
}
122
}
123
--
124
2.20.1
125
126
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Alex Chen <alex.chen@huawei.com>
2
2
3
The linux-headers/asm-arm/unistd.h file has been split in three
3
We should use printf format specifier "%u" instead of "%d" for
4
sub-files, copy them along. However, building them requires
4
argument of type "unsigned int".
5
setting ARCH rather than SRCARCH.
6
5
7
SRCARCH defaults to $(ARCH) anyway; to avoid future occurrence of
6
Reported-by: Euler Robot <euler.robot@huawei.com>
8
the same problem use ARCH for all architectures where SRCARCH=ARCH.
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
9
Currently these are all except x86, sparc, sh and tile.
8
Message-id: 20201126111109.112238-5-alex.chen@huawei.com
10
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12
Message-id: 20170221122920.16245-2-pbonzini@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
scripts/update-linux-headers.sh | 13 ++++++++++++-
12
hw/misc/imx6ul_ccm.c | 4 ++--
16
1 file changed, 12 insertions(+), 1 deletion(-)
13
1 file changed, 2 insertions(+), 2 deletions(-)
17
14
18
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
15
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
19
index XXXXXXX..XXXXXXX 100755
16
index XXXXXXX..XXXXXXX 100644
20
--- a/scripts/update-linux-headers.sh
17
--- a/hw/misc/imx6ul_ccm.c
21
+++ b/scripts/update-linux-headers.sh
18
+++ b/hw/misc/imx6ul_ccm.c
22
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
19
@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_ccm_reg_name(uint32_t reg)
23
continue
20
case CCM_CMEOR:
24
fi
21
return "CMEOR";
25
22
default:
26
- make -C "$linux" INSTALL_HDR_PATH="$tmpdir" SRCARCH=$arch headers_install
23
- sprintf(unknown, "%d ?", reg);
27
+ if [ "$arch" = x86 ]; then
24
+ sprintf(unknown, "%u ?", reg);
28
+ arch_var=SRCARCH
25
return unknown;
29
+ else
26
}
30
+ arch_var=ARCH
27
}
31
+ fi
28
@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_analog_reg_name(uint32_t reg)
32
+
29
case USB_ANALOG_DIGPROG:
33
+ make -C "$linux" INSTALL_HDR_PATH="$tmpdir" $arch_var=$arch headers_install
30
return "USB_ANALOG_DIGPROG";
34
31
default:
35
rm -rf "$output/linux-headers/asm-$arch"
32
- sprintf(unknown, "%d ?", reg);
36
mkdir -p "$output/linux-headers/asm-$arch"
33
+ sprintf(unknown, "%u ?", reg);
37
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
34
return unknown;
38
cp_portable "$tmpdir/include/asm/kvm_virtio.h" "$output/include/standard-headers/asm-s390/"
35
}
39
cp_portable "$tmpdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/"
36
}
40
fi
41
+ if [ $arch = arm ]; then
42
+ cp "$tmpdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/"
43
+ cp "$tmpdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/"
44
+ cp "$tmpdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/"
45
+ fi
46
if [ $arch = x86 ]; then
47
cp_portable "$tmpdir/include/asm/hyperv.h" "$output/include/standard-headers/asm-x86/"
48
cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/"
49
--
37
--
50
2.7.4
38
2.20.1
51
39
52
40
diff view generated by jsdifflib
1
Make the NVIC device expose a memory region for its users
1
For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the
2
to map, rather than mapping itself into the system memory
2
Private Peripheral Bus range, which includes all of the memory mapped
3
space on realize, and get the one user (the ARMv7M object)
3
devices and registers that are part of the CPU itself, including the
4
to do this.
4
NVIC, systick timer, and debug and trace components like the Data
5
Watchpoint and Trace unit (DWT). Within this large region, the range
6
0xe000e000 to 0xe000efff is the System Control Space (NVIC, system
7
registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure
8
alias.
9
10
The architecture is clear that within the SCS unimplemented registers
11
should be RES0 for privileged accesses and generate BusFault for
12
unprivileged accesses, and we currently implement this.
13
14
It is less clear about how to handle accesses to unimplemented
15
regions of the wider PPB. Unprivileged accesses should definitely
16
cause BusFaults (R_DQQS), but the behaviour of privileged accesses is
17
not given as a general rule. However, the register definitions of
18
individual registers for components like the DWT all state that they
19
are RES0 if the relevant component is not implemented, so the
20
simplest way to provide that is to provide RAZ/WI for the whole range
21
for privileged accesses. (The v7M Arm ARM does say that reserved
22
registers should be UNK/SBZP.)
23
24
Expand the container MemoryRegion that the NVIC exposes so that
25
it covers the whole PPB space. This means:
26
* moving the address that the ARMV7M device maps it to down by
27
0xe000 bytes
28
* moving the off and the offsets within the container of all the
29
subregions forward by 0xe000 bytes
30
* adding a new default MemoryRegion that covers the whole container
31
at a lower priority than anything else and which provides the
32
RAZWI/BusFault behaviour
5
33
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1487604965-23220-7-git-send-email-peter.maydell@linaro.org
36
Message-id: 20201119215617.29887-2-peter.maydell@linaro.org
9
---
37
---
10
hw/arm/armv7m.c | 7 ++++++-
38
include/hw/intc/armv7m_nvic.h | 1 +
11
hw/intc/armv7m_nvic.c | 7 ++-----
39
hw/arm/armv7m.c | 2 +-
12
2 files changed, 8 insertions(+), 6 deletions(-)
40
hw/intc/armv7m_nvic.c | 78 ++++++++++++++++++++++++++++++-----
41
3 files changed, 69 insertions(+), 12 deletions(-)
13
42
43
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/include/hw/intc/armv7m_nvic.h
46
+++ b/include/hw/intc/armv7m_nvic.h
47
@@ -XXX,XX +XXX,XX @@ struct NVICState {
48
MemoryRegion systickmem;
49
MemoryRegion systick_ns_mem;
50
MemoryRegion container;
51
+ MemoryRegion defaultmem;
52
53
uint32_t num_irq;
54
qemu_irq excpout;
14
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
55
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
15
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/armv7m.c
57
--- a/hw/arm/armv7m.c
17
+++ b/hw/arm/armv7m.c
58
+++ b/hw/arm/armv7m.c
18
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
19
static void armv7m_realize(DeviceState *dev, Error **errp)
20
{
21
ARMv7MState *s = ARMV7M(dev);
22
+ SysBusDevice *sbd;
23
Error *err = NULL;
24
int i;
25
char **cpustr;
26
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
59
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
27
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
60
sysbus_connect_irq(sbd, 0,
28
29
/* Wire the NVIC up to the CPU */
30
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
31
+ sbd = SYS_BUS_DEVICE(&s->nvic);
32
+ sysbus_connect_irq(sbd, 0,
33
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
61
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
34
s->cpu->env.nvic = &s->nvic;
62
35
63
- memory_region_add_subregion(&s->container, 0xe000e000,
36
+ memory_region_add_subregion(&s->container, 0xe000e000,
64
+ memory_region_add_subregion(&s->container, 0xe0000000,
37
+ sysbus_mmio_get_region(sbd, 0));
65
sysbus_mmio_get_region(sbd, 0));
38
+
66
39
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
67
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
40
Object *obj = OBJECT(&s->bitband[i]);
41
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
42
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
43
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/intc/armv7m_nvic.c
70
--- a/hw/intc/armv7m_nvic.c
45
+++ b/hw/intc/armv7m_nvic.c
71
+++ b/hw/intc/armv7m_nvic.c
46
@@ -XXX,XX +XXX,XX @@
72
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
47
#include "hw/arm/arm.h"
73
.endianness = DEVICE_NATIVE_ENDIAN,
48
#include "hw/arm/armv7m_nvic.h"
74
};
49
#include "target/arm/cpu.h"
75
50
-#include "exec/address-spaces.h"
76
+/*
51
#include "qemu/log.h"
77
+ * Unassigned portions of the PPB space are RAZ/WI for privileged
52
#include "trace.h"
78
+ * accesses, and fault for non-privileged accesses.
53
79
+ */
80
+static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
81
+ uint64_t *data, unsigned size,
82
+ MemTxAttrs attrs)
83
+{
84
+ qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
85
+ (uint32_t)addr);
86
+ if (attrs.user) {
87
+ return MEMTX_ERROR;
88
+ }
89
+ *data = 0;
90
+ return MEMTX_OK;
91
+}
92
+
93
+static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
94
+ uint64_t value, unsigned size,
95
+ MemTxAttrs attrs)
96
+{
97
+ qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
98
+ (uint32_t)addr);
99
+ if (attrs.user) {
100
+ return MEMTX_ERROR;
101
+ }
102
+ return MEMTX_OK;
103
+}
104
+
105
+static const MemoryRegionOps ppb_default_ops = {
106
+ .read_with_attrs = ppb_default_read,
107
+ .write_with_attrs = ppb_default_write,
108
+ .endianness = DEVICE_NATIVE_ENDIAN,
109
+ .valid.min_access_size = 1,
110
+ .valid.max_access_size = 8,
111
+};
112
+
113
static int nvic_post_load(void *opaque, int version_id)
114
{
115
NVICState *s = opaque;
116
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
117
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
118
{
119
NVICState *s = NVIC(dev);
120
- int regionlen;
121
122
/* The armv7m container object will have set our CPU pointer */
123
if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
54
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
124
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
125
M_REG_S));
126
}
127
128
- /* The NVIC and System Control Space (SCS) starts at 0xe000e000
129
+ /*
130
+ * This device provides a single sysbus memory region which
131
+ * represents the whole of the "System PPB" space. This is the
132
+ * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
133
+ * the System Control Space (system registers), the systick timer,
134
+ * and for CPUs with the Security extension an NS banked version
135
+ * of all of these.
136
+ *
137
+ * The default behaviour for unimplemented registers/ranges
138
+ * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
139
+ * is to RAZ/WI for privileged access and BusFault for non-privileged
140
+ * access.
141
+ *
142
+ * The NVIC and System Control Space (SCS) starts at 0xe000e000
143
* and looks like this:
144
* 0x004 - ICTR
145
* 0x010 - 0xff - systick
146
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
147
* generally code determining which banked register to use should
148
* use attrs.secure; code determining actual behaviour of the system
149
* should use env->v7m.secure.
150
+ *
151
+ * The container covers the whole PPB space. Within it the priority
152
+ * of overlapping regions is:
153
+ * - default region (for RAZ/WI and BusFault) : -1
154
+ * - system register regions : 0
155
+ * - systick : 1
156
+ * This is because the systick device is a small block of registers
157
+ * in the middle of the other system control registers.
158
*/
159
- regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
160
- memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
161
- /* The system register region goes at the bottom of the priority
162
- * stack as it covers the whole page.
163
- */
164
+ memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
165
+ memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
166
+ "nvic-default", 0x100000);
167
+ memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
168
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
55
"nvic_sysregs", 0x1000);
169
"nvic_sysregs", 0x1000);
56
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
170
- memory_region_add_subregion(&s->container, 0, &s->sysregmem);
57
171
+ memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
58
- /* Map the whole thing into system memory at the location required
172
59
- * by the v7M architecture.
173
memory_region_init_io(&s->systickmem, OBJECT(s),
60
- */
174
&nvic_systick_ops, s,
61
- memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
175
"nvic_systick", 0xe0);
62
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
176
63
+
177
- memory_region_add_subregion_overlap(&s->container, 0x10,
64
s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
178
+ memory_region_add_subregion_overlap(&s->container, 0xe010,
65
}
179
&s->systickmem, 1);
180
181
if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
182
memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
183
&nvic_sysreg_ns_ops, &s->sysregmem,
184
"nvic_sysregs_ns", 0x1000);
185
- memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
186
+ memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
187
memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
188
&nvic_sysreg_ns_ops, &s->systickmem,
189
"nvic_systick_ns", 0xe0);
190
- memory_region_add_subregion_overlap(&s->container, 0x20010,
191
+ memory_region_add_subregion_overlap(&s->container, 0x2e010,
192
&s->systick_ns_mem, 1);
193
}
66
194
67
--
195
--
68
2.7.4
196
2.20.1
69
197
70
198
diff view generated by jsdifflib
New patch
1
In v8.1M the PXN architecture extension adds a new PXN bit to the
2
MPU_RLAR registers, which forbids execution of code in the region
3
from a privileged mode.
1
4
5
This is another feature which is just in the generic "in v8.1M" set
6
and has no ID register field indicating its presence.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20201119215617.29887-3-peter.maydell@linaro.org
11
---
12
target/arm/helper.c | 7 ++++++-
13
1 file changed, 6 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
20
} else {
21
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
22
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
23
+ bool pxn = false;
24
+
25
+ if (arm_feature(env, ARM_FEATURE_V8_1M)) {
26
+ pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
27
+ }
28
29
if (m_is_system_region(env, address)) {
30
/* System space is always execute never */
31
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
32
}
33
34
*prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
35
- if (*prot && !xn) {
36
+ if (*prot && !xn && !(pxn && !is_user)) {
37
*prot |= PAGE_EXEC;
38
}
39
/* We don't need to look the attribute up in the MAIR0/MAIR1
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
1
Abstract the "load kernel" code out of armv7m_init() into its own
1
In arm_cpu_realizefn() we check whether the board code disabled EL3
2
function. This includes the registration of the CPU reset function,
2
via the has_el3 CPU object property, which we create if the CPU
3
to parallel how we handle this for A profile cores.
3
starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then
4
we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
5
the ID_PFR1 and ID_AA64PFR0 registers.
4
6
5
We make the function public so that boards which choose to
7
This codepath was incorrectly being taken for M-profile CPUs, which
6
directly instantiate an ARMv7M device object can call it.
8
do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
9
the M-profile Security extension and so should have non-zero values
10
in the ID_PFR1.Security field.
11
12
Restrict the handling of the feature flag to A/R-profile cores.
7
13
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
16
Message-id: 20201119215617.29887-4-peter.maydell@linaro.org
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
13
---
17
---
14
include/hw/arm/arm.h | 12 ++++++++++++
18
target/arm/cpu.c | 2 +-
15
hw/arm/armv7m.c | 23 ++++++++++++++++++-----
19
1 file changed, 1 insertion(+), 1 deletion(-)
16
2 files changed, 30 insertions(+), 5 deletions(-)
17
20
18
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/arm.h
23
--- a/target/arm/cpu.c
21
+++ b/include/hw/arm/arm.h
24
+++ b/target/arm/cpu.c
22
@@ -XXX,XX +XXX,XX @@ typedef enum {
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
23
/* armv7m.c */
24
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
25
const char *kernel_filename, const char *cpu_model);
26
+/**
27
+ * armv7m_load_kernel:
28
+ * @cpu: CPU
29
+ * @kernel_filename: file to load
30
+ * @mem_size: mem_size: maximum image size to load
31
+ *
32
+ * Load the guest image for an ARMv7M system. This must be called by
33
+ * any ARMv7M board, either directly or via armv7m_init(). (This is
34
+ * necessary to ensure that the CPU resets correctly on system reset,
35
+ * as well as for kernel loading.)
36
+ */
37
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
38
39
/*
40
* struct used as a parameter of the arm_load_kernel machine init
41
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/armv7m.c
44
+++ b/hw/arm/armv7m.c
45
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
46
ARMCPU *cpu;
47
CPUARMState *env;
48
DeviceState *nvic;
49
- int image_size;
50
- uint64_t entry;
51
- uint64_t lowaddr;
52
- int big_endian;
53
54
if (cpu_model == NULL) {
55
    cpu_model = "cortex-m3";
56
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
57
qdev_init_nofail(nvic);
58
sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
59
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
60
+ armv7m_load_kernel(cpu, kernel_filename, mem_size);
61
+ return nvic;
62
+}
63
+
64
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
65
+{
66
+ int image_size;
67
+ uint64_t entry;
68
+ uint64_t lowaddr;
69
+ int big_endian;
70
71
#ifdef TARGET_WORDS_BIGENDIAN
72
big_endian = 1;
73
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
74
}
26
}
75
}
27
}
76
28
77
+ /* CPU objects (unlike devices) are not automatically reset on system
29
- if (!cpu->has_el3) {
78
+ * reset, so we must always register a handler to do so. Unlike
30
+ if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
79
+ * A-profile CPUs, we don't need to do anything special in the
31
/* If the has_el3 CPU property is disabled then we need to disable the
80
+ * handler to arrange that it starts correctly.
32
* feature.
81
+ * This is arguably the wrong place to do this, but it matches the
33
*/
82
+ * way A-profile does it. Note that this means that every M profile
83
+ * board must call this function!
84
+ */
85
qemu_register_reset(armv7m_reset, cpu);
86
- return nvic;
87
}
88
89
static Property bitband_properties[] = {
90
--
34
--
91
2.7.4
35
2.20.1
92
36
93
37
diff view generated by jsdifflib
New patch
1
1
Implement the v8.1M VSCCLRM insn, which zeros floating point
2
registers if there is an active floating point context.
3
This requires support in write_neon_element32() for the MO_32
4
element size, so add it.
5
6
Because we want to use arm_gen_condlabel(), we need to move
7
the definition of that function up in translate.c so it is
8
before the #include of translate-vfp.c.inc.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20201119215617.29887-5-peter.maydell@linaro.org
13
---
14
target/arm/cpu.h | 9 ++++
15
target/arm/m-nocp.decode | 8 +++-
16
target/arm/translate.c | 21 +++++----
17
target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++
18
4 files changed, 111 insertions(+), 11 deletions(-)
19
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
25
return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
26
}
27
28
+static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
29
+{
30
+ /*
31
+ * Return true if M-profile state handling insns
32
+ * (VSCCLRM, CLRM, FPCTX access insns) are implemented
33
+ */
34
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
35
+}
36
+
37
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
38
{
39
/* Sadly this is encoded differently for A-profile and M-profile */
40
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/m-nocp.decode
43
+++ b/target/arm/m-nocp.decode
44
@@ -XXX,XX +XXX,XX @@
45
# If the coprocessor is not present or disabled then we will generate
46
# the NOCP exception; otherwise we let the insn through to the main decode.
47
48
+%vd_dp 22:1 12:4
49
+%vd_sp 12:4 22:1
50
+
51
&nocp cp
52
53
{
54
# Special cases which do not take an early NOCP: VLLDM and VLSTM
55
VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
56
- # TODO: VSCCLRM (new in v8.1M) is similar:
57
- #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0
58
+ # VSCCLRM (new in v8.1M) is similar:
59
+ VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3
60
+ VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2
61
62
NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
63
NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
64
diff --git a/target/arm/translate.c b/target/arm/translate.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/translate.c
67
+++ b/target/arm/translate.c
68
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
69
a64_translate_init();
70
}
71
72
+/* Generate a label used for skipping this instruction */
73
+static void arm_gen_condlabel(DisasContext *s)
74
+{
75
+ if (!s->condjmp) {
76
+ s->condlabel = gen_new_label();
77
+ s->condjmp = 1;
78
+ }
79
+}
80
+
81
/* Flags for the disas_set_da_iss info argument:
82
* lower bits hold the Rt register number, higher bits are flags.
83
*/
84
@@ -XXX,XX +XXX,XX @@ static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
85
long off = neon_element_offset(reg, ele, memop);
86
87
switch (memop) {
88
+ case MO_32:
89
+ tcg_gen_st32_i64(src, cpu_env, off);
90
+ break;
91
case MO_64:
92
tcg_gen_st_i64(src, cpu_env, off);
93
break;
94
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
95
s->base.is_jmp = DISAS_UPDATE_EXIT;
96
}
97
98
-/* Generate a label used for skipping this instruction */
99
-static void arm_gen_condlabel(DisasContext *s)
100
-{
101
- if (!s->condjmp) {
102
- s->condlabel = gen_new_label();
103
- s->condjmp = 1;
104
- }
105
-}
106
-
107
/* Skip this instruction if the ARM condition is false */
108
static void arm_skip_unless(DisasContext *s, uint32_t cond)
109
{
110
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/translate-vfp.c.inc
113
+++ b/target/arm/translate-vfp.c.inc
114
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
115
return true;
116
}
117
118
+static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
119
+{
120
+ int btmreg, topreg;
121
+ TCGv_i64 zero;
122
+ TCGv_i32 aspen, sfpa;
123
+
124
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
125
+ /* Before v8.1M, fall through in decode to NOCP check */
126
+ return false;
127
+ }
128
+
129
+ /* Explicitly UNDEF because this takes precedence over NOCP */
130
+ if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
131
+ unallocated_encoding(s);
132
+ return true;
133
+ }
134
+
135
+ if (!dc_isar_feature(aa32_vfp_simd, s)) {
136
+ /* NOP if we have neither FP nor MVE */
137
+ return true;
138
+ }
139
+
140
+ /*
141
+ * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
142
+ * active floating point context so we must NOP (without doing
143
+ * any lazy state preservation or the NOCP check).
144
+ */
145
+ aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
146
+ sfpa = load_cpu_field(v7m.control[M_REG_S]);
147
+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
148
+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
149
+ tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
150
+ tcg_gen_or_i32(sfpa, sfpa, aspen);
151
+ arm_gen_condlabel(s);
152
+ tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
153
+
154
+ if (s->fp_excp_el != 0) {
155
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
156
+ syn_uncategorized(), s->fp_excp_el);
157
+ return true;
158
+ }
159
+
160
+ topreg = a->vd + a->imm - 1;
161
+ btmreg = a->vd;
162
+
163
+ /* Convert to Sreg numbers if the insn specified in Dregs */
164
+ if (a->size == 3) {
165
+ topreg = topreg * 2 + 1;
166
+ btmreg *= 2;
167
+ }
168
+
169
+ if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
170
+ /* UNPREDICTABLE: we choose to undef */
171
+ unallocated_encoding(s);
172
+ return true;
173
+ }
174
+
175
+ /* Silently ignore requests to clear D16-D31 if they don't exist */
176
+ if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
177
+ topreg = 31;
178
+ }
179
+
180
+ if (!vfp_access_check(s)) {
181
+ return true;
182
+ }
183
+
184
+ /* Zero the Sregs from btmreg to topreg inclusive. */
185
+ zero = tcg_const_i64(0);
186
+ if (btmreg & 1) {
187
+ write_neon_element64(zero, btmreg >> 1, 1, MO_32);
188
+ btmreg++;
189
+ }
190
+ for (; btmreg + 1 <= topreg; btmreg += 2) {
191
+ write_neon_element64(zero, btmreg >> 1, 0, MO_64);
192
+ }
193
+ if (btmreg == topreg) {
194
+ write_neon_element64(zero, btmreg >> 1, 0, MO_32);
195
+ btmreg++;
196
+ }
197
+ assert(btmreg == topreg + 1);
198
+ /* TODO: when MVE is implemented, zero VPR here */
199
+ return true;
200
+}
201
+
202
static bool trans_NOCP(DisasContext *s, arg_nocp *a)
203
{
204
/*
205
--
206
2.20.1
207
208
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
2
the general-purpose registers and APSR. Implement this.
2
3
3
Provide a new function sdbus_reparent_card() in sd core for reparenting
4
The encoding is a subset of the LDMIA T2 encoding, using what would
4
a card from a SDBus to another one.
5
be Rn=0b1111 (which UNDEFs for LDMIA).
5
6
6
This function is required by the raspi platform, where the two SD
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
controllers can be dynamically switched.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201119215617.29887-6-peter.maydell@linaro.org
10
---
11
target/arm/t32.decode | 6 +++++-
12
target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
13
2 files changed, 43 insertions(+), 1 deletion(-)
8
14
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
15
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org
13
Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a doc comment to the header file; changed to
16
use new behaviour of qdev_set_parent_bus()]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/sd/sd.h | 11 +++++++++++
20
hw/sd/core.c | 27 +++++++++++++++++++++++++++
21
2 files changed, 38 insertions(+)
22
23
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/sd/sd.h
17
--- a/target/arm/t32.decode
26
+++ b/include/hw/sd/sd.h
18
+++ b/target/arm/t32.decode
27
@@ -XXX,XX +XXX,XX @@ uint8_t sdbus_read_data(SDBus *sd);
19
@@ -XXX,XX +XXX,XX @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot
28
bool sdbus_data_ready(SDBus *sd);
20
29
bool sdbus_get_inserted(SDBus *sd);
21
STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0
30
bool sdbus_get_readonly(SDBus *sd);
22
STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1
31
+/**
23
-LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
32
+ * sdbus_reparent_card: Reparent an SD card from one controller to another
24
+{
33
+ * @from: controller bus to remove card from
25
+ # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding
34
+ * @to: controller bus to move card to
26
+ CLRM 1110 1000 1001 1111 list:16
35
+ *
27
+ LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
36
+ * Reparent an SD card, effectively unplugging it from one controller
28
+}
37
+ * and inserting it into another. This is useful for SoCs like the
29
LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1
38
+ * bcm2835 which have two SD controllers and connect a single SD card
30
39
+ * to them, selected by the guest reprogramming GPIO line routing.
31
&rfe !extern rn w pu
40
+ */
32
diff --git a/target/arm/translate.c b/target/arm/translate.c
41
+void sdbus_reparent_card(SDBus *from, SDBus *to);
42
43
/* Functions to be used by SD devices to report back to qdevified controllers */
44
void sdbus_set_inserted(SDBus *sd, bool inserted);
45
diff --git a/hw/sd/core.c b/hw/sd/core.c
46
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/sd/core.c
34
--- a/target/arm/translate.c
48
+++ b/hw/sd/core.c
35
+++ b/target/arm/translate.c
49
@@ -XXX,XX +XXX,XX @@ void sdbus_set_readonly(SDBus *sdbus, bool readonly)
36
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
50
}
37
return do_ldm(s, a, 1);
51
}
38
}
52
39
53
+void sdbus_reparent_card(SDBus *from, SDBus *to)
40
+static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
54
+{
41
+{
55
+ SDState *card = get_card(from);
42
+ int i;
56
+ SDCardClass *sc;
43
+ TCGv_i32 zero;
57
+ bool readonly;
58
+
44
+
59
+ /* We directly reparent the card object rather than implementing this
45
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
60
+ * as a hotpluggable connection because we don't want to expose SD cards
46
+ return false;
61
+ * to users as being hotpluggable, and we can get away with it in this
62
+ * limited use case. This could perhaps be implemented more cleanly in
63
+ * future by adding support to the hotplug infrastructure for "device
64
+ * can be hotplugged only via code, not by user".
65
+ */
66
+
67
+ if (!card) {
68
+ return;
69
+ }
47
+ }
70
+
48
+
71
+ sc = SD_CARD_GET_CLASS(card);
49
+ if (extract32(a->list, 13, 1)) {
72
+ readonly = sc->get_readonly(card);
50
+ return false;
51
+ }
73
+
52
+
74
+ sdbus_set_inserted(from, false);
53
+ if (!a->list) {
75
+ qdev_set_parent_bus(DEVICE(card), &to->qbus);
54
+ /* UNPREDICTABLE; we choose to UNDEF */
76
+ sdbus_set_inserted(to, true);
55
+ return false;
77
+ sdbus_set_readonly(to, readonly);
56
+ }
57
+
58
+ zero = tcg_const_i32(0);
59
+ for (i = 0; i < 15; i++) {
60
+ if (extract32(a->list, i, 1)) {
61
+ /* Clear R[i] */
62
+ tcg_gen_mov_i32(cpu_R[i], zero);
63
+ }
64
+ }
65
+ if (extract32(a->list, 15, 1)) {
66
+ /*
67
+ * Clear APSR (by calling the MSR helper with the same argument
68
+ * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
69
+ */
70
+ TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
71
+ gen_helper_v7m_msr(cpu_env, maskreg, zero);
72
+ tcg_temp_free_i32(maskreg);
73
+ }
74
+ tcg_temp_free_i32(zero);
75
+ return true;
78
+}
76
+}
79
+
77
+
80
static const TypeInfo sd_bus_info = {
78
/*
81
.name = TYPE_SD_BUS,
79
* Branch, branch with link
82
.parent = TYPE_BUS,
80
*/
83
--
81
--
84
2.7.4
82
2.20.1
85
83
86
84
diff view generated by jsdifflib
New patch
1
For M-profile before v8.1M, the only valid register for VMSR/VMRS is
2
the FPSCR. We have a comment that states this, but the actual logic
3
to forbid accesses for any other register value is missing, so we
4
would end up with A-profile style behaviour. Add the missing check.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-7-peter.maydell@linaro.org
9
---
10
target/arm/translate-vfp.c.inc | 5 ++++-
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.c.inc
16
+++ b/target/arm/translate-vfp.c.inc
17
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
18
* Accesses to R15 are UNPREDICTABLE; we choose to undef.
19
* (FPSCR -> r15 is a special case which writes to the PSR flags.)
20
*/
21
- if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
22
+ if (a->reg != ARM_VFP_FPSCR) {
23
+ return false;
24
+ }
25
+ if (a->rt == 15 && !a->l) {
26
return false;
27
}
28
}
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
New patch
1
1
Currently M-profile borrows the A-profile code for VMSR and VMRS
2
(access to the FP system registers), because all it needs to support
3
is the FPSCR. In v8.1M things become significantly more complicated
4
in two ways:
5
6
* there are several new FP system registers; some have side effects
7
on read, and one (FPCXT_NS) needs to avoid the usual
8
vfp_access_check() and the "only if FPU implemented" check
9
10
* all sysregs are now accessible both by VMRS/VMSR (which
11
reads/writes a general purpose register) and also by VLDR/VSTR
12
(which reads/writes them directly to memory)
13
14
Refactor the structure of how we handle VMSR/VMRS to cope with this:
15
16
* keep the M-profile code entirely separate from the A-profile code
17
18
* abstract out the "read or write the general purpose register" part
19
of the code into a loadfn or storefn function pointer, so we can
20
reuse it for VLDR/VSTR.
21
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Message-id: 20201119215617.29887-8-peter.maydell@linaro.org
25
---
26
target/arm/cpu.h | 3 +
27
target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++---
28
2 files changed, 171 insertions(+), 14 deletions(-)
29
30
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu.h
33
+++ b/target/arm/cpu.h
34
@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
35
#define ARM_VFP_FPINST 9
36
#define ARM_VFP_FPINST2 10
37
38
+/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
39
+#define QEMU_VFP_FPSCR_NZCV 0xffff
40
+
41
/* iwMMXt coprocessor control registers. */
42
#define ARM_IWMMXT_wCID 0
43
#define ARM_IWMMXT_wCon 1
44
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate-vfp.c.inc
47
+++ b/target/arm/translate-vfp.c.inc
48
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
49
return true;
50
}
51
52
+/*
53
+ * M-profile provides two different sets of instructions that can
54
+ * access floating point system registers: VMSR/VMRS (which move
55
+ * to/from a general purpose register) and VLDR/VSTR sysreg (which
56
+ * move directly to/from memory). In some cases there are also side
57
+ * effects which must happen after any write to memory (which could
58
+ * cause an exception). So we implement the common logic for the
59
+ * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(),
60
+ * which take pointers to callback functions which will perform the
61
+ * actual "read/write general purpose register" and "read/write
62
+ * memory" operations.
63
+ */
64
+
65
+/*
66
+ * Emit code to store the sysreg to its final destination; frees the
67
+ * TCG temp 'value' it is passed.
68
+ */
69
+typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value);
70
+/*
71
+ * Emit code to load the value to be copied to the sysreg; returns
72
+ * a new TCG temporary
73
+ */
74
+typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque);
75
+
76
+/* Common decode/access checks for fp sysreg read/write */
77
+typedef enum FPSysRegCheckResult {
78
+ FPSysRegCheckFailed, /* caller should return false */
79
+ FPSysRegCheckDone, /* caller should return true */
80
+ FPSysRegCheckContinue, /* caller should continue generating code */
81
+} FPSysRegCheckResult;
82
+
83
+static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
84
+{
85
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
86
+ return FPSysRegCheckFailed;
87
+ }
88
+
89
+ switch (regno) {
90
+ case ARM_VFP_FPSCR:
91
+ case QEMU_VFP_FPSCR_NZCV:
92
+ break;
93
+ default:
94
+ return FPSysRegCheckFailed;
95
+ }
96
+
97
+ if (!vfp_access_check(s)) {
98
+ return FPSysRegCheckDone;
99
+ }
100
+
101
+ return FPSysRegCheckContinue;
102
+}
103
+
104
+static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
105
+
106
+ fp_sysreg_loadfn *loadfn,
107
+ void *opaque)
108
+{
109
+ /* Do a write to an M-profile floating point system register */
110
+ TCGv_i32 tmp;
111
+
112
+ switch (fp_sysreg_checks(s, regno)) {
113
+ case FPSysRegCheckFailed:
114
+ return false;
115
+ case FPSysRegCheckDone:
116
+ return true;
117
+ case FPSysRegCheckContinue:
118
+ break;
119
+ }
120
+
121
+ switch (regno) {
122
+ case ARM_VFP_FPSCR:
123
+ tmp = loadfn(s, opaque);
124
+ gen_helper_vfp_set_fpscr(cpu_env, tmp);
125
+ tcg_temp_free_i32(tmp);
126
+ gen_lookup_tb(s);
127
+ break;
128
+ default:
129
+ g_assert_not_reached();
130
+ }
131
+ return true;
132
+}
133
+
134
+static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
135
+ fp_sysreg_storefn *storefn,
136
+ void *opaque)
137
+{
138
+ /* Do a read from an M-profile floating point system register */
139
+ TCGv_i32 tmp;
140
+
141
+ switch (fp_sysreg_checks(s, regno)) {
142
+ case FPSysRegCheckFailed:
143
+ return false;
144
+ case FPSysRegCheckDone:
145
+ return true;
146
+ case FPSysRegCheckContinue:
147
+ break;
148
+ }
149
+
150
+ switch (regno) {
151
+ case ARM_VFP_FPSCR:
152
+ tmp = tcg_temp_new_i32();
153
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
154
+ storefn(s, opaque, tmp);
155
+ break;
156
+ case QEMU_VFP_FPSCR_NZCV:
157
+ /*
158
+ * Read just NZCV; this is a special case to avoid the
159
+ * helper call for the "VMRS to CPSR.NZCV" insn.
160
+ */
161
+ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
162
+ tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
163
+ storefn(s, opaque, tmp);
164
+ break;
165
+ default:
166
+ g_assert_not_reached();
167
+ }
168
+ return true;
169
+}
170
+
171
+static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value)
172
+{
173
+ arg_VMSR_VMRS *a = opaque;
174
+
175
+ if (a->rt == 15) {
176
+ /* Set the 4 flag bits in the CPSR */
177
+ gen_set_nzcv(value);
178
+ tcg_temp_free_i32(value);
179
+ } else {
180
+ store_reg(s, a->rt, value);
181
+ }
182
+}
183
+
184
+static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque)
185
+{
186
+ arg_VMSR_VMRS *a = opaque;
187
+
188
+ return load_reg(s, a->rt);
189
+}
190
+
191
+static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
192
+{
193
+ /*
194
+ * Accesses to R15 are UNPREDICTABLE; we choose to undef.
195
+ * FPSCR -> r15 is a special case which writes to the PSR flags;
196
+ * set a->reg to a special value to tell gen_M_fp_sysreg_read()
197
+ * we only care about the top 4 bits of FPSCR there.
198
+ */
199
+ if (a->rt == 15) {
200
+ if (a->l && a->reg == ARM_VFP_FPSCR) {
201
+ a->reg = QEMU_VFP_FPSCR_NZCV;
202
+ } else {
203
+ return false;
204
+ }
205
+ }
206
+
207
+ if (a->l) {
208
+ /* VMRS, move FP system register to gp register */
209
+ return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
210
+ } else {
211
+ /* VMSR, move gp register to FP system register */
212
+ return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
213
+ }
214
+}
215
+
216
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
217
{
218
TCGv_i32 tmp;
219
bool ignore_vfp_enabled = false;
220
221
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
222
- return false;
223
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
224
+ return gen_M_VMSR_VMRS(s, a);
225
}
226
227
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
228
- /*
229
- * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
230
- * Accesses to R15 are UNPREDICTABLE; we choose to undef.
231
- * (FPSCR -> r15 is a special case which writes to the PSR flags.)
232
- */
233
- if (a->reg != ARM_VFP_FPSCR) {
234
- return false;
235
- }
236
- if (a->rt == 15 && !a->l) {
237
- return false;
238
- }
239
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
240
+ return false;
241
}
242
243
switch (a->reg) {
244
--
245
2.20.1
246
247
diff view generated by jsdifflib
1
Instead of the bitband device doing a cpu_physical_memory_read/write,
1
The constant-expander functions like negate, plus_2, etc, are
2
make it take a MemoryRegion which specifies where it should be
2
generally useful; move them up in translate.c so we can use them in
3
accessing, and use address_space_read/write to access the
3
the VFP/Neon decoders as well as in the A32/T32/T16 decoders.
4
corresponding AddressSpace.
5
6
Since this entails pretty much a rewrite, convert away from
7
old_mmio in the process.
8
4
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
7
Message-id: 20201119215617.29887-9-peter.maydell@linaro.org
12
---
8
---
13
include/hw/arm/armv7m.h | 2 +
9
target/arm/translate.c | 46 +++++++++++++++++++++++-------------------
14
hw/arm/armv7m.c | 166 +++++++++++++++++++++++-------------------------
10
1 file changed, 25 insertions(+), 21 deletions(-)
15
2 files changed, 81 insertions(+), 87 deletions(-)
16
11
17
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
12
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/armv7m.h
14
--- a/target/arm/translate.c
20
+++ b/include/hw/arm/armv7m.h
15
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct {
16
@@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s)
22
SysBusDevice parent_obj;
17
}
23
/*< public >*/
18
}
24
19
25
+ AddressSpace *source_as;
20
+/*
26
MemoryRegion iomem;
21
+ * Constant expanders for the decoders.
27
uint32_t base;
22
+ */
28
+ MemoryRegion *source_memory;
23
+
29
} BitBandState;
24
+static int negate(DisasContext *s, int x)
30
25
+{
31
#define TYPE_ARMV7M "armv7m"
26
+ return -x;
32
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
27
+}
33
index XXXXXXX..XXXXXXX 100644
28
+
34
--- a/hw/arm/armv7m.c
29
+static int plus_2(DisasContext *s, int x)
35
+++ b/hw/arm/armv7m.c
30
+{
36
@@ -XXX,XX +XXX,XX @@
31
+ return x + 2;
37
/* Bitbanded IO. Each word corresponds to a single bit. */
32
+}
38
33
+
39
/* Get the byte address of the real memory for a bitband access. */
34
+static int times_2(DisasContext *s, int x)
40
-static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
35
+{
41
+static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
36
+ return x * 2;
42
{
37
+}
43
- uint32_t res;
38
+
44
-
39
+static int times_4(DisasContext *s, int x)
45
- res = *(uint32_t *)opaque;
40
+{
46
- res |= (addr & 0x1ffffff) >> 5;
41
+ return x * 4;
47
- return res;
42
+}
48
-
43
+
44
/* Flags for the disas_set_da_iss info argument:
45
* lower bits hold the Rt register number, higher bits are flags.
46
*/
47
@@ -XXX,XX +XXX,XX @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
48
49
50
/*
51
- * Constant expanders for the decoders.
52
+ * Constant expanders used by T16/T32 decode
53
*/
54
55
-static int negate(DisasContext *s, int x)
56
-{
57
- return -x;
49
-}
58
-}
50
-
59
-
51
-static uint32_t bitband_readb(void *opaque, hwaddr offset)
60
-static int plus_2(DisasContext *s, int x)
52
-{
61
-{
53
- uint8_t v;
62
- return x + 2;
54
- cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
55
- return (v & (1 << ((offset >> 2) & 7))) != 0;
56
-}
63
-}
57
-
64
-
58
-static void bitband_writeb(void *opaque, hwaddr offset,
65
-static int times_2(DisasContext *s, int x)
59
- uint32_t value)
60
-{
66
-{
61
- uint32_t addr;
67
- return x * 2;
62
- uint8_t mask;
63
- uint8_t v;
64
- addr = bitband_addr(opaque, offset);
65
- mask = (1 << ((offset >> 2) & 7));
66
- cpu_physical_memory_read(addr, &v, 1);
67
- if (value & 1)
68
- v |= mask;
69
- else
70
- v &= ~mask;
71
- cpu_physical_memory_write(addr, &v, 1);
72
-}
68
-}
73
-
69
-
74
-static uint32_t bitband_readw(void *opaque, hwaddr offset)
70
-static int times_4(DisasContext *s, int x)
75
-{
71
-{
76
- uint32_t addr;
72
- return x * 4;
77
- uint16_t mask;
78
- uint16_t v;
79
- addr = bitband_addr(opaque, offset) & ~1;
80
- mask = (1 << ((offset >> 2) & 15));
81
- mask = tswap16(mask);
82
- cpu_physical_memory_read(addr, &v, 2);
83
- return (v & mask) != 0;
84
-}
73
-}
85
-
74
-
86
-static void bitband_writew(void *opaque, hwaddr offset,
75
/* Return only the rotation part of T32ExpandImm. */
87
- uint32_t value)
76
static int t32_expandimm_rot(DisasContext *s, int x)
88
-{
89
- uint32_t addr;
90
- uint16_t mask;
91
- uint16_t v;
92
- addr = bitband_addr(opaque, offset) & ~1;
93
- mask = (1 << ((offset >> 2) & 15));
94
- mask = tswap16(mask);
95
- cpu_physical_memory_read(addr, &v, 2);
96
- if (value & 1)
97
- v |= mask;
98
- else
99
- v &= ~mask;
100
- cpu_physical_memory_write(addr, &v, 2);
101
+ return s->base | (offset & 0x1ffffff) >> 5;
102
}
103
104
-static uint32_t bitband_readl(void *opaque, hwaddr offset)
105
+static MemTxResult bitband_read(void *opaque, hwaddr offset,
106
+ uint64_t *data, unsigned size, MemTxAttrs attrs)
107
{
77
{
108
- uint32_t addr;
109
- uint32_t mask;
110
- uint32_t v;
111
- addr = bitband_addr(opaque, offset) & ~3;
112
- mask = (1 << ((offset >> 2) & 31));
113
- mask = tswap32(mask);
114
- cpu_physical_memory_read(addr, &v, 4);
115
- return (v & mask) != 0;
116
+ BitBandState *s = opaque;
117
+ uint8_t buf[4];
118
+ MemTxResult res;
119
+ int bitpos, bit;
120
+ hwaddr addr;
121
+
122
+ assert(size <= 4);
123
+
124
+ /* Find address in underlying memory and round down to multiple of size */
125
+ addr = bitband_addr(s, offset) & (-size);
126
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
127
+ if (res) {
128
+ return res;
129
+ }
130
+ /* Bit position in the N bytes read... */
131
+ bitpos = (offset >> 2) & ((size * 8) - 1);
132
+ /* ...converted to byte in buffer and bit in byte */
133
+ bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
134
+ *data = bit;
135
+ return MEMTX_OK;
136
}
137
138
-static void bitband_writel(void *opaque, hwaddr offset,
139
- uint32_t value)
140
+static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
141
+ unsigned size, MemTxAttrs attrs)
142
{
143
- uint32_t addr;
144
- uint32_t mask;
145
- uint32_t v;
146
- addr = bitband_addr(opaque, offset) & ~3;
147
- mask = (1 << ((offset >> 2) & 31));
148
- mask = tswap32(mask);
149
- cpu_physical_memory_read(addr, &v, 4);
150
- if (value & 1)
151
- v |= mask;
152
- else
153
- v &= ~mask;
154
- cpu_physical_memory_write(addr, &v, 4);
155
+ BitBandState *s = opaque;
156
+ uint8_t buf[4];
157
+ MemTxResult res;
158
+ int bitpos, bit;
159
+ hwaddr addr;
160
+
161
+ assert(size <= 4);
162
+
163
+ /* Find address in underlying memory and round down to multiple of size */
164
+ addr = bitband_addr(s, offset) & (-size);
165
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
166
+ if (res) {
167
+ return res;
168
+ }
169
+ /* Bit position in the N bytes read... */
170
+ bitpos = (offset >> 2) & ((size * 8) - 1);
171
+ /* ...converted to byte in buffer and bit in byte */
172
+ bit = 1 << (bitpos & 7);
173
+ if (value & 1) {
174
+ buf[bitpos >> 3] |= bit;
175
+ } else {
176
+ buf[bitpos >> 3] &= ~bit;
177
+ }
178
+ return address_space_write(s->source_as, addr, attrs, buf, size);
179
}
180
181
static const MemoryRegionOps bitband_ops = {
182
- .old_mmio = {
183
- .read = { bitband_readb, bitband_readw, bitband_readl, },
184
- .write = { bitband_writeb, bitband_writew, bitband_writel, },
185
- },
186
+ .read_with_attrs = bitband_read,
187
+ .write_with_attrs = bitband_write,
188
.endianness = DEVICE_NATIVE_ENDIAN,
189
+ .impl.min_access_size = 1,
190
+ .impl.max_access_size = 4,
191
+ .valid.min_access_size = 1,
192
+ .valid.max_access_size = 4,
193
};
194
195
static void bitband_init(Object *obj)
196
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
197
BitBandState *s = BITBAND(obj);
198
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
199
200
- memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
201
+ object_property_add_link(obj, "source-memory",
202
+ TYPE_MEMORY_REGION,
203
+ (Object **)&s->source_memory,
204
+ qdev_prop_allow_set_link_before_realize,
205
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
206
+ &error_abort);
207
+ memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
208
"bitband", 0x02000000);
209
sysbus_init_mmio(dev, &s->iomem);
210
}
211
212
+static void bitband_realize(DeviceState *dev, Error **errp)
213
+{
214
+ BitBandState *s = BITBAND(dev);
215
+
216
+ if (!s->source_memory) {
217
+ error_setg(errp, "source-memory property not set");
218
+ return;
219
+ }
220
+
221
+ s->source_as = address_space_init_shareable(s->source_memory,
222
+ "bitband-source");
223
+}
224
+
225
/* Board init. */
226
227
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
228
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
229
error_propagate(errp, err);
230
return;
231
}
232
+ object_property_set_link(obj, OBJECT(s->board_memory),
233
+ "source-memory", &error_abort);
234
object_property_set_bool(obj, true, "realized", &err);
235
if (err != NULL) {
236
error_propagate(errp, err);
237
@@ -XXX,XX +XXX,XX @@ static void bitband_class_init(ObjectClass *klass, void *data)
238
{
239
DeviceClass *dc = DEVICE_CLASS(klass);
240
241
+ dc->realize = bitband_realize;
242
dc->props = bitband_properties;
243
}
244
245
--
78
--
246
2.7.4
79
2.20.1
247
80
248
81
diff view generated by jsdifflib
1
Create a proper QOM object for the armv7m container, which
1
Implement the new-in-v8.1M VLDR/VSTR variants which directly
2
holds the CPU, the NVIC and the bitband regions.
2
read or write FP system registers to memory.
3
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
6
Message-id: 20201119215617.29887-10-peter.maydell@linaro.org
7
---
7
---
8
include/hw/arm/armv7m.h | 51 ++++++++++++++++++
8
target/arm/vfp.decode | 14 ++++++
9
hw/arm/armv7m.c | 139 +++++++++++++++++++++++++++++++++++++++++++-----
9
target/arm/translate-vfp.c.inc | 91 ++++++++++++++++++++++++++++++++++
10
2 files changed, 178 insertions(+), 12 deletions(-)
10
2 files changed, 105 insertions(+)
11
create mode 100644 include/hw/arm/armv7m.h
12
11
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
12
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
14
new file mode 100644
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX
14
--- a/target/arm/vfp.decode
16
--- /dev/null
15
+++ b/target/arm/vfp.decode
17
+++ b/include/hw/arm/armv7m.h
16
@@ -XXX,XX +XXX,XX @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp
18
@@ -XXX,XX +XXX,XX @@
17
VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
19
+/*
18
VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
20
+ * ARMv7M CPU object
19
21
+ *
20
+# M-profile VLDR/VSTR to sysreg
22
+ * Copyright (c) 2017 Linaro Ltd
21
+%vldr_sysreg 22:1 13:3
23
+ * Written by Peter Maydell <peter.maydell@linaro.org>
22
+%imm7_0x4 0:7 !function=times_4
24
+ *
25
+ * This code is licensed under the GPL version 2 or later.
26
+ */
27
+
23
+
28
+#ifndef HW_ARM_ARMV7M_H
24
+&vldr_sysreg rn reg imm a w p
29
+#define HW_ARM_ARMV7M_H
25
+@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
26
+ reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg
30
+
27
+
31
+#include "hw/sysbus.h"
28
+# P=0 W=0 is SEE "Related encodings", so split into two patterns
32
+#include "hw/arm/armv7m_nvic.h"
29
+VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
30
+VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
31
+VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1
32
+VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
33
+
33
+
34
+#define TYPE_BITBAND "ARM,bitband-memory"
34
# We split the load/store multiple up into two patterns to avoid
35
+#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
35
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
36
# grouping:
37
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate-vfp.c.inc
40
+++ b/target/arm/translate-vfp.c.inc
41
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
42
return true;
43
}
44
45
+static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value)
46
+{
47
+ arg_vldr_sysreg *a = opaque;
48
+ uint32_t offset = a->imm;
49
+ TCGv_i32 addr;
36
+
50
+
37
+typedef struct {
51
+ if (!a->a) {
38
+ /*< private >*/
52
+ offset = - offset;
39
+ SysBusDevice parent_obj;
53
+ }
40
+ /*< public >*/
41
+
54
+
42
+ MemoryRegion iomem;
55
+ addr = load_reg(s, a->rn);
43
+ uint32_t base;
56
+ if (a->p) {
44
+} BitBandState;
57
+ tcg_gen_addi_i32(addr, addr, offset);
58
+ }
45
+
59
+
46
+#define TYPE_ARMV7M "armv7m"
60
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
47
+#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
61
+ gen_helper_v8m_stackcheck(cpu_env, addr);
62
+ }
48
+
63
+
49
+#define ARMV7M_NUM_BITBANDS 2
64
+ gen_aa32_st_i32(s, value, addr, get_mem_index(s),
65
+ MO_UL | MO_ALIGN | s->be_data);
66
+ tcg_temp_free_i32(value);
50
+
67
+
51
+/* ARMv7M container object.
68
+ if (a->w) {
52
+ * + Unnamed GPIO input lines: external IRQ lines for the NVIC
69
+ /* writeback */
53
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
70
+ if (!a->p) {
54
+ * + Property "cpu-model": CPU model to instantiate
71
+ tcg_gen_addi_i32(addr, addr, offset);
55
+ * + Property "num-irq": number of external IRQ lines
72
+ }
56
+ */
73
+ store_reg(s, a->rn, addr);
57
+typedef struct ARMv7MState {
74
+ } else {
58
+ /*< private >*/
75
+ tcg_temp_free_i32(addr);
59
+ SysBusDevice parent_obj;
60
+ /*< public >*/
61
+ NVICState nvic;
62
+ BitBandState bitband[ARMV7M_NUM_BITBANDS];
63
+ ARMCPU *cpu;
64
+
65
+ /* Properties */
66
+ char *cpu_model;
67
+} ARMv7MState;
68
+
69
+#endif
70
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/armv7m.c
73
+++ b/hw/arm/armv7m.c
74
@@ -XXX,XX +XXX,XX @@
75
*/
76
77
#include "qemu/osdep.h"
78
+#include "hw/arm/armv7m.h"
79
#include "qapi/error.h"
80
#include "qemu-common.h"
81
#include "cpu.h"
82
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bitband_ops = {
83
.endianness = DEVICE_NATIVE_ENDIAN,
84
};
85
86
-#define TYPE_BITBAND "ARM,bitband-memory"
87
-#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
88
-
89
-typedef struct {
90
- /*< private >*/
91
- SysBusDevice parent_obj;
92
- /*< public >*/
93
-
94
- MemoryRegion iomem;
95
- uint32_t base;
96
-} BitBandState;
97
-
98
static void bitband_init(Object *obj)
99
{
100
BitBandState *s = BITBAND(obj);
101
@@ -XXX,XX +XXX,XX @@ static void armv7m_bitband_init(void)
102
103
/* Board init. */
104
105
+static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
106
+ 0x20000000, 0x40000000
107
+};
108
+
109
+static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
110
+ 0x22000000, 0x42000000
111
+};
112
+
113
+static void armv7m_instance_init(Object *obj)
114
+{
115
+ ARMv7MState *s = ARMV7M(obj);
116
+ int i;
117
+
118
+ /* Can't init the cpu here, we don't yet know which model to use */
119
+
120
+ object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
121
+ qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
122
+ object_property_add_alias(obj, "num-irq",
123
+ OBJECT(&s->nvic), "num-irq", &error_abort);
124
+
125
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
126
+ object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
127
+ qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
128
+ }
76
+ }
129
+}
77
+}
130
+
78
+
131
+static void armv7m_realize(DeviceState *dev, Error **errp)
79
+static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque)
132
+{
80
+{
133
+ ARMv7MState *s = ARMV7M(dev);
81
+ arg_vldr_sysreg *a = opaque;
134
+ Error *err = NULL;
82
+ uint32_t offset = a->imm;
135
+ int i;
83
+ TCGv_i32 addr;
136
+ char **cpustr;
84
+ TCGv_i32 value = tcg_temp_new_i32();
137
+ ObjectClass *oc;
138
+ const char *typename;
139
+ CPUClass *cc;
140
+
85
+
141
+ cpustr = g_strsplit(s->cpu_model, ",", 2);
86
+ if (!a->a) {
142
+
87
+ offset = - offset;
143
+ oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
144
+ if (!oc) {
145
+ error_setg(errp, "Unknown CPU model %s", cpustr[0]);
146
+ g_strfreev(cpustr);
147
+ return;
148
+ }
88
+ }
149
+
89
+
150
+ cc = CPU_CLASS(oc);
90
+ addr = load_reg(s, a->rn);
151
+ typename = object_class_get_name(oc);
91
+ if (a->p) {
152
+ cc->parse_features(typename, cpustr[1], &err);
92
+ tcg_gen_addi_i32(addr, addr, offset);
153
+ g_strfreev(cpustr);
154
+ if (err) {
155
+ error_propagate(errp, err);
156
+ return;
157
+ }
93
+ }
158
+
94
+
159
+ s->cpu = ARM_CPU(object_new(typename));
95
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
160
+ if (!s->cpu) {
96
+ gen_helper_v8m_stackcheck(cpu_env, addr);
161
+ error_setg(errp, "Unknown CPU model %s", s->cpu_model);
162
+ return;
163
+ }
97
+ }
164
+
98
+
165
+ object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
99
+ gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
166
+ if (err != NULL) {
100
+ MO_UL | MO_ALIGN | s->be_data);
167
+ error_propagate(errp, err);
101
+
168
+ return;
102
+ if (a->w) {
103
+ /* writeback */
104
+ if (!a->p) {
105
+ tcg_gen_addi_i32(addr, addr, offset);
106
+ }
107
+ store_reg(s, a->rn, addr);
108
+ } else {
109
+ tcg_temp_free_i32(addr);
169
+ }
110
+ }
170
+
111
+ return value;
171
+ /* Note that we must realize the NVIC after the CPU */
172
+ object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
173
+ if (err != NULL) {
174
+ error_propagate(errp, err);
175
+ return;
176
+ }
177
+
178
+ /* Alias the NVIC's input and output GPIOs as our own so the board
179
+ * code can wire them up. (We do this in realize because the
180
+ * NVIC doesn't create the input GPIO array until realize.)
181
+ */
182
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
183
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
184
+
185
+ /* Wire the NVIC up to the CPU */
186
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
187
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
188
+ s->cpu->env.nvic = &s->nvic;
189
+
190
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
191
+ Object *obj = OBJECT(&s->bitband[i]);
192
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
193
+
194
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
195
+ if (err != NULL) {
196
+ error_propagate(errp, err);
197
+ return;
198
+ }
199
+ object_property_set_bool(obj, true, "realized", &err);
200
+ if (err != NULL) {
201
+ error_propagate(errp, err);
202
+ return;
203
+ }
204
+
205
+ sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
206
+ }
207
+}
112
+}
208
+
113
+
209
+static Property armv7m_properties[] = {
114
+static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
210
+ DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
211
+ DEFINE_PROP_END_OF_LIST(),
212
+};
213
+
214
+static void armv7m_class_init(ObjectClass *klass, void *data)
215
+{
115
+{
216
+ DeviceClass *dc = DEVICE_CLASS(klass);
116
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
217
+
117
+ return false;
218
+ dc->realize = armv7m_realize;
118
+ }
219
+ dc->props = armv7m_properties;
119
+ if (a->rn == 15) {
120
+ return false;
121
+ }
122
+ return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
220
+}
123
+}
221
+
124
+
222
+static const TypeInfo armv7m_info = {
125
+static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
223
+ .name = TYPE_ARMV7M,
126
+{
224
+ .parent = TYPE_SYS_BUS_DEVICE,
127
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ .instance_size = sizeof(ARMv7MState),
128
+ return false;
226
+ .instance_init = armv7m_instance_init,
129
+ }
227
+ .class_init = armv7m_class_init,
130
+ if (a->rn == 15) {
228
+};
131
+ return false;
132
+ }
133
+ return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
134
+}
229
+
135
+
230
static void armv7m_reset(void *opaque)
136
static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
231
{
137
{
232
ARMCPU *cpu = opaque;
138
TCGv_i32 tmp;
233
@@ -XXX,XX +XXX,XX @@ static const TypeInfo bitband_info = {
234
static void armv7m_register_types(void)
235
{
236
type_register_static(&bitband_info);
237
+ type_register_static(&armv7m_info);
238
}
239
240
type_init(armv7m_register_types)
241
--
139
--
242
2.7.4
140
2.20.1
243
141
244
142
diff view generated by jsdifflib
New patch
1
v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
2
like the existing FPSCR, except that it reads and writes only bits
3
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the
4
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
5
permitted.)
1
6
7
Implement the register. Since we don't yet implement MVE, we handle
8
the QC bit as RES0, with todo comments for where we will need to add
9
support later.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
14
---
15
target/arm/cpu.h | 13 +++++++++++++
16
target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++
17
2 files changed, 40 insertions(+)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
24
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
25
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
26
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
27
+#define FPCR_V (1 << 28) /* FP overflow flag */
28
+#define FPCR_C (1 << 29) /* FP carry flag */
29
+#define FPCR_Z (1 << 30) /* FP zero flag */
30
+#define FPCR_N (1 << 31) /* FP negative flag */
31
+
32
+#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
33
+#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
34
35
static inline uint32_t vfp_get_fpsr(CPUARMState *env)
36
{
37
@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
38
#define ARM_VFP_FPEXC 8
39
#define ARM_VFP_FPINST 9
40
#define ARM_VFP_FPINST2 10
41
+/* These ones are M-profile only */
42
+#define ARM_VFP_FPSCR_NZCVQC 2
43
+#define ARM_VFP_VPR 12
44
+#define ARM_VFP_P0 13
45
+#define ARM_VFP_FPCXT_NS 14
46
+#define ARM_VFP_FPCXT_S 15
47
48
/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
49
#define QEMU_VFP_FPSCR_NZCV 0xffff
50
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate-vfp.c.inc
53
+++ b/target/arm/translate-vfp.c.inc
54
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
55
case ARM_VFP_FPSCR:
56
case QEMU_VFP_FPSCR_NZCV:
57
break;
58
+ case ARM_VFP_FPSCR_NZCVQC:
59
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
60
+ return false;
61
+ }
62
+ break;
63
default:
64
return FPSysRegCheckFailed;
65
}
66
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
67
tcg_temp_free_i32(tmp);
68
gen_lookup_tb(s);
69
break;
70
+ case ARM_VFP_FPSCR_NZCVQC:
71
+ {
72
+ TCGv_i32 fpscr;
73
+ tmp = loadfn(s, opaque);
74
+ /*
75
+ * TODO: when we implement MVE, write the QC bit.
76
+ * For non-MVE, QC is RES0.
77
+ */
78
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
79
+ fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
80
+ tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
81
+ tcg_gen_or_i32(fpscr, fpscr, tmp);
82
+ store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
83
+ tcg_temp_free_i32(tmp);
84
+ break;
85
+ }
86
default:
87
g_assert_not_reached();
88
}
89
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
90
gen_helper_vfp_get_fpscr(tmp, cpu_env);
91
storefn(s, opaque, tmp);
92
break;
93
+ case ARM_VFP_FPSCR_NZCVQC:
94
+ /*
95
+ * TODO: MVE has a QC bit, which we probably won't store
96
+ * in the xregs[] field. For non-MVE, where QC is RES0,
97
+ * we can just fall through to the FPSCR_NZCV case.
98
+ */
99
case QEMU_VFP_FPSCR_NZCV:
100
/*
101
* Read just NZCV; this is a special case to avoid the
102
--
103
2.20.1
104
105
diff view generated by jsdifflib
New patch
1
We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
2
in the previous commit; use it in a couple of places in existing code,
3
where we're masking out everything except NZCV for the "load to Rt=15
4
sets CPSR.NZCV" special case.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
9
---
10
target/arm/translate-vfp.c.inc | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.c.inc
16
+++ b/target/arm/translate-vfp.c.inc
17
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
18
* helper call for the "VMRS to CPSR.NZCV" insn.
19
*/
20
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
21
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
22
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
23
storefn(s, opaque, tmp);
24
break;
25
default:
26
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
27
case ARM_VFP_FPSCR:
28
if (a->rt == 15) {
29
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
30
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
31
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
32
} else {
33
tmp = tcg_temp_new_i32();
34
gen_helper_vfp_get_fpscr(tmp, cpu_env);
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
1
The local variable 'nvic' in stm32f205_soc_realize() no longer
1
Factor out the code which handles M-profile lazy FP state preservation
2
holds a direct pointer to the NVIC device; it is a pointer to
2
from full_vfp_access_check(); accesses to the FPCXT_NS register are
3
the ARMv7M container object. Rename it 'armv7m' accordingly.
3
a special case which need to do just this part (corresponding in the
4
pseudocode to the PreserveFPState() function), and not the full
5
set of actions matching the pseudocode ExecuteFPCheck() which
6
normal FP instructions need to do.
4
7
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Message-id: 20201119215617.29887-13-peter.maydell@linaro.org
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 1487604965-23220-12-git-send-email-peter.maydell@linaro.org
10
---
12
---
11
hw/arm/stm32f205_soc.c | 18 +++++++++---------
13
target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++--------------
12
1 file changed, 9 insertions(+), 9 deletions(-)
14
1 file changed, 27 insertions(+), 18 deletions(-)
13
15
14
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
16
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/stm32f205_soc.c
18
--- a/target/arm/translate-vfp.c.inc
17
+++ b/hw/arm/stm32f205_soc.c
19
+++ b/target/arm/translate-vfp.c.inc
18
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)
19
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
21
return offs;
20
{
21
STM32F205State *s = STM32F205_SOC(dev_soc);
22
- DeviceState *dev, *nvic;
23
+ DeviceState *dev, *armv7m;
24
SysBusDevice *busdev;
25
Error *err = NULL;
26
int i;
27
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
28
vmstate_register_ram_global(sram);
29
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
30
31
- nvic = DEVICE(&s->armv7m);
32
- qdev_prop_set_uint32(nvic, "num-irq", 96);
33
- qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
34
+ armv7m = DEVICE(&s->armv7m);
35
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
36
+ qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
37
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
38
"memory", &error_abort);
39
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
40
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
41
}
42
busdev = SYS_BUS_DEVICE(dev);
43
sysbus_mmio_map(busdev, 0, 0x40013800);
44
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
45
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
46
47
/* Attach UART (uses USART registers) and USART controllers */
48
for (i = 0; i < STM_NUM_USARTS; i++) {
49
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
50
}
51
busdev = SYS_BUS_DEVICE(dev);
52
sysbus_mmio_map(busdev, 0, usart_addr[i]);
53
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
54
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
55
}
56
57
/* Timer 2 to 5 */
58
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
59
}
60
busdev = SYS_BUS_DEVICE(dev);
61
sysbus_mmio_map(busdev, 0, timer_addr[i]);
62
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
63
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
64
}
65
66
/* ADC 1 to 3 */
67
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
68
return;
69
}
70
qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
71
- qdev_get_gpio_in(nvic, ADC_IRQ));
72
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
73
74
for (i = 0; i < STM_NUM_ADCS; i++) {
75
dev = DEVICE(&(s->adc[i]));
76
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
77
}
78
busdev = SYS_BUS_DEVICE(dev);
79
sysbus_mmio_map(busdev, 0, spi_addr[i]);
80
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
81
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
82
}
83
}
22
}
84
23
24
+/*
25
+ * Generate code for M-profile lazy FP state preservation if needed;
26
+ * this corresponds to the pseudocode PreserveFPState() function.
27
+ */
28
+static void gen_preserve_fp_state(DisasContext *s)
29
+{
30
+ if (s->v7m_lspact) {
31
+ /*
32
+ * Lazy state saving affects external memory and also the NVIC,
33
+ * so we must mark it as an IO operation for icount (and cause
34
+ * this to be the last insn in the TB).
35
+ */
36
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
37
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
38
+ gen_io_start();
39
+ }
40
+ gen_helper_v7m_preserve_fp_state(cpu_env);
41
+ /*
42
+ * If the preserve_fp_state helper doesn't throw an exception
43
+ * then it will clear LSPACT; we don't need to repeat this for
44
+ * any further FP insns in this TB.
45
+ */
46
+ s->v7m_lspact = false;
47
+ }
48
+}
49
+
50
/*
51
* Check that VFP access is enabled. If it is, do the necessary
52
* M-profile lazy-FP handling and then return true.
53
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
54
/* Handle M-profile lazy FP state mechanics */
55
56
/* Trigger lazy-state preservation if necessary */
57
- if (s->v7m_lspact) {
58
- /*
59
- * Lazy state saving affects external memory and also the NVIC,
60
- * so we must mark it as an IO operation for icount (and cause
61
- * this to be the last insn in the TB).
62
- */
63
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
64
- s->base.is_jmp = DISAS_UPDATE_EXIT;
65
- gen_io_start();
66
- }
67
- gen_helper_v7m_preserve_fp_state(cpu_env);
68
- /*
69
- * If the preserve_fp_state helper doesn't throw an exception
70
- * then it will clear LSPACT; we don't need to repeat this for
71
- * any further FP insns in this TB.
72
- */
73
- s->v7m_lspact = false;
74
- }
75
+ gen_preserve_fp_state(s);
76
77
/* Update ownership of FP context: set FPCCR.S to match current state */
78
if (s->v8m_fpccr_s_wrong) {
85
--
79
--
86
2.7.4
80
2.20.1
87
81
88
82
diff view generated by jsdifflib
New patch
1
Implement the new-in-v8.1M FPCXT_S floating point system register.
2
This is for saving and restoring the secure floating point context,
3
and it reads and writes bits [27:0] from the FPSCR and the
4
CONTROL.SFPA bit in bit [31].
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-14-peter.maydell@linaro.org
9
---
10
target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++
11
1 file changed, 58 insertions(+)
12
13
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.c.inc
16
+++ b/target/arm/translate-vfp.c.inc
17
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
18
return false;
19
}
20
break;
21
+ case ARM_VFP_FPCXT_S:
22
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
23
+ return false;
24
+ }
25
+ if (!s->v8m_secure) {
26
+ return false;
27
+ }
28
+ break;
29
default:
30
return FPSysRegCheckFailed;
31
}
32
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
33
tcg_temp_free_i32(tmp);
34
break;
35
}
36
+ case ARM_VFP_FPCXT_S:
37
+ {
38
+ TCGv_i32 sfpa, control, fpscr;
39
+ /* Set FPSCR[27:0] and CONTROL.SFPA from value */
40
+ tmp = loadfn(s, opaque);
41
+ sfpa = tcg_temp_new_i32();
42
+ tcg_gen_shri_i32(sfpa, tmp, 31);
43
+ control = load_cpu_field(v7m.control[M_REG_S]);
44
+ tcg_gen_deposit_i32(control, control, sfpa,
45
+ R_V7M_CONTROL_SFPA_SHIFT, 1);
46
+ store_cpu_field(control, v7m.control[M_REG_S]);
47
+ fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
48
+ tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
49
+ tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
50
+ tcg_gen_or_i32(fpscr, fpscr, tmp);
51
+ store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
52
+ tcg_temp_free_i32(tmp);
53
+ tcg_temp_free_i32(sfpa);
54
+ break;
55
+ }
56
default:
57
g_assert_not_reached();
58
}
59
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
60
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
61
storefn(s, opaque, tmp);
62
break;
63
+ case ARM_VFP_FPCXT_S:
64
+ {
65
+ TCGv_i32 control, sfpa, fpscr;
66
+ /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
67
+ tmp = tcg_temp_new_i32();
68
+ sfpa = tcg_temp_new_i32();
69
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
70
+ tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
71
+ control = load_cpu_field(v7m.control[M_REG_S]);
72
+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
73
+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
74
+ tcg_gen_or_i32(tmp, tmp, sfpa);
75
+ tcg_temp_free_i32(sfpa);
76
+ /*
77
+ * Store result before updating FPSCR etc, in case
78
+ * it is a memory write which causes an exception.
79
+ */
80
+ storefn(s, opaque, tmp);
81
+ /*
82
+ * Now we must reset FPSCR from FPDSCR_NS, and clear
83
+ * CONTROL.SFPA; so we'll end the TB here.
84
+ */
85
+ tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
86
+ store_cpu_field(control, v7m.control[M_REG_S]);
87
+ fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
88
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
89
+ tcg_temp_free_i32(fpscr);
90
+ gen_lookup_tb(s);
91
+ break;
92
+ }
93
default:
94
g_assert_not_reached();
95
}
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
New patch
1
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it
2
gains new fields FZ16 (if half-precision floating point is supported)
3
and LTPSIZE (always reads as 4). Update the reset value and the code
4
that handles writes to this register accordingly.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
9
---
10
target/arm/cpu.h | 5 +++++
11
hw/intc/armv7m_nvic.c | 9 ++++++++-
12
target/arm/cpu.c | 3 +++
13
3 files changed, 16 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
20
#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
21
#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
22
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
23
+#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
24
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
25
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
26
+#define FPCR_AHP (1 << 26) /* Alternative half-precision */
27
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
28
#define FPCR_V (1 << 28) /* FP overflow flag */
29
#define FPCR_C (1 << 29) /* FP carry flag */
30
#define FPCR_Z (1 << 30) /* FP zero flag */
31
#define FPCR_N (1 << 31) /* FP negative flag */
32
33
+#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
34
+#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
35
+
36
#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
37
#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
38
39
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/intc/armv7m_nvic.c
42
+++ b/hw/intc/armv7m_nvic.c
43
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
44
break;
45
case 0xf3c: /* FPDSCR */
46
if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
47
- value &= 0x07c00000;
48
+ uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK;
49
+ if (cpu_isar_feature(any_fp16, cpu)) {
50
+ mask |= FPCR_FZ16;
51
+ }
52
+ value &= mask;
53
+ if (cpu_isar_feature(aa32_lob, cpu)) {
54
+ value |= 4 << FPCR_LTPSIZE_SHIFT;
55
+ }
56
cpu->env.v7m.fpdscr[attrs.secure] = value;
57
}
58
break;
59
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/cpu.c
62
+++ b/target/arm/cpu.c
63
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
64
* always reset to 4.
65
*/
66
env->v7m.ltpsize = 4;
67
+ /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
68
+ env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
69
+ env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
70
}
71
72
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
73
--
74
2.20.1
75
76
diff view generated by jsdifflib
New patch
1
In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
2
are zeroed for an exception taken to Non-secure state; for an
3
exception taken to Secure state they become UNKNOWN, and we chose to
4
leave them at their previous values.
1
5
6
In v8.1M the behaviour is specified more tightly and these registers
7
are always zeroed regardless of the security state that the exception
8
targets (see rule R_KPZV). Implement this.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
13
---
14
target/arm/m_helper.c | 16 ++++++++++++----
15
1 file changed, 12 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/m_helper.c
20
+++ b/target/arm/m_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
22
* Clear registers if necessary to prevent non-secure exception
23
* code being able to see register values from secure code.
24
* Where register values become architecturally UNKNOWN we leave
25
- * them with their previous values.
26
+ * them with their previous values. v8.1M is tighter than v8.0M
27
+ * here and always zeroes the caller-saved registers regardless
28
+ * of the security state the exception is targeting.
29
*/
30
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
31
- if (!targets_secure) {
32
+ if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) {
33
/*
34
* Always clear the caller-saved registers (they have been
35
* pushed to the stack earlier in v7m_push_stack()).
36
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
37
* v7m_push_callee_stack()).
38
*/
39
int i;
40
+ /*
41
+ * r4..r11 are callee-saves, zero only if background
42
+ * state was Secure (EXCRET.S == 1) and exception
43
+ * targets Non-secure state
44
+ */
45
+ bool zero_callee_saves = !targets_secure &&
46
+ (lr & R_V7M_EXCRET_S_MASK);
47
48
for (i = 0; i < 13; i++) {
49
- /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
50
- if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) {
51
+ if (i < 4 || i > 11 || zero_callee_saves) {
52
env->regs[i] = 0;
53
}
54
}
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
New patch
1
In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
2
R_LLRP). (In previous versions of the architecture this was either
3
required or IMPDEF.)
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201119215617.29887-18-peter.maydell@linaro.org
8
---
9
target/arm/m_helper.c | 6 +++++-
10
1 file changed, 5 insertions(+), 1 deletion(-)
11
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/m_helper.c
15
+++ b/target/arm/m_helper.c
16
@@ -XXX,XX +XXX,XX @@ load_fail:
17
* The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
18
* secure); otherwise it targets the same security state as the
19
* underlying exception.
20
+ * In v8.1M HardFaults from vector table fetch fails don't set FORCED.
21
*/
22
if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
23
exc_secure = true;
24
}
25
- env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
26
+ env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK;
27
+ if (!arm_feature(env, ARM_FEATURE_V8_1M)) {
28
+ env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
29
+ }
30
armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
31
return false;
32
}
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
1
Move the NVICState struct definition into a header, so we can
1
In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
2
embed it into other QOM objects like SoCs.
2
and is a read-only IMPDEF register providing implementation specific
3
minor revision information, like the v8A REVIDR_EL1. Implement this.
3
4
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
7
Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
8
---
8
---
9
include/hw/arm/armv7m_nvic.h | 66 ++++++++++++++++++++++++++++++++++++++++++++
9
hw/intc/armv7m_nvic.c | 5 +++++
10
hw/intc/armv7m_nvic.c | 49 +-------------------------------
10
1 file changed, 5 insertions(+)
11
2 files changed, 67 insertions(+), 48 deletions(-)
12
create mode 100644 include/hw/arm/armv7m_nvic.h
13
11
14
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/include/hw/arm/armv7m_nvic.h
19
@@ -XXX,XX +XXX,XX @@
20
+/*
21
+ * ARMv7M NVIC object
22
+ *
23
+ * Copyright (c) 2017 Linaro Ltd
24
+ * Written by Peter Maydell <peter.maydell@linaro.org>
25
+ *
26
+ * This code is licensed under the GPL version 2 or later.
27
+ */
28
+
29
+#ifndef HW_ARM_ARMV7M_NVIC_H
30
+#define HW_ARM_ARMV7M_NVIC_H
31
+
32
+#include "target/arm/cpu.h"
33
+#include "hw/sysbus.h"
34
+
35
+#define TYPE_NVIC "armv7m_nvic"
36
+
37
+#define NVIC(obj) \
38
+ OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
39
+
40
+/* Highest permitted number of exceptions (architectural limit) */
41
+#define NVIC_MAX_VECTORS 512
42
+
43
+typedef struct VecInfo {
44
+ /* Exception priorities can range from -3 to 255; only the unmodifiable
45
+ * priority values for RESET, NMI and HardFault can be negative.
46
+ */
47
+ int16_t prio;
48
+ uint8_t enabled;
49
+ uint8_t pending;
50
+ uint8_t active;
51
+ uint8_t level; /* exceptions <=15 never set level */
52
+} VecInfo;
53
+
54
+typedef struct NVICState {
55
+ /*< private >*/
56
+ SysBusDevice parent_obj;
57
+ /*< public >*/
58
+
59
+ ARMCPU *cpu;
60
+
61
+ VecInfo vectors[NVIC_MAX_VECTORS];
62
+ uint32_t prigroup;
63
+
64
+ /* vectpending and exception_prio are both cached state that can
65
+ * be recalculated from the vectors[] array and the prigroup field.
66
+ */
67
+ unsigned int vectpending; /* highest prio pending enabled exception */
68
+ int exception_prio; /* group prio of the highest prio active exception */
69
+
70
+ struct {
71
+ uint32_t control;
72
+ uint32_t reload;
73
+ int64_t tick;
74
+ QEMUTimer *timer;
75
+ } systick;
76
+
77
+ MemoryRegion sysregmem;
78
+ MemoryRegion container;
79
+
80
+ uint32_t num_irq;
81
+ qemu_irq excpout;
82
+ qemu_irq sysresetreq;
83
+} NVICState;
84
+
85
+#endif
86
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
87
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/intc/armv7m_nvic.c
14
--- a/hw/intc/armv7m_nvic.c
89
+++ b/hw/intc/armv7m_nvic.c
15
+++ b/hw/intc/armv7m_nvic.c
90
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
91
#include "hw/sysbus.h"
17
}
92
#include "qemu/timer.h"
18
return val;
93
#include "hw/arm/arm.h"
19
}
94
+#include "hw/arm/armv7m_nvic.h"
20
+ case 0xcfc:
95
#include "target/arm/cpu.h"
21
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) {
96
#include "exec/address-spaces.h"
22
+ goto bad_offset;
97
#include "qemu/log.h"
23
+ }
98
@@ -XXX,XX +XXX,XX @@
24
+ return cpu->revidr;
99
* "exception" more or less interchangeably.
25
case 0xd00: /* CPUID Base. */
100
*/
26
return cpu->midr;
101
#define NVIC_FIRST_IRQ 16
27
case 0xd04: /* Interrupt Control State (ICSR) */
102
-#define NVIC_MAX_VECTORS 512
103
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
104
105
/* Effective running priority of the CPU when no exception is active
106
@@ -XXX,XX +XXX,XX @@
107
*/
108
#define NVIC_NOEXC_PRIO 0x100
109
110
-typedef struct VecInfo {
111
- /* Exception priorities can range from -3 to 255; only the unmodifiable
112
- * priority values for RESET, NMI and HardFault can be negative.
113
- */
114
- int16_t prio;
115
- uint8_t enabled;
116
- uint8_t pending;
117
- uint8_t active;
118
- uint8_t level; /* exceptions <=15 never set level */
119
-} VecInfo;
120
-
121
-typedef struct NVICState {
122
- /*< private >*/
123
- SysBusDevice parent_obj;
124
- /*< public >*/
125
-
126
- ARMCPU *cpu;
127
-
128
- VecInfo vectors[NVIC_MAX_VECTORS];
129
- uint32_t prigroup;
130
-
131
- /* vectpending and exception_prio are both cached state that can
132
- * be recalculated from the vectors[] array and the prigroup field.
133
- */
134
- unsigned int vectpending; /* highest prio pending enabled exception */
135
- int exception_prio; /* group prio of the highest prio active exception */
136
-
137
- struct {
138
- uint32_t control;
139
- uint32_t reload;
140
- int64_t tick;
141
- QEMUTimer *timer;
142
- } systick;
143
-
144
- MemoryRegion sysregmem;
145
- MemoryRegion container;
146
-
147
- uint32_t num_irq;
148
- qemu_irq excpout;
149
- qemu_irq sysresetreq;
150
-} NVICState;
151
-
152
-#define TYPE_NVIC "armv7m_nvic"
153
-
154
-#define NVIC(obj) \
155
- OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
156
-
157
static const uint8_t nvic_id[] = {
158
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
159
};
160
--
28
--
161
2.7.4
29
2.20.1
162
30
163
31
diff view generated by jsdifflib
1
Switch the stm32f205 SoC to create the armv7m object directly
1
In v8.1M a new exception return check is added which may cause a NOCP
2
rather than via the armv7m_init() wrapper. This fits better
2
UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
3
with the SoC model's very QOMified design.
3
we must check whether access to CP10 from the Security state of the
4
returning exception is disabled; if it is then we must take a fault.
4
5
5
In particular this means we can push loading the guest image
6
(Note that for our implementation CPPWR is always RAZ/WI and so can
6
out to the top level board code where it belongs, rather
7
never cause CP10 accesses to fail.)
7
than the SoC object having a QOM property for the filename
8
8
to load.
9
The other v8.1M change to this register-clearing code is that if MVE
10
is implemented VPR must also be cleared, so add a TODO comment to
11
that effect.
9
12
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
15
Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
15
---
16
---
16
include/hw/arm/stm32f205_soc.h | 4 +++-
17
target/arm/m_helper.c | 22 +++++++++++++++++++++-
17
hw/arm/netduino2.c | 7 ++++---
18
1 file changed, 21 insertions(+), 1 deletion(-)
18
hw/arm/stm32f205_soc.c | 16 +++++++++++++---
19
3 files changed, 20 insertions(+), 7 deletions(-)
20
19
21
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
20
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
22
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/stm32f205_soc.h
22
--- a/target/arm/m_helper.c
24
+++ b/include/hw/arm/stm32f205_soc.h
23
+++ b/target/arm/m_helper.c
25
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
26
#include "hw/adc/stm32f2xx_adc.h"
25
v7m_exception_taken(cpu, excret, true, false);
27
#include "hw/or-irq.h"
26
return;
28
#include "hw/ssi/stm32f2xx_spi.h"
27
} else {
29
+#include "hw/arm/armv7m.h"
28
- /* Clear s0..s15 and FPSCR */
30
29
+ if (arm_feature(env, ARM_FEATURE_V8_1M)) {
31
#define TYPE_STM32F205_SOC "stm32f205-soc"
30
+ /* v8.1M adds this NOCP check */
32
#define STM32F205_SOC(obj) \
31
+ bool nsacr_pass = exc_secure ||
33
@@ -XXX,XX +XXX,XX @@ typedef struct STM32F205State {
32
+ extract32(env->v7m.nsacr, 10, 1);
34
SysBusDevice parent_obj;
33
+ bool cpacr_pass = v7m_cpacr_pass(env, exc_secure, true);
35
/*< public >*/
34
+ if (!nsacr_pass) {
36
35
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true);
37
- char *kernel_filename;
36
+ env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK;
38
char *cpu_model;
37
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
39
38
+ "stackframe: NSACR prevents clearing FPU registers\n");
40
+ ARMv7MState armv7m;
39
+ v7m_exception_taken(cpu, excret, true, false);
41
+
40
+ } else if (!cpacr_pass) {
42
STM32F2XXSyscfgState syscfg;
41
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
43
STM32F2XXUsartState usart[STM_NUM_USARTS];
42
+ exc_secure);
44
STM32F2XXTimerState timer[STM_NUM_TIMERS];
43
+ env->v7m.cfsr[exc_secure] |= R_V7M_CFSR_NOCP_MASK;
45
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
44
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
46
index XXXXXXX..XXXXXXX 100644
45
+ "stackframe: CPACR prevents clearing FPU registers\n");
47
--- a/hw/arm/netduino2.c
46
+ v7m_exception_taken(cpu, excret, true, false);
48
+++ b/hw/arm/netduino2.c
47
+ }
49
@@ -XXX,XX +XXX,XX @@
48
+ }
50
#include "hw/boards.h"
49
+ /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemented */
51
#include "qemu/error-report.h"
50
int i;
52
#include "hw/arm/stm32f205_soc.h"
51
53
+#include "hw/arm/arm.h"
52
for (i = 0; i < 16; i += 2) {
54
55
static void netduino2_init(MachineState *machine)
56
{
57
DeviceState *dev;
58
59
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
60
- if (machine->kernel_filename) {
61
- qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
62
- }
63
qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
64
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
65
+
66
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
67
+ FLASH_SIZE);
68
}
69
70
static void netduino2_machine_init(MachineClass *mc)
71
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/arm/stm32f205_soc.c
74
+++ b/hw/arm/stm32f205_soc.c
75
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
76
STM32F205State *s = STM32F205_SOC(obj);
77
int i;
78
79
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
80
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
81
+
82
object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
83
qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
84
85
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
86
vmstate_register_ram_global(sram);
87
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
88
89
- nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
90
- s->kernel_filename, s->cpu_model);
91
+ nvic = DEVICE(&s->armv7m);
92
+ qdev_prop_set_uint32(nvic, "num-irq", 96);
93
+ qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
94
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
95
+ "memory", &error_abort);
96
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
97
+ if (err != NULL) {
98
+ error_propagate(errp, err);
99
+ return;
100
+ }
101
102
/* System configuration controller */
103
dev = DEVICE(&s->syscfg);
104
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
105
}
106
107
static Property stm32f205_soc_properties[] = {
108
- DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
109
DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
110
DEFINE_PROP_END_OF_LIST(),
111
};
112
--
53
--
113
2.7.4
54
2.20.1
114
55
115
56
diff view generated by jsdifflib
1
The NVIC is a core v7M device that exists for all v7M CPUs;
1
v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set).
2
put it under a CONFIG_ARM_V7M rather than hiding it under
2
The only difference is that:
3
CONFIG_STELLARIS.
3
* the old T1 encodings UNDEF if the implementation implements 32
4
Dregs (this is currently architecturally impossible for M-profile)
5
* the new T2 encodings have the implementation-defined option to
6
read from memory (discarding the data) or write UNKNOWN values to
7
memory for the stack slots that would be D16-D31
4
8
5
(We'll use CONFIG_ARM_V7M for the SysTick device too
9
We choose not to make those accesses, so for us the two
6
when we split it out of the NVIC.)
10
instructions behave identically assuming they don't UNDEF.
7
11
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20201119215617.29887-21-peter.maydell@linaro.org
11
Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
12
---
15
---
13
hw/intc/Makefile.objs | 2 +-
16
target/arm/m-nocp.decode | 2 +-
14
default-configs/arm-softmmu.mak | 2 ++
17
target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++
15
2 files changed, 3 insertions(+), 1 deletion(-)
18
2 files changed, 26 insertions(+), 1 deletion(-)
16
19
17
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
20
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/Makefile.objs
22
--- a/target/arm/m-nocp.decode
20
+++ b/hw/intc/Makefile.objs
23
+++ b/target/arm/m-nocp.decode
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_APIC) += apic.o apic_common.o
24
@@ -XXX,XX +XXX,XX @@
22
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
25
23
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
26
{
24
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
27
# Special cases which do not take an early NOCP: VLLDM and VLSTM
25
-obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
28
- VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
26
+obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o
29
+ VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000
27
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
30
# VSCCLRM (new in v8.1M) is similar:
28
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
31
VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3
29
obj-$(CONFIG_IOAPIC) += ioapic.o
32
VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2
30
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
33
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
31
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
32
--- a/default-configs/arm-softmmu.mak
35
--- a/target/arm/translate-vfp.c.inc
33
+++ b/default-configs/arm-softmmu.mak
36
+++ b/target/arm/translate-vfp.c.inc
34
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM11MPCORE=y
37
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
35
CONFIG_A9MPCORE=y
38
!arm_dc_feature(s, ARM_FEATURE_V8)) {
36
CONFIG_A15MPCORE=y
39
return false;
37
40
}
38
+CONFIG_ARM_V7M=y
39
+
41
+
40
CONFIG_ARM_GIC=y
42
+ if (a->op) {
41
CONFIG_ARM_GIC_KVM=$(CONFIG_KVM)
43
+ /*
42
CONFIG_ARM_TIMER=y
44
+ * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
45
+ * to take the IMPDEF option to make memory accesses to the stack
46
+ * slots that correspond to the D16-D31 registers (discarding
47
+ * read data and writing UNKNOWN values), so for us the T2
48
+ * encoding behaves identically to the T1 encoding.
49
+ */
50
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
51
+ return false;
52
+ }
53
+ } else {
54
+ /*
55
+ * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
56
+ * This is currently architecturally impossible, but we add the
57
+ * check to stay in line with the pseudocode. Note that we must
58
+ * emit code for the UNDEF so it takes precedence over the NOCP.
59
+ */
60
+ if (dc_isar_feature(aa32_simd_r32, s)) {
61
+ unallocated_encoding(s);
62
+ return true;
63
+ }
64
+ }
65
+
66
/*
67
* If not secure, UNDEF. We must emit code for this
68
* rather than returning false so that this takes
43
--
69
--
44
2.7.4
70
2.20.1
45
71
46
72
diff view generated by jsdifflib
1
Instead of qdev_set_parent_bus() silently doing the wrong
1
v8.1M introduces a new TRD flag in the CCR register, which enables
2
thing if it's handed a device that's already on a bus,
2
checking for stack frame integrity signatures on SG instructions.
3
have it remove the device from the old bus and add it to
3
This bit is not banked, and is always RAZ/WI to Non-secure code.
4
the new one. This is useful for the raspi2 sdcard.
4
Adjust the code for handling CCR reads and writes to handle this.
5
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 1488293711-14195-2-git-send-email-peter.maydell@linaro.org
8
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
9
---
9
---
10
hw/core/qdev.c | 14 ++++++++++++++
10
target/arm/cpu.h | 2 ++
11
1 file changed, 14 insertions(+)
11
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++--------
12
2 files changed, 20 insertions(+), 8 deletions(-)
12
13
13
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/core/qdev.c
16
--- a/target/arm/cpu.h
16
+++ b/hw/core/qdev.c
17
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
18
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
18
19
FIELD(V7M_CCR, DC, 16, 1)
19
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
20
FIELD(V7M_CCR, IC, 17, 1)
20
{
21
FIELD(V7M_CCR, BP, 18, 1)
21
+ bool replugging = dev->parent_bus != NULL;
22
+FIELD(V7M_CCR, LOB, 19, 1)
23
+FIELD(V7M_CCR, TRD, 20, 1)
24
25
/* V7M SCR bits */
26
FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
27
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/intc/armv7m_nvic.c
30
+++ b/hw/intc/armv7m_nvic.c
31
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
32
}
33
return cpu->env.v7m.scr[attrs.secure];
34
case 0xd14: /* Configuration Control. */
35
- /* The BFHFNMIGN bit is the only non-banked bit; we
36
- * keep it in the non-secure copy of the register.
37
+ /*
38
+ * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
39
+ * and TRD (stored in the S copy of the register)
40
*/
41
val = cpu->env.v7m.ccr[attrs.secure];
42
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
43
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
44
cpu->env.v7m.scr[attrs.secure] = value;
45
break;
46
case 0xd14: /* Configuration Control. */
47
+ {
48
+ uint32_t mask;
22
+
49
+
23
+ if (replugging) {
50
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
24
+ /* Keep a reference to the device while it's not plugged into
51
goto bad_offset;
25
+ * any bus, to avoid it potentially evaporating when it is
52
}
26
+ * dereffed in bus_remove_child().
53
27
+ */
54
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
28
+ object_ref(OBJECT(dev));
55
- value &= (R_V7M_CCR_STKALIGN_MASK |
29
+ bus_remove_child(dev->parent_bus, dev);
56
- R_V7M_CCR_BFHFNMIGN_MASK |
30
+ object_unref(OBJECT(dev->parent_bus));
57
- R_V7M_CCR_DIV_0_TRP_MASK |
58
- R_V7M_CCR_UNALIGN_TRP_MASK |
59
- R_V7M_CCR_USERSETMPEND_MASK |
60
- R_V7M_CCR_NONBASETHRDENA_MASK);
61
+ mask = R_V7M_CCR_STKALIGN_MASK |
62
+ R_V7M_CCR_BFHFNMIGN_MASK |
63
+ R_V7M_CCR_DIV_0_TRP_MASK |
64
+ R_V7M_CCR_UNALIGN_TRP_MASK |
65
+ R_V7M_CCR_USERSETMPEND_MASK |
66
+ R_V7M_CCR_NONBASETHRDENA_MASK;
67
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
68
+ /* TRD is always RAZ/WI from NS */
69
+ mask |= R_V7M_CCR_TRD_MASK;
70
+ }
71
+ value &= mask;
72
73
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
74
/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
75
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
76
77
cpu->env.v7m.ccr[attrs.secure] = value;
78
break;
31
+ }
79
+ }
32
dev->parent_bus = bus;
80
case 0xd24: /* System Handler Control and State (SHCSR) */
33
object_ref(OBJECT(bus));
81
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
34
bus_add_child(bus, dev);
82
goto bad_offset;
35
+ if (replugging) {
36
+ object_unref(OBJECT(dev));
37
+ }
38
}
39
40
/* Create a new device. This only initializes the device state
41
--
83
--
42
2.7.4
84
2.20.1
43
85
44
86
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
v8.1M introduces a new TRD flag in the CCR register, which enables
2
checking for stack frame integrity signatures on SG instructions.
3
Add the code in the SG insn implementation for the new behaviour.
2
4
3
Reset CPU interface registers of GICv3 when CPU is reset.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
For this, ARMCPRegInfo struct is registered with one ICC
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
register whose resetfn is called when cpu is reset.
7
Message-id: 20201119215617.29887-24-peter.maydell@linaro.org
8
---
9
target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++
10
1 file changed, 86 insertions(+)
6
11
7
All the ICC registers are reset under one single register
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
8
reset function instead of calling resetfn for each ICC
9
register.
10
11
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1487850673-26455-6-git-send-email-vijay.kilari@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/intc/arm_gicv3_kvm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
18
1 file changed, 60 insertions(+)
19
20
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_kvm.c
14
--- a/target/arm/m_helper.c
23
+++ b/hw/intc/arm_gicv3_kvm.c
15
+++ b/target/arm/m_helper.c
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
16
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
25
}
17
return true;
26
}
18
}
27
19
28
+static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
20
+static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
21
+ uint32_t addr, uint32_t *spdata)
29
+{
22
+{
30
+ ARMCPU *cpu;
23
+ /*
31
+ GICv3State *s;
24
+ * Read a word of data from the stack for the SG instruction,
32
+ GICv3CPUState *c;
25
+ * writing the value into *spdata. If the load succeeds, return
26
+ * true; otherwise pend an appropriate exception and return false.
27
+ * (We can't use data load helpers here that throw an exception
28
+ * because of the context we're called in, which is halfway through
29
+ * arm_v7m_cpu_do_interrupt().)
30
+ */
31
+ CPUState *cs = CPU(cpu);
32
+ CPUARMState *env = &cpu->env;
33
+ MemTxAttrs attrs = {};
34
+ MemTxResult txres;
35
+ target_ulong page_size;
36
+ hwaddr physaddr;
37
+ int prot;
38
+ ARMMMUFaultInfo fi = {};
39
+ ARMCacheAttrs cacheattrs = {};
40
+ uint32_t value;
33
+
41
+
34
+ c = (GICv3CPUState *)env->gicv3state;
42
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
35
+ s = c->gic;
43
+ &attrs, &prot, &page_size, &fi, &cacheattrs)) {
36
+ cpu = ARM_CPU(c->cpu);
44
+ /* MPU/SAU lookup failed */
45
+ if (fi.type == ARMFault_QEMU_SFault) {
46
+ qemu_log_mask(CPU_LOG_INT,
47
+ "...SecureFault during stack word read\n");
48
+ env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
49
+ env->v7m.sfar = addr;
50
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
51
+ } else {
52
+ qemu_log_mask(CPU_LOG_INT,
53
+ "...MemManageFault during stack word read\n");
54
+ env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_DACCVIOL_MASK |
55
+ R_V7M_CFSR_MMARVALID_MASK;
56
+ env->v7m.mmfar[M_REG_S] = addr;
57
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false);
58
+ }
59
+ return false;
60
+ }
61
+ value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
62
+ attrs, &txres);
63
+ if (txres != MEMTX_OK) {
64
+ /* BusFault trying to read the data */
65
+ qemu_log_mask(CPU_LOG_INT,
66
+ "...BusFault during stack word read\n");
67
+ env->v7m.cfsr[M_REG_NS] |=
68
+ (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
69
+ env->v7m.bfar = addr;
70
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
71
+ return false;
72
+ }
37
+
73
+
38
+ /* Initialize to actual HW supported configuration */
74
+ *spdata = value;
39
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
75
+ return true;
40
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
41
+ &c->icc_ctlr_el1[GICV3_NS], false);
42
+
43
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
44
+ c->icc_pmr_el1 = 0;
45
+ c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
46
+ c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
47
+ c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
48
+
49
+ c->icc_sre_el1 = 0x7;
50
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
51
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
52
+}
76
+}
53
+
77
+
54
static void kvm_arm_gicv3_reset(DeviceState *dev)
78
static bool v7m_handle_execute_nsc(ARMCPU *cpu)
55
{
79
{
56
GICv3State *s = ARM_GICV3_COMMON(dev);
80
/*
57
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
81
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
58
kvm_arm_gicv3_put(s);
82
*/
59
}
83
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
60
84
", executing it\n", env->regs[15]);
61
+/*
62
+ * CPU interface registers of GIC needs to be reset on CPU reset.
63
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
64
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
65
+ * register reset, we define only one register of CPU interface instead
66
+ * of defining all the registers.
67
+ */
68
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
69
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
70
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
71
+ /*
72
+ * If ARM_CP_NOP is used, resetfn is not called,
73
+ * So ARM_CP_NO_RAW is appropriate type.
74
+ */
75
+ .type = ARM_CP_NO_RAW,
76
+ .access = PL1_RW,
77
+ .readfn = arm_cp_read_zero,
78
+ .writefn = arm_cp_write_ignore,
79
+ /*
80
+ * We hang the whole cpu interface reset routine off here
81
+ * rather than parcelling it out into one little function
82
+ * per register
83
+ */
84
+ .resetfn = arm_gicv3_icc_reset,
85
+ },
86
+ REGINFO_SENTINEL
87
+};
88
+
85
+
89
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
86
+ if (cpu_isar_feature(aa32_m_sec_state, cpu) &&
90
{
87
+ !arm_v7m_is_handler_mode(env)) {
91
GICv3State *s = KVM_ARM_GICV3(dev);
88
+ /*
92
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
89
+ * v8.1M exception stack frame integrity check. Note that we
93
90
+ * must perform the memory access even if CCR_S.TRD is zero
94
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
91
+ * and we aren't going to check what the data loaded is.
95
92
+ */
96
+ for (i = 0; i < s->num_cpu; i++) {
93
+ uint32_t spdata, sp;
97
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
98
+
94
+
99
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
95
+ /*
96
+ * We know we are currently NS, so the S stack pointers must be
97
+ * in other_ss_{psp,msp}, not in regs[13]/other_sp.
98
+ */
99
+ sp = v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other_ss_msp;
100
+ if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) {
101
+ /* Stack access failed and an exception has been pended */
102
+ return false;
103
+ }
104
+
105
+ if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) {
106
+ if (((spdata & ~1) == 0xfefa125a) ||
107
+ !(env->v7m.control[M_REG_S] & 1)) {
108
+ goto gen_invep;
109
+ }
110
+ }
100
+ }
111
+ }
101
+
112
+
102
/* Try to create the device via the device control API */
113
env->regs[14] &= ~1;
103
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
114
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
104
if (s->dev_fd < 0) {
115
switch_v7m_security_state(env, true);
105
--
116
--
106
2.7.4
117
2.20.1
107
118
108
119
diff view generated by jsdifflib
1
Make the ARMv7M object take a memory region link which it uses
1
In commit 077d7449100d824a4 we added code to handle the v8M
2
to wire up the bitband rather than having them always put
2
requirement that returns from NMI or HardFault forcibly deactivate
3
themselves in the system address space.
3
those exceptions regardless of what interrupt the guest is trying to
4
deactivate. Unfortunately this broke the handling of the "illegal
5
exception return because the returning exception number is not
6
active" check for those cases. In the pseudocode this test is done
7
on the exception the guest asks to return from, but because our
8
implementation was doing this in armv7m_nvic_complete_irq() after the
9
new "deactivate NMI/HardFault regardless" code we ended up doing the
10
test on the VecInfo for that exception instead, which usually meant
11
failing to raise the illegal exception return fault.
12
13
In the case for "configurable exception targeting the opposite
14
security state" we detected the illegal-return case but went ahead
15
and deactivated the VecInfo anyway, which is wrong because that is
16
the VecInfo for the other security state.
17
18
Rearrange the code so that we first identify the illegal return
19
cases, then see if we really need to deactivate NMI or HardFault
20
instead, and finally do the deactivation.
4
21
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
24
Message-id: 20201119215617.29887-25-peter.maydell@linaro.org
8
---
25
---
9
include/hw/arm/armv7m.h | 10 ++++++++++
26
hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++--------------------
10
hw/arm/armv7m.c | 23 ++++++++++++++++++++++-
27
1 file changed, 32 insertions(+), 27 deletions(-)
11
2 files changed, 32 insertions(+), 1 deletion(-)
12
28
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
29
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
14
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/armv7m.h
31
--- a/hw/intc/armv7m_nvic.c
16
+++ b/include/hw/arm/armv7m.h
32
+++ b/hw/intc/armv7m_nvic.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct {
33
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
18
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
34
{
19
* + Property "cpu-model": CPU model to instantiate
35
NVICState *s = (NVICState *)opaque;
20
* + Property "num-irq": number of external IRQ lines
36
VecInfo *vec = NULL;
21
+ * + Property "memory": MemoryRegion defining the physical address space
37
- int ret;
22
+ * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
38
+ int ret = 0;
23
+ * devices will be automatically layered on top of this view.)
39
24
*/
40
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
25
typedef struct ARMv7MState {
41
26
/*< private >*/
42
+ trace_nvic_complete_irq(irq, secure);
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
28
BitBandState bitband[ARMV7M_NUM_BITBANDS];
29
ARMCPU *cpu;
30
31
+ /* MemoryRegion we pass to the CPU, with our devices layered on
32
+ * top of the ones the board provides in board_memory.
33
+ */
34
+ MemoryRegion container;
35
+
43
+
36
/* Properties */
44
+ if (secure && exc_is_banked(irq)) {
37
char *cpu_model;
45
+ vec = &s->sec_vectors[irq];
38
+ /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
46
+ } else {
39
+ MemoryRegion *board_memory;
47
+ vec = &s->vectors[irq];
40
} ARMv7MState;
41
42
#endif
43
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/armv7m.c
46
+++ b/hw/arm/armv7m.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "elf.h"
49
#include "sysemu/qtest.h"
50
#include "qemu/error-report.h"
51
+#include "exec/address-spaces.h"
52
53
/* Bitbanded IO. Each word corresponds to a single bit. */
54
55
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
56
57
/* Can't init the cpu here, we don't yet know which model to use */
58
59
+ object_property_add_link(obj, "memory",
60
+ TYPE_MEMORY_REGION,
61
+ (Object **)&s->board_memory,
62
+ qdev_prop_allow_set_link_before_realize,
63
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
64
+ &error_abort);
65
+ memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
66
+
67
object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
68
qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
69
object_property_add_alias(obj, "num-irq",
70
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
71
const char *typename;
72
CPUClass *cc;
73
74
+ if (!s->board_memory) {
75
+ error_setg(errp, "memory property was not set");
76
+ return;
77
+ }
48
+ }
78
+
49
+
79
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
50
+ /*
51
+ * Identify illegal exception return cases. We can't immediately
52
+ * return at this point because we still need to deactivate
53
+ * (either this exception or NMI/HardFault) first.
54
+ */
55
+ if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
56
+ /*
57
+ * Return from a configurable exception targeting the opposite
58
+ * security state from the one we're trying to complete it for.
59
+ * Clear vec because it's not really the VecInfo for this
60
+ * (irq, secstate) so we mustn't deactivate it.
61
+ */
62
+ ret = -1;
63
+ vec = NULL;
64
+ } else if (!vec->active) {
65
+ /* Return from an inactive interrupt */
66
+ ret = -1;
67
+ } else {
68
+ /* Legal return, we will return the RETTOBASE bit value to the caller */
69
+ ret = nvic_rettobase(s);
70
+ }
80
+
71
+
81
cpustr = g_strsplit(s->cpu_model, ",", 2);
72
/*
82
73
* For negative priorities, v8M will forcibly deactivate the appropriate
83
oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
74
* NMI or HardFault regardless of what interrupt we're being asked to
84
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
75
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
85
return;
86
}
76
}
87
77
88
+ object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
78
if (!vec) {
89
+ &error_abort);
79
- if (secure && exc_is_banked(irq)) {
90
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
80
- vec = &s->sec_vectors[irq];
91
if (err != NULL) {
81
- } else {
92
error_propagate(errp, err);
82
- vec = &s->vectors[irq];
93
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
83
- }
94
return;
84
- }
95
}
85
-
96
86
- trace_nvic_complete_irq(irq, secure);
97
- sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
87
-
98
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
88
- if (!vec->active) {
99
+ sysbus_mmio_get_region(sbd, 0));
89
- /* Tell the caller this was an illegal exception return */
90
- return -1;
91
- }
92
-
93
- /*
94
- * If this is a configurable exception and it is currently
95
- * targeting the opposite security state from the one we're trying
96
- * to complete it for, this counts as an illegal exception return.
97
- * We still need to deactivate whatever vector the logic above has
98
- * selected, though, as it might not be the same as the one for the
99
- * requested exception number.
100
- */
101
- if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
102
- ret = -1;
103
- } else {
104
- ret = nvic_rettobase(s);
105
+ return ret;
100
}
106
}
101
}
107
102
108
vec->active = 0;
103
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
104
armv7m = qdev_create(NULL, "armv7m");
105
qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
106
qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
107
+ object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
108
+ "memory", &error_abort);
109
/* This will exit with an error if the user passed us a bad cpu_model */
110
qdev_init_nofail(armv7m);
111
112
--
109
--
113
2.7.4
110
2.20.1
114
111
115
112
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
For v8.1M the architecture mandates that CPUs must provide at
2
least the "minimal RAS implementation" from the Reliability,
3
Availability and Serviceability extension. This consists of:
4
* an ESB instruction which is a NOP
5
-- since it is in the HINT space we need only add a comment
6
* an RFSR register which will RAZ/WI
7
* a RAZ/WI AIRCR.IESB bit
8
-- the code which handles writes to AIRCR does not allow setting
9
of RES0 bits, so we already treat this as RAZ/WI; add a comment
10
noting that this is deliberate
11
* minimal implementation of the RAS register block at 0xe0005000
12
-- this will be in a subsequent commit
13
* setting the ID_PFR0.RAS field to 0b0010
14
-- we will do this when we add the Cortex-M55 CPU model
2
15
3
Add gicv3state void pointer to CPUARMState struct
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to store GICv3CPUState.
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20201119215617.29887-26-peter.maydell@linaro.org
19
---
20
target/arm/cpu.h | 14 ++++++++++++++
21
target/arm/t32.decode | 4 ++++
22
hw/intc/armv7m_nvic.c | 13 +++++++++++++
23
3 files changed, 31 insertions(+)
5
24
6
In case of usecase like CPU reset, we need to reset
7
GICv3CPUState of the CPU. In such scenario, this pointer
8
becomes handy.
9
10
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 1487850673-26455-5-git-send-email-vijay.kilari@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/intc/gicv3_internal.h | 2 ++
17
target/arm/cpu.h | 2 ++
18
hw/intc/arm_gicv3_common.c | 2 ++
19
hw/intc/arm_gicv3_cpuif.c | 8 ++++++++
20
4 files changed, 14 insertions(+)
21
22
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/gicv3_internal.h
25
+++ b/hw/intc/gicv3_internal.h
26
@@ -XXX,XX +XXX,XX @@ static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
27
}
28
}
29
30
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
31
+
32
#endif /* QEMU_ARM_GICV3_INTERNAL_H */
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
27
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
28
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
29
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
38
30
FIELD(ID_MMFR4, CCIDX, 24, 4)
39
void *nvic;
31
FIELD(ID_MMFR4, EVT, 28, 4)
40
const struct arm_boot_info *boot_info;
32
41
+ /* Store GICv3CPUState to access from this struct */
33
+FIELD(ID_PFR0, STATE0, 0, 4)
42
+ void *gicv3state;
34
+FIELD(ID_PFR0, STATE1, 4, 4)
43
} CPUARMState;
35
+FIELD(ID_PFR0, STATE2, 8, 4)
44
36
+FIELD(ID_PFR0, STATE3, 12, 4)
45
/**
37
+FIELD(ID_PFR0, CSV2, 16, 4)
46
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
38
+FIELD(ID_PFR0, AMU, 20, 4)
39
+FIELD(ID_PFR0, DIT, 24, 4)
40
+FIELD(ID_PFR0, RAS, 28, 4)
41
+
42
FIELD(ID_PFR1, PROGMOD, 0, 4)
43
FIELD(ID_PFR1, SECURITY, 4, 4)
44
FIELD(ID_PFR1, MPROGMOD, 8, 4)
45
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
46
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
47
}
48
49
+static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
50
+{
51
+ return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
52
+}
53
+
54
static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
55
{
56
return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
57
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
47
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_common.c
59
--- a/target/arm/t32.decode
49
+++ b/hw/intc/arm_gicv3_common.c
60
+++ b/target/arm/t32.decode
50
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
61
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
51
62
# SEV 1111 0011 1010 1111 1000 0000 0000 0100
52
s->cpu[i].cpu = cpu;
63
# SEVL 1111 0011 1010 1111 1000 0000 0000 0101
53
s->cpu[i].gic = s;
64
54
+ /* Store GICv3CPUState in CPUARMState gicv3state pointer */
65
+ # For M-profile minimal-RAS ESB can be a NOP, which is the
55
+ gicv3_set_gicv3state(cpu, &s->cpu[i]);
66
+ # default behaviour since it is in the hint space.
56
67
+ # ESB 1111 0011 1010 1111 1000 0000 0001 0000
57
/* Pre-construct the GICR_TYPER:
68
+
58
* For our implementation:
69
# The canonical nop ends in 0000 0000, but the whole rest
59
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
70
# of the space is "reserved hint, behaves as nop".
71
NOP 1111 0011 1010 1111 1000 0000 ---- ----
72
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
60
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/intc/arm_gicv3_cpuif.c
74
--- a/hw/intc/armv7m_nvic.c
62
+++ b/hw/intc/arm_gicv3_cpuif.c
75
+++ b/hw/intc/armv7m_nvic.c
63
@@ -XXX,XX +XXX,XX @@
76
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
64
#include "gicv3_internal.h"
77
return 0;
65
#include "cpu.h"
78
}
66
79
return cpu->env.v7m.sfar;
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
80
+ case 0xf04: /* RFSR */
68
+{
81
+ if (!cpu_isar_feature(aa32_ras, cpu)) {
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
82
+ goto bad_offset;
70
+ CPUARMState *env = &arm_cpu->env;
83
+ }
71
+
84
+ /* We provide minimal-RAS only: RFSR is RAZ/WI */
72
+ env->gicv3state = (void *)s;
85
+ return 0;
73
+};
86
case 0xf34: /* FPCCR */
74
+
87
if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
75
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
88
return 0;
76
{
89
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
77
/* Given the CPU, find the right GICv3CPUState struct.
90
R_V7M_AIRCR_PRIGROUP_SHIFT,
91
R_V7M_AIRCR_PRIGROUP_LENGTH);
92
}
93
+ /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS */
94
if (attrs.secure) {
95
/* These bits are only writable by secure */
96
cpu->env.v7m.aircr = value &
97
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
98
}
99
break;
100
}
101
+ case 0xf04: /* RFSR */
102
+ if (!cpu_isar_feature(aa32_ras, cpu)) {
103
+ goto bad_offset;
104
+ }
105
+ /* We provide minimal-RAS only: RFSR is RAZ/WI */
106
+ break;
107
case 0xf34: /* FPCCR */
108
if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
109
/* Not all bits here are banked. */
78
--
110
--
79
2.7.4
111
2.20.1
80
112
81
113
diff view generated by jsdifflib
1
The SysTick timer isn't really part of the NVIC proper;
1
The RAS feature has a block of memory-mapped registers at offset
2
we just modelled it that way back when we couldn't
2
0x5000 within the PPB. For a "minimal RAS" implementation we provide
3
easily have devices that only occupied a small chunk
3
no error records and so the only registers that exist in the block
4
of a memory region. Split it out into its own device.
4
are ERRIIDR and ERRDEVID.
5
6
The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
7
of the "nvic-default" region is actually valid for minimal-RAS,
8
so the main benefit of providing an explicit implementation of
9
the register block is more accurate LOG_UNIMP messages, and a
10
framework for where we could add a real RAS implementation later
11
if necessary.
5
12
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
9
---
16
---
10
hw/timer/Makefile.objs | 1 +
17
include/hw/intc/armv7m_nvic.h | 1 +
11
include/hw/arm/armv7m_nvic.h | 10 +-
18
hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++
12
include/hw/timer/armv7m_systick.h | 34 ++++++
19
2 files changed, 57 insertions(+)
13
hw/intc/armv7m_nvic.c | 160 ++++++-------------------
14
hw/timer/armv7m_systick.c | 240 ++++++++++++++++++++++++++++++++++++++
15
hw/timer/trace-events | 6 +
16
6 files changed, 318 insertions(+), 133 deletions(-)
17
create mode 100644 include/hw/timer/armv7m_systick.h
18
create mode 100644 hw/timer/armv7m_systick.c
19
20
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
21
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
23
--- a/include/hw/intc/armv7m_nvic.h
23
+++ b/hw/timer/Makefile.objs
24
+++ b/include/hw/intc/armv7m_nvic.h
24
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ struct NVICState {
25
common-obj-$(CONFIG_ARM_TIMER) += arm_timer.o
26
MemoryRegion sysreg_ns_mem;
26
common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
27
MemoryRegion systickmem;
27
+common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o
28
MemoryRegion systick_ns_mem;
28
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
29
+ MemoryRegion ras_mem;
29
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
30
common-obj-$(CONFIG_DS1338) += ds1338.o
31
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armv7m_nvic.h
34
+++ b/include/hw/arm/armv7m_nvic.h
35
@@ -XXX,XX +XXX,XX @@
36
37
#include "target/arm/cpu.h"
38
#include "hw/sysbus.h"
39
+#include "hw/timer/armv7m_systick.h"
40
41
#define TYPE_NVIC "armv7m_nvic"
42
43
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
44
unsigned int vectpending; /* highest prio pending enabled exception */
45
int exception_prio; /* group prio of the highest prio active exception */
46
47
- struct {
48
- uint32_t control;
49
- uint32_t reload;
50
- int64_t tick;
51
- QEMUTimer *timer;
52
- } systick;
53
-
54
MemoryRegion sysregmem;
55
MemoryRegion container;
30
MemoryRegion container;
56
31
MemoryRegion defaultmem;
57
uint32_t num_irq;
32
58
qemu_irq excpout;
59
qemu_irq sysresetreq;
60
+
61
+ SysTickState systick;
62
} NVICState;
63
64
#endif
65
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
66
new file mode 100644
67
index XXXXXXX..XXXXXXX
68
--- /dev/null
69
+++ b/include/hw/timer/armv7m_systick.h
70
@@ -XXX,XX +XXX,XX @@
71
+/*
72
+ * ARMv7M SysTick timer
73
+ *
74
+ * Copyright (c) 2006-2007 CodeSourcery.
75
+ * Written by Paul Brook
76
+ * Copyright (c) 2017 Linaro Ltd
77
+ * Written by Peter Maydell
78
+ *
79
+ * This code is licensed under the GPL (version 2 or later).
80
+ */
81
+
82
+#ifndef HW_TIMER_ARMV7M_SYSTICK_H
83
+#define HW_TIMER_ARMV7M_SYSTICK_H
84
+
85
+#include "hw/sysbus.h"
86
+
87
+#define TYPE_SYSTICK "armv7m_systick"
88
+
89
+#define SYSTICK(obj) OBJECT_CHECK(SysTickState, (obj), TYPE_SYSTICK)
90
+
91
+typedef struct SysTickState {
92
+ /*< private >*/
93
+ SysBusDevice parent_obj;
94
+ /*< public >*/
95
+
96
+ uint32_t control;
97
+ uint32_t reload;
98
+ int64_t tick;
99
+ QEMUTimer *timer;
100
+ MemoryRegion iomem;
101
+ qemu_irq irq;
102
+} SysTickState;
103
+
104
+#endif
105
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
33
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
106
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/intc/armv7m_nvic.c
35
--- a/hw/intc/armv7m_nvic.c
108
+++ b/hw/intc/armv7m_nvic.c
36
+++ b/hw/intc/armv7m_nvic.c
109
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
37
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
110
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
38
.endianness = DEVICE_NATIVE_ENDIAN,
111
};
39
};
112
40
113
-/* qemu timers run at 1GHz. We want something closer to 1MHz. */
114
-#define SYSTICK_SCALE 1000ULL
115
-
116
-#define SYSTICK_ENABLE (1 << 0)
117
-#define SYSTICK_TICKINT (1 << 1)
118
-#define SYSTICK_CLKSOURCE (1 << 2)
119
-#define SYSTICK_COUNTFLAG (1 << 16)
120
-
121
-int system_clock_scale;
122
-
123
-/* Conversion factor from qemu timer to SysTick frequencies. */
124
-static inline int64_t systick_scale(NVICState *s)
125
-{
126
- if (s->systick.control & SYSTICK_CLKSOURCE)
127
- return system_clock_scale;
128
- else
129
- return 1000;
130
-}
131
-
132
-static void systick_reload(NVICState *s, int reset)
133
-{
134
- /* The Cortex-M3 Devices Generic User Guide says that "When the
135
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
136
- * SYST RVR register and then counts down". So, we need to check the
137
- * ENABLE bit before reloading the value.
138
- */
139
- if ((s->systick.control & SYSTICK_ENABLE) == 0) {
140
- return;
141
- }
142
-
143
- if (reset)
144
- s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
145
- s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
146
- timer_mod(s->systick.timer, s->systick.tick);
147
-}
148
-
149
-static void systick_timer_tick(void * opaque)
150
-{
151
- NVICState *s = (NVICState *)opaque;
152
- s->systick.control |= SYSTICK_COUNTFLAG;
153
- if (s->systick.control & SYSTICK_TICKINT) {
154
- /* Trigger the interrupt. */
155
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
156
- }
157
- if (s->systick.reload == 0) {
158
- s->systick.control &= ~SYSTICK_ENABLE;
159
- } else {
160
- systick_reload(s, 0);
161
- }
162
-}
163
-
164
-static void systick_reset(NVICState *s)
165
-{
166
- s->systick.control = 0;
167
- s->systick.reload = 0;
168
- s->systick.tick = 0;
169
- timer_del(s->systick.timer);
170
-}
171
-
172
static int nvic_pending_prio(NVICState *s)
173
{
174
/* return the priority of the current pending interrupt,
175
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
176
switch (offset) {
177
case 4: /* Interrupt Control Type. */
178
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
179
- case 0x10: /* SysTick Control and Status. */
180
- val = s->systick.control;
181
- s->systick.control &= ~SYSTICK_COUNTFLAG;
182
- return val;
183
- case 0x14: /* SysTick Reload Value. */
184
- return s->systick.reload;
185
- case 0x18: /* SysTick Current Value. */
186
- {
187
- int64_t t;
188
- if ((s->systick.control & SYSTICK_ENABLE) == 0)
189
- return 0;
190
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
191
- if (t >= s->systick.tick)
192
- return 0;
193
- val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
194
- /* The interrupt in triggered when the timer reaches zero.
195
- However the counter is not reloaded until the next clock
196
- tick. This is a hack to return zero during the first tick. */
197
- if (val > s->systick.reload)
198
- val = 0;
199
- return val;
200
- }
201
- case 0x1c: /* SysTick Calibration Value. */
202
- return 10000;
203
case 0xd00: /* CPUID Base. */
204
return cpu->midr;
205
case 0xd04: /* Interrupt Control State. */
206
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
207
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
208
{
209
ARMCPU *cpu = s->cpu;
210
- uint32_t oldval;
211
+
41
+
212
switch (offset) {
42
+static MemTxResult ras_read(void *opaque, hwaddr addr,
213
- case 0x10: /* SysTick Control and Status. */
43
+ uint64_t *data, unsigned size,
214
- oldval = s->systick.control;
44
+ MemTxAttrs attrs)
215
- s->systick.control &= 0xfffffff8;
216
- s->systick.control |= value & 7;
217
- if ((oldval ^ value) & SYSTICK_ENABLE) {
218
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
219
- if (value & SYSTICK_ENABLE) {
220
- if (s->systick.tick) {
221
- s->systick.tick += now;
222
- timer_mod(s->systick.timer, s->systick.tick);
223
- } else {
224
- systick_reload(s, 1);
225
- }
226
- } else {
227
- timer_del(s->systick.timer);
228
- s->systick.tick -= now;
229
- if (s->systick.tick < 0)
230
- s->systick.tick = 0;
231
- }
232
- } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
233
- /* This is a hack. Force the timer to be reloaded
234
- when the reference clock is changed. */
235
- systick_reload(s, 1);
236
- }
237
- break;
238
- case 0x14: /* SysTick Reload Value. */
239
- s->systick.reload = value;
240
- break;
241
- case 0x18: /* SysTick Current Value. Writes reload the timer. */
242
- systick_reload(s, 1);
243
- s->systick.control &= ~SYSTICK_COUNTFLAG;
244
- break;
245
case 0xd04: /* Interrupt Control State. */
246
if (value & (1 << 31)) {
247
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
248
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
249
250
static const VMStateDescription vmstate_nvic = {
251
.name = "armv7m_nvic",
252
- .version_id = 3,
253
- .minimum_version_id = 3,
254
+ .version_id = 4,
255
+ .minimum_version_id = 4,
256
.post_load = &nvic_post_load,
257
.fields = (VMStateField[]) {
258
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
259
vmstate_VecInfo, VecInfo),
260
- VMSTATE_UINT32(systick.control, NVICState),
261
- VMSTATE_UINT32(systick.reload, NVICState),
262
- VMSTATE_INT64(systick.tick, NVICState),
263
- VMSTATE_TIMER_PTR(systick.timer, NVICState),
264
VMSTATE_UINT32(prigroup, NVICState),
265
VMSTATE_END_OF_LIST()
266
}
267
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
268
269
s->exception_prio = NVIC_NOEXC_PRIO;
270
s->vectpending = 0;
271
+}
272
273
- systick_reset(s);
274
+static void nvic_systick_trigger(void *opaque, int n, int level)
275
+{
45
+{
276
+ NVICState *s = opaque;
46
+ if (attrs.user) {
47
+ return MEMTX_ERROR;
48
+ }
277
+
49
+
278
+ if (level) {
50
+ switch (addr) {
279
+ /* SysTick just asked us to pend its exception.
51
+ case 0xe10: /* ERRIIDR */
280
+ * (This is different from an external interrupt line's
52
+ /* architect field = Arm; product/variant/revision 0 */
281
+ * behaviour.)
53
+ *data = 0x43b;
282
+ */
54
+ break;
283
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
55
+ case 0xfc8: /* ERRDEVID */
56
+ /* Minimal RAS: we implement 0 error record indexes */
57
+ *data = 0;
58
+ break;
59
+ default:
60
+ qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
61
+ (uint32_t)addr);
62
+ *data = 0;
63
+ break;
284
+ }
64
+ }
285
}
65
+ return MEMTX_OK;
286
287
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
288
{
289
NVICState *s = NVIC(dev);
290
+ SysBusDevice *systick_sbd;
291
+ Error *err = NULL;
292
293
s->cpu = ARM_CPU(qemu_get_cpu(0));
294
assert(s->cpu);
295
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
296
/* include space for internal exception vectors */
297
s->num_irq += NVIC_FIRST_IRQ;
298
299
+ object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
300
+ if (err != NULL) {
301
+ error_propagate(errp, err);
302
+ return;
303
+ }
304
+ systick_sbd = SYS_BUS_DEVICE(&s->systick);
305
+ sysbus_connect_irq(systick_sbd, 0,
306
+ qdev_get_gpio_in_named(dev, "systick-trigger", 0));
307
+
308
/* The NVIC and System Control Space (SCS) starts at 0xe000e000
309
* and looks like this:
310
* 0x004 - ICTR
311
- * 0x010 - 0x1c - systick
312
+ * 0x010 - 0xff - systick
313
* 0x100..0x7ec - NVIC
314
* 0x7f0..0xcff - Reserved
315
* 0xd00..0xd3c - SCS registers
316
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
317
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
318
"nvic_sysregs", 0x1000);
319
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
320
+ memory_region_add_subregion_overlap(&s->container, 0x10,
321
+ sysbus_mmio_get_region(systick_sbd, 0),
322
+ 1);
323
324
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
325
-
326
- s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
327
}
328
329
static void armv7m_nvic_instance_init(Object *obj)
330
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_instance_init(Object *obj)
331
NVICState *nvic = NVIC(obj);
332
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
333
334
+ object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
335
+ qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
336
+
337
sysbus_init_irq(sbd, &nvic->excpout);
338
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
339
+ qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
340
}
341
342
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
343
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
344
new file mode 100644
345
index XXXXXXX..XXXXXXX
346
--- /dev/null
347
+++ b/hw/timer/armv7m_systick.c
348
@@ -XXX,XX +XXX,XX @@
349
+/*
350
+ * ARMv7M SysTick timer
351
+ *
352
+ * Copyright (c) 2006-2007 CodeSourcery.
353
+ * Written by Paul Brook
354
+ * Copyright (c) 2017 Linaro Ltd
355
+ * Written by Peter Maydell
356
+ *
357
+ * This code is licensed under the GPL (version 2 or later).
358
+ */
359
+
360
+#include "qemu/osdep.h"
361
+#include "hw/timer/armv7m_systick.h"
362
+#include "qemu-common.h"
363
+#include "hw/sysbus.h"
364
+#include "qemu/timer.h"
365
+#include "qemu/log.h"
366
+#include "trace.h"
367
+
368
+/* qemu timers run at 1GHz. We want something closer to 1MHz. */
369
+#define SYSTICK_SCALE 1000ULL
370
+
371
+#define SYSTICK_ENABLE (1 << 0)
372
+#define SYSTICK_TICKINT (1 << 1)
373
+#define SYSTICK_CLKSOURCE (1 << 2)
374
+#define SYSTICK_COUNTFLAG (1 << 16)
375
+
376
+int system_clock_scale;
377
+
378
+/* Conversion factor from qemu timer to SysTick frequencies. */
379
+static inline int64_t systick_scale(SysTickState *s)
380
+{
381
+ if (s->control & SYSTICK_CLKSOURCE) {
382
+ return system_clock_scale;
383
+ } else {
384
+ return 1000;
385
+ }
386
+}
66
+}
387
+
67
+
388
+static void systick_reload(SysTickState *s, int reset)
68
+static MemTxResult ras_write(void *opaque, hwaddr addr,
69
+ uint64_t value, unsigned size,
70
+ MemTxAttrs attrs)
389
+{
71
+{
390
+ /* The Cortex-M3 Devices Generic User Guide says that "When the
72
+ if (attrs.user) {
391
+ * ENABLE bit is set to 1, the counter loads the RELOAD value from the
73
+ return MEMTX_ERROR;
392
+ * SYST RVR register and then counts down". So, we need to check the
393
+ * ENABLE bit before reloading the value.
394
+ */
395
+ trace_systick_reload();
396
+
397
+ if ((s->control & SYSTICK_ENABLE) == 0) {
398
+ return;
399
+ }
74
+ }
400
+
75
+
401
+ if (reset) {
76
+ switch (addr) {
402
+ s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
77
+ default:
78
+ qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
79
+ (uint32_t)addr);
80
+ break;
403
+ }
81
+ }
404
+ s->tick += (s->reload + 1) * systick_scale(s);
82
+ return MEMTX_OK;
405
+ timer_mod(s->timer, s->tick);
406
+}
83
+}
407
+
84
+
408
+static void systick_timer_tick(void *opaque)
85
+static const MemoryRegionOps ras_ops = {
409
+{
86
+ .read_with_attrs = ras_read,
410
+ SysTickState *s = (SysTickState *)opaque;
87
+ .write_with_attrs = ras_write,
88
+ .endianness = DEVICE_NATIVE_ENDIAN,
89
+};
411
+
90
+
412
+ trace_systick_timer_tick();
91
/*
413
+
92
* Unassigned portions of the PPB space are RAZ/WI for privileged
414
+ s->control |= SYSTICK_COUNTFLAG;
93
* accesses, and fault for non-privileged accesses.
415
+ if (s->control & SYSTICK_TICKINT) {
94
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
416
+ /* Tell the NVIC to pend the SysTick exception */
95
&s->systick_ns_mem, 1);
417
+ qemu_irq_pulse(s->irq);
96
}
418
+ }
97
419
+ if (s->reload == 0) {
98
+ if (cpu_isar_feature(aa32_ras, s->cpu)) {
420
+ s->control &= ~SYSTICK_ENABLE;
99
+ memory_region_init_io(&s->ras_mem, OBJECT(s),
421
+ } else {
100
+ &ras_ops, s, "nvic_ras", 0x1000);
422
+ systick_reload(s, 0);
101
+ memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
423
+ }
424
+}
425
+
426
+static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
427
+{
428
+ SysTickState *s = opaque;
429
+ uint32_t val;
430
+
431
+ switch (addr) {
432
+ case 0x0: /* SysTick Control and Status. */
433
+ val = s->control;
434
+ s->control &= ~SYSTICK_COUNTFLAG;
435
+ break;
436
+ case 0x4: /* SysTick Reload Value. */
437
+ val = s->reload;
438
+ break;
439
+ case 0x8: /* SysTick Current Value. */
440
+ {
441
+ int64_t t;
442
+
443
+ if ((s->control & SYSTICK_ENABLE) == 0) {
444
+ val = 0;
445
+ break;
446
+ }
447
+ t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
448
+ if (t >= s->tick) {
449
+ val = 0;
450
+ break;
451
+ }
452
+ val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
453
+ /* The interrupt in triggered when the timer reaches zero.
454
+ However the counter is not reloaded until the next clock
455
+ tick. This is a hack to return zero during the first tick. */
456
+ if (val > s->reload) {
457
+ val = 0;
458
+ }
459
+ break;
460
+ }
461
+ case 0xc: /* SysTick Calibration Value. */
462
+ val = 10000;
463
+ break;
464
+ default:
465
+ val = 0;
466
+ qemu_log_mask(LOG_GUEST_ERROR,
467
+ "SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
468
+ break;
469
+ }
102
+ }
470
+
103
+
471
+ trace_systick_read(addr, val, size);
104
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
472
+ return val;
105
}
473
+}
106
474
+
475
+static void systick_write(void *opaque, hwaddr addr,
476
+ uint64_t value, unsigned size)
477
+{
478
+ SysTickState *s = opaque;
479
+
480
+ trace_systick_write(addr, value, size);
481
+
482
+ switch (addr) {
483
+ case 0x0: /* SysTick Control and Status. */
484
+ {
485
+ uint32_t oldval = s->control;
486
+
487
+ s->control &= 0xfffffff8;
488
+ s->control |= value & 7;
489
+ if ((oldval ^ value) & SYSTICK_ENABLE) {
490
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
491
+ if (value & SYSTICK_ENABLE) {
492
+ if (s->tick) {
493
+ s->tick += now;
494
+ timer_mod(s->timer, s->tick);
495
+ } else {
496
+ systick_reload(s, 1);
497
+ }
498
+ } else {
499
+ timer_del(s->timer);
500
+ s->tick -= now;
501
+ if (s->tick < 0) {
502
+ s->tick = 0;
503
+ }
504
+ }
505
+ } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
506
+ /* This is a hack. Force the timer to be reloaded
507
+ when the reference clock is changed. */
508
+ systick_reload(s, 1);
509
+ }
510
+ break;
511
+ }
512
+ case 0x4: /* SysTick Reload Value. */
513
+ s->reload = value;
514
+ break;
515
+ case 0x8: /* SysTick Current Value. Writes reload the timer. */
516
+ systick_reload(s, 1);
517
+ s->control &= ~SYSTICK_COUNTFLAG;
518
+ break;
519
+ default:
520
+ qemu_log_mask(LOG_GUEST_ERROR,
521
+ "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
522
+ }
523
+}
524
+
525
+static const MemoryRegionOps systick_ops = {
526
+ .read = systick_read,
527
+ .write = systick_write,
528
+ .endianness = DEVICE_NATIVE_ENDIAN,
529
+ .valid.min_access_size = 4,
530
+ .valid.max_access_size = 4,
531
+};
532
+
533
+static void systick_reset(DeviceState *dev)
534
+{
535
+ SysTickState *s = SYSTICK(dev);
536
+
537
+ s->control = 0;
538
+ s->reload = 0;
539
+ s->tick = 0;
540
+ timer_del(s->timer);
541
+}
542
+
543
+static void systick_instance_init(Object *obj)
544
+{
545
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
546
+ SysTickState *s = SYSTICK(obj);
547
+
548
+ memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
549
+ sysbus_init_mmio(sbd, &s->iomem);
550
+ sysbus_init_irq(sbd, &s->irq);
551
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
552
+}
553
+
554
+static const VMStateDescription vmstate_systick = {
555
+ .name = "armv7m_systick",
556
+ .version_id = 1,
557
+ .minimum_version_id = 1,
558
+ .fields = (VMStateField[]) {
559
+ VMSTATE_UINT32(control, SysTickState),
560
+ VMSTATE_UINT32(reload, SysTickState),
561
+ VMSTATE_INT64(tick, SysTickState),
562
+ VMSTATE_TIMER_PTR(timer, SysTickState),
563
+ VMSTATE_END_OF_LIST()
564
+ }
565
+};
566
+
567
+static void systick_class_init(ObjectClass *klass, void *data)
568
+{
569
+ DeviceClass *dc = DEVICE_CLASS(klass);
570
+
571
+ dc->vmsd = &vmstate_systick;
572
+ dc->reset = systick_reset;
573
+}
574
+
575
+static const TypeInfo armv7m_systick_info = {
576
+ .name = TYPE_SYSTICK,
577
+ .parent = TYPE_SYS_BUS_DEVICE,
578
+ .instance_init = systick_instance_init,
579
+ .instance_size = sizeof(SysTickState),
580
+ .class_init = systick_class_init,
581
+};
582
+
583
+static void armv7m_systick_register_types(void)
584
+{
585
+ type_register_static(&armv7m_systick_info);
586
+}
587
+
588
+type_init(armv7m_systick_register_types)
589
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
590
index XXXXXXX..XXXXXXX 100644
591
--- a/hw/timer/trace-events
592
+++ b/hw/timer/trace-events
593
@@ -XXX,XX +XXX,XX @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
594
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
595
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
596
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
597
+
598
+# hw/timer/armv7m_systick.c
599
+systick_reload(void) "systick reload"
600
+systick_timer_tick(void) "systick reload"
601
+systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
602
+systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
603
--
107
--
604
2.7.4
108
2.20.1
605
109
606
110
diff view generated by jsdifflib
1
Make the legacy armv7m_init() function use the newly QOMified
1
Correct a typo in the name we give the NVIC object.
2
armv7m object rather than doing everything by hand.
3
4
We can return the armv7m object rather than the NVIC from
5
armv7m_init() because its interface to the rest of the
6
board (GPIOs, etc) is identical.
7
2
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1487604965-23220-5-git-send-email-peter.maydell@linaro.org
6
Message-id: 20201119215617.29887-28-peter.maydell@linaro.org
12
---
7
---
13
hw/arm/armv7m.c | 49 ++++++++++++-------------------------------------
8
hw/arm/armv7m.c | 2 +-
14
1 file changed, 12 insertions(+), 37 deletions(-)
9
1 file changed, 1 insertion(+), 1 deletion(-)
15
10
16
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
11
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/armv7m.c
13
--- a/hw/arm/armv7m.c
19
+++ b/hw/arm/armv7m.c
14
+++ b/hw/arm/armv7m.c
20
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
15
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
21
sysbus_init_mmio(dev, &s->iomem);
16
22
}
17
memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
23
18
24
-static void armv7m_bitband_init(void)
19
- object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC);
25
-{
20
+ object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC);
26
- DeviceState *dev;
21
object_property_add_alias(obj, "num-irq",
27
-
22
OBJECT(&s->nvic), "num-irq");
28
- dev = qdev_create(NULL, TYPE_BITBAND);
23
29
- qdev_prop_set_uint32(dev, "base", 0x20000000);
30
- qdev_init_nofail(dev);
31
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
32
-
33
- dev = qdev_create(NULL, TYPE_BITBAND);
34
- qdev_prop_set_uint32(dev, "base", 0x40000000);
35
- qdev_init_nofail(dev);
36
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
37
-}
38
-
39
/* Board init. */
40
41
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
43
44
/* Init CPU and memory for a v7-M based board.
45
mem_size is in bytes.
46
- Returns the NVIC array. */
47
+ Returns the ARMv7M device. */
48
49
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
50
const char *kernel_filename, const char *cpu_model)
51
{
52
- ARMCPU *cpu;
53
- CPUARMState *env;
54
- DeviceState *nvic;
55
+ DeviceState *armv7m;
56
57
if (cpu_model == NULL) {
58
-    cpu_model = "cortex-m3";
59
+ cpu_model = "cortex-m3";
60
}
61
- cpu = cpu_arm_init(cpu_model);
62
- if (cpu == NULL) {
63
- fprintf(stderr, "Unable to find CPU definition\n");
64
- exit(1);
65
- }
66
- env = &cpu->env;
67
-
68
- armv7m_bitband_init();
69
-
70
- nvic = qdev_create(NULL, "armv7m_nvic");
71
- qdev_prop_set_uint32(nvic, "num-irq", num_irq);
72
- env->nvic = nvic;
73
- qdev_init_nofail(nvic);
74
- sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
75
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
76
- armv7m_load_kernel(cpu, kernel_filename, mem_size);
77
- return nvic;
78
+
79
+ armv7m = qdev_create(NULL, "armv7m");
80
+ qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
81
+ qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
82
+ /* This will exit with an error if the user passed us a bad cpu_model */
83
+ qdev_init_nofail(armv7m);
84
+
85
+ armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
86
+ return armv7m;
87
}
88
89
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
90
--
24
--
91
2.7.4
25
2.20.1
92
26
93
27
diff view generated by jsdifflib