1
Second lot of ARM changes to sneak in before freeze:
1
Patches for rc1: nothing major, just some minor bugfixes and
2
* fixed version of the raspi2 sd controller patches
2
code cleanups.
3
* GICv3 save/restore
4
* v7M QOMify
5
3
6
I've also included the Linux header update patches stolen
7
from Paolo's pullreq since it hasn't quite hit master yet.
8
9
thanks
10
-- PMM
4
-- PMM
11
5
12
The following changes since commit 1bbe5dc66b770d7bedd1d51d7935da948a510dd6:
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
13
7
14
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging (2017-02-28 14:50:17 +0000)
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
15
9
16
are available in the git repository at:
10
are available in the Git repository at:
17
11
18
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228-1
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
19
13
20
for you to fetch changes up to 1eeb5c7deacbfb4d4cad17590a16a99f3d85eabb:
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
21
15
22
bcm2835: add sdhost and gpio controllers (2017-02-28 17:10:00 +0000)
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
23
17
24
----------------------------------------------------------------
18
----------------------------------------------------------------
25
target-arm queue:
19
target-arm queue:
26
* raspi2: add gpio controller and sdhost controller, with
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
27
the wiring so the guest can switch which controller the
21
* Minor coding style fixes
28
SD card is attached to
22
* docs: add some notes on the sbsa-ref machine
29
(this is sufficient to get raspbian kernels to boot)
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
30
* GICv3: support state save/restore from KVM
24
* target/arm: Fix neon VTBL/VTBX for len > 1
31
* update Linux headers to 4.11
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
32
* refactor and QOMify the ARMv7M container object
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
33
33
34
----------------------------------------------------------------
34
----------------------------------------------------------------
35
Clement Deschamps (3):
35
Alex Bennée (1):
36
hw/sd: add card-reparenting function
36
docs: add some notes on the sbsa-ref machine
37
bcm2835_gpio: add bcm2835 gpio controller
38
bcm2835: add sdhost and gpio controllers
39
37
40
Paolo Bonzini (2):
38
AlexChen (1):
41
update-linux-headers: update for 4.11
39
ssi: Fix bad printf format specifiers
42
update Linux headers to 4.11
43
40
44
Peter Maydell (12):
41
Andrew Jones (1):
45
armv7m: Abstract out the "load kernel" code
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
46
armv7m: Move NVICState struct definition into header
47
armv7m: QOMify the armv7m container
48
armv7m: Use QOMified armv7m object in armv7m_init()
49
armv7m: Make ARMv7M object take memory region link
50
armv7m: Make NVIC expose a memory region rather than mapping itself
51
armv7m: Make bitband device take the address space to access
52
armv7m: Don't put core v7M devices under CONFIG_STELLARIS
53
armv7m: Split systick out from NVIC
54
stm32f205: Create armv7m object without using armv7m_init()
55
stm32f205: Rename 'nvic' local to 'armv7m'
56
qdev: Have qdev_set_parent_bus() handle devices already on a bus
57
43
58
Vijaya Kumar K (4):
44
Havard Skinnemoen (1):
59
hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate
45
tests/qtest/npcm7xx_rng-test: count runs properly
60
hw/intc/arm_gicv3_kvm: Implement get/put functions
61
target-arm: Add GICv3CPUState in CPUARMState struct
62
hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers
63
46
64
hw/gpio/Makefile.objs | 1 +
47
Peter Maydell (2):
65
hw/intc/Makefile.objs | 2 +-
48
hw/arm/nseries: Check return value from load_image_targphys()
66
hw/timer/Makefile.objs | 1 +
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
67
hw/intc/gicv3_internal.h | 3 +
68
include/hw/arm/arm.h | 12 +
69
include/hw/arm/armv7m.h | 63 +++
70
include/hw/arm/armv7m_nvic.h | 62 ++
71
include/hw/arm/bcm2835_peripherals.h | 4 +
72
include/hw/arm/stm32f205_soc.h | 4 +-
73
include/hw/gpio/bcm2835_gpio.h | 39 ++
74
include/hw/intc/arm_gicv3_common.h | 1 +
75
include/hw/sd/sd.h | 11 +
76
include/hw/timer/armv7m_systick.h | 34 ++
77
include/standard-headers/asm-x86/hyperv.h | 8 +
78
include/standard-headers/linux/input-event-codes.h | 2 +-
79
include/standard-headers/linux/pci_regs.h | 25 +
80
include/standard-headers/linux/virtio_ids.h | 1 +
81
linux-headers/asm-arm/kvm.h | 15 +
82
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++
83
linux-headers/asm-arm/unistd-eabi.h | 5 +
84
linux-headers/asm-arm/unistd-oabi.h | 17 +
85
linux-headers/asm-arm/unistd.h | 419 +-------------
86
linux-headers/asm-arm64/kvm.h | 13 +
87
linux-headers/asm-powerpc/kvm.h | 27 +
88
linux-headers/asm-powerpc/unistd.h | 1 +
89
linux-headers/asm-x86/kvm_para.h | 13 +-
90
linux-headers/linux/kvm.h | 24 +-
91
linux-headers/linux/kvm_para.h | 2 +
92
linux-headers/linux/userfaultfd.h | 67 ++-
93
linux-headers/linux/vfio.h | 10 +
94
target/arm/cpu.h | 2 +
95
hw/arm/armv7m.c | 379 ++++++++-----
96
hw/arm/bcm2835_peripherals.c | 43 +-
97
hw/arm/netduino2.c | 7 +-
98
hw/arm/stm32f205_soc.c | 28 +-
99
hw/core/qdev.c | 14 +
100
hw/gpio/bcm2835_gpio.c | 353 ++++++++++++
101
hw/intc/arm_gicv3_common.c | 38 ++
102
hw/intc/arm_gicv3_cpuif.c | 8 +
103
hw/intc/arm_gicv3_kvm.c | 629 ++++++++++++++++++++-
104
hw/intc/armv7m_nvic.c | 214 ++-----
105
hw/sd/core.c | 27 +
106
hw/timer/armv7m_systick.c | 240 ++++++++
107
default-configs/arm-softmmu.mak | 2 +
108
hw/timer/trace-events | 6 +
109
scripts/update-linux-headers.sh | 13 +-
110
46 files changed, 2479 insertions(+), 767 deletions(-)
111
create mode 100644 include/hw/arm/armv7m.h
112
create mode 100644 include/hw/arm/armv7m_nvic.h
113
create mode 100644 include/hw/gpio/bcm2835_gpio.h
114
create mode 100644 include/hw/timer/armv7m_systick.h
115
create mode 100644 linux-headers/asm-arm/unistd-common.h
116
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
117
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
118
create mode 100644 hw/gpio/bcm2835_gpio.c
119
create mode 100644 hw/timer/armv7m_systick.c
120
50
51
Philippe Mathieu-Daudé (6):
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
58
59
Richard Henderson (1):
60
target/arm: Fix neon VTBL/VTBX for len > 1
61
62
Xinhao Zhang (3):
63
target/arm: add spaces around operator
64
target/arm: Don't use '#' flag of printf format
65
target/arm: add space before the open parenthesis '('
66
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
1
Instead of qdev_set_parent_bus() silently doing the wrong
1
From: Andrew Jones <drjones@redhat.com>
2
thing if it's handed a device that's already on a bus,
3
have it remove the device from the old bus and add it to
4
the new one. This is useful for the raspi2 sdcard.
5
2
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
5
in the build when building armv7m_systick.
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
Message-id: 1488293711-14195-2-git-send-email-peter.maydell@linaro.org
9
---
11
---
10
hw/core/qdev.c | 14 ++++++++++++++
12
hw/arm/Kconfig | 1 +
11
1 file changed, 14 insertions(+)
13
1 file changed, 1 insertion(+)
12
14
13
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/core/qdev.c
17
--- a/hw/arm/Kconfig
16
+++ b/hw/core/qdev.c
18
+++ b/hw/arm/Kconfig
17
@@ -XXX,XX +XXX,XX @@ static void bus_add_child(BusState *bus, DeviceState *child)
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
18
20
19
void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
21
config ARM_V7M
20
{
22
bool
21
+ bool replugging = dev->parent_bus != NULL;
23
+ select PTIMER
22
+
24
23
+ if (replugging) {
25
config ALLWINNER_A10
24
+ /* Keep a reference to the device while it's not plugged into
26
bool
25
+ * any bus, to avoid it potentially evaporating when it is
26
+ * dereffed in bus_remove_child().
27
+ */
28
+ object_ref(OBJECT(dev));
29
+ bus_remove_child(dev->parent_bus, dev);
30
+ object_unref(OBJECT(dev->parent_bus));
31
+ }
32
dev->parent_bus = bus;
33
object_ref(OBJECT(bus));
34
bus_add_child(bus, dev);
35
+ if (replugging) {
36
+ object_unref(OBJECT(dev));
37
+ }
38
}
39
40
/* Create a new device. This only initializes the device state
41
--
27
--
42
2.7.4
28
2.20.1
43
29
44
30
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
Provide a new function sdbus_reparent_card() in sd core for reparenting
3
We should use printf format specifier "%u" instead of "%d" for
4
a card from a SDBus to another one.
4
argument of type "unsigned int".
5
5
6
This function is required by the raspi platform, where the two SD
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
controllers can be dynamically switched.
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
9
Message-id: 5FA280F5.8060902@huawei.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1488293711-14195-3-git-send-email-peter.maydell@linaro.org
13
Message-id: 20170224164021.9066-3-clement.deschamps@antfield.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
[PMM: added a doc comment to the header file; changed to
16
use new behaviour of qdev_set_parent_bus()]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/sd/sd.h | 11 +++++++++++
12
hw/ssi/imx_spi.c | 2 +-
20
hw/sd/core.c | 27 +++++++++++++++++++++++++++
13
hw/ssi/xilinx_spi.c | 2 +-
21
2 files changed, 38 insertions(+)
14
2 files changed, 2 insertions(+), 2 deletions(-)
22
15
23
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/sd/sd.h
18
--- a/hw/ssi/imx_spi.c
26
+++ b/include/hw/sd/sd.h
19
+++ b/hw/ssi/imx_spi.c
27
@@ -XXX,XX +XXX,XX @@ uint8_t sdbus_read_data(SDBus *sd);
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
28
bool sdbus_data_ready(SDBus *sd);
21
case ECSPI_MSGDATA:
29
bool sdbus_get_inserted(SDBus *sd);
22
return "ECSPI_MSGDATA";
30
bool sdbus_get_readonly(SDBus *sd);
23
default:
31
+/**
24
- sprintf(unknown, "%d ?", reg);
32
+ * sdbus_reparent_card: Reparent an SD card from one controller to another
25
+ sprintf(unknown, "%u ?", reg);
33
+ * @from: controller bus to remove card from
26
return unknown;
34
+ * @to: controller bus to move card to
35
+ *
36
+ * Reparent an SD card, effectively unplugging it from one controller
37
+ * and inserting it into another. This is useful for SoCs like the
38
+ * bcm2835 which have two SD controllers and connect a single SD card
39
+ * to them, selected by the guest reprogramming GPIO line routing.
40
+ */
41
+void sdbus_reparent_card(SDBus *from, SDBus *to);
42
43
/* Functions to be used by SD devices to report back to qdevified controllers */
44
void sdbus_set_inserted(SDBus *sd, bool inserted);
45
diff --git a/hw/sd/core.c b/hw/sd/core.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/sd/core.c
48
+++ b/hw/sd/core.c
49
@@ -XXX,XX +XXX,XX @@ void sdbus_set_readonly(SDBus *sdbus, bool readonly)
50
}
27
}
51
}
28
}
52
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
53
+void sdbus_reparent_card(SDBus *from, SDBus *to)
30
index XXXXXXX..XXXXXXX 100644
54
+{
31
--- a/hw/ssi/xilinx_spi.c
55
+ SDState *card = get_card(from);
32
+++ b/hw/ssi/xilinx_spi.c
56
+ SDCardClass *sc;
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
57
+ bool readonly;
34
irq chain unless things really changed. */
58
+
35
if (pending != s->irqline) {
59
+ /* We directly reparent the card object rather than implementing this
36
s->irqline = pending;
60
+ * as a hotpluggable connection because we don't want to expose SD cards
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
61
+ * to users as being hotpluggable, and we can get away with it in this
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
62
+ * limited use case. This could perhaps be implemented more cleanly in
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
63
+ * future by adding support to the hotplug infrastructure for "device
40
qemu_set_irq(s->irq, pending);
64
+ * can be hotplugged only via code, not by user".
41
}
65
+ */
66
+
67
+ if (!card) {
68
+ return;
69
+ }
70
+
71
+ sc = SD_CARD_GET_CLASS(card);
72
+ readonly = sc->get_readonly(card);
73
+
74
+ sdbus_set_inserted(from, false);
75
+ qdev_set_parent_bus(DEVICE(card), &to->qbus);
76
+ sdbus_set_inserted(to, true);
77
+ sdbus_set_readonly(to, readonly);
78
+}
79
+
80
static const TypeInfo sd_bus_info = {
81
.name = TYPE_SD_BUS,
82
.parent = TYPE_BUS,
83
--
42
--
84
2.7.4
43
2.20.1
85
44
86
45
diff view generated by jsdifflib
1
Abstract the "load kernel" code out of armv7m_init() into its own
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
function. This includes the registration of the CPU reset function,
3
to parallel how we handle this for A profile cores.
4
2
5
We make the function public so that boards which choose to
3
Fix code style. Operator needs spaces both sides.
6
directly instantiate an ARMv7M device object can call it.
7
4
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
13
---
10
---
14
include/hw/arm/arm.h | 12 ++++++++++++
11
target/arm/arch_dump.c | 8 ++++----
15
hw/arm/armv7m.c | 23 ++++++++++++++++++-----
12
target/arm/arm-semi.c | 8 ++++----
16
2 files changed, 30 insertions(+), 5 deletions(-)
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
17
15
18
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/arm.h
18
--- a/target/arm/arch_dump.c
21
+++ b/include/hw/arm/arm.h
19
+++ b/target/arm/arch_dump.c
22
@@ -XXX,XX +XXX,XX @@ typedef enum {
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
23
/* armv7m.c */
21
24
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
22
for (i = 0; i < 32; ++i) {
25
const char *kernel_filename, const char *cpu_model);
23
uint64_t *q = aa64_vfp_qreg(env, i);
26
+/**
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
27
+ * armv7m_load_kernel:
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
28
+ * @cpu: CPU
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
29
+ * @kernel_filename: file to load
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
30
+ * @mem_size: mem_size: maximum image size to load
28
}
31
+ *
29
32
+ * Load the guest image for an ARMv7M system. This must be called by
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
33
+ * any ARMv7M board, either directly or via armv7m_init(). (This is
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
34
+ * necessary to ensure that the CPU resets correctly on system reset,
32
*/
35
+ * as well as for kernel loading.)
33
for (i = 0; i < 32; ++i) {
36
+ */
34
uint64_t tmp = note.vfp.vregs[2*i];
37
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size);
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
38
36
- note.vfp.vregs[2*i+1] = tmp;
39
/*
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
40
* struct used as a parameter of the arm_load_kernel machine init
38
+ note.vfp.vregs[2 * i + 1] = tmp;
41
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/armv7m.c
44
+++ b/hw/arm/armv7m.c
45
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
46
ARMCPU *cpu;
47
CPUARMState *env;
48
DeviceState *nvic;
49
- int image_size;
50
- uint64_t entry;
51
- uint64_t lowaddr;
52
- int big_endian;
53
54
if (cpu_model == NULL) {
55
    cpu_model = "cortex-m3";
56
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
57
qdev_init_nofail(nvic);
58
sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
59
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
60
+ armv7m_load_kernel(cpu, kernel_filename, mem_size);
61
+ return nvic;
62
+}
63
+
64
+void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
65
+{
66
+ int image_size;
67
+ uint64_t entry;
68
+ uint64_t lowaddr;
69
+ int big_endian;
70
71
#ifdef TARGET_WORDS_BIGENDIAN
72
big_endian = 1;
73
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
74
}
39
}
75
}
40
}
76
41
77
+ /* CPU objects (unlike devices) are not automatically reset on system
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
78
+ * reset, so we must always register a handler to do so. Unlike
43
index XXXXXXX..XXXXXXX 100644
79
+ * A-profile CPUs, we don't need to do anything special in the
44
--- a/target/arm/arm-semi.c
80
+ * handler to arrange that it starts correctly.
45
+++ b/target/arm/arm-semi.c
81
+ * This is arguably the wrong place to do this, but it matches the
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
82
+ * way A-profile does it. Note that this means that every M profile
47
if (use_gdb_syscalls()) {
83
+ * board must call this function!
48
arm_semi_open_guestfd = guestfd;
84
+ */
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
85
qemu_register_reset(armv7m_reset, cpu);
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
86
- return nvic;
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
87
uint32_t sum;
88
sum = do_usad(a, b);
89
sum += do_usad(a >> 8, b >> 8);
90
- sum += do_usad(a >> 16, b >>16);
91
+ sum += do_usad(a >> 16, b >> 16);
92
sum += do_usad(a >> 24, b >> 24);
93
return sum;
87
}
94
}
88
89
static Property bitband_properties[] = {
90
--
95
--
91
2.7.4
96
2.20.1
92
97
93
98
diff view generated by jsdifflib
Deleted patch
1
Move the NVICState struct definition into a header, so we can
2
embed it into other QOM objects like SoCs.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
8
---
9
include/hw/arm/armv7m_nvic.h | 66 ++++++++++++++++++++++++++++++++++++++++++++
10
hw/intc/armv7m_nvic.c | 49 +-------------------------------
11
2 files changed, 67 insertions(+), 48 deletions(-)
12
create mode 100644 include/hw/arm/armv7m_nvic.h
13
14
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/include/hw/arm/armv7m_nvic.h
19
@@ -XXX,XX +XXX,XX @@
20
+/*
21
+ * ARMv7M NVIC object
22
+ *
23
+ * Copyright (c) 2017 Linaro Ltd
24
+ * Written by Peter Maydell <peter.maydell@linaro.org>
25
+ *
26
+ * This code is licensed under the GPL version 2 or later.
27
+ */
28
+
29
+#ifndef HW_ARM_ARMV7M_NVIC_H
30
+#define HW_ARM_ARMV7M_NVIC_H
31
+
32
+#include "target/arm/cpu.h"
33
+#include "hw/sysbus.h"
34
+
35
+#define TYPE_NVIC "armv7m_nvic"
36
+
37
+#define NVIC(obj) \
38
+ OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
39
+
40
+/* Highest permitted number of exceptions (architectural limit) */
41
+#define NVIC_MAX_VECTORS 512
42
+
43
+typedef struct VecInfo {
44
+ /* Exception priorities can range from -3 to 255; only the unmodifiable
45
+ * priority values for RESET, NMI and HardFault can be negative.
46
+ */
47
+ int16_t prio;
48
+ uint8_t enabled;
49
+ uint8_t pending;
50
+ uint8_t active;
51
+ uint8_t level; /* exceptions <=15 never set level */
52
+} VecInfo;
53
+
54
+typedef struct NVICState {
55
+ /*< private >*/
56
+ SysBusDevice parent_obj;
57
+ /*< public >*/
58
+
59
+ ARMCPU *cpu;
60
+
61
+ VecInfo vectors[NVIC_MAX_VECTORS];
62
+ uint32_t prigroup;
63
+
64
+ /* vectpending and exception_prio are both cached state that can
65
+ * be recalculated from the vectors[] array and the prigroup field.
66
+ */
67
+ unsigned int vectpending; /* highest prio pending enabled exception */
68
+ int exception_prio; /* group prio of the highest prio active exception */
69
+
70
+ struct {
71
+ uint32_t control;
72
+ uint32_t reload;
73
+ int64_t tick;
74
+ QEMUTimer *timer;
75
+ } systick;
76
+
77
+ MemoryRegion sysregmem;
78
+ MemoryRegion container;
79
+
80
+ uint32_t num_irq;
81
+ qemu_irq excpout;
82
+ qemu_irq sysresetreq;
83
+} NVICState;
84
+
85
+#endif
86
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/intc/armv7m_nvic.c
89
+++ b/hw/intc/armv7m_nvic.c
90
@@ -XXX,XX +XXX,XX @@
91
#include "hw/sysbus.h"
92
#include "qemu/timer.h"
93
#include "hw/arm/arm.h"
94
+#include "hw/arm/armv7m_nvic.h"
95
#include "target/arm/cpu.h"
96
#include "exec/address-spaces.h"
97
#include "qemu/log.h"
98
@@ -XXX,XX +XXX,XX @@
99
* "exception" more or less interchangeably.
100
*/
101
#define NVIC_FIRST_IRQ 16
102
-#define NVIC_MAX_VECTORS 512
103
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
104
105
/* Effective running priority of the CPU when no exception is active
106
@@ -XXX,XX +XXX,XX @@
107
*/
108
#define NVIC_NOEXC_PRIO 0x100
109
110
-typedef struct VecInfo {
111
- /* Exception priorities can range from -3 to 255; only the unmodifiable
112
- * priority values for RESET, NMI and HardFault can be negative.
113
- */
114
- int16_t prio;
115
- uint8_t enabled;
116
- uint8_t pending;
117
- uint8_t active;
118
- uint8_t level; /* exceptions <=15 never set level */
119
-} VecInfo;
120
-
121
-typedef struct NVICState {
122
- /*< private >*/
123
- SysBusDevice parent_obj;
124
- /*< public >*/
125
-
126
- ARMCPU *cpu;
127
-
128
- VecInfo vectors[NVIC_MAX_VECTORS];
129
- uint32_t prigroup;
130
-
131
- /* vectpending and exception_prio are both cached state that can
132
- * be recalculated from the vectors[] array and the prigroup field.
133
- */
134
- unsigned int vectpending; /* highest prio pending enabled exception */
135
- int exception_prio; /* group prio of the highest prio active exception */
136
-
137
- struct {
138
- uint32_t control;
139
- uint32_t reload;
140
- int64_t tick;
141
- QEMUTimer *timer;
142
- } systick;
143
-
144
- MemoryRegion sysregmem;
145
- MemoryRegion container;
146
-
147
- uint32_t num_irq;
148
- qemu_irq excpout;
149
- qemu_irq sysresetreq;
150
-} NVICState;
151
-
152
-#define TYPE_NVIC "armv7m_nvic"
153
-
154
-#define NVIC(obj) \
155
- OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
156
-
157
static const uint8_t nvic_id[] = {
158
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
159
};
160
--
161
2.7.4
162
163
diff view generated by jsdifflib
Deleted patch
1
Create a proper QOM object for the armv7m container, which
2
holds the CPU, the NVIC and the bitband regions.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
7
---
8
include/hw/arm/armv7m.h | 51 ++++++++++++++++++
9
hw/arm/armv7m.c | 139 +++++++++++++++++++++++++++++++++++++++++++-----
10
2 files changed, 178 insertions(+), 12 deletions(-)
11
create mode 100644 include/hw/arm/armv7m.h
12
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
14
new file mode 100644
15
index XXXXXXX..XXXXXXX
16
--- /dev/null
17
+++ b/include/hw/arm/armv7m.h
18
@@ -XXX,XX +XXX,XX @@
19
+/*
20
+ * ARMv7M CPU object
21
+ *
22
+ * Copyright (c) 2017 Linaro Ltd
23
+ * Written by Peter Maydell <peter.maydell@linaro.org>
24
+ *
25
+ * This code is licensed under the GPL version 2 or later.
26
+ */
27
+
28
+#ifndef HW_ARM_ARMV7M_H
29
+#define HW_ARM_ARMV7M_H
30
+
31
+#include "hw/sysbus.h"
32
+#include "hw/arm/armv7m_nvic.h"
33
+
34
+#define TYPE_BITBAND "ARM,bitband-memory"
35
+#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
36
+
37
+typedef struct {
38
+ /*< private >*/
39
+ SysBusDevice parent_obj;
40
+ /*< public >*/
41
+
42
+ MemoryRegion iomem;
43
+ uint32_t base;
44
+} BitBandState;
45
+
46
+#define TYPE_ARMV7M "armv7m"
47
+#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
48
+
49
+#define ARMV7M_NUM_BITBANDS 2
50
+
51
+/* ARMv7M container object.
52
+ * + Unnamed GPIO input lines: external IRQ lines for the NVIC
53
+ * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
54
+ * + Property "cpu-model": CPU model to instantiate
55
+ * + Property "num-irq": number of external IRQ lines
56
+ */
57
+typedef struct ARMv7MState {
58
+ /*< private >*/
59
+ SysBusDevice parent_obj;
60
+ /*< public >*/
61
+ NVICState nvic;
62
+ BitBandState bitband[ARMV7M_NUM_BITBANDS];
63
+ ARMCPU *cpu;
64
+
65
+ /* Properties */
66
+ char *cpu_model;
67
+} ARMv7MState;
68
+
69
+#endif
70
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/armv7m.c
73
+++ b/hw/arm/armv7m.c
74
@@ -XXX,XX +XXX,XX @@
75
*/
76
77
#include "qemu/osdep.h"
78
+#include "hw/arm/armv7m.h"
79
#include "qapi/error.h"
80
#include "qemu-common.h"
81
#include "cpu.h"
82
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bitband_ops = {
83
.endianness = DEVICE_NATIVE_ENDIAN,
84
};
85
86
-#define TYPE_BITBAND "ARM,bitband-memory"
87
-#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
88
-
89
-typedef struct {
90
- /*< private >*/
91
- SysBusDevice parent_obj;
92
- /*< public >*/
93
-
94
- MemoryRegion iomem;
95
- uint32_t base;
96
-} BitBandState;
97
-
98
static void bitband_init(Object *obj)
99
{
100
BitBandState *s = BITBAND(obj);
101
@@ -XXX,XX +XXX,XX @@ static void armv7m_bitband_init(void)
102
103
/* Board init. */
104
105
+static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
106
+ 0x20000000, 0x40000000
107
+};
108
+
109
+static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
110
+ 0x22000000, 0x42000000
111
+};
112
+
113
+static void armv7m_instance_init(Object *obj)
114
+{
115
+ ARMv7MState *s = ARMV7M(obj);
116
+ int i;
117
+
118
+ /* Can't init the cpu here, we don't yet know which model to use */
119
+
120
+ object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
121
+ qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
122
+ object_property_add_alias(obj, "num-irq",
123
+ OBJECT(&s->nvic), "num-irq", &error_abort);
124
+
125
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
126
+ object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
127
+ qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
128
+ }
129
+}
130
+
131
+static void armv7m_realize(DeviceState *dev, Error **errp)
132
+{
133
+ ARMv7MState *s = ARMV7M(dev);
134
+ Error *err = NULL;
135
+ int i;
136
+ char **cpustr;
137
+ ObjectClass *oc;
138
+ const char *typename;
139
+ CPUClass *cc;
140
+
141
+ cpustr = g_strsplit(s->cpu_model, ",", 2);
142
+
143
+ oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
144
+ if (!oc) {
145
+ error_setg(errp, "Unknown CPU model %s", cpustr[0]);
146
+ g_strfreev(cpustr);
147
+ return;
148
+ }
149
+
150
+ cc = CPU_CLASS(oc);
151
+ typename = object_class_get_name(oc);
152
+ cc->parse_features(typename, cpustr[1], &err);
153
+ g_strfreev(cpustr);
154
+ if (err) {
155
+ error_propagate(errp, err);
156
+ return;
157
+ }
158
+
159
+ s->cpu = ARM_CPU(object_new(typename));
160
+ if (!s->cpu) {
161
+ error_setg(errp, "Unknown CPU model %s", s->cpu_model);
162
+ return;
163
+ }
164
+
165
+ object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
166
+ if (err != NULL) {
167
+ error_propagate(errp, err);
168
+ return;
169
+ }
170
+
171
+ /* Note that we must realize the NVIC after the CPU */
172
+ object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
173
+ if (err != NULL) {
174
+ error_propagate(errp, err);
175
+ return;
176
+ }
177
+
178
+ /* Alias the NVIC's input and output GPIOs as our own so the board
179
+ * code can wire them up. (We do this in realize because the
180
+ * NVIC doesn't create the input GPIO array until realize.)
181
+ */
182
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
183
+ qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
184
+
185
+ /* Wire the NVIC up to the CPU */
186
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
187
+ qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
188
+ s->cpu->env.nvic = &s->nvic;
189
+
190
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
191
+ Object *obj = OBJECT(&s->bitband[i]);
192
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
193
+
194
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
195
+ if (err != NULL) {
196
+ error_propagate(errp, err);
197
+ return;
198
+ }
199
+ object_property_set_bool(obj, true, "realized", &err);
200
+ if (err != NULL) {
201
+ error_propagate(errp, err);
202
+ return;
203
+ }
204
+
205
+ sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
206
+ }
207
+}
208
+
209
+static Property armv7m_properties[] = {
210
+ DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
211
+ DEFINE_PROP_END_OF_LIST(),
212
+};
213
+
214
+static void armv7m_class_init(ObjectClass *klass, void *data)
215
+{
216
+ DeviceClass *dc = DEVICE_CLASS(klass);
217
+
218
+ dc->realize = armv7m_realize;
219
+ dc->props = armv7m_properties;
220
+}
221
+
222
+static const TypeInfo armv7m_info = {
223
+ .name = TYPE_ARMV7M,
224
+ .parent = TYPE_SYS_BUS_DEVICE,
225
+ .instance_size = sizeof(ARMv7MState),
226
+ .instance_init = armv7m_instance_init,
227
+ .class_init = armv7m_class_init,
228
+};
229
+
230
static void armv7m_reset(void *opaque)
231
{
232
ARMCPU *cpu = opaque;
233
@@ -XXX,XX +XXX,XX @@ static const TypeInfo bitband_info = {
234
static void armv7m_register_types(void)
235
{
236
type_register_static(&bitband_info);
237
+ type_register_static(&armv7m_info);
238
}
239
240
type_init(armv7m_register_types)
241
--
242
2.7.4
243
244
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
This adds the bcm2835_sdhost and bcm2835_gpio to the BCM2835 platform.
3
Fix code style. Don't use '#' flag of printf format ('%#') in
4
format strings, use '0x' prefix instead
4
5
5
For supporting the SD controller selection (alternate function of GPIOs
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
48-53), the bcm2835_gpio now exposes an sdbus.
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
It also has a link to both the sdbus of sdhci and sdhost controllers,
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
8
and the card is reparented from one bus to another when the alternate
9
function of GPIOs 48-53 is modified.
10
11
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 1488293711-14195-5-git-send-email-peter.maydell@linaro.org
15
Message-id: 20170224164021.9066-5-clement.deschamps@antfield.fr
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
11
---
19
include/hw/arm/bcm2835_peripherals.h | 4 ++++
12
target/arm/translate-a64.c | 4 ++--
20
hw/arm/bcm2835_peripherals.c | 43 ++++++++++++++++++++++++++++++++++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
21
2 files changed, 45 insertions(+), 2 deletions(-)
22
14
23
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/bcm2835_peripherals.h
17
--- a/target/arm/translate-a64.c
26
+++ b/include/hw/arm/bcm2835_peripherals.h
18
+++ b/target/arm/translate-a64.c
27
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
28
#include "hw/misc/bcm2835_rng.h"
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
29
#include "hw/misc/bcm2835_mbox.h"
21
break;
30
#include "hw/sd/sdhci.h"
22
default:
31
+#include "hw/sd/bcm2835_sdhost.h"
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
32
+#include "hw/gpio/bcm2835_gpio.h"
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
33
25
__func__, insn, fpopcode, s->pc_curr);
34
#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
26
g_assert_not_reached();
35
#define BCM2835_PERIPHERALS(obj) \
27
}
36
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState {
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
37
BCM2835RngState rng;
29
case 0x7f: /* FSQRT (vector) */
38
BCM2835MboxState mboxes;
30
break;
39
SDHCIState sdhci;
31
default:
40
+ BCM2835SDHostState sdhost;
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
41
+ BCM2835GpioState gpio;
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
42
} BCM2835PeripheralState;
34
g_assert_not_reached();
43
44
#endif /* BCM2835_PERIPHERALS_H */
45
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/arm/bcm2835_peripherals.c
48
+++ b/hw/arm/bcm2835_peripherals.c
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
50
object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
51
qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
52
53
+ /* SDHOST */
54
+ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
55
+ object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
56
+ qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
57
+
58
/* DMA Channels */
59
object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
60
object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
61
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
62
63
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
64
OBJECT(&s->gpu_bus_mr), &error_abort);
65
+
66
+ /* GPIO */
67
+ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
68
+ object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
69
+ qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
70
+
71
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
72
+ OBJECT(&s->sdhci.sdbus), &error_abort);
73
+ object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost",
74
+ OBJECT(&s->sdhost.sdbus), &error_abort);
75
}
76
77
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
78
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
79
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
80
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
81
INTERRUPT_ARASANSDIO));
82
- object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->sdhci), "sd-bus",
83
- &err);
84
+
85
+ /* SDHOST */
86
+ object_property_set_bool(OBJECT(&s->sdhost), true, "realized", &err);
87
if (err) {
88
error_propagate(errp, err);
89
return;
90
}
35
}
91
36
92
+ memory_region_add_subregion(&s->peri_mr, MMCI0_OFFSET,
93
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhost), 0));
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhost), 0,
95
+ qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
96
+ INTERRUPT_SDIO));
97
+
98
/* DMA Channels */
99
object_property_set_bool(OBJECT(&s->dma), true, "realized", &err);
100
if (err) {
101
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
102
BCM2835_IC_GPU_IRQ,
103
INTERRUPT_DMA0 + n));
104
}
105
+
106
+ /* GPIO */
107
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
108
+ if (err) {
109
+ error_propagate(errp, err);
110
+ return;
111
+ }
112
+
113
+ memory_region_add_subregion(&s->peri_mr, GPIO_OFFSET,
114
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0));
115
+
116
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus",
117
+ &err);
118
+ if (err) {
119
+ error_propagate(errp, err);
120
+ return;
121
+ }
122
}
123
124
static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
125
--
37
--
126
2.7.4
38
2.20.1
127
39
128
40
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
Reset CPU interface registers of GICv3 when CPU is reset.
3
Fix code style. Space required before the open parenthesis '('.
4
For this, ARMCPRegInfo struct is registered with one ICC
5
register whose resetfn is called when cpu is reset.
6
4
7
All the ICC registers are reset under one single register
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
8
reset function instead of calling resetfn for each ICC
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
9
register.
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
10
11
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1487850673-26455-6-git-send-email-vijay.kilari@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
10
---
17
hw/intc/arm_gicv3_kvm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
11
target/arm/translate.c | 2 +-
18
1 file changed, 60 insertions(+)
12
1 file changed, 1 insertion(+), 1 deletion(-)
19
13
20
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_kvm.c
16
--- a/target/arm/translate.c
23
+++ b/hw/intc/arm_gicv3_kvm.c
17
+++ b/target/arm/translate.c
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_get(GICv3State *s)
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
25
}
19
- Hardware watchpoints.
26
}
20
Hardware breakpoints have already been handled and skip this code.
27
21
*/
28
+static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
22
- switch(dc->base.is_jmp) {
29
+{
23
+ switch (dc->base.is_jmp) {
30
+ ARMCPU *cpu;
24
case DISAS_NEXT:
31
+ GICv3State *s;
25
case DISAS_TOO_MANY:
32
+ GICv3CPUState *c;
26
gen_goto_tb(dc, 1, dc->base.pc_next);
33
+
34
+ c = (GICv3CPUState *)env->gicv3state;
35
+ s = c->gic;
36
+ cpu = ARM_CPU(c->cpu);
37
+
38
+ /* Initialize to actual HW supported configuration */
39
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
40
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
41
+ &c->icc_ctlr_el1[GICV3_NS], false);
42
+
43
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
44
+ c->icc_pmr_el1 = 0;
45
+ c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
46
+ c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
47
+ c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
48
+
49
+ c->icc_sre_el1 = 0x7;
50
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
51
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
52
+}
53
+
54
static void kvm_arm_gicv3_reset(DeviceState *dev)
55
{
56
GICv3State *s = ARM_GICV3_COMMON(dev);
57
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
58
kvm_arm_gicv3_put(s);
59
}
60
61
+/*
62
+ * CPU interface registers of GIC needs to be reset on CPU reset.
63
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
64
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
65
+ * register reset, we define only one register of CPU interface instead
66
+ * of defining all the registers.
67
+ */
68
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
69
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
70
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
71
+ /*
72
+ * If ARM_CP_NOP is used, resetfn is not called,
73
+ * So ARM_CP_NO_RAW is appropriate type.
74
+ */
75
+ .type = ARM_CP_NO_RAW,
76
+ .access = PL1_RW,
77
+ .readfn = arm_cp_read_zero,
78
+ .writefn = arm_cp_write_ignore,
79
+ /*
80
+ * We hang the whole cpu interface reset routine off here
81
+ * rather than parcelling it out into one little function
82
+ * per register
83
+ */
84
+ .resetfn = arm_gicv3_icc_reset,
85
+ },
86
+ REGINFO_SENTINEL
87
+};
88
+
89
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
90
{
91
GICv3State *s = KVM_ARM_GICV3(dev);
92
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
93
94
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
95
96
+ for (i = 0; i < s->num_cpu; i++) {
97
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
98
+
99
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
100
+ }
101
+
102
/* Try to create the device via the device control API */
103
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
104
if (s->dev_fd < 0) {
105
--
27
--
106
2.7.4
28
2.20.1
107
29
108
30
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
virtio_mmio.h would be deleted; I am leaving it in though it was a
3
We should at least document what this machine is about.
4
mistake to add it.
5
4
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
13
---
9
include/standard-headers/asm-x86/hyperv.h | 8 +
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
10
include/standard-headers/linux/input-event-codes.h | 2 +-
15
docs/system/target-arm.rst | 1 +
11
include/standard-headers/linux/pci_regs.h | 25 ++
16
2 files changed, 33 insertions(+)
12
include/standard-headers/linux/virtio_ids.h | 1 +
17
create mode 100644 docs/system/arm/sbsa.rst
13
linux-headers/asm-arm/kvm.h | 15 +
14
linux-headers/asm-arm/unistd-common.h | 357 ++++++++++++++++++
15
linux-headers/asm-arm/unistd-eabi.h | 5 +
16
linux-headers/asm-arm/unistd-oabi.h | 17 +
17
linux-headers/asm-arm/unistd.h | 419 +--------------------
18
linux-headers/asm-arm64/kvm.h | 13 +
19
linux-headers/asm-powerpc/kvm.h | 27 ++
20
linux-headers/asm-powerpc/unistd.h | 1 +
21
linux-headers/asm-x86/kvm_para.h | 13 +-
22
linux-headers/linux/kvm.h | 24 +-
23
linux-headers/linux/kvm_para.h | 2 +
24
linux-headers/linux/userfaultfd.h | 67 +++-
25
linux-headers/linux/vfio.h | 10 +
26
17 files changed, 577 insertions(+), 429 deletions(-)
27
create mode 100644 linux-headers/asm-arm/unistd-common.h
28
create mode 100644 linux-headers/asm-arm/unistd-eabi.h
29
create mode 100644 linux-headers/asm-arm/unistd-oabi.h
30
18
31
diff --git a/include/standard-headers/asm-x86/hyperv.h b/include/standard-headers/asm-x86/hyperv.h
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/standard-headers/asm-x86/hyperv.h
34
+++ b/include/standard-headers/asm-x86/hyperv.h
35
@@ -XXX,XX +XXX,XX @@
36
*/
37
#define HV_X64_MSR_STAT_PAGES_AVAILABLE        (1 << 8)
38
39
+/* Crash MSR available */
40
+#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10)
41
+
42
/*
43
* Feature identification: EBX indicates which flags were specified at
44
* partition creation. The format is the same as the partition creation
45
@@ -XXX,XX +XXX,XX @@
46
*/
47
#define HV_X64_RELAXED_TIMING_RECOMMENDED    (1 << 5)
48
49
+/*
50
+ * Crash notification flag.
51
+ */
52
+#define HV_CRASH_CTL_CRASH_NOTIFY (1ULL << 63)
53
+
54
/* MSR used to identify the guest OS. */
55
#define HV_X64_MSR_GUEST_OS_ID            0x40000000
56
57
diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/standard-headers/linux/input-event-codes.h
60
+++ b/include/standard-headers/linux/input-event-codes.h
61
@@ -XXX,XX +XXX,XX @@
62
* Control a data application associated with the currently viewed channel,
63
* e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
64
*/
65
-#define KEY_DATA            0x275
66
+#define KEY_DATA            0x277
67
68
#define BTN_TRIGGER_HAPPY        0x2c0
69
#define BTN_TRIGGER_HAPPY1        0x2c0
70
diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/standard-headers/linux/pci_regs.h
73
+++ b/include/standard-headers/linux/pci_regs.h
74
@@ -XXX,XX +XXX,XX @@
75
#define LINUX_PCI_REGS_H
76
77
/*
78
+ * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
79
+ * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
80
+ * configuration space.
81
+ */
82
+#define PCI_CFG_SPACE_SIZE    256
83
+#define PCI_CFG_SPACE_EXP_SIZE    4096
84
+
85
+/*
86
* Under PCI, each device has 256 bytes of configuration address space,
87
* of which the first 64 bytes are standardized as follows:
88
*/
89
@@ -XXX,XX +XXX,XX @@
90
#define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
91
#define PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */
92
#define PCI_EXT_CAP_ID_DPC    0x1D    /* Downstream Port Containment */
93
+#define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
94
#define PCI_EXT_CAP_ID_PTM    0x1F    /* Precision Time Measurement */
95
#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PTM
96
97
@@ -XXX,XX +XXX,XX @@
98
#define PCI_EXP_DPC_STATUS        8    /* DPC Status */
99
#define PCI_EXP_DPC_STATUS_TRIGGER    0x01    /* Trigger Status */
100
#define PCI_EXP_DPC_STATUS_INTERRUPT    0x08    /* Interrupt Status */
101
+#define PCI_EXP_DPC_RP_BUSY        0x10    /* Root Port Busy */
102
103
#define PCI_EXP_DPC_SOURCE_ID        10    /* DPC Source Identifier */
104
105
@@ -XXX,XX +XXX,XX @@
106
#define PCI_PTM_CTRL_ENABLE        0x00000001 /* PTM enable */
107
#define PCI_PTM_CTRL_ROOT        0x00000002 /* Root select */
108
109
+/* L1 PM Substates */
110
+#define PCI_L1SS_CAP         4    /* capability register */
111
+#define PCI_L1SS_CAP_PCIPM_L1_2     1    /* PCI PM L1.2 Support */
112
+#define PCI_L1SS_CAP_PCIPM_L1_1     2    /* PCI PM L1.1 Support */
113
+#define PCI_L1SS_CAP_ASPM_L1_2         4    /* ASPM L1.2 Support */
114
+#define PCI_L1SS_CAP_ASPM_L1_1         8    /* ASPM L1.1 Support */
115
+#define PCI_L1SS_CAP_L1_PM_SS        16    /* L1 PM Substates Support */
116
+#define PCI_L1SS_CTL1         8    /* Control Register 1 */
117
+#define PCI_L1SS_CTL1_PCIPM_L1_2    1    /* PCI PM L1.2 Enable */
118
+#define PCI_L1SS_CTL1_PCIPM_L1_1    2    /* PCI PM L1.1 Support */
119
+#define PCI_L1SS_CTL1_ASPM_L1_2    4    /* ASPM L1.2 Support */
120
+#define PCI_L1SS_CTL1_ASPM_L1_1    8    /* ASPM L1.1 Support */
121
+#define PCI_L1SS_CTL1_L1SS_MASK    0x0000000F
122
+#define PCI_L1SS_CTL2         0xC    /* Control Register 2 */
123
+
124
#endif /* LINUX_PCI_REGS_H */
125
diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h
126
index XXXXXXX..XXXXXXX 100644
127
--- a/include/standard-headers/linux/virtio_ids.h
128
+++ b/include/standard-headers/linux/virtio_ids.h
129
@@ -XXX,XX +XXX,XX @@
130
#define VIRTIO_ID_INPUT 18 /* virtio input */
131
#define VIRTIO_ID_VSOCK 19 /* virtio vsock transport */
132
#define VIRTIO_ID_CRYPTO 20 /* virtio crypto */
133
+
134
#endif /* _LINUX_VIRTIO_IDS_H */
135
diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/linux-headers/asm-arm/kvm.h
138
+++ b/linux-headers/asm-arm/kvm.h
139
@@ -XXX,XX +XXX,XX @@ struct kvm_regs {
140
/* Supported VGICv3 address types */
141
#define KVM_VGIC_V3_ADDR_TYPE_DIST    2
142
#define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
143
+#define KVM_VGIC_ITS_ADDR_TYPE        4
144
145
#define KVM_VGIC_V3_DIST_SIZE        SZ_64K
146
#define KVM_VGIC_V3_REDIST_SIZE        (2 * SZ_64K)
147
+#define KVM_VGIC_V3_ITS_SIZE        (2 * SZ_64K)
148
149
#define KVM_ARM_VCPU_POWER_OFF        0 /* CPU is started in OFF state */
150
#define KVM_ARM_VCPU_PSCI_0_2        1 /* CPU uses PSCI v0.2 */
151
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
152
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
153
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
154
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
155
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
156
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
157
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
158
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
159
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
160
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
161
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
162
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
163
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
164
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
165
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
166
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
167
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
168
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
169
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
170
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
171
+
172
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
173
174
/* KVM_IRQ_LINE irq field index values */
175
diff --git a/linux-headers/asm-arm/unistd-common.h b/linux-headers/asm-arm/unistd-common.h
176
new file mode 100644
20
new file mode 100644
177
index XXXXXXX..XXXXXXX
21
index XXXXXXX..XXXXXXX
178
--- /dev/null
22
--- /dev/null
179
+++ b/linux-headers/asm-arm/unistd-common.h
23
+++ b/docs/system/arm/sbsa.rst
180
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
181
+#ifndef _ASM_ARM_UNISTD_COMMON_H
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
182
+#define _ASM_ARM_UNISTD_COMMON_H 1
26
+==================================================================
183
+
27
+
184
+#define __NR_restart_syscall (__NR_SYSCALL_BASE + 0)
28
+While the `virt` board is a generic board platform that doesn't match
185
+#define __NR_exit (__NR_SYSCALL_BASE + 1)
29
+any real hardware the `sbsa-ref` board intends to look like real
186
+#define __NR_fork (__NR_SYSCALL_BASE + 2)
30
+hardware. The `Server Base System Architecture
187
+#define __NR_read (__NR_SYSCALL_BASE + 3)
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
188
+#define __NR_write (__NR_SYSCALL_BASE + 4)
32
+minimum base line of hardware support and importantly how the firmware
189
+#define __NR_open (__NR_SYSCALL_BASE + 5)
33
+reports that to any operating system. It is a static system that
190
+#define __NR_close (__NR_SYSCALL_BASE + 6)
34
+reports a very minimal DT to the firmware for non-discoverable
191
+#define __NR_creat (__NR_SYSCALL_BASE + 8)
35
+information about components affected by the qemu command line (i.e.
192
+#define __NR_link (__NR_SYSCALL_BASE + 9)
36
+cpus and memory). As a result it must have a firmware specifically
193
+#define __NR_unlink (__NR_SYSCALL_BASE + 10)
37
+built to expect a certain hardware layout (as you would in a real
194
+#define __NR_execve (__NR_SYSCALL_BASE + 11)
38
+machine).
195
+#define __NR_chdir (__NR_SYSCALL_BASE + 12)
196
+#define __NR_mknod (__NR_SYSCALL_BASE + 14)
197
+#define __NR_chmod (__NR_SYSCALL_BASE + 15)
198
+#define __NR_lchown (__NR_SYSCALL_BASE + 16)
199
+#define __NR_lseek (__NR_SYSCALL_BASE + 19)
200
+#define __NR_getpid (__NR_SYSCALL_BASE + 20)
201
+#define __NR_mount (__NR_SYSCALL_BASE + 21)
202
+#define __NR_setuid (__NR_SYSCALL_BASE + 23)
203
+#define __NR_getuid (__NR_SYSCALL_BASE + 24)
204
+#define __NR_ptrace (__NR_SYSCALL_BASE + 26)
205
+#define __NR_pause (__NR_SYSCALL_BASE + 29)
206
+#define __NR_access (__NR_SYSCALL_BASE + 33)
207
+#define __NR_nice (__NR_SYSCALL_BASE + 34)
208
+#define __NR_sync (__NR_SYSCALL_BASE + 36)
209
+#define __NR_kill (__NR_SYSCALL_BASE + 37)
210
+#define __NR_rename (__NR_SYSCALL_BASE + 38)
211
+#define __NR_mkdir (__NR_SYSCALL_BASE + 39)
212
+#define __NR_rmdir (__NR_SYSCALL_BASE + 40)
213
+#define __NR_dup (__NR_SYSCALL_BASE + 41)
214
+#define __NR_pipe (__NR_SYSCALL_BASE + 42)
215
+#define __NR_times (__NR_SYSCALL_BASE + 43)
216
+#define __NR_brk (__NR_SYSCALL_BASE + 45)
217
+#define __NR_setgid (__NR_SYSCALL_BASE + 46)
218
+#define __NR_getgid (__NR_SYSCALL_BASE + 47)
219
+#define __NR_geteuid (__NR_SYSCALL_BASE + 49)
220
+#define __NR_getegid (__NR_SYSCALL_BASE + 50)
221
+#define __NR_acct (__NR_SYSCALL_BASE + 51)
222
+#define __NR_umount2 (__NR_SYSCALL_BASE + 52)
223
+#define __NR_ioctl (__NR_SYSCALL_BASE + 54)
224
+#define __NR_fcntl (__NR_SYSCALL_BASE + 55)
225
+#define __NR_setpgid (__NR_SYSCALL_BASE + 57)
226
+#define __NR_umask (__NR_SYSCALL_BASE + 60)
227
+#define __NR_chroot (__NR_SYSCALL_BASE + 61)
228
+#define __NR_ustat (__NR_SYSCALL_BASE + 62)
229
+#define __NR_dup2 (__NR_SYSCALL_BASE + 63)
230
+#define __NR_getppid (__NR_SYSCALL_BASE + 64)
231
+#define __NR_getpgrp (__NR_SYSCALL_BASE + 65)
232
+#define __NR_setsid (__NR_SYSCALL_BASE + 66)
233
+#define __NR_sigaction (__NR_SYSCALL_BASE + 67)
234
+#define __NR_setreuid (__NR_SYSCALL_BASE + 70)
235
+#define __NR_setregid (__NR_SYSCALL_BASE + 71)
236
+#define __NR_sigsuspend (__NR_SYSCALL_BASE + 72)
237
+#define __NR_sigpending (__NR_SYSCALL_BASE + 73)
238
+#define __NR_sethostname (__NR_SYSCALL_BASE + 74)
239
+#define __NR_setrlimit (__NR_SYSCALL_BASE + 75)
240
+#define __NR_getrusage (__NR_SYSCALL_BASE + 77)
241
+#define __NR_gettimeofday (__NR_SYSCALL_BASE + 78)
242
+#define __NR_settimeofday (__NR_SYSCALL_BASE + 79)
243
+#define __NR_getgroups (__NR_SYSCALL_BASE + 80)
244
+#define __NR_setgroups (__NR_SYSCALL_BASE + 81)
245
+#define __NR_symlink (__NR_SYSCALL_BASE + 83)
246
+#define __NR_readlink (__NR_SYSCALL_BASE + 85)
247
+#define __NR_uselib (__NR_SYSCALL_BASE + 86)
248
+#define __NR_swapon (__NR_SYSCALL_BASE + 87)
249
+#define __NR_reboot (__NR_SYSCALL_BASE + 88)
250
+#define __NR_munmap (__NR_SYSCALL_BASE + 91)
251
+#define __NR_truncate (__NR_SYSCALL_BASE + 92)
252
+#define __NR_ftruncate (__NR_SYSCALL_BASE + 93)
253
+#define __NR_fchmod (__NR_SYSCALL_BASE + 94)
254
+#define __NR_fchown (__NR_SYSCALL_BASE + 95)
255
+#define __NR_getpriority (__NR_SYSCALL_BASE + 96)
256
+#define __NR_setpriority (__NR_SYSCALL_BASE + 97)
257
+#define __NR_statfs (__NR_SYSCALL_BASE + 99)
258
+#define __NR_fstatfs (__NR_SYSCALL_BASE + 100)
259
+#define __NR_syslog (__NR_SYSCALL_BASE + 103)
260
+#define __NR_setitimer (__NR_SYSCALL_BASE + 104)
261
+#define __NR_getitimer (__NR_SYSCALL_BASE + 105)
262
+#define __NR_stat (__NR_SYSCALL_BASE + 106)
263
+#define __NR_lstat (__NR_SYSCALL_BASE + 107)
264
+#define __NR_fstat (__NR_SYSCALL_BASE + 108)
265
+#define __NR_vhangup (__NR_SYSCALL_BASE + 111)
266
+#define __NR_wait4 (__NR_SYSCALL_BASE + 114)
267
+#define __NR_swapoff (__NR_SYSCALL_BASE + 115)
268
+#define __NR_sysinfo (__NR_SYSCALL_BASE + 116)
269
+#define __NR_fsync (__NR_SYSCALL_BASE + 118)
270
+#define __NR_sigreturn (__NR_SYSCALL_BASE + 119)
271
+#define __NR_clone (__NR_SYSCALL_BASE + 120)
272
+#define __NR_setdomainname (__NR_SYSCALL_BASE + 121)
273
+#define __NR_uname (__NR_SYSCALL_BASE + 122)
274
+#define __NR_adjtimex (__NR_SYSCALL_BASE + 124)
275
+#define __NR_mprotect (__NR_SYSCALL_BASE + 125)
276
+#define __NR_sigprocmask (__NR_SYSCALL_BASE + 126)
277
+#define __NR_init_module (__NR_SYSCALL_BASE + 128)
278
+#define __NR_delete_module (__NR_SYSCALL_BASE + 129)
279
+#define __NR_quotactl (__NR_SYSCALL_BASE + 131)
280
+#define __NR_getpgid (__NR_SYSCALL_BASE + 132)
281
+#define __NR_fchdir (__NR_SYSCALL_BASE + 133)
282
+#define __NR_bdflush (__NR_SYSCALL_BASE + 134)
283
+#define __NR_sysfs (__NR_SYSCALL_BASE + 135)
284
+#define __NR_personality (__NR_SYSCALL_BASE + 136)
285
+#define __NR_setfsuid (__NR_SYSCALL_BASE + 138)
286
+#define __NR_setfsgid (__NR_SYSCALL_BASE + 139)
287
+#define __NR__llseek (__NR_SYSCALL_BASE + 140)
288
+#define __NR_getdents (__NR_SYSCALL_BASE + 141)
289
+#define __NR__newselect (__NR_SYSCALL_BASE + 142)
290
+#define __NR_flock (__NR_SYSCALL_BASE + 143)
291
+#define __NR_msync (__NR_SYSCALL_BASE + 144)
292
+#define __NR_readv (__NR_SYSCALL_BASE + 145)
293
+#define __NR_writev (__NR_SYSCALL_BASE + 146)
294
+#define __NR_getsid (__NR_SYSCALL_BASE + 147)
295
+#define __NR_fdatasync (__NR_SYSCALL_BASE + 148)
296
+#define __NR__sysctl (__NR_SYSCALL_BASE + 149)
297
+#define __NR_mlock (__NR_SYSCALL_BASE + 150)
298
+#define __NR_munlock (__NR_SYSCALL_BASE + 151)
299
+#define __NR_mlockall (__NR_SYSCALL_BASE + 152)
300
+#define __NR_munlockall (__NR_SYSCALL_BASE + 153)
301
+#define __NR_sched_setparam (__NR_SYSCALL_BASE + 154)
302
+#define __NR_sched_getparam (__NR_SYSCALL_BASE + 155)
303
+#define __NR_sched_setscheduler (__NR_SYSCALL_BASE + 156)
304
+#define __NR_sched_getscheduler (__NR_SYSCALL_BASE + 157)
305
+#define __NR_sched_yield (__NR_SYSCALL_BASE + 158)
306
+#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE + 159)
307
+#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE + 160)
308
+#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE + 161)
309
+#define __NR_nanosleep (__NR_SYSCALL_BASE + 162)
310
+#define __NR_mremap (__NR_SYSCALL_BASE + 163)
311
+#define __NR_setresuid (__NR_SYSCALL_BASE + 164)
312
+#define __NR_getresuid (__NR_SYSCALL_BASE + 165)
313
+#define __NR_poll (__NR_SYSCALL_BASE + 168)
314
+#define __NR_nfsservctl (__NR_SYSCALL_BASE + 169)
315
+#define __NR_setresgid (__NR_SYSCALL_BASE + 170)
316
+#define __NR_getresgid (__NR_SYSCALL_BASE + 171)
317
+#define __NR_prctl (__NR_SYSCALL_BASE + 172)
318
+#define __NR_rt_sigreturn (__NR_SYSCALL_BASE + 173)
319
+#define __NR_rt_sigaction (__NR_SYSCALL_BASE + 174)
320
+#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE + 175)
321
+#define __NR_rt_sigpending (__NR_SYSCALL_BASE + 176)
322
+#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE + 177)
323
+#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE + 178)
324
+#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE + 179)
325
+#define __NR_pread64 (__NR_SYSCALL_BASE + 180)
326
+#define __NR_pwrite64 (__NR_SYSCALL_BASE + 181)
327
+#define __NR_chown (__NR_SYSCALL_BASE + 182)
328
+#define __NR_getcwd (__NR_SYSCALL_BASE + 183)
329
+#define __NR_capget (__NR_SYSCALL_BASE + 184)
330
+#define __NR_capset (__NR_SYSCALL_BASE + 185)
331
+#define __NR_sigaltstack (__NR_SYSCALL_BASE + 186)
332
+#define __NR_sendfile (__NR_SYSCALL_BASE + 187)
333
+#define __NR_vfork (__NR_SYSCALL_BASE + 190)
334
+#define __NR_ugetrlimit (__NR_SYSCALL_BASE + 191)
335
+#define __NR_mmap2 (__NR_SYSCALL_BASE + 192)
336
+#define __NR_truncate64 (__NR_SYSCALL_BASE + 193)
337
+#define __NR_ftruncate64 (__NR_SYSCALL_BASE + 194)
338
+#define __NR_stat64 (__NR_SYSCALL_BASE + 195)
339
+#define __NR_lstat64 (__NR_SYSCALL_BASE + 196)
340
+#define __NR_fstat64 (__NR_SYSCALL_BASE + 197)
341
+#define __NR_lchown32 (__NR_SYSCALL_BASE + 198)
342
+#define __NR_getuid32 (__NR_SYSCALL_BASE + 199)
343
+#define __NR_getgid32 (__NR_SYSCALL_BASE + 200)
344
+#define __NR_geteuid32 (__NR_SYSCALL_BASE + 201)
345
+#define __NR_getegid32 (__NR_SYSCALL_BASE + 202)
346
+#define __NR_setreuid32 (__NR_SYSCALL_BASE + 203)
347
+#define __NR_setregid32 (__NR_SYSCALL_BASE + 204)
348
+#define __NR_getgroups32 (__NR_SYSCALL_BASE + 205)
349
+#define __NR_setgroups32 (__NR_SYSCALL_BASE + 206)
350
+#define __NR_fchown32 (__NR_SYSCALL_BASE + 207)
351
+#define __NR_setresuid32 (__NR_SYSCALL_BASE + 208)
352
+#define __NR_getresuid32 (__NR_SYSCALL_BASE + 209)
353
+#define __NR_setresgid32 (__NR_SYSCALL_BASE + 210)
354
+#define __NR_getresgid32 (__NR_SYSCALL_BASE + 211)
355
+#define __NR_chown32 (__NR_SYSCALL_BASE + 212)
356
+#define __NR_setuid32 (__NR_SYSCALL_BASE + 213)
357
+#define __NR_setgid32 (__NR_SYSCALL_BASE + 214)
358
+#define __NR_setfsuid32 (__NR_SYSCALL_BASE + 215)
359
+#define __NR_setfsgid32 (__NR_SYSCALL_BASE + 216)
360
+#define __NR_getdents64 (__NR_SYSCALL_BASE + 217)
361
+#define __NR_pivot_root (__NR_SYSCALL_BASE + 218)
362
+#define __NR_mincore (__NR_SYSCALL_BASE + 219)
363
+#define __NR_madvise (__NR_SYSCALL_BASE + 220)
364
+#define __NR_fcntl64 (__NR_SYSCALL_BASE + 221)
365
+#define __NR_gettid (__NR_SYSCALL_BASE + 224)
366
+#define __NR_readahead (__NR_SYSCALL_BASE + 225)
367
+#define __NR_setxattr (__NR_SYSCALL_BASE + 226)
368
+#define __NR_lsetxattr (__NR_SYSCALL_BASE + 227)
369
+#define __NR_fsetxattr (__NR_SYSCALL_BASE + 228)
370
+#define __NR_getxattr (__NR_SYSCALL_BASE + 229)
371
+#define __NR_lgetxattr (__NR_SYSCALL_BASE + 230)
372
+#define __NR_fgetxattr (__NR_SYSCALL_BASE + 231)
373
+#define __NR_listxattr (__NR_SYSCALL_BASE + 232)
374
+#define __NR_llistxattr (__NR_SYSCALL_BASE + 233)
375
+#define __NR_flistxattr (__NR_SYSCALL_BASE + 234)
376
+#define __NR_removexattr (__NR_SYSCALL_BASE + 235)
377
+#define __NR_lremovexattr (__NR_SYSCALL_BASE + 236)
378
+#define __NR_fremovexattr (__NR_SYSCALL_BASE + 237)
379
+#define __NR_tkill (__NR_SYSCALL_BASE + 238)
380
+#define __NR_sendfile64 (__NR_SYSCALL_BASE + 239)
381
+#define __NR_futex (__NR_SYSCALL_BASE + 240)
382
+#define __NR_sched_setaffinity (__NR_SYSCALL_BASE + 241)
383
+#define __NR_sched_getaffinity (__NR_SYSCALL_BASE + 242)
384
+#define __NR_io_setup (__NR_SYSCALL_BASE + 243)
385
+#define __NR_io_destroy (__NR_SYSCALL_BASE + 244)
386
+#define __NR_io_getevents (__NR_SYSCALL_BASE + 245)
387
+#define __NR_io_submit (__NR_SYSCALL_BASE + 246)
388
+#define __NR_io_cancel (__NR_SYSCALL_BASE + 247)
389
+#define __NR_exit_group (__NR_SYSCALL_BASE + 248)
390
+#define __NR_lookup_dcookie (__NR_SYSCALL_BASE + 249)
391
+#define __NR_epoll_create (__NR_SYSCALL_BASE + 250)
392
+#define __NR_epoll_ctl (__NR_SYSCALL_BASE + 251)
393
+#define __NR_epoll_wait (__NR_SYSCALL_BASE + 252)
394
+#define __NR_remap_file_pages (__NR_SYSCALL_BASE + 253)
395
+#define __NR_set_tid_address (__NR_SYSCALL_BASE + 256)
396
+#define __NR_timer_create (__NR_SYSCALL_BASE + 257)
397
+#define __NR_timer_settime (__NR_SYSCALL_BASE + 258)
398
+#define __NR_timer_gettime (__NR_SYSCALL_BASE + 259)
399
+#define __NR_timer_getoverrun (__NR_SYSCALL_BASE + 260)
400
+#define __NR_timer_delete (__NR_SYSCALL_BASE + 261)
401
+#define __NR_clock_settime (__NR_SYSCALL_BASE + 262)
402
+#define __NR_clock_gettime (__NR_SYSCALL_BASE + 263)
403
+#define __NR_clock_getres (__NR_SYSCALL_BASE + 264)
404
+#define __NR_clock_nanosleep (__NR_SYSCALL_BASE + 265)
405
+#define __NR_statfs64 (__NR_SYSCALL_BASE + 266)
406
+#define __NR_fstatfs64 (__NR_SYSCALL_BASE + 267)
407
+#define __NR_tgkill (__NR_SYSCALL_BASE + 268)
408
+#define __NR_utimes (__NR_SYSCALL_BASE + 269)
409
+#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE + 270)
410
+#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE + 271)
411
+#define __NR_pciconfig_read (__NR_SYSCALL_BASE + 272)
412
+#define __NR_pciconfig_write (__NR_SYSCALL_BASE + 273)
413
+#define __NR_mq_open (__NR_SYSCALL_BASE + 274)
414
+#define __NR_mq_unlink (__NR_SYSCALL_BASE + 275)
415
+#define __NR_mq_timedsend (__NR_SYSCALL_BASE + 276)
416
+#define __NR_mq_timedreceive (__NR_SYSCALL_BASE + 277)
417
+#define __NR_mq_notify (__NR_SYSCALL_BASE + 278)
418
+#define __NR_mq_getsetattr (__NR_SYSCALL_BASE + 279)
419
+#define __NR_waitid (__NR_SYSCALL_BASE + 280)
420
+#define __NR_socket (__NR_SYSCALL_BASE + 281)
421
+#define __NR_bind (__NR_SYSCALL_BASE + 282)
422
+#define __NR_connect (__NR_SYSCALL_BASE + 283)
423
+#define __NR_listen (__NR_SYSCALL_BASE + 284)
424
+#define __NR_accept (__NR_SYSCALL_BASE + 285)
425
+#define __NR_getsockname (__NR_SYSCALL_BASE + 286)
426
+#define __NR_getpeername (__NR_SYSCALL_BASE + 287)
427
+#define __NR_socketpair (__NR_SYSCALL_BASE + 288)
428
+#define __NR_send (__NR_SYSCALL_BASE + 289)
429
+#define __NR_sendto (__NR_SYSCALL_BASE + 290)
430
+#define __NR_recv (__NR_SYSCALL_BASE + 291)
431
+#define __NR_recvfrom (__NR_SYSCALL_BASE + 292)
432
+#define __NR_shutdown (__NR_SYSCALL_BASE + 293)
433
+#define __NR_setsockopt (__NR_SYSCALL_BASE + 294)
434
+#define __NR_getsockopt (__NR_SYSCALL_BASE + 295)
435
+#define __NR_sendmsg (__NR_SYSCALL_BASE + 296)
436
+#define __NR_recvmsg (__NR_SYSCALL_BASE + 297)
437
+#define __NR_semop (__NR_SYSCALL_BASE + 298)
438
+#define __NR_semget (__NR_SYSCALL_BASE + 299)
439
+#define __NR_semctl (__NR_SYSCALL_BASE + 300)
440
+#define __NR_msgsnd (__NR_SYSCALL_BASE + 301)
441
+#define __NR_msgrcv (__NR_SYSCALL_BASE + 302)
442
+#define __NR_msgget (__NR_SYSCALL_BASE + 303)
443
+#define __NR_msgctl (__NR_SYSCALL_BASE + 304)
444
+#define __NR_shmat (__NR_SYSCALL_BASE + 305)
445
+#define __NR_shmdt (__NR_SYSCALL_BASE + 306)
446
+#define __NR_shmget (__NR_SYSCALL_BASE + 307)
447
+#define __NR_shmctl (__NR_SYSCALL_BASE + 308)
448
+#define __NR_add_key (__NR_SYSCALL_BASE + 309)
449
+#define __NR_request_key (__NR_SYSCALL_BASE + 310)
450
+#define __NR_keyctl (__NR_SYSCALL_BASE + 311)
451
+#define __NR_semtimedop (__NR_SYSCALL_BASE + 312)
452
+#define __NR_vserver (__NR_SYSCALL_BASE + 313)
453
+#define __NR_ioprio_set (__NR_SYSCALL_BASE + 314)
454
+#define __NR_ioprio_get (__NR_SYSCALL_BASE + 315)
455
+#define __NR_inotify_init (__NR_SYSCALL_BASE + 316)
456
+#define __NR_inotify_add_watch (__NR_SYSCALL_BASE + 317)
457
+#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE + 318)
458
+#define __NR_mbind (__NR_SYSCALL_BASE + 319)
459
+#define __NR_get_mempolicy (__NR_SYSCALL_BASE + 320)
460
+#define __NR_set_mempolicy (__NR_SYSCALL_BASE + 321)
461
+#define __NR_openat (__NR_SYSCALL_BASE + 322)
462
+#define __NR_mkdirat (__NR_SYSCALL_BASE + 323)
463
+#define __NR_mknodat (__NR_SYSCALL_BASE + 324)
464
+#define __NR_fchownat (__NR_SYSCALL_BASE + 325)
465
+#define __NR_futimesat (__NR_SYSCALL_BASE + 326)
466
+#define __NR_fstatat64 (__NR_SYSCALL_BASE + 327)
467
+#define __NR_unlinkat (__NR_SYSCALL_BASE + 328)
468
+#define __NR_renameat (__NR_SYSCALL_BASE + 329)
469
+#define __NR_linkat (__NR_SYSCALL_BASE + 330)
470
+#define __NR_symlinkat (__NR_SYSCALL_BASE + 331)
471
+#define __NR_readlinkat (__NR_SYSCALL_BASE + 332)
472
+#define __NR_fchmodat (__NR_SYSCALL_BASE + 333)
473
+#define __NR_faccessat (__NR_SYSCALL_BASE + 334)
474
+#define __NR_pselect6 (__NR_SYSCALL_BASE + 335)
475
+#define __NR_ppoll (__NR_SYSCALL_BASE + 336)
476
+#define __NR_unshare (__NR_SYSCALL_BASE + 337)
477
+#define __NR_set_robust_list (__NR_SYSCALL_BASE + 338)
478
+#define __NR_get_robust_list (__NR_SYSCALL_BASE + 339)
479
+#define __NR_splice (__NR_SYSCALL_BASE + 340)
480
+#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE + 341)
481
+#define __NR_tee (__NR_SYSCALL_BASE + 342)
482
+#define __NR_vmsplice (__NR_SYSCALL_BASE + 343)
483
+#define __NR_move_pages (__NR_SYSCALL_BASE + 344)
484
+#define __NR_getcpu (__NR_SYSCALL_BASE + 345)
485
+#define __NR_epoll_pwait (__NR_SYSCALL_BASE + 346)
486
+#define __NR_kexec_load (__NR_SYSCALL_BASE + 347)
487
+#define __NR_utimensat (__NR_SYSCALL_BASE + 348)
488
+#define __NR_signalfd (__NR_SYSCALL_BASE + 349)
489
+#define __NR_timerfd_create (__NR_SYSCALL_BASE + 350)
490
+#define __NR_eventfd (__NR_SYSCALL_BASE + 351)
491
+#define __NR_fallocate (__NR_SYSCALL_BASE + 352)
492
+#define __NR_timerfd_settime (__NR_SYSCALL_BASE + 353)
493
+#define __NR_timerfd_gettime (__NR_SYSCALL_BASE + 354)
494
+#define __NR_signalfd4 (__NR_SYSCALL_BASE + 355)
495
+#define __NR_eventfd2 (__NR_SYSCALL_BASE + 356)
496
+#define __NR_epoll_create1 (__NR_SYSCALL_BASE + 357)
497
+#define __NR_dup3 (__NR_SYSCALL_BASE + 358)
498
+#define __NR_pipe2 (__NR_SYSCALL_BASE + 359)
499
+#define __NR_inotify_init1 (__NR_SYSCALL_BASE + 360)
500
+#define __NR_preadv (__NR_SYSCALL_BASE + 361)
501
+#define __NR_pwritev (__NR_SYSCALL_BASE + 362)
502
+#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE + 363)
503
+#define __NR_perf_event_open (__NR_SYSCALL_BASE + 364)
504
+#define __NR_recvmmsg (__NR_SYSCALL_BASE + 365)
505
+#define __NR_accept4 (__NR_SYSCALL_BASE + 366)
506
+#define __NR_fanotify_init (__NR_SYSCALL_BASE + 367)
507
+#define __NR_fanotify_mark (__NR_SYSCALL_BASE + 368)
508
+#define __NR_prlimit64 (__NR_SYSCALL_BASE + 369)
509
+#define __NR_name_to_handle_at (__NR_SYSCALL_BASE + 370)
510
+#define __NR_open_by_handle_at (__NR_SYSCALL_BASE + 371)
511
+#define __NR_clock_adjtime (__NR_SYSCALL_BASE + 372)
512
+#define __NR_syncfs (__NR_SYSCALL_BASE + 373)
513
+#define __NR_sendmmsg (__NR_SYSCALL_BASE + 374)
514
+#define __NR_setns (__NR_SYSCALL_BASE + 375)
515
+#define __NR_process_vm_readv (__NR_SYSCALL_BASE + 376)
516
+#define __NR_process_vm_writev (__NR_SYSCALL_BASE + 377)
517
+#define __NR_kcmp (__NR_SYSCALL_BASE + 378)
518
+#define __NR_finit_module (__NR_SYSCALL_BASE + 379)
519
+#define __NR_sched_setattr (__NR_SYSCALL_BASE + 380)
520
+#define __NR_sched_getattr (__NR_SYSCALL_BASE + 381)
521
+#define __NR_renameat2 (__NR_SYSCALL_BASE + 382)
522
+#define __NR_seccomp (__NR_SYSCALL_BASE + 383)
523
+#define __NR_getrandom (__NR_SYSCALL_BASE + 384)
524
+#define __NR_memfd_create (__NR_SYSCALL_BASE + 385)
525
+#define __NR_bpf (__NR_SYSCALL_BASE + 386)
526
+#define __NR_execveat (__NR_SYSCALL_BASE + 387)
527
+#define __NR_userfaultfd (__NR_SYSCALL_BASE + 388)
528
+#define __NR_membarrier (__NR_SYSCALL_BASE + 389)
529
+#define __NR_mlock2 (__NR_SYSCALL_BASE + 390)
530
+#define __NR_copy_file_range (__NR_SYSCALL_BASE + 391)
531
+#define __NR_preadv2 (__NR_SYSCALL_BASE + 392)
532
+#define __NR_pwritev2 (__NR_SYSCALL_BASE + 393)
533
+#define __NR_pkey_mprotect (__NR_SYSCALL_BASE + 394)
534
+#define __NR_pkey_alloc (__NR_SYSCALL_BASE + 395)
535
+#define __NR_pkey_free (__NR_SYSCALL_BASE + 396)
536
+
39
+
537
+#endif /* _ASM_ARM_UNISTD_COMMON_H */
40
+It is intended to be a machine for developing firmware and testing
538
diff --git a/linux-headers/asm-arm/unistd-eabi.h b/linux-headers/asm-arm/unistd-eabi.h
41
+standards compliance with operating systems.
539
new file mode 100644
540
index XXXXXXX..XXXXXXX
541
--- /dev/null
542
+++ b/linux-headers/asm-arm/unistd-eabi.h
543
@@ -XXX,XX +XXX,XX @@
544
+#ifndef _ASM_ARM_UNISTD_EABI_H
545
+#define _ASM_ARM_UNISTD_EABI_H 1
546
+
42
+
43
+Supported devices
44
+"""""""""""""""""
547
+
45
+
548
+#endif /* _ASM_ARM_UNISTD_EABI_H */
46
+The sbsa-ref board supports:
549
diff --git a/linux-headers/asm-arm/unistd-oabi.h b/linux-headers/asm-arm/unistd-oabi.h
550
new file mode 100644
551
index XXXXXXX..XXXXXXX
552
--- /dev/null
553
+++ b/linux-headers/asm-arm/unistd-oabi.h
554
@@ -XXX,XX +XXX,XX @@
555
+#ifndef _ASM_ARM_UNISTD_OABI_H
556
+#define _ASM_ARM_UNISTD_OABI_H 1
557
+
47
+
558
+#define __NR_time (__NR_SYSCALL_BASE + 13)
48
+ - A configurable number of AArch64 CPUs
559
+#define __NR_umount (__NR_SYSCALL_BASE + 22)
49
+ - GIC version 3
560
+#define __NR_stime (__NR_SYSCALL_BASE + 25)
50
+ - System bus AHCI controller
561
+#define __NR_alarm (__NR_SYSCALL_BASE + 27)
51
+ - System bus EHCI controller
562
+#define __NR_utime (__NR_SYSCALL_BASE + 30)
52
+ - CDROM and hard disc on AHCI bus
563
+#define __NR_getrlimit (__NR_SYSCALL_BASE + 76)
53
+ - E1000E ethernet card on PCIe bus
564
+#define __NR_select (__NR_SYSCALL_BASE + 82)
54
+ - VGA display adaptor on PCIe bus
565
+#define __NR_readdir (__NR_SYSCALL_BASE + 89)
55
+ - A generic SBSA watchdog device
566
+#define __NR_mmap (__NR_SYSCALL_BASE + 90)
567
+#define __NR_socketcall (__NR_SYSCALL_BASE + 102)
568
+#define __NR_syscall (__NR_SYSCALL_BASE + 113)
569
+#define __NR_ipc (__NR_SYSCALL_BASE + 117)
570
+
56
+
571
+#endif /* _ASM_ARM_UNISTD_OABI_H */
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
572
diff --git a/linux-headers/asm-arm/unistd.h b/linux-headers/asm-arm/unistd.h
573
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
574
--- a/linux-headers/asm-arm/unistd.h
59
--- a/docs/system/target-arm.rst
575
+++ b/linux-headers/asm-arm/unistd.h
60
+++ b/docs/system/target-arm.rst
576
@@ -XXX,XX +XXX,XX @@
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
577
62
arm/mps2
578
#if defined(__thumb__) || defined(__ARM_EABI__)
63
arm/musca
579
#define __NR_SYSCALL_BASE    0
64
arm/realview
580
+#include <asm/unistd-eabi.h>
65
+ arm/sbsa
581
#else
66
arm/versatile
582
#define __NR_SYSCALL_BASE    __NR_OABI_SYSCALL_BASE
67
arm/vexpress
583
+#include <asm/unistd-oabi.h>
68
arm/aspeed
584
#endif
585
586
-/*
587
- * This file contains the system call numbers.
588
- */
589
-
590
-#define __NR_restart_syscall        (__NR_SYSCALL_BASE+ 0)
591
-#define __NR_exit            (__NR_SYSCALL_BASE+ 1)
592
-#define __NR_fork            (__NR_SYSCALL_BASE+ 2)
593
-#define __NR_read            (__NR_SYSCALL_BASE+ 3)
594
-#define __NR_write            (__NR_SYSCALL_BASE+ 4)
595
-#define __NR_open            (__NR_SYSCALL_BASE+ 5)
596
-#define __NR_close            (__NR_SYSCALL_BASE+ 6)
597
-                    /* 7 was sys_waitpid */
598
-#define __NR_creat            (__NR_SYSCALL_BASE+ 8)
599
-#define __NR_link            (__NR_SYSCALL_BASE+ 9)
600
-#define __NR_unlink            (__NR_SYSCALL_BASE+ 10)
601
-#define __NR_execve            (__NR_SYSCALL_BASE+ 11)
602
-#define __NR_chdir            (__NR_SYSCALL_BASE+ 12)
603
-#define __NR_time            (__NR_SYSCALL_BASE+ 13)
604
-#define __NR_mknod            (__NR_SYSCALL_BASE+ 14)
605
-#define __NR_chmod            (__NR_SYSCALL_BASE+ 15)
606
-#define __NR_lchown            (__NR_SYSCALL_BASE+ 16)
607
-                    /* 17 was sys_break */
608
-                    /* 18 was sys_stat */
609
-#define __NR_lseek            (__NR_SYSCALL_BASE+ 19)
610
-#define __NR_getpid            (__NR_SYSCALL_BASE+ 20)
611
-#define __NR_mount            (__NR_SYSCALL_BASE+ 21)
612
-#define __NR_umount            (__NR_SYSCALL_BASE+ 22)
613
-#define __NR_setuid            (__NR_SYSCALL_BASE+ 23)
614
-#define __NR_getuid            (__NR_SYSCALL_BASE+ 24)
615
-#define __NR_stime            (__NR_SYSCALL_BASE+ 25)
616
-#define __NR_ptrace            (__NR_SYSCALL_BASE+ 26)
617
-#define __NR_alarm            (__NR_SYSCALL_BASE+ 27)
618
-                    /* 28 was sys_fstat */
619
-#define __NR_pause            (__NR_SYSCALL_BASE+ 29)
620
-#define __NR_utime            (__NR_SYSCALL_BASE+ 30)
621
-                    /* 31 was sys_stty */
622
-                    /* 32 was sys_gtty */
623
-#define __NR_access            (__NR_SYSCALL_BASE+ 33)
624
-#define __NR_nice            (__NR_SYSCALL_BASE+ 34)
625
-                    /* 35 was sys_ftime */
626
-#define __NR_sync            (__NR_SYSCALL_BASE+ 36)
627
-#define __NR_kill            (__NR_SYSCALL_BASE+ 37)
628
-#define __NR_rename            (__NR_SYSCALL_BASE+ 38)
629
-#define __NR_mkdir            (__NR_SYSCALL_BASE+ 39)
630
-#define __NR_rmdir            (__NR_SYSCALL_BASE+ 40)
631
-#define __NR_dup            (__NR_SYSCALL_BASE+ 41)
632
-#define __NR_pipe            (__NR_SYSCALL_BASE+ 42)
633
-#define __NR_times            (__NR_SYSCALL_BASE+ 43)
634
-                    /* 44 was sys_prof */
635
-#define __NR_brk            (__NR_SYSCALL_BASE+ 45)
636
-#define __NR_setgid            (__NR_SYSCALL_BASE+ 46)
637
-#define __NR_getgid            (__NR_SYSCALL_BASE+ 47)
638
-                    /* 48 was sys_signal */
639
-#define __NR_geteuid            (__NR_SYSCALL_BASE+ 49)
640
-#define __NR_getegid            (__NR_SYSCALL_BASE+ 50)
641
-#define __NR_acct            (__NR_SYSCALL_BASE+ 51)
642
-#define __NR_umount2            (__NR_SYSCALL_BASE+ 52)
643
-                    /* 53 was sys_lock */
644
-#define __NR_ioctl            (__NR_SYSCALL_BASE+ 54)
645
-#define __NR_fcntl            (__NR_SYSCALL_BASE+ 55)
646
-                    /* 56 was sys_mpx */
647
-#define __NR_setpgid            (__NR_SYSCALL_BASE+ 57)
648
-                    /* 58 was sys_ulimit */
649
-                    /* 59 was sys_olduname */
650
-#define __NR_umask            (__NR_SYSCALL_BASE+ 60)
651
-#define __NR_chroot            (__NR_SYSCALL_BASE+ 61)
652
-#define __NR_ustat            (__NR_SYSCALL_BASE+ 62)
653
-#define __NR_dup2            (__NR_SYSCALL_BASE+ 63)
654
-#define __NR_getppid            (__NR_SYSCALL_BASE+ 64)
655
-#define __NR_getpgrp            (__NR_SYSCALL_BASE+ 65)
656
-#define __NR_setsid            (__NR_SYSCALL_BASE+ 66)
657
-#define __NR_sigaction            (__NR_SYSCALL_BASE+ 67)
658
-                    /* 68 was sys_sgetmask */
659
-                    /* 69 was sys_ssetmask */
660
-#define __NR_setreuid            (__NR_SYSCALL_BASE+ 70)
661
-#define __NR_setregid            (__NR_SYSCALL_BASE+ 71)
662
-#define __NR_sigsuspend            (__NR_SYSCALL_BASE+ 72)
663
-#define __NR_sigpending            (__NR_SYSCALL_BASE+ 73)
664
-#define __NR_sethostname        (__NR_SYSCALL_BASE+ 74)
665
-#define __NR_setrlimit            (__NR_SYSCALL_BASE+ 75)
666
-#define __NR_getrlimit            (__NR_SYSCALL_BASE+ 76)    /* Back compat 2GB limited rlimit */
667
-#define __NR_getrusage            (__NR_SYSCALL_BASE+ 77)
668
-#define __NR_gettimeofday        (__NR_SYSCALL_BASE+ 78)
669
-#define __NR_settimeofday        (__NR_SYSCALL_BASE+ 79)
670
-#define __NR_getgroups            (__NR_SYSCALL_BASE+ 80)
671
-#define __NR_setgroups            (__NR_SYSCALL_BASE+ 81)
672
-#define __NR_select            (__NR_SYSCALL_BASE+ 82)
673
-#define __NR_symlink            (__NR_SYSCALL_BASE+ 83)
674
-                    /* 84 was sys_lstat */
675
-#define __NR_readlink            (__NR_SYSCALL_BASE+ 85)
676
-#define __NR_uselib            (__NR_SYSCALL_BASE+ 86)
677
-#define __NR_swapon            (__NR_SYSCALL_BASE+ 87)
678
-#define __NR_reboot            (__NR_SYSCALL_BASE+ 88)
679
-#define __NR_readdir            (__NR_SYSCALL_BASE+ 89)
680
-#define __NR_mmap            (__NR_SYSCALL_BASE+ 90)
681
-#define __NR_munmap            (__NR_SYSCALL_BASE+ 91)
682
-#define __NR_truncate            (__NR_SYSCALL_BASE+ 92)
683
-#define __NR_ftruncate            (__NR_SYSCALL_BASE+ 93)
684
-#define __NR_fchmod            (__NR_SYSCALL_BASE+ 94)
685
-#define __NR_fchown            (__NR_SYSCALL_BASE+ 95)
686
-#define __NR_getpriority        (__NR_SYSCALL_BASE+ 96)
687
-#define __NR_setpriority        (__NR_SYSCALL_BASE+ 97)
688
-                    /* 98 was sys_profil */
689
-#define __NR_statfs            (__NR_SYSCALL_BASE+ 99)
690
-#define __NR_fstatfs            (__NR_SYSCALL_BASE+100)
691
-                    /* 101 was sys_ioperm */
692
-#define __NR_socketcall            (__NR_SYSCALL_BASE+102)
693
-#define __NR_syslog            (__NR_SYSCALL_BASE+103)
694
-#define __NR_setitimer            (__NR_SYSCALL_BASE+104)
695
-#define __NR_getitimer            (__NR_SYSCALL_BASE+105)
696
-#define __NR_stat            (__NR_SYSCALL_BASE+106)
697
-#define __NR_lstat            (__NR_SYSCALL_BASE+107)
698
-#define __NR_fstat            (__NR_SYSCALL_BASE+108)
699
-                    /* 109 was sys_uname */
700
-                    /* 110 was sys_iopl */
701
-#define __NR_vhangup            (__NR_SYSCALL_BASE+111)
702
-                    /* 112 was sys_idle */
703
-#define __NR_syscall            (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
704
-#define __NR_wait4            (__NR_SYSCALL_BASE+114)
705
-#define __NR_swapoff            (__NR_SYSCALL_BASE+115)
706
-#define __NR_sysinfo            (__NR_SYSCALL_BASE+116)
707
-#define __NR_ipc            (__NR_SYSCALL_BASE+117)
708
-#define __NR_fsync            (__NR_SYSCALL_BASE+118)
709
-#define __NR_sigreturn            (__NR_SYSCALL_BASE+119)
710
-#define __NR_clone            (__NR_SYSCALL_BASE+120)
711
-#define __NR_setdomainname        (__NR_SYSCALL_BASE+121)
712
-#define __NR_uname            (__NR_SYSCALL_BASE+122)
713
-                    /* 123 was sys_modify_ldt */
714
-#define __NR_adjtimex            (__NR_SYSCALL_BASE+124)
715
-#define __NR_mprotect            (__NR_SYSCALL_BASE+125)
716
-#define __NR_sigprocmask        (__NR_SYSCALL_BASE+126)
717
-                    /* 127 was sys_create_module */
718
-#define __NR_init_module        (__NR_SYSCALL_BASE+128)
719
-#define __NR_delete_module        (__NR_SYSCALL_BASE+129)
720
-                    /* 130 was sys_get_kernel_syms */
721
-#define __NR_quotactl            (__NR_SYSCALL_BASE+131)
722
-#define __NR_getpgid            (__NR_SYSCALL_BASE+132)
723
-#define __NR_fchdir            (__NR_SYSCALL_BASE+133)
724
-#define __NR_bdflush            (__NR_SYSCALL_BASE+134)
725
-#define __NR_sysfs            (__NR_SYSCALL_BASE+135)
726
-#define __NR_personality        (__NR_SYSCALL_BASE+136)
727
-                    /* 137 was sys_afs_syscall */
728
-#define __NR_setfsuid            (__NR_SYSCALL_BASE+138)
729
-#define __NR_setfsgid            (__NR_SYSCALL_BASE+139)
730
-#define __NR__llseek            (__NR_SYSCALL_BASE+140)
731
-#define __NR_getdents            (__NR_SYSCALL_BASE+141)
732
-#define __NR__newselect            (__NR_SYSCALL_BASE+142)
733
-#define __NR_flock            (__NR_SYSCALL_BASE+143)
734
-#define __NR_msync            (__NR_SYSCALL_BASE+144)
735
-#define __NR_readv            (__NR_SYSCALL_BASE+145)
736
-#define __NR_writev            (__NR_SYSCALL_BASE+146)
737
-#define __NR_getsid            (__NR_SYSCALL_BASE+147)
738
-#define __NR_fdatasync            (__NR_SYSCALL_BASE+148)
739
-#define __NR__sysctl            (__NR_SYSCALL_BASE+149)
740
-#define __NR_mlock            (__NR_SYSCALL_BASE+150)
741
-#define __NR_munlock            (__NR_SYSCALL_BASE+151)
742
-#define __NR_mlockall            (__NR_SYSCALL_BASE+152)
743
-#define __NR_munlockall            (__NR_SYSCALL_BASE+153)
744
-#define __NR_sched_setparam        (__NR_SYSCALL_BASE+154)
745
-#define __NR_sched_getparam        (__NR_SYSCALL_BASE+155)
746
-#define __NR_sched_setscheduler        (__NR_SYSCALL_BASE+156)
747
-#define __NR_sched_getscheduler        (__NR_SYSCALL_BASE+157)
748
-#define __NR_sched_yield        (__NR_SYSCALL_BASE+158)
749
-#define __NR_sched_get_priority_max    (__NR_SYSCALL_BASE+159)
750
-#define __NR_sched_get_priority_min    (__NR_SYSCALL_BASE+160)
751
-#define __NR_sched_rr_get_interval    (__NR_SYSCALL_BASE+161)
752
-#define __NR_nanosleep            (__NR_SYSCALL_BASE+162)
753
-#define __NR_mremap            (__NR_SYSCALL_BASE+163)
754
-#define __NR_setresuid            (__NR_SYSCALL_BASE+164)
755
-#define __NR_getresuid            (__NR_SYSCALL_BASE+165)
756
-                    /* 166 was sys_vm86 */
757
-                    /* 167 was sys_query_module */
758
-#define __NR_poll            (__NR_SYSCALL_BASE+168)
759
-#define __NR_nfsservctl            (__NR_SYSCALL_BASE+169)
760
-#define __NR_setresgid            (__NR_SYSCALL_BASE+170)
761
-#define __NR_getresgid            (__NR_SYSCALL_BASE+171)
762
-#define __NR_prctl            (__NR_SYSCALL_BASE+172)
763
-#define __NR_rt_sigreturn        (__NR_SYSCALL_BASE+173)
764
-#define __NR_rt_sigaction        (__NR_SYSCALL_BASE+174)
765
-#define __NR_rt_sigprocmask        (__NR_SYSCALL_BASE+175)
766
-#define __NR_rt_sigpending        (__NR_SYSCALL_BASE+176)
767
-#define __NR_rt_sigtimedwait        (__NR_SYSCALL_BASE+177)
768
-#define __NR_rt_sigqueueinfo        (__NR_SYSCALL_BASE+178)
769
-#define __NR_rt_sigsuspend        (__NR_SYSCALL_BASE+179)
770
-#define __NR_pread64            (__NR_SYSCALL_BASE+180)
771
-#define __NR_pwrite64            (__NR_SYSCALL_BASE+181)
772
-#define __NR_chown            (__NR_SYSCALL_BASE+182)
773
-#define __NR_getcwd            (__NR_SYSCALL_BASE+183)
774
-#define __NR_capget            (__NR_SYSCALL_BASE+184)
775
-#define __NR_capset            (__NR_SYSCALL_BASE+185)
776
-#define __NR_sigaltstack        (__NR_SYSCALL_BASE+186)
777
-#define __NR_sendfile            (__NR_SYSCALL_BASE+187)
778
-                    /* 188 reserved */
779
-                    /* 189 reserved */
780
-#define __NR_vfork            (__NR_SYSCALL_BASE+190)
781
-#define __NR_ugetrlimit            (__NR_SYSCALL_BASE+191)    /* SuS compliant getrlimit */
782
-#define __NR_mmap2            (__NR_SYSCALL_BASE+192)
783
-#define __NR_truncate64            (__NR_SYSCALL_BASE+193)
784
-#define __NR_ftruncate64        (__NR_SYSCALL_BASE+194)
785
-#define __NR_stat64            (__NR_SYSCALL_BASE+195)
786
-#define __NR_lstat64            (__NR_SYSCALL_BASE+196)
787
-#define __NR_fstat64            (__NR_SYSCALL_BASE+197)
788
-#define __NR_lchown32            (__NR_SYSCALL_BASE+198)
789
-#define __NR_getuid32            (__NR_SYSCALL_BASE+199)
790
-#define __NR_getgid32            (__NR_SYSCALL_BASE+200)
791
-#define __NR_geteuid32            (__NR_SYSCALL_BASE+201)
792
-#define __NR_getegid32            (__NR_SYSCALL_BASE+202)
793
-#define __NR_setreuid32            (__NR_SYSCALL_BASE+203)
794
-#define __NR_setregid32            (__NR_SYSCALL_BASE+204)
795
-#define __NR_getgroups32        (__NR_SYSCALL_BASE+205)
796
-#define __NR_setgroups32        (__NR_SYSCALL_BASE+206)
797
-#define __NR_fchown32            (__NR_SYSCALL_BASE+207)
798
-#define __NR_setresuid32        (__NR_SYSCALL_BASE+208)
799
-#define __NR_getresuid32        (__NR_SYSCALL_BASE+209)
800
-#define __NR_setresgid32        (__NR_SYSCALL_BASE+210)
801
-#define __NR_getresgid32        (__NR_SYSCALL_BASE+211)
802
-#define __NR_chown32            (__NR_SYSCALL_BASE+212)
803
-#define __NR_setuid32            (__NR_SYSCALL_BASE+213)
804
-#define __NR_setgid32            (__NR_SYSCALL_BASE+214)
805
-#define __NR_setfsuid32            (__NR_SYSCALL_BASE+215)
806
-#define __NR_setfsgid32            (__NR_SYSCALL_BASE+216)
807
-#define __NR_getdents64            (__NR_SYSCALL_BASE+217)
808
-#define __NR_pivot_root            (__NR_SYSCALL_BASE+218)
809
-#define __NR_mincore            (__NR_SYSCALL_BASE+219)
810
-#define __NR_madvise            (__NR_SYSCALL_BASE+220)
811
-#define __NR_fcntl64            (__NR_SYSCALL_BASE+221)
812
-                    /* 222 for tux */
813
-                    /* 223 is unused */
814
-#define __NR_gettid            (__NR_SYSCALL_BASE+224)
815
-#define __NR_readahead            (__NR_SYSCALL_BASE+225)
816
-#define __NR_setxattr            (__NR_SYSCALL_BASE+226)
817
-#define __NR_lsetxattr            (__NR_SYSCALL_BASE+227)
818
-#define __NR_fsetxattr            (__NR_SYSCALL_BASE+228)
819
-#define __NR_getxattr            (__NR_SYSCALL_BASE+229)
820
-#define __NR_lgetxattr            (__NR_SYSCALL_BASE+230)
821
-#define __NR_fgetxattr            (__NR_SYSCALL_BASE+231)
822
-#define __NR_listxattr            (__NR_SYSCALL_BASE+232)
823
-#define __NR_llistxattr            (__NR_SYSCALL_BASE+233)
824
-#define __NR_flistxattr            (__NR_SYSCALL_BASE+234)
825
-#define __NR_removexattr        (__NR_SYSCALL_BASE+235)
826
-#define __NR_lremovexattr        (__NR_SYSCALL_BASE+236)
827
-#define __NR_fremovexattr        (__NR_SYSCALL_BASE+237)
828
-#define __NR_tkill            (__NR_SYSCALL_BASE+238)
829
-#define __NR_sendfile64            (__NR_SYSCALL_BASE+239)
830
-#define __NR_futex            (__NR_SYSCALL_BASE+240)
831
-#define __NR_sched_setaffinity        (__NR_SYSCALL_BASE+241)
832
-#define __NR_sched_getaffinity        (__NR_SYSCALL_BASE+242)
833
-#define __NR_io_setup            (__NR_SYSCALL_BASE+243)
834
-#define __NR_io_destroy            (__NR_SYSCALL_BASE+244)
835
-#define __NR_io_getevents        (__NR_SYSCALL_BASE+245)
836
-#define __NR_io_submit            (__NR_SYSCALL_BASE+246)
837
-#define __NR_io_cancel            (__NR_SYSCALL_BASE+247)
838
-#define __NR_exit_group            (__NR_SYSCALL_BASE+248)
839
-#define __NR_lookup_dcookie        (__NR_SYSCALL_BASE+249)
840
-#define __NR_epoll_create        (__NR_SYSCALL_BASE+250)
841
-#define __NR_epoll_ctl            (__NR_SYSCALL_BASE+251)
842
-#define __NR_epoll_wait            (__NR_SYSCALL_BASE+252)
843
-#define __NR_remap_file_pages        (__NR_SYSCALL_BASE+253)
844
-                    /* 254 for set_thread_area */
845
-                    /* 255 for get_thread_area */
846
-#define __NR_set_tid_address        (__NR_SYSCALL_BASE+256)
847
-#define __NR_timer_create        (__NR_SYSCALL_BASE+257)
848
-#define __NR_timer_settime        (__NR_SYSCALL_BASE+258)
849
-#define __NR_timer_gettime        (__NR_SYSCALL_BASE+259)
850
-#define __NR_timer_getoverrun        (__NR_SYSCALL_BASE+260)
851
-#define __NR_timer_delete        (__NR_SYSCALL_BASE+261)
852
-#define __NR_clock_settime        (__NR_SYSCALL_BASE+262)
853
-#define __NR_clock_gettime        (__NR_SYSCALL_BASE+263)
854
-#define __NR_clock_getres        (__NR_SYSCALL_BASE+264)
855
-#define __NR_clock_nanosleep        (__NR_SYSCALL_BASE+265)
856
-#define __NR_statfs64            (__NR_SYSCALL_BASE+266)
857
-#define __NR_fstatfs64            (__NR_SYSCALL_BASE+267)
858
-#define __NR_tgkill            (__NR_SYSCALL_BASE+268)
859
-#define __NR_utimes            (__NR_SYSCALL_BASE+269)
860
-#define __NR_arm_fadvise64_64        (__NR_SYSCALL_BASE+270)
861
-#define __NR_pciconfig_iobase        (__NR_SYSCALL_BASE+271)
862
-#define __NR_pciconfig_read        (__NR_SYSCALL_BASE+272)
863
-#define __NR_pciconfig_write        (__NR_SYSCALL_BASE+273)
864
-#define __NR_mq_open            (__NR_SYSCALL_BASE+274)
865
-#define __NR_mq_unlink            (__NR_SYSCALL_BASE+275)
866
-#define __NR_mq_timedsend        (__NR_SYSCALL_BASE+276)
867
-#define __NR_mq_timedreceive        (__NR_SYSCALL_BASE+277)
868
-#define __NR_mq_notify            (__NR_SYSCALL_BASE+278)
869
-#define __NR_mq_getsetattr        (__NR_SYSCALL_BASE+279)
870
-#define __NR_waitid            (__NR_SYSCALL_BASE+280)
871
-#define __NR_socket            (__NR_SYSCALL_BASE+281)
872
-#define __NR_bind            (__NR_SYSCALL_BASE+282)
873
-#define __NR_connect            (__NR_SYSCALL_BASE+283)
874
-#define __NR_listen            (__NR_SYSCALL_BASE+284)
875
-#define __NR_accept            (__NR_SYSCALL_BASE+285)
876
-#define __NR_getsockname        (__NR_SYSCALL_BASE+286)
877
-#define __NR_getpeername        (__NR_SYSCALL_BASE+287)
878
-#define __NR_socketpair            (__NR_SYSCALL_BASE+288)
879
-#define __NR_send            (__NR_SYSCALL_BASE+289)
880
-#define __NR_sendto            (__NR_SYSCALL_BASE+290)
881
-#define __NR_recv            (__NR_SYSCALL_BASE+291)
882
-#define __NR_recvfrom            (__NR_SYSCALL_BASE+292)
883
-#define __NR_shutdown            (__NR_SYSCALL_BASE+293)
884
-#define __NR_setsockopt            (__NR_SYSCALL_BASE+294)
885
-#define __NR_getsockopt            (__NR_SYSCALL_BASE+295)
886
-#define __NR_sendmsg            (__NR_SYSCALL_BASE+296)
887
-#define __NR_recvmsg            (__NR_SYSCALL_BASE+297)
888
-#define __NR_semop            (__NR_SYSCALL_BASE+298)
889
-#define __NR_semget            (__NR_SYSCALL_BASE+299)
890
-#define __NR_semctl            (__NR_SYSCALL_BASE+300)
891
-#define __NR_msgsnd            (__NR_SYSCALL_BASE+301)
892
-#define __NR_msgrcv            (__NR_SYSCALL_BASE+302)
893
-#define __NR_msgget            (__NR_SYSCALL_BASE+303)
894
-#define __NR_msgctl            (__NR_SYSCALL_BASE+304)
895
-#define __NR_shmat            (__NR_SYSCALL_BASE+305)
896
-#define __NR_shmdt            (__NR_SYSCALL_BASE+306)
897
-#define __NR_shmget            (__NR_SYSCALL_BASE+307)
898
-#define __NR_shmctl            (__NR_SYSCALL_BASE+308)
899
-#define __NR_add_key            (__NR_SYSCALL_BASE+309)
900
-#define __NR_request_key        (__NR_SYSCALL_BASE+310)
901
-#define __NR_keyctl            (__NR_SYSCALL_BASE+311)
902
-#define __NR_semtimedop            (__NR_SYSCALL_BASE+312)
903
-#define __NR_vserver            (__NR_SYSCALL_BASE+313)
904
-#define __NR_ioprio_set            (__NR_SYSCALL_BASE+314)
905
-#define __NR_ioprio_get            (__NR_SYSCALL_BASE+315)
906
-#define __NR_inotify_init        (__NR_SYSCALL_BASE+316)
907
-#define __NR_inotify_add_watch        (__NR_SYSCALL_BASE+317)
908
-#define __NR_inotify_rm_watch        (__NR_SYSCALL_BASE+318)
909
-#define __NR_mbind            (__NR_SYSCALL_BASE+319)
910
-#define __NR_get_mempolicy        (__NR_SYSCALL_BASE+320)
911
-#define __NR_set_mempolicy        (__NR_SYSCALL_BASE+321)
912
-#define __NR_openat            (__NR_SYSCALL_BASE+322)
913
-#define __NR_mkdirat            (__NR_SYSCALL_BASE+323)
914
-#define __NR_mknodat            (__NR_SYSCALL_BASE+324)
915
-#define __NR_fchownat            (__NR_SYSCALL_BASE+325)
916
-#define __NR_futimesat            (__NR_SYSCALL_BASE+326)
917
-#define __NR_fstatat64            (__NR_SYSCALL_BASE+327)
918
-#define __NR_unlinkat            (__NR_SYSCALL_BASE+328)
919
-#define __NR_renameat            (__NR_SYSCALL_BASE+329)
920
-#define __NR_linkat            (__NR_SYSCALL_BASE+330)
921
-#define __NR_symlinkat            (__NR_SYSCALL_BASE+331)
922
-#define __NR_readlinkat            (__NR_SYSCALL_BASE+332)
923
-#define __NR_fchmodat            (__NR_SYSCALL_BASE+333)
924
-#define __NR_faccessat            (__NR_SYSCALL_BASE+334)
925
-#define __NR_pselect6            (__NR_SYSCALL_BASE+335)
926
-#define __NR_ppoll            (__NR_SYSCALL_BASE+336)
927
-#define __NR_unshare            (__NR_SYSCALL_BASE+337)
928
-#define __NR_set_robust_list        (__NR_SYSCALL_BASE+338)
929
-#define __NR_get_robust_list        (__NR_SYSCALL_BASE+339)
930
-#define __NR_splice            (__NR_SYSCALL_BASE+340)
931
-#define __NR_arm_sync_file_range    (__NR_SYSCALL_BASE+341)
932
+#include <asm/unistd-common.h>
933
#define __NR_sync_file_range2        __NR_arm_sync_file_range
934
-#define __NR_tee            (__NR_SYSCALL_BASE+342)
935
-#define __NR_vmsplice            (__NR_SYSCALL_BASE+343)
936
-#define __NR_move_pages            (__NR_SYSCALL_BASE+344)
937
-#define __NR_getcpu            (__NR_SYSCALL_BASE+345)
938
-#define __NR_epoll_pwait        (__NR_SYSCALL_BASE+346)
939
-#define __NR_kexec_load            (__NR_SYSCALL_BASE+347)
940
-#define __NR_utimensat            (__NR_SYSCALL_BASE+348)
941
-#define __NR_signalfd            (__NR_SYSCALL_BASE+349)
942
-#define __NR_timerfd_create        (__NR_SYSCALL_BASE+350)
943
-#define __NR_eventfd            (__NR_SYSCALL_BASE+351)
944
-#define __NR_fallocate            (__NR_SYSCALL_BASE+352)
945
-#define __NR_timerfd_settime        (__NR_SYSCALL_BASE+353)
946
-#define __NR_timerfd_gettime        (__NR_SYSCALL_BASE+354)
947
-#define __NR_signalfd4            (__NR_SYSCALL_BASE+355)
948
-#define __NR_eventfd2            (__NR_SYSCALL_BASE+356)
949
-#define __NR_epoll_create1        (__NR_SYSCALL_BASE+357)
950
-#define __NR_dup3            (__NR_SYSCALL_BASE+358)
951
-#define __NR_pipe2            (__NR_SYSCALL_BASE+359)
952
-#define __NR_inotify_init1        (__NR_SYSCALL_BASE+360)
953
-#define __NR_preadv            (__NR_SYSCALL_BASE+361)
954
-#define __NR_pwritev            (__NR_SYSCALL_BASE+362)
955
-#define __NR_rt_tgsigqueueinfo        (__NR_SYSCALL_BASE+363)
956
-#define __NR_perf_event_open        (__NR_SYSCALL_BASE+364)
957
-#define __NR_recvmmsg            (__NR_SYSCALL_BASE+365)
958
-#define __NR_accept4            (__NR_SYSCALL_BASE+366)
959
-#define __NR_fanotify_init        (__NR_SYSCALL_BASE+367)
960
-#define __NR_fanotify_mark        (__NR_SYSCALL_BASE+368)
961
-#define __NR_prlimit64            (__NR_SYSCALL_BASE+369)
962
-#define __NR_name_to_handle_at        (__NR_SYSCALL_BASE+370)
963
-#define __NR_open_by_handle_at        (__NR_SYSCALL_BASE+371)
964
-#define __NR_clock_adjtime        (__NR_SYSCALL_BASE+372)
965
-#define __NR_syncfs            (__NR_SYSCALL_BASE+373)
966
-#define __NR_sendmmsg            (__NR_SYSCALL_BASE+374)
967
-#define __NR_setns            (__NR_SYSCALL_BASE+375)
968
-#define __NR_process_vm_readv        (__NR_SYSCALL_BASE+376)
969
-#define __NR_process_vm_writev        (__NR_SYSCALL_BASE+377)
970
-#define __NR_kcmp            (__NR_SYSCALL_BASE+378)
971
-#define __NR_finit_module        (__NR_SYSCALL_BASE+379)
972
-#define __NR_sched_setattr        (__NR_SYSCALL_BASE+380)
973
-#define __NR_sched_getattr        (__NR_SYSCALL_BASE+381)
974
-#define __NR_renameat2            (__NR_SYSCALL_BASE+382)
975
-#define __NR_seccomp            (__NR_SYSCALL_BASE+383)
976
-#define __NR_getrandom            (__NR_SYSCALL_BASE+384)
977
-#define __NR_memfd_create        (__NR_SYSCALL_BASE+385)
978
-#define __NR_bpf            (__NR_SYSCALL_BASE+386)
979
-#define __NR_execveat            (__NR_SYSCALL_BASE+387)
980
-#define __NR_userfaultfd        (__NR_SYSCALL_BASE+388)
981
-#define __NR_membarrier            (__NR_SYSCALL_BASE+389)
982
-#define __NR_mlock2            (__NR_SYSCALL_BASE+390)
983
-#define __NR_copy_file_range        (__NR_SYSCALL_BASE+391)
984
-#define __NR_preadv2            (__NR_SYSCALL_BASE+392)
985
-#define __NR_pwritev2            (__NR_SYSCALL_BASE+393)
986
987
/*
988
* The following SWIs are ARM private.
989
@@ -XXX,XX +XXX,XX @@
990
#define __ARM_NR_usr32            (__ARM_NR_BASE+4)
991
#define __ARM_NR_set_tls        (__ARM_NR_BASE+5)
992
993
-/*
994
- * The following syscalls are obsolete and no longer available for EABI.
995
- */
996
-#if defined(__ARM_EABI__)
997
-#undef __NR_time
998
-#undef __NR_umount
999
-#undef __NR_stime
1000
-#undef __NR_alarm
1001
-#undef __NR_utime
1002
-#undef __NR_getrlimit
1003
-#undef __NR_select
1004
-#undef __NR_readdir
1005
-#undef __NR_mmap
1006
-#undef __NR_socketcall
1007
-#undef __NR_syscall
1008
-#undef __NR_ipc
1009
-#endif
1010
-
1011
#endif /* __ASM_ARM_UNISTD_H */
1012
diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h
1013
index XXXXXXX..XXXXXXX 100644
1014
--- a/linux-headers/asm-arm64/kvm.h
1015
+++ b/linux-headers/asm-arm64/kvm.h
1016
@@ -XXX,XX +XXX,XX @@ struct kvm_arch_memory_slot {
1017
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS    2
1018
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT    32
1019
#define KVM_DEV_ARM_VGIC_CPUID_MASK    (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
1020
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
1021
+#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
1022
+            (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
1023
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT    0
1024
#define KVM_DEV_ARM_VGIC_OFFSET_MASK    (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
1025
+#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
1026
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
1027
#define KVM_DEV_ARM_VGIC_GRP_CTRL    4
1028
+#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
1029
+#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
1030
+#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
1031
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT    10
1032
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
1033
+            (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
1034
+#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK    0x3ff
1035
+#define VGIC_LEVEL_INFO_LINE_LEVEL    0
1036
+
1037
#define KVM_DEV_ARM_VGIC_CTRL_INIT    0
1038
1039
/* Device Control API on vcpu fd */
1040
diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
1041
index XXXXXXX..XXXXXXX 100644
1042
--- a/linux-headers/asm-powerpc/kvm.h
1043
+++ b/linux-headers/asm-powerpc/kvm.h
1044
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1045
    __u16    n_invalid;
1046
};
1047
1048
+/* For KVM_PPC_CONFIGURE_V3_MMU */
1049
+struct kvm_ppc_mmuv3_cfg {
1050
+    __u64    flags;
1051
+    __u64    process_table;    /* second doubleword of partition table entry */
1052
+};
1053
+
1054
+/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
1055
+#define KVM_PPC_MMUV3_RADIX    1    /* 1 = radix mode, 0 = HPT */
1056
+#define KVM_PPC_MMUV3_GTSE    2    /* global translation shootdown enb. */
1057
+
1058
+/* For KVM_PPC_GET_RMMU_INFO */
1059
+struct kvm_ppc_rmmu_info {
1060
+    struct kvm_ppc_radix_geom {
1061
+        __u8    page_shift;
1062
+        __u8    level_bits[4];
1063
+        __u8    pad[3];
1064
+    }    geometries[8];
1065
+    __u32    ap_encodings[8];
1066
+};
1067
+
1068
/* Per-vcpu XICS interrupt controller state */
1069
#define KVM_REG_PPC_ICP_STATE    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
1070
1071
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1072
#define KVM_REG_PPC_SPRG9    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
1073
#define KVM_REG_PPC_DBSR    (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
1074
1075
+/* POWER9 registers */
1076
+#define KVM_REG_PPC_TIDR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
1077
+#define KVM_REG_PPC_PSSCR    (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
1078
+
1079
/* Transactional Memory checkpointed state:
1080
* This is all GPRs, all VSX regs and a subset of SPRs
1081
*/
1082
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1083
#define KVM_REG_PPC_TM_VSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
1084
#define KVM_REG_PPC_TM_DSCR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
1085
#define KVM_REG_PPC_TM_TAR    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
1086
+#define KVM_REG_PPC_TM_XER    (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
1087
1088
/* PPC64 eXternal Interrupt Controller Specification */
1089
#define KVM_DEV_XICS_GRP_SOURCES    1    /* 64-bit source attributes */
1090
@@ -XXX,XX +XXX,XX @@ struct kvm_get_htab_header {
1091
#define KVM_XICS_LEVEL_SENSITIVE    (1ULL << 40)
1092
#define KVM_XICS_MASKED        (1ULL << 41)
1093
#define KVM_XICS_PENDING        (1ULL << 42)
1094
+#define KVM_XICS_PRESENTED        (1ULL << 43)
1095
+#define KVM_XICS_QUEUED        (1ULL << 44)
1096
1097
#endif /* __LINUX_KVM_POWERPC_H */
1098
diff --git a/linux-headers/asm-powerpc/unistd.h b/linux-headers/asm-powerpc/unistd.h
1099
index XXXXXXX..XXXXXXX 100644
1100
--- a/linux-headers/asm-powerpc/unistd.h
1101
+++ b/linux-headers/asm-powerpc/unistd.h
1102
@@ -XXX,XX +XXX,XX @@
1103
#define __NR_copy_file_range    379
1104
#define __NR_preadv2        380
1105
#define __NR_pwritev2        381
1106
+#define __NR_kexec_file_load    382
1107
1108
#endif /* _ASM_POWERPC_UNISTD_H_ */
1109
diff --git a/linux-headers/asm-x86/kvm_para.h b/linux-headers/asm-x86/kvm_para.h
1110
index XXXXXXX..XXXXXXX 100644
1111
--- a/linux-headers/asm-x86/kvm_para.h
1112
+++ b/linux-headers/asm-x86/kvm_para.h
1113
@@ -XXX,XX +XXX,XX @@ struct kvm_steal_time {
1114
    __u64 steal;
1115
    __u32 version;
1116
    __u32 flags;
1117
-    __u32 pad[12];
1118
+    __u8 preempted;
1119
+    __u8 u8_pad[3];
1120
+    __u32 pad[11];
1121
+};
1122
+
1123
+#define KVM_CLOCK_PAIRING_WALLCLOCK 0
1124
+struct kvm_clock_pairing {
1125
+    __s64 sec;
1126
+    __s64 nsec;
1127
+    __u64 tsc;
1128
+    __u32 flags;
1129
+    __u32 pad[9];
1130
};
1131
1132
#define KVM_STEAL_ALIGNMENT_BITS 5
1133
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
1134
index XXXXXXX..XXXXXXX 100644
1135
--- a/linux-headers/linux/kvm.h
1136
+++ b/linux-headers/linux/kvm.h
1137
@@ -XXX,XX +XXX,XX @@ struct kvm_hyperv_exit {
1138
struct kvm_run {
1139
    /* in */
1140
    __u8 request_interrupt_window;
1141
-    __u8 padding1[7];
1142
+    __u8 immediate_exit;
1143
+    __u8 padding1[6];
1144
1145
    /* out */
1146
    __u32 exit_reason;
1147
@@ -XXX,XX +XXX,XX @@ struct kvm_enable_cap {
1148
};
1149
1150
/* for KVM_PPC_GET_PVINFO */
1151
+
1152
+#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1153
+
1154
struct kvm_ppc_pvinfo {
1155
    /* out */
1156
    __u32 flags;
1157
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1158
    struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
1159
};
1160
1161
-#define KVM_PPC_PVINFO_FLAGS_EV_IDLE (1<<0)
1162
+/* for KVM_PPC_RESIZE_HPT_{PREPARE,COMMIT} */
1163
+struct kvm_ppc_resize_hpt {
1164
+    __u64 flags;
1165
+    __u32 shift;
1166
+    __u32 pad;
1167
+};
1168
1169
#define KVMIO 0xAE
1170
1171
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_smmu_info {
1172
#define KVM_CAP_S390_USER_INSTR0 130
1173
#define KVM_CAP_MSI_DEVID 131
1174
#define KVM_CAP_PPC_HTM 132
1175
+#define KVM_CAP_SPAPR_RESIZE_HPT 133
1176
+#define KVM_CAP_PPC_MMU_RADIX 134
1177
+#define KVM_CAP_PPC_MMU_HASH_V3 135
1178
+#define KVM_CAP_IMMEDIATE_EXIT 136
1179
1180
#ifdef KVM_CAP_IRQ_ROUTING
1181
1182
@@ -XXX,XX +XXX,XX @@ struct kvm_s390_ucas_mapping {
1183
#define KVM_ARM_SET_DEVICE_ADDR     _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
1184
/* Available with KVM_CAP_PPC_RTAS */
1185
#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
1186
+/* Available with KVM_CAP_SPAPR_RESIZE_HPT */
1187
+#define KVM_PPC_RESIZE_HPT_PREPARE _IOR(KVMIO, 0xad, struct kvm_ppc_resize_hpt)
1188
+#define KVM_PPC_RESIZE_HPT_COMMIT _IOR(KVMIO, 0xae, struct kvm_ppc_resize_hpt)
1189
+/* Available with KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3 */
1190
+#define KVM_PPC_CONFIGURE_V3_MMU _IOW(KVMIO, 0xaf, struct kvm_ppc_mmuv3_cfg)
1191
+/* Available with KVM_CAP_PPC_RADIX_MMU */
1192
+#define KVM_PPC_GET_RMMU_INFO     _IOW(KVMIO, 0xb0, struct kvm_ppc_rmmu_info)
1193
1194
/* ioctl for vm fd */
1195
#define KVM_CREATE_DEVICE     _IOWR(KVMIO, 0xe0, struct kvm_create_device)
1196
diff --git a/linux-headers/linux/kvm_para.h b/linux-headers/linux/kvm_para.h
1197
index XXXXXXX..XXXXXXX 100644
1198
--- a/linux-headers/linux/kvm_para.h
1199
+++ b/linux-headers/linux/kvm_para.h
1200
@@ -XXX,XX +XXX,XX @@
1201
#define KVM_EFAULT        EFAULT
1202
#define KVM_E2BIG        E2BIG
1203
#define KVM_EPERM        EPERM
1204
+#define KVM_EOPNOTSUPP        95
1205
1206
#define KVM_HC_VAPIC_POLL_IRQ        1
1207
#define KVM_HC_MMU_OP            2
1208
@@ -XXX,XX +XXX,XX @@
1209
#define KVM_HC_MIPS_GET_CLOCK_FREQ    6
1210
#define KVM_HC_MIPS_EXIT_VM        7
1211
#define KVM_HC_MIPS_CONSOLE_OUTPUT    8
1212
+#define KVM_HC_CLOCK_PAIRING        9
1213
1214
/*
1215
* hypercalls use architecture specific
1216
diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfaultfd.h
1217
index XXXXXXX..XXXXXXX 100644
1218
--- a/linux-headers/linux/userfaultfd.h
1219
+++ b/linux-headers/linux/userfaultfd.h
1220
@@ -XXX,XX +XXX,XX @@
1221
1222
#include <linux/types.h>
1223
1224
-#define UFFD_API ((__u64)0xAA)
1225
/*
1226
- * After implementing the respective features it will become:
1227
- * #define UFFD_API_FEATURES (UFFD_FEATURE_PAGEFAULT_FLAG_WP | \
1228
- *             UFFD_FEATURE_EVENT_FORK)
1229
+ * If the UFFDIO_API is upgraded someday, the UFFDIO_UNREGISTER and
1230
+ * UFFDIO_WAKE ioctls should be defined as _IOW and not as _IOR. In
1231
+ * userfaultfd.h we assumed the kernel was reading (instead _IOC_READ
1232
+ * means the userland is reading).
1233
*/
1234
-#define UFFD_API_FEATURES (0)
1235
+#define UFFD_API ((__u64)0xAA)
1236
+#define UFFD_API_FEATURES (UFFD_FEATURE_EVENT_FORK |        \
1237
+             UFFD_FEATURE_EVENT_REMAP |        \
1238
+             UFFD_FEATURE_EVENT_MADVDONTNEED |    \
1239
+             UFFD_FEATURE_MISSING_HUGETLBFS |    \
1240
+             UFFD_FEATURE_MISSING_SHMEM)
1241
#define UFFD_API_IOCTLS                \
1242
    ((__u64)1 << _UFFDIO_REGISTER |        \
1243
     (__u64)1 << _UFFDIO_UNREGISTER |    \
1244
@@ -XXX,XX +XXX,XX @@
1245
    ((__u64)1 << _UFFDIO_WAKE |        \
1246
     (__u64)1 << _UFFDIO_COPY |        \
1247
     (__u64)1 << _UFFDIO_ZEROPAGE)
1248
+#define UFFD_API_RANGE_IOCTLS_BASIC        \
1249
+    ((__u64)1 << _UFFDIO_WAKE |        \
1250
+     (__u64)1 << _UFFDIO_COPY)
1251
1252
/*
1253
* Valid ioctl command number range with this API is from 0x00 to
1254
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1255
        } pagefault;
1256
1257
        struct {
1258
+            __u32    ufd;
1259
+        } fork;
1260
+
1261
+        struct {
1262
+            __u64    from;
1263
+            __u64    to;
1264
+            __u64    len;
1265
+        } remap;
1266
+
1267
+        struct {
1268
+            __u64    start;
1269
+            __u64    end;
1270
+        } madv_dn;
1271
+
1272
+        struct {
1273
            /* unused reserved fields */
1274
            __u64    reserved1;
1275
            __u64    reserved2;
1276
@@ -XXX,XX +XXX,XX @@ struct uffd_msg {
1277
* Start at 0x12 and not at 0 to be more strict against bugs.
1278
*/
1279
#define UFFD_EVENT_PAGEFAULT    0x12
1280
-#if 0 /* not available yet */
1281
#define UFFD_EVENT_FORK        0x13
1282
-#endif
1283
+#define UFFD_EVENT_REMAP    0x14
1284
+#define UFFD_EVENT_MADVDONTNEED    0x15
1285
1286
/* flags for UFFD_EVENT_PAGEFAULT */
1287
#define UFFD_PAGEFAULT_FLAG_WRITE    (1<<0)    /* If this was a write fault */
1288
@@ -XXX,XX +XXX,XX @@ struct uffdio_api {
1289
     * Note: UFFD_EVENT_PAGEFAULT and UFFD_PAGEFAULT_FLAG_WRITE
1290
     * are to be considered implicitly always enabled in all kernels as
1291
     * long as the uffdio_api.api requested matches UFFD_API.
1292
+     *
1293
+     * UFFD_FEATURE_MISSING_HUGETLBFS means an UFFDIO_REGISTER
1294
+     * with UFFDIO_REGISTER_MODE_MISSING mode will succeed on
1295
+     * hugetlbfs virtual memory ranges. Adding or not adding
1296
+     * UFFD_FEATURE_MISSING_HUGETLBFS to uffdio_api.features has
1297
+     * no real functional effect after UFFDIO_API returns, but
1298
+     * it's only useful for an initial feature set probe at
1299
+     * UFFDIO_API time. There are two ways to use it:
1300
+     *
1301
+     * 1) by adding UFFD_FEATURE_MISSING_HUGETLBFS to the
1302
+     * uffdio_api.features before calling UFFDIO_API, an error
1303
+     * will be returned by UFFDIO_API on a kernel without
1304
+     * hugetlbfs missing support
1305
+     *
1306
+     * 2) the UFFD_FEATURE_MISSING_HUGETLBFS can not be added in
1307
+     * uffdio_api.features and instead it will be set by the
1308
+     * kernel in the uffdio_api.features if the kernel supports
1309
+     * it, so userland can later check if the feature flag is
1310
+     * present in uffdio_api.features after UFFDIO_API
1311
+     * succeeded.
1312
+     *
1313
+     * UFFD_FEATURE_MISSING_SHMEM works the same as
1314
+     * UFFD_FEATURE_MISSING_HUGETLBFS, but it applies to shmem
1315
+     * (i.e. tmpfs and other shmem based APIs).
1316
     */
1317
-#if 0 /* not available yet */
1318
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP        (1<<0)
1319
#define UFFD_FEATURE_EVENT_FORK            (1<<1)
1320
-#endif
1321
+#define UFFD_FEATURE_EVENT_REMAP        (1<<2)
1322
+#define UFFD_FEATURE_EVENT_MADVDONTNEED        (1<<3)
1323
+#define UFFD_FEATURE_MISSING_HUGETLBFS        (1<<4)
1324
+#define UFFD_FEATURE_MISSING_SHMEM        (1<<5)
1325
    __u64 features;
1326
1327
    __u64 ioctls;
1328
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
1329
index XXXXXXX..XXXXXXX 100644
1330
--- a/linux-headers/linux/vfio.h
1331
+++ b/linux-headers/linux/vfio.h
1332
@@ -XXX,XX +XXX,XX @@ struct vfio_device_info {
1333
};
1334
#define VFIO_DEVICE_GET_INFO        _IO(VFIO_TYPE, VFIO_BASE + 7)
1335
1336
+/*
1337
+ * Vendor driver using Mediated device framework should provide device_api
1338
+ * attribute in supported type attribute groups. Device API string should be one
1339
+ * of the following corresponding to device flags in vfio_device_info structure.
1340
+ */
1341
+
1342
+#define VFIO_DEVICE_API_PCI_STRING        "vfio-pci"
1343
+#define VFIO_DEVICE_API_PLATFORM_STRING        "vfio-platform"
1344
+#define VFIO_DEVICE_API_AMBA_STRING        "vfio-amba"
1345
+
1346
/**
1347
* VFIO_DEVICE_GET_REGION_INFO - _IOWR(VFIO_TYPE, VFIO_BASE + 8,
1348
*                 struct vfio_region_info)
1349
--
69
--
1350
2.7.4
70
2.20.1
1351
71
1352
72
diff view generated by jsdifflib
1
From: Clement Deschamps <clement.deschamps@antfield.fr>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
This adds the BCM2835 GPIO controller.
3
When using a Cortex-A15, the Virt machine does not use any
4
MPCore peripherals. Remove the dependency.
4
5
5
It currently implements:
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
6
- The 54 GPIOs as outputs (qemu_irq)
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
7
- The SD controller selection via alternate function of GPIOs 48-53
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
9
Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 1488293711-14195-4-git-send-email-peter.maydell@linaro.org
13
Message-id: 20170224164021.9066-4-clement.deschamps@antfield.fr
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
12
---
17
hw/gpio/Makefile.objs | 1 +
13
hw/arm/Kconfig | 1 -
18
include/hw/gpio/bcm2835_gpio.h | 39 +++++
14
1 file changed, 1 deletion(-)
19
hw/gpio/bcm2835_gpio.c | 353 +++++++++++++++++++++++++++++++++++++++++
20
3 files changed, 393 insertions(+)
21
create mode 100644 include/hw/gpio/bcm2835_gpio.h
22
create mode 100644 hw/gpio/bcm2835_gpio.c
23
15
24
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
25
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/gpio/Makefile.objs
18
--- a/hw/arm/Kconfig
27
+++ b/hw/gpio/Makefile.objs
19
+++ b/hw/arm/Kconfig
28
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
29
21
imply VFIO_PLATFORM
30
obj-$(CONFIG_OMAP) += omap_gpio.o
22
imply VFIO_XGMAC
31
obj-$(CONFIG_IMX) += imx_gpio.o
23
imply TPM_TIS_SYSBUS
32
+obj-$(CONFIG_RASPI) += bcm2835_gpio.o
24
- select A15MPCORE
33
diff --git a/include/hw/gpio/bcm2835_gpio.h b/include/hw/gpio/bcm2835_gpio.h
25
select ACPI
34
new file mode 100644
26
select ARM_SMMUV3
35
index XXXXXXX..XXXXXXX
27
select GPIO_KEY
36
--- /dev/null
37
+++ b/include/hw/gpio/bcm2835_gpio.h
38
@@ -XXX,XX +XXX,XX @@
39
+/*
40
+ * Raspberry Pi (BCM2835) GPIO Controller
41
+ *
42
+ * Copyright (c) 2017 Antfield SAS
43
+ *
44
+ * Authors:
45
+ * Clement Deschamps <clement.deschamps@antfield.fr>
46
+ * Luc Michel <luc.michel@antfield.fr>
47
+ *
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
49
+ * See the COPYING file in the top-level directory.
50
+ */
51
+
52
+#ifndef BCM2835_GPIO_H
53
+#define BCM2835_GPIO_H
54
+
55
+#include "hw/sd/sd.h"
56
+
57
+typedef struct BCM2835GpioState {
58
+ SysBusDevice parent_obj;
59
+
60
+ MemoryRegion iomem;
61
+
62
+ /* SDBus selector */
63
+ SDBus sdbus;
64
+ SDBus *sdbus_sdhci;
65
+ SDBus *sdbus_sdhost;
66
+
67
+ uint8_t fsel[54];
68
+ uint32_t lev0, lev1;
69
+ uint8_t sd_fsel;
70
+ qemu_irq out[54];
71
+} BCM2835GpioState;
72
+
73
+#define TYPE_BCM2835_GPIO "bcm2835_gpio"
74
+#define BCM2835_GPIO(obj) \
75
+ OBJECT_CHECK(BCM2835GpioState, (obj), TYPE_BCM2835_GPIO)
76
+
77
+#endif
78
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
79
new file mode 100644
80
index XXXXXXX..XXXXXXX
81
--- /dev/null
82
+++ b/hw/gpio/bcm2835_gpio.c
83
@@ -XXX,XX +XXX,XX @@
84
+/*
85
+ * Raspberry Pi (BCM2835) GPIO Controller
86
+ *
87
+ * Copyright (c) 2017 Antfield SAS
88
+ *
89
+ * Authors:
90
+ * Clement Deschamps <clement.deschamps@antfield.fr>
91
+ * Luc Michel <luc.michel@antfield.fr>
92
+ *
93
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
94
+ * See the COPYING file in the top-level directory.
95
+ */
96
+
97
+#include "qemu/osdep.h"
98
+#include "qemu/log.h"
99
+#include "qemu/timer.h"
100
+#include "qapi/error.h"
101
+#include "hw/sysbus.h"
102
+#include "hw/sd/sd.h"
103
+#include "hw/gpio/bcm2835_gpio.h"
104
+
105
+#define GPFSEL0 0x00
106
+#define GPFSEL1 0x04
107
+#define GPFSEL2 0x08
108
+#define GPFSEL3 0x0C
109
+#define GPFSEL4 0x10
110
+#define GPFSEL5 0x14
111
+#define GPSET0 0x1C
112
+#define GPSET1 0x20
113
+#define GPCLR0 0x28
114
+#define GPCLR1 0x2C
115
+#define GPLEV0 0x34
116
+#define GPLEV1 0x38
117
+#define GPEDS0 0x40
118
+#define GPEDS1 0x44
119
+#define GPREN0 0x4C
120
+#define GPREN1 0x50
121
+#define GPFEN0 0x58
122
+#define GPFEN1 0x5C
123
+#define GPHEN0 0x64
124
+#define GPHEN1 0x68
125
+#define GPLEN0 0x70
126
+#define GPLEN1 0x74
127
+#define GPAREN0 0x7C
128
+#define GPAREN1 0x80
129
+#define GPAFEN0 0x88
130
+#define GPAFEN1 0x8C
131
+#define GPPUD 0x94
132
+#define GPPUDCLK0 0x98
133
+#define GPPUDCLK1 0x9C
134
+
135
+static uint32_t gpfsel_get(BCM2835GpioState *s, uint8_t reg)
136
+{
137
+ int i;
138
+ uint32_t value = 0;
139
+ for (i = 0; i < 10; i++) {
140
+ uint32_t index = 10 * reg + i;
141
+ if (index < sizeof(s->fsel)) {
142
+ value |= (s->fsel[index] & 0x7) << (3 * i);
143
+ }
144
+ }
145
+ return value;
146
+}
147
+
148
+static void gpfsel_set(BCM2835GpioState *s, uint8_t reg, uint32_t value)
149
+{
150
+ int i;
151
+ for (i = 0; i < 10; i++) {
152
+ uint32_t index = 10 * reg + i;
153
+ if (index < sizeof(s->fsel)) {
154
+ int fsel = (value >> (3 * i)) & 0x7;
155
+ s->fsel[index] = fsel;
156
+ }
157
+ }
158
+
159
+ /* SD controller selection (48-53) */
160
+ if (s->sd_fsel != 0
161
+ && (s->fsel[48] == 0) /* SD_CLK_R */
162
+ && (s->fsel[49] == 0) /* SD_CMD_R */
163
+ && (s->fsel[50] == 0) /* SD_DATA0_R */
164
+ && (s->fsel[51] == 0) /* SD_DATA1_R */
165
+ && (s->fsel[52] == 0) /* SD_DATA2_R */
166
+ && (s->fsel[53] == 0) /* SD_DATA3_R */
167
+ ) {
168
+ /* SDHCI controller selected */
169
+ sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci);
170
+ s->sd_fsel = 0;
171
+ } else if (s->sd_fsel != 4
172
+ && (s->fsel[48] == 4) /* SD_CLK_R */
173
+ && (s->fsel[49] == 4) /* SD_CMD_R */
174
+ && (s->fsel[50] == 4) /* SD_DATA0_R */
175
+ && (s->fsel[51] == 4) /* SD_DATA1_R */
176
+ && (s->fsel[52] == 4) /* SD_DATA2_R */
177
+ && (s->fsel[53] == 4) /* SD_DATA3_R */
178
+ ) {
179
+ /* SDHost controller selected */
180
+ sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost);
181
+ s->sd_fsel = 4;
182
+ }
183
+}
184
+
185
+static int gpfsel_is_out(BCM2835GpioState *s, int index)
186
+{
187
+ if (index >= 0 && index < 54) {
188
+ return s->fsel[index] == 1;
189
+ }
190
+ return 0;
191
+}
192
+
193
+static void gpset(BCM2835GpioState *s,
194
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
195
+{
196
+ uint32_t changes = val & ~*lev;
197
+ uint32_t cur = 1;
198
+
199
+ int i;
200
+ for (i = 0; i < count; i++) {
201
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
202
+ qemu_set_irq(s->out[start + i], 1);
203
+ }
204
+ cur <<= 1;
205
+ }
206
+
207
+ *lev |= val;
208
+}
209
+
210
+static void gpclr(BCM2835GpioState *s,
211
+ uint32_t val, uint8_t start, uint8_t count, uint32_t *lev)
212
+{
213
+ uint32_t changes = val & *lev;
214
+ uint32_t cur = 1;
215
+
216
+ int i;
217
+ for (i = 0; i < count; i++) {
218
+ if ((changes & cur) && (gpfsel_is_out(s, start + i))) {
219
+ qemu_set_irq(s->out[start + i], 0);
220
+ }
221
+ cur <<= 1;
222
+ }
223
+
224
+ *lev &= ~val;
225
+}
226
+
227
+static uint64_t bcm2835_gpio_read(void *opaque, hwaddr offset,
228
+ unsigned size)
229
+{
230
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
231
+
232
+ switch (offset) {
233
+ case GPFSEL0:
234
+ case GPFSEL1:
235
+ case GPFSEL2:
236
+ case GPFSEL3:
237
+ case GPFSEL4:
238
+ case GPFSEL5:
239
+ return gpfsel_get(s, offset / 4);
240
+ case GPSET0:
241
+ case GPSET1:
242
+ /* Write Only */
243
+ return 0;
244
+ case GPCLR0:
245
+ case GPCLR1:
246
+ /* Write Only */
247
+ return 0;
248
+ case GPLEV0:
249
+ return s->lev0;
250
+ case GPLEV1:
251
+ return s->lev1;
252
+ case GPEDS0:
253
+ case GPEDS1:
254
+ case GPREN0:
255
+ case GPREN1:
256
+ case GPFEN0:
257
+ case GPFEN1:
258
+ case GPHEN0:
259
+ case GPHEN1:
260
+ case GPLEN0:
261
+ case GPLEN1:
262
+ case GPAREN0:
263
+ case GPAREN1:
264
+ case GPAFEN0:
265
+ case GPAFEN1:
266
+ case GPPUD:
267
+ case GPPUDCLK0:
268
+ case GPPUDCLK1:
269
+ /* Not implemented */
270
+ return 0;
271
+ default:
272
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
273
+ __func__, offset);
274
+ break;
275
+ }
276
+
277
+ return 0;
278
+}
279
+
280
+static void bcm2835_gpio_write(void *opaque, hwaddr offset,
281
+ uint64_t value, unsigned size)
282
+{
283
+ BCM2835GpioState *s = (BCM2835GpioState *)opaque;
284
+
285
+ switch (offset) {
286
+ case GPFSEL0:
287
+ case GPFSEL1:
288
+ case GPFSEL2:
289
+ case GPFSEL3:
290
+ case GPFSEL4:
291
+ case GPFSEL5:
292
+ gpfsel_set(s, offset / 4, value);
293
+ break;
294
+ case GPSET0:
295
+ gpset(s, value, 0, 32, &s->lev0);
296
+ break;
297
+ case GPSET1:
298
+ gpset(s, value, 32, 22, &s->lev1);
299
+ break;
300
+ case GPCLR0:
301
+ gpclr(s, value, 0, 32, &s->lev0);
302
+ break;
303
+ case GPCLR1:
304
+ gpclr(s, value, 32, 22, &s->lev1);
305
+ break;
306
+ case GPLEV0:
307
+ case GPLEV1:
308
+ /* Read Only */
309
+ break;
310
+ case GPEDS0:
311
+ case GPEDS1:
312
+ case GPREN0:
313
+ case GPREN1:
314
+ case GPFEN0:
315
+ case GPFEN1:
316
+ case GPHEN0:
317
+ case GPHEN1:
318
+ case GPLEN0:
319
+ case GPLEN1:
320
+ case GPAREN0:
321
+ case GPAREN1:
322
+ case GPAFEN0:
323
+ case GPAFEN1:
324
+ case GPPUD:
325
+ case GPPUDCLK0:
326
+ case GPPUDCLK1:
327
+ /* Not implemented */
328
+ break;
329
+ default:
330
+ goto err_out;
331
+ }
332
+ return;
333
+
334
+err_out:
335
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
336
+ __func__, offset);
337
+}
338
+
339
+static void bcm2835_gpio_reset(DeviceState *dev)
340
+{
341
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
342
+
343
+ int i;
344
+ for (i = 0; i < 6; i++) {
345
+ gpfsel_set(s, i, 0);
346
+ }
347
+
348
+ s->sd_fsel = 0;
349
+
350
+ /* SDHCI is selected by default */
351
+ sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci);
352
+
353
+ s->lev0 = 0;
354
+ s->lev1 = 0;
355
+}
356
+
357
+static const MemoryRegionOps bcm2835_gpio_ops = {
358
+ .read = bcm2835_gpio_read,
359
+ .write = bcm2835_gpio_write,
360
+ .endianness = DEVICE_NATIVE_ENDIAN,
361
+};
362
+
363
+static const VMStateDescription vmstate_bcm2835_gpio = {
364
+ .name = "bcm2835_gpio",
365
+ .version_id = 1,
366
+ .minimum_version_id = 1,
367
+ .fields = (VMStateField[]) {
368
+ VMSTATE_UINT8_ARRAY(fsel, BCM2835GpioState, 54),
369
+ VMSTATE_UINT32(lev0, BCM2835GpioState),
370
+ VMSTATE_UINT32(lev1, BCM2835GpioState),
371
+ VMSTATE_UINT8(sd_fsel, BCM2835GpioState),
372
+ VMSTATE_END_OF_LIST()
373
+ }
374
+};
375
+
376
+static void bcm2835_gpio_init(Object *obj)
377
+{
378
+ BCM2835GpioState *s = BCM2835_GPIO(obj);
379
+ DeviceState *dev = DEVICE(obj);
380
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
381
+
382
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
383
+ TYPE_SD_BUS, DEVICE(s), "sd-bus");
384
+
385
+ memory_region_init_io(&s->iomem, obj,
386
+ &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
387
+ sysbus_init_mmio(sbd, &s->iomem);
388
+ qdev_init_gpio_out(dev, s->out, 54);
389
+}
390
+
391
+static void bcm2835_gpio_realize(DeviceState *dev, Error **errp)
392
+{
393
+ BCM2835GpioState *s = BCM2835_GPIO(dev);
394
+ Object *obj;
395
+ Error *err = NULL;
396
+
397
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhci", &err);
398
+ if (obj == NULL) {
399
+ error_setg(errp, "%s: required sdhci link not found: %s",
400
+ __func__, error_get_pretty(err));
401
+ return;
402
+ }
403
+ s->sdbus_sdhci = SD_BUS(obj);
404
+
405
+ obj = object_property_get_link(OBJECT(dev), "sdbus-sdhost", &err);
406
+ if (obj == NULL) {
407
+ error_setg(errp, "%s: required sdhost link not found: %s",
408
+ __func__, error_get_pretty(err));
409
+ return;
410
+ }
411
+ s->sdbus_sdhost = SD_BUS(obj);
412
+}
413
+
414
+static void bcm2835_gpio_class_init(ObjectClass *klass, void *data)
415
+{
416
+ DeviceClass *dc = DEVICE_CLASS(klass);
417
+
418
+ dc->vmsd = &vmstate_bcm2835_gpio;
419
+ dc->realize = &bcm2835_gpio_realize;
420
+ dc->reset = &bcm2835_gpio_reset;
421
+}
422
+
423
+static const TypeInfo bcm2835_gpio_info = {
424
+ .name = TYPE_BCM2835_GPIO,
425
+ .parent = TYPE_SYS_BUS_DEVICE,
426
+ .instance_size = sizeof(BCM2835GpioState),
427
+ .instance_init = bcm2835_gpio_init,
428
+ .class_init = bcm2835_gpio_class_init,
429
+};
430
+
431
+static void bcm2835_gpio_register_types(void)
432
+{
433
+ type_register_static(&bcm2835_gpio_info);
434
+}
435
+
436
+type_init(bcm2835_gpio_register_types)
437
--
28
--
438
2.7.4
29
2.20.1
439
30
440
31
diff view generated by jsdifflib
1
Make the NVIC device expose a memory region for its users
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to map, rather than mapping itself into the system memory
3
space on realize, and get the one user (the ARMv7M object)
4
to do this.
5
2
3
The helper function did not get updated when we reorganized
4
the vector register file for SVE. Since then, the neon dregs
5
are non-sequential and cannot be simply indexed.
6
7
At the same time, make the helper function operate on 64-bit
8
quantities so that we do not have to call it twice.
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 1487604965-23220-7-git-send-email-peter.maydell@linaro.org
9
---
17
---
10
hw/arm/armv7m.c | 7 ++++++-
18
target/arm/helper.h | 2 +-
11
hw/intc/armv7m_nvic.c | 7 ++-----
19
target/arm/op_helper.c | 23 +++++++++--------
12
2 files changed, 8 insertions(+), 6 deletions(-)
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
13
22
14
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/armv7m.c
25
--- a/target/arm/helper.h
17
+++ b/hw/arm/armv7m.c
26
+++ b/target/arm/helper.h
18
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
19
static void armv7m_realize(DeviceState *dev, Error **errp)
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
33
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
20
{
48
{
21
ARMv7MState *s = ARMV7M(dev);
49
- uint32_t val, shift;
22
+ SysBusDevice *sbd;
50
- uint64_t *table = vn;
23
Error *err = NULL;
51
+ uint64_t tmp, val = 0;
24
int i;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
25
char **cpustr;
53
+ uint32_t base_reg = desc >> 2;
26
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
54
+ uint32_t shift, index, reg;
27
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
55
28
56
- val = 0;
29
/* Wire the NVIC up to the CPU */
57
- for (shift = 0; shift < 32; shift += 8) {
30
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->nvic), 0,
58
- uint32_t index = (ireg >> shift) & 0xff;
31
+ sbd = SYS_BUS_DEVICE(&s->nvic);
59
+ for (shift = 0; shift < 64; shift += 8) {
32
+ sysbus_connect_irq(sbd, 0,
60
+ index = (ireg >> shift) & 0xff;
33
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
61
if (index < maxindex) {
34
s->cpu->env.nvic = &s->nvic;
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
35
63
- val |= tmp << shift;
36
+ memory_region_add_subregion(&s->container, 0xe000e000,
64
+ reg = base_reg + (index >> 3);
37
+ sysbus_mmio_get_region(sbd, 0));
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
38
+
141
+
39
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
142
+ tcg_temp_free_i64(def);
40
Object *obj = OBJECT(&s->bitband[i]);
143
+ tcg_temp_free_i64(val);
41
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
144
+ tcg_temp_free_i32(desc);
42
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
145
return true;
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/intc/armv7m_nvic.c
45
+++ b/hw/intc/armv7m_nvic.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "hw/arm/arm.h"
48
#include "hw/arm/armv7m_nvic.h"
49
#include "target/arm/cpu.h"
50
-#include "exec/address-spaces.h"
51
#include "qemu/log.h"
52
#include "trace.h"
53
54
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
55
"nvic_sysregs", 0x1000);
56
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
57
58
- /* Map the whole thing into system memory at the location required
59
- * by the v7M architecture.
60
- */
61
- memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
62
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
63
+
64
s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
65
}
146
}
66
147
67
--
148
--
68
2.7.4
149
2.20.1
69
150
70
151
diff view generated by jsdifflib
1
Make the ARMv7M object take a memory region link which it uses
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
to wire up the bitband rather than having them always put
3
themselves in the system address space.
4
2
3
We can use one MPC per SRAM bank, but we currently only wire the
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1487604965-23220-6-git-send-email-peter.maydell@linaro.org
8
---
11
---
9
include/hw/arm/armv7m.h | 10 ++++++++++
12
hw/arm/armsse.c | 3 ++-
10
hw/arm/armv7m.c | 23 ++++++++++++++++++++++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
11
2 files changed, 32 insertions(+), 1 deletion(-)
12
14
13
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/armv7m.h
17
--- a/hw/arm/armsse.c
16
+++ b/include/hw/arm/armv7m.h
18
+++ b/hw/arm/armsse.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
18
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
20
qdev_get_gpio_in(dev_splitter, 0));
19
* + Property "cpu-model": CPU model to instantiate
21
qdev_connect_gpio_out(dev_splitter, 0,
20
* + Property "num-irq": number of external IRQ lines
22
qdev_get_gpio_in_named(dev_secctl,
21
+ * + Property "memory": MemoryRegion defining the physical address space
23
- "mpc_status", 0));
22
+ * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
24
+ "mpc_status",
23
+ * devices will be automatically layered on top of this view.)
25
+ i - IOTS_NUM_EXP_MPC));
24
*/
25
typedef struct ARMv7MState {
26
/*< private >*/
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
28
BitBandState bitband[ARMV7M_NUM_BITBANDS];
29
ARMCPU *cpu;
30
31
+ /* MemoryRegion we pass to the CPU, with our devices layered on
32
+ * top of the ones the board provides in board_memory.
33
+ */
34
+ MemoryRegion container;
35
+
36
/* Properties */
37
char *cpu_model;
38
+ /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
39
+ MemoryRegion *board_memory;
40
} ARMv7MState;
41
42
#endif
43
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/armv7m.c
46
+++ b/hw/arm/armv7m.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "elf.h"
49
#include "sysemu/qtest.h"
50
#include "qemu/error-report.h"
51
+#include "exec/address-spaces.h"
52
53
/* Bitbanded IO. Each word corresponds to a single bit. */
54
55
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
56
57
/* Can't init the cpu here, we don't yet know which model to use */
58
59
+ object_property_add_link(obj, "memory",
60
+ TYPE_MEMORY_REGION,
61
+ (Object **)&s->board_memory,
62
+ qdev_prop_allow_set_link_before_realize,
63
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
64
+ &error_abort);
65
+ memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
66
+
67
object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
68
qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
69
object_property_add_alias(obj, "num-irq",
70
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
71
const char *typename;
72
CPUClass *cc;
73
74
+ if (!s->board_memory) {
75
+ error_setg(errp, "memory property was not set");
76
+ return;
77
+ }
78
+
79
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
80
+
81
cpustr = g_strsplit(s->cpu_model, ",", 2);
82
83
oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
84
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
85
return;
86
}
87
88
+ object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
89
+ &error_abort);
90
object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
91
if (err != NULL) {
92
error_propagate(errp, err);
93
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
94
return;
95
}
26
}
96
27
97
- sysbus_mmio_map(sbd, 0, bitband_output_addr[i]);
28
qdev_connect_gpio_out(dev_splitter, 1,
98
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
99
+ sysbus_mmio_get_region(sbd, 0));
100
}
101
}
102
103
@@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
104
armv7m = qdev_create(NULL, "armv7m");
105
qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
106
qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
107
+ object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
108
+ "memory", &error_abort);
109
/* This will exit with an error if the user passed us a bad cpu_model */
110
qdev_init_nofail(armv7m);
111
112
--
29
--
113
2.7.4
30
2.20.1
114
31
115
32
diff view generated by jsdifflib
1
The local variable 'nvic' in stm32f205_soc_realize() no longer
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
holds a direct pointer to the NVIC device; it is a pointer to
3
the ARMv7M container object. Rename it 'armv7m' accordingly.
4
2
3
The system configuration controller (SYSCFG) doesn't have
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
Remove the invalid code.
6
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 1487604965-23220-12-git-send-email-peter.maydell@linaro.org
10
---
12
---
11
hw/arm/stm32f205_soc.c | 18 +++++++++---------
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
12
1 file changed, 9 insertions(+), 9 deletions(-)
14
hw/arm/stm32f205_soc.c | 1 -
15
hw/misc/stm32f2xx_syscfg.c | 2 --
16
3 files changed, 5 deletions(-)
13
17
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
23
uint32_t syscfg_exticr3;
24
uint32_t syscfg_exticr4;
25
uint32_t syscfg_cmpcr;
26
-
27
- qemu_irq irq;
28
};
29
30
#endif /* HW_STM32F2XX_SYSCFG_H */
14
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
15
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/stm32f205_soc.c
33
--- a/hw/arm/stm32f205_soc.c
17
+++ b/hw/arm/stm32f205_soc.c
34
+++ b/hw/arm/stm32f205_soc.c
18
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
19
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
20
{
21
STM32F205State *s = STM32F205_SOC(dev_soc);
22
- DeviceState *dev, *nvic;
23
+ DeviceState *dev, *armv7m;
24
SysBusDevice *busdev;
25
Error *err = NULL;
26
int i;
27
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
28
vmstate_register_ram_global(sram);
29
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
30
31
- nvic = DEVICE(&s->armv7m);
32
- qdev_prop_set_uint32(nvic, "num-irq", 96);
33
- qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
34
+ armv7m = DEVICE(&s->armv7m);
35
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
36
+ qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
37
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
38
"memory", &error_abort);
39
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
40
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
41
}
36
}
42
busdev = SYS_BUS_DEVICE(dev);
37
busdev = SYS_BUS_DEVICE(dev);
43
sysbus_mmio_map(busdev, 0, 0x40013800);
38
sysbus_mmio_map(busdev, 0, 0x40013800);
44
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, 71));
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
45
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
46
40
47
/* Attach UART (uses USART registers) and USART controllers */
41
/* Attach UART (uses USART registers) and USART controllers */
48
for (i = 0; i < STM_NUM_USARTS; i++) {
42
for (i = 0; i < STM_NUM_USARTS; i++) {
49
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
50
}
44
index XXXXXXX..XXXXXXX 100644
51
busdev = SYS_BUS_DEVICE(dev);
45
--- a/hw/misc/stm32f2xx_syscfg.c
52
sysbus_mmio_map(busdev, 0, usart_addr[i]);
46
+++ b/hw/misc/stm32f2xx_syscfg.c
53
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, usart_irq[i]));
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
54
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
48
{
55
}
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
56
50
57
/* Timer 2 to 5 */
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
58
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
52
-
59
}
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
60
busdev = SYS_BUS_DEVICE(dev);
54
TYPE_STM32F2XX_SYSCFG, 0x400);
61
sysbus_mmio_map(busdev, 0, timer_addr[i]);
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
62
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
63
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
64
}
65
66
/* ADC 1 to 3 */
67
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
68
return;
69
}
70
qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
71
- qdev_get_gpio_in(nvic, ADC_IRQ));
72
+ qdev_get_gpio_in(armv7m, ADC_IRQ));
73
74
for (i = 0; i < STM_NUM_ADCS; i++) {
75
dev = DEVICE(&(s->adc[i]));
76
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
77
}
78
busdev = SYS_BUS_DEVICE(dev);
79
sysbus_mmio_map(busdev, 0, spi_addr[i]);
80
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i]));
81
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
82
}
83
}
84
85
--
56
--
86
2.7.4
57
2.20.1
87
58
88
59
diff view generated by jsdifflib
1
Make the legacy armv7m_init() function use the newly QOMified
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
armv7m object rather than doing everything by hand.
3
2
4
We can return the armv7m object rather than the NVIC from
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
5
armv7m_init() because its interface to the rest of the
4
OMAP2 chip support") takes care of creating the 3 UARTs.
6
board (GPIOs, etc) is identical.
7
5
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487604965-23220-5-git-send-email-peter.maydell@linaro.org
12
---
21
---
13
hw/arm/armv7m.c | 49 ++++++++++++-------------------------------------
22
hw/arm/nseries.c | 11 -----------
14
1 file changed, 12 insertions(+), 37 deletions(-)
23
1 file changed, 11 deletions(-)
15
24
16
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
17
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/armv7m.c
27
--- a/hw/arm/nseries.c
19
+++ b/hw/arm/armv7m.c
28
+++ b/hw/arm/nseries.c
20
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
21
sysbus_init_mmio(dev, &s->iomem);
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
22
}
31
}
23
32
24
-static void armv7m_bitband_init(void)
33
-static void n8x0_uart_setup(struct n800_s *s)
25
-{
34
-{
26
- DeviceState *dev;
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
27
-
36
- /*
28
- dev = qdev_create(NULL, TYPE_BITBAND);
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
29
- qdev_prop_set_uint32(dev, "base", 0x20000000);
38
- * here, but this code has been removed with the bluetooth backend.
30
- qdev_init_nofail(dev);
39
- */
31
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x22000000);
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
32
-
33
- dev = qdev_create(NULL, TYPE_BITBAND);
34
- qdev_prop_set_uint32(dev, "base", 0x40000000);
35
- qdev_init_nofail(dev);
36
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x42000000);
37
-}
41
-}
38
-
42
-
39
/* Board init. */
43
static void n8x0_usb_setup(struct n800_s *s)
40
41
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
42
@@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque)
43
44
/* Init CPU and memory for a v7-M based board.
45
mem_size is in bytes.
46
- Returns the NVIC array. */
47
+ Returns the ARMv7M device. */
48
49
DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
50
const char *kernel_filename, const char *cpu_model)
51
{
44
{
52
- ARMCPU *cpu;
45
SysBusDevice *dev;
53
- CPUARMState *env;
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
54
- DeviceState *nvic;
47
n8x0_spi_setup(s);
55
+ DeviceState *armv7m;
48
n8x0_dss_setup(s);
56
49
n8x0_cbus_setup(s);
57
if (cpu_model == NULL) {
50
- n8x0_uart_setup(s);
58
-    cpu_model = "cortex-m3";
51
if (machine_usb(machine)) {
59
+ cpu_model = "cortex-m3";
52
n8x0_usb_setup(s);
60
}
53
}
61
- cpu = cpu_arm_init(cpu_model);
62
- if (cpu == NULL) {
63
- fprintf(stderr, "Unable to find CPU definition\n");
64
- exit(1);
65
- }
66
- env = &cpu->env;
67
-
68
- armv7m_bitband_init();
69
-
70
- nvic = qdev_create(NULL, "armv7m_nvic");
71
- qdev_prop_set_uint32(nvic, "num-irq", num_irq);
72
- env->nvic = nvic;
73
- qdev_init_nofail(nvic);
74
- sysbus_connect_irq(SYS_BUS_DEVICE(nvic), 0,
75
- qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
76
- armv7m_load_kernel(cpu, kernel_filename, mem_size);
77
- return nvic;
78
+
79
+ armv7m = qdev_create(NULL, "armv7m");
80
+ qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
81
+ qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
82
+ /* This will exit with an error if the user passed us a bad cpu_model */
83
+ qdev_init_nofail(armv7m);
84
+
85
+ armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
86
+ return armv7m;
87
}
88
89
void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
90
--
54
--
91
2.7.4
55
2.20.1
92
56
93
57
diff view generated by jsdifflib
Deleted patch
1
Instead of the bitband device doing a cpu_physical_memory_read/write,
2
make it take a MemoryRegion which specifies where it should be
3
accessing, and use address_space_read/write to access the
4
corresponding AddressSpace.
5
1
6
Since this entails pretty much a rewrite, convert away from
7
old_mmio in the process.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487604965-23220-8-git-send-email-peter.maydell@linaro.org
12
---
13
include/hw/arm/armv7m.h | 2 +
14
hw/arm/armv7m.c | 166 +++++++++++++++++++++++-------------------------
15
2 files changed, 81 insertions(+), 87 deletions(-)
16
17
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/armv7m.h
20
+++ b/include/hw/arm/armv7m.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct {
22
SysBusDevice parent_obj;
23
/*< public >*/
24
25
+ AddressSpace *source_as;
26
MemoryRegion iomem;
27
uint32_t base;
28
+ MemoryRegion *source_memory;
29
} BitBandState;
30
31
#define TYPE_ARMV7M "armv7m"
32
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/armv7m.c
35
+++ b/hw/arm/armv7m.c
36
@@ -XXX,XX +XXX,XX @@
37
/* Bitbanded IO. Each word corresponds to a single bit. */
38
39
/* Get the byte address of the real memory for a bitband access. */
40
-static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
41
+static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
42
{
43
- uint32_t res;
44
-
45
- res = *(uint32_t *)opaque;
46
- res |= (addr & 0x1ffffff) >> 5;
47
- return res;
48
-
49
-}
50
-
51
-static uint32_t bitband_readb(void *opaque, hwaddr offset)
52
-{
53
- uint8_t v;
54
- cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
55
- return (v & (1 << ((offset >> 2) & 7))) != 0;
56
-}
57
-
58
-static void bitband_writeb(void *opaque, hwaddr offset,
59
- uint32_t value)
60
-{
61
- uint32_t addr;
62
- uint8_t mask;
63
- uint8_t v;
64
- addr = bitband_addr(opaque, offset);
65
- mask = (1 << ((offset >> 2) & 7));
66
- cpu_physical_memory_read(addr, &v, 1);
67
- if (value & 1)
68
- v |= mask;
69
- else
70
- v &= ~mask;
71
- cpu_physical_memory_write(addr, &v, 1);
72
-}
73
-
74
-static uint32_t bitband_readw(void *opaque, hwaddr offset)
75
-{
76
- uint32_t addr;
77
- uint16_t mask;
78
- uint16_t v;
79
- addr = bitband_addr(opaque, offset) & ~1;
80
- mask = (1 << ((offset >> 2) & 15));
81
- mask = tswap16(mask);
82
- cpu_physical_memory_read(addr, &v, 2);
83
- return (v & mask) != 0;
84
-}
85
-
86
-static void bitband_writew(void *opaque, hwaddr offset,
87
- uint32_t value)
88
-{
89
- uint32_t addr;
90
- uint16_t mask;
91
- uint16_t v;
92
- addr = bitband_addr(opaque, offset) & ~1;
93
- mask = (1 << ((offset >> 2) & 15));
94
- mask = tswap16(mask);
95
- cpu_physical_memory_read(addr, &v, 2);
96
- if (value & 1)
97
- v |= mask;
98
- else
99
- v &= ~mask;
100
- cpu_physical_memory_write(addr, &v, 2);
101
+ return s->base | (offset & 0x1ffffff) >> 5;
102
}
103
104
-static uint32_t bitband_readl(void *opaque, hwaddr offset)
105
+static MemTxResult bitband_read(void *opaque, hwaddr offset,
106
+ uint64_t *data, unsigned size, MemTxAttrs attrs)
107
{
108
- uint32_t addr;
109
- uint32_t mask;
110
- uint32_t v;
111
- addr = bitband_addr(opaque, offset) & ~3;
112
- mask = (1 << ((offset >> 2) & 31));
113
- mask = tswap32(mask);
114
- cpu_physical_memory_read(addr, &v, 4);
115
- return (v & mask) != 0;
116
+ BitBandState *s = opaque;
117
+ uint8_t buf[4];
118
+ MemTxResult res;
119
+ int bitpos, bit;
120
+ hwaddr addr;
121
+
122
+ assert(size <= 4);
123
+
124
+ /* Find address in underlying memory and round down to multiple of size */
125
+ addr = bitband_addr(s, offset) & (-size);
126
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
127
+ if (res) {
128
+ return res;
129
+ }
130
+ /* Bit position in the N bytes read... */
131
+ bitpos = (offset >> 2) & ((size * 8) - 1);
132
+ /* ...converted to byte in buffer and bit in byte */
133
+ bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
134
+ *data = bit;
135
+ return MEMTX_OK;
136
}
137
138
-static void bitband_writel(void *opaque, hwaddr offset,
139
- uint32_t value)
140
+static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
141
+ unsigned size, MemTxAttrs attrs)
142
{
143
- uint32_t addr;
144
- uint32_t mask;
145
- uint32_t v;
146
- addr = bitband_addr(opaque, offset) & ~3;
147
- mask = (1 << ((offset >> 2) & 31));
148
- mask = tswap32(mask);
149
- cpu_physical_memory_read(addr, &v, 4);
150
- if (value & 1)
151
- v |= mask;
152
- else
153
- v &= ~mask;
154
- cpu_physical_memory_write(addr, &v, 4);
155
+ BitBandState *s = opaque;
156
+ uint8_t buf[4];
157
+ MemTxResult res;
158
+ int bitpos, bit;
159
+ hwaddr addr;
160
+
161
+ assert(size <= 4);
162
+
163
+ /* Find address in underlying memory and round down to multiple of size */
164
+ addr = bitband_addr(s, offset) & (-size);
165
+ res = address_space_read(s->source_as, addr, attrs, buf, size);
166
+ if (res) {
167
+ return res;
168
+ }
169
+ /* Bit position in the N bytes read... */
170
+ bitpos = (offset >> 2) & ((size * 8) - 1);
171
+ /* ...converted to byte in buffer and bit in byte */
172
+ bit = 1 << (bitpos & 7);
173
+ if (value & 1) {
174
+ buf[bitpos >> 3] |= bit;
175
+ } else {
176
+ buf[bitpos >> 3] &= ~bit;
177
+ }
178
+ return address_space_write(s->source_as, addr, attrs, buf, size);
179
}
180
181
static const MemoryRegionOps bitband_ops = {
182
- .old_mmio = {
183
- .read = { bitband_readb, bitband_readw, bitband_readl, },
184
- .write = { bitband_writeb, bitband_writew, bitband_writel, },
185
- },
186
+ .read_with_attrs = bitband_read,
187
+ .write_with_attrs = bitband_write,
188
.endianness = DEVICE_NATIVE_ENDIAN,
189
+ .impl.min_access_size = 1,
190
+ .impl.max_access_size = 4,
191
+ .valid.min_access_size = 1,
192
+ .valid.max_access_size = 4,
193
};
194
195
static void bitband_init(Object *obj)
196
@@ -XXX,XX +XXX,XX @@ static void bitband_init(Object *obj)
197
BitBandState *s = BITBAND(obj);
198
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
199
200
- memory_region_init_io(&s->iomem, obj, &bitband_ops, &s->base,
201
+ object_property_add_link(obj, "source-memory",
202
+ TYPE_MEMORY_REGION,
203
+ (Object **)&s->source_memory,
204
+ qdev_prop_allow_set_link_before_realize,
205
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
206
+ &error_abort);
207
+ memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
208
"bitband", 0x02000000);
209
sysbus_init_mmio(dev, &s->iomem);
210
}
211
212
+static void bitband_realize(DeviceState *dev, Error **errp)
213
+{
214
+ BitBandState *s = BITBAND(dev);
215
+
216
+ if (!s->source_memory) {
217
+ error_setg(errp, "source-memory property not set");
218
+ return;
219
+ }
220
+
221
+ s->source_as = address_space_init_shareable(s->source_memory,
222
+ "bitband-source");
223
+}
224
+
225
/* Board init. */
226
227
static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
228
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
229
error_propagate(errp, err);
230
return;
231
}
232
+ object_property_set_link(obj, OBJECT(s->board_memory),
233
+ "source-memory", &error_abort);
234
object_property_set_bool(obj, true, "realized", &err);
235
if (err != NULL) {
236
error_propagate(errp, err);
237
@@ -XXX,XX +XXX,XX @@ static void bitband_class_init(ObjectClass *klass, void *data)
238
{
239
DeviceClass *dc = DEVICE_CLASS(klass);
240
241
+ dc->realize = bitband_realize;
242
dc->props = bitband_properties;
243
}
244
245
--
246
2.7.4
247
248
diff view generated by jsdifflib
Deleted patch
1
The NVIC is a core v7M device that exists for all v7M CPUs;
2
put it under a CONFIG_ARM_V7M rather than hiding it under
3
CONFIG_STELLARIS.
4
1
5
(We'll use CONFIG_ARM_V7M for the SysTick device too
6
when we split it out of the NVIC.)
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
12
---
13
hw/intc/Makefile.objs | 2 +-
14
default-configs/arm-softmmu.mak | 2 ++
15
2 files changed, 3 insertions(+), 1 deletion(-)
16
17
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/Makefile.objs
20
+++ b/hw/intc/Makefile.objs
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_APIC) += apic.o apic_common.o
22
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
23
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_kvm.o
24
obj-$(call land,$(CONFIG_ARM_GIC_KVM),$(TARGET_AARCH64)) += arm_gicv3_its_kvm.o
25
-obj-$(CONFIG_STELLARIS) += armv7m_nvic.o
26
+obj-$(CONFIG_ARM_V7M) += armv7m_nvic.o
27
obj-$(CONFIG_EXYNOS4) += exynos4210_gic.o exynos4210_combiner.o
28
obj-$(CONFIG_GRLIB) += grlib_irqmp.o
29
obj-$(CONFIG_IOAPIC) += ioapic.o
30
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
31
index XXXXXXX..XXXXXXX 100644
32
--- a/default-configs/arm-softmmu.mak
33
+++ b/default-configs/arm-softmmu.mak
34
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM11MPCORE=y
35
CONFIG_A9MPCORE=y
36
CONFIG_A15MPCORE=y
37
38
+CONFIG_ARM_V7M=y
39
+
40
CONFIG_ARM_GIC=y
41
CONFIG_ARM_GIC_KVM=$(CONFIG_KVM)
42
CONFIG_ARM_TIMER=y
43
--
44
2.7.4
45
46
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Add gicv3state void pointer to CPUARMState struct
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
to store GICv3CPUState.
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
5
9
6
In case of usecase like CPU reset, we need to reset
10
This kind of wiring needs an explicitly created OR gate; add one.
7
GICv3CPUState of the CPU. In such scenario, this pointer
8
becomes handy.
9
11
10
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 1487850673-26455-5-git-send-email-vijay.kilari@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
17
---
16
hw/intc/gicv3_internal.h | 2 ++
18
hw/arm/musicpal.c | 17 +++++++++++++----
17
target/arm/cpu.h | 2 ++
19
hw/arm/Kconfig | 1 +
18
hw/intc/arm_gicv3_common.c | 2 ++
20
2 files changed, 14 insertions(+), 4 deletions(-)
19
hw/intc/arm_gicv3_cpuif.c | 8 ++++++++
20
4 files changed, 14 insertions(+)
21
21
22
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
23
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/gicv3_internal.h
24
--- a/hw/arm/musicpal.c
25
+++ b/hw/intc/gicv3_internal.h
25
+++ b/hw/arm/musicpal.c
26
@@ -XXX,XX +XXX,XX @@ static inline void gicv3_cache_all_target_cpustates(GICv3State *s)
26
@@ -XXX,XX +XXX,XX @@
27
}
27
#include "ui/console.h"
28
}
28
#include "hw/i2c/i2c.h"
29
29
#include "hw/irq.h"
30
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s);
30
+#include "hw/or-irq.h"
31
#include "hw/audio/wm8750.h"
32
#include "sysemu/block-backend.h"
33
#include "sysemu/runstate.h"
34
@@ -XXX,XX +XXX,XX @@
35
#define MP_TIMER4_IRQ 7
36
#define MP_EHCI_IRQ 8
37
#define MP_ETH_IRQ 9
38
-#define MP_UART1_IRQ 11
39
-#define MP_UART2_IRQ 11
40
+#define MP_UART_SHARED_IRQ 11
41
#define MP_GPIO_IRQ 12
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
31
+
62
+
32
#endif /* QEMU_ARM_GICV3_INTERNAL_H */
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
64
+ qdev_get_gpio_in(uart_orgate, 0),
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
68
+ qdev_get_gpio_in(uart_orgate, 1),
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
70
71
/* Register flash */
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
34
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
74
--- a/hw/arm/Kconfig
36
+++ b/target/arm/cpu.h
75
+++ b/hw/arm/Kconfig
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
38
77
39
void *nvic;
78
config MUSICPAL
40
const struct arm_boot_info *boot_info;
79
bool
41
+ /* Store GICv3CPUState to access from this struct */
80
+ select OR_IRQ
42
+ void *gicv3state;
81
select BITBANG_I2C
43
} CPUARMState;
82
select MARVELL_88W8618
44
83
select PTIMER
45
/**
46
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_common.c
49
+++ b/hw/intc/arm_gicv3_common.c
50
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
51
52
s->cpu[i].cpu = cpu;
53
s->cpu[i].gic = s;
54
+ /* Store GICv3CPUState in CPUARMState gicv3state pointer */
55
+ gicv3_set_gicv3state(cpu, &s->cpu[i]);
56
57
/* Pre-construct the GICR_TYPER:
58
* For our implementation:
59
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/intc/arm_gicv3_cpuif.c
62
+++ b/hw/intc/arm_gicv3_cpuif.c
63
@@ -XXX,XX +XXX,XX @@
64
#include "gicv3_internal.h"
65
#include "cpu.h"
66
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
68
+{
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
70
+ CPUARMState *env = &arm_cpu->env;
71
+
72
+ env->gicv3state = (void *)s;
73
+};
74
+
75
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
76
{
77
/* Given the CPU, find the right GICv3CPUState struct.
78
--
84
--
79
2.7.4
85
2.20.1
80
86
81
87
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The linux-headers/asm-arm/unistd.h file has been split in three
3
We don't need to fill the full pic[] array if we only use
4
sub-files, copy them along. However, building them requires
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
setting ARCH rather than SRCARCH.
5
when necessary.
6
6
7
SRCARCH defaults to $(ARCH) anyway; to avoid future occurrence of
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
the same problem use ARCH for all architectures where SRCARCH=ARCH.
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
9
Currently these are all except x86, sparc, sh and tile.
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
11
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12
Message-id: 20170221122920.16245-2-pbonzini@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
scripts/update-linux-headers.sh | 13 ++++++++++++-
12
hw/arm/musicpal.c | 25 +++++++++++++------------
16
1 file changed, 12 insertions(+), 1 deletion(-)
13
1 file changed, 13 insertions(+), 12 deletions(-)
17
14
18
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
19
index XXXXXXX..XXXXXXX 100755
16
index XXXXXXX..XXXXXXX 100644
20
--- a/scripts/update-linux-headers.sh
17
--- a/hw/arm/musicpal.c
21
+++ b/scripts/update-linux-headers.sh
18
+++ b/hw/arm/musicpal.c
22
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
23
continue
20
static void musicpal_init(MachineState *machine)
24
fi
21
{
25
22
ARMCPU *cpu;
26
- make -C "$linux" INSTALL_HDR_PATH="$tmpdir" SRCARCH=$arch headers_install
23
- qemu_irq pic[32];
27
+ if [ "$arch" = x86 ]; then
24
DeviceState *dev;
28
+ arch_var=SRCARCH
25
+ DeviceState *pic;
29
+ else
26
DeviceState *uart_orgate;
30
+ arch_var=ARCH
27
DeviceState *i2c_dev;
31
+ fi
28
DeviceState *lcd_dev;
32
+
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
33
+ make -C "$linux" INSTALL_HDR_PATH="$tmpdir" $arch_var=$arch headers_install
30
&error_fatal);
34
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
35
rm -rf "$output/linux-headers/asm-$arch"
32
36
mkdir -p "$output/linux-headers/asm-$arch"
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
37
@@ -XXX,XX +XXX,XX @@ for arch in $ARCHLIST; do
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
38
cp_portable "$tmpdir/include/asm/kvm_virtio.h" "$output/include/standard-headers/asm-s390/"
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
39
cp_portable "$tmpdir/include/asm/virtio-ccw.h" "$output/include/standard-headers/asm-s390/"
36
- for (i = 0; i < 32; i++) {
40
fi
37
- pic[i] = qdev_get_gpio_in(dev, i);
41
+ if [ $arch = arm ]; then
38
- }
42
+ cp "$tmpdir/include/asm/unistd-eabi.h" "$output/linux-headers/asm-arm/"
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
43
+ cp "$tmpdir/include/asm/unistd-oabi.h" "$output/linux-headers/asm-arm/"
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
44
+ cp "$tmpdir/include/asm/unistd-common.h" "$output/linux-headers/asm-arm/"
41
- pic[MP_TIMER4_IRQ], NULL);
45
+ fi
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
46
if [ $arch = x86 ]; then
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
47
cp_portable "$tmpdir/include/asm/hyperv.h" "$output/include/standard-headers/asm-x86/"
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
48
cp "$tmpdir/include/asm/unistd_32.h" "$output/linux-headers/asm-x86/"
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
47
48
/* Logically OR both UART IRQs together */
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
55
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
57
qdev_get_gpio_in(uart_orgate, 0),
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
59
OBJECT(get_system_memory()), &error_fatal);
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
65
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
67
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
69
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
71
- pic[MP_GPIO_IRQ]);
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
75
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
77
NULL);
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
49
--
85
--
50
2.7.4
86
2.20.1
51
87
52
88
diff view generated by jsdifflib
1
Switch the stm32f205 SoC to create the armv7m object directly
1
The nseries machines have a codepath that allows them to load a
2
rather than via the armv7m_init() wrapper. This fits better
2
secondary bootloader. This code wasn't checking that the
3
with the SoC model's very QOMified design.
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
4
5
5
In particular this means we can push loading the guest image
6
While we're in the vicinity, fix the comment style of the
6
out to the top level board code where it belongs, rather
7
comment documenting what this image load is doing.
7
than the SoC object having a QOM property for the filename
8
to load.
9
8
9
Fixes: Coverity CID 1192904
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 1487604965-23220-11-git-send-email-peter.maydell@linaro.org
15
---
13
---
16
include/hw/arm/stm32f205_soc.h | 4 +++-
14
hw/arm/nseries.c | 15 +++++++++++----
17
hw/arm/netduino2.c | 7 ++++---
15
1 file changed, 11 insertions(+), 4 deletions(-)
18
hw/arm/stm32f205_soc.c | 16 +++++++++++++---
19
3 files changed, 20 insertions(+), 7 deletions(-)
20
16
21
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/stm32f205_soc.h
19
--- a/hw/arm/nseries.c
24
+++ b/include/hw/arm/stm32f205_soc.h
20
+++ b/hw/arm/nseries.c
25
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
26
#include "hw/adc/stm32f2xx_adc.h"
22
/* No, wait, better start at the ROM. */
27
#include "hw/or-irq.h"
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
28
#include "hw/ssi/stm32f2xx_spi.h"
24
29
+#include "hw/arm/armv7m.h"
25
- /* This is intended for loading the `secondary.bin' program from
30
26
+ /*
31
#define TYPE_STM32F205_SOC "stm32f205-soc"
27
+ * This is intended for loading the `secondary.bin' program from
32
#define STM32F205_SOC(obj) \
28
* Nokia images (the NOLO bootloader). The entry point seems
33
@@ -XXX,XX +XXX,XX @@ typedef struct STM32F205State {
29
* to be at OMAP2_Q2_BASE + 0x400000.
34
SysBusDevice parent_obj;
30
*
35
/*< public >*/
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
36
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
37
- char *kernel_filename;
33
*
38
char *cpu_model;
34
* The code above is for loading the `zImage' file from Nokia
39
35
- * images. */
40
+ ARMv7MState armv7m;
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
41
+
37
- machine->ram_size - 0x400000);
42
STM32F2XXSyscfgState syscfg;
38
+ * images.
43
STM32F2XXUsartState usart[STM_NUM_USARTS];
39
+ */
44
STM32F2XXTimerState timer[STM_NUM_TIMERS];
40
+ if (load_image_targphys(option_rom[0].name,
45
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
41
+ OMAP2_Q2_BASE + 0x400000,
46
index XXXXXXX..XXXXXXX 100644
42
+ machine->ram_size - 0x400000) < 0) {
47
--- a/hw/arm/netduino2.c
43
+ error_report("Failed to load secondary bootloader %s",
48
+++ b/hw/arm/netduino2.c
44
+ option_rom[0].name);
49
@@ -XXX,XX +XXX,XX @@
45
+ exit(EXIT_FAILURE);
50
#include "hw/boards.h"
46
+ }
51
#include "qemu/error-report.h"
47
52
#include "hw/arm/stm32f205_soc.h"
48
n800_setup_nolo_tags(nolo_tags);
53
+#include "hw/arm/arm.h"
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
54
55
static void netduino2_init(MachineState *machine)
56
{
57
DeviceState *dev;
58
59
dev = qdev_create(NULL, TYPE_STM32F205_SOC);
60
- if (machine->kernel_filename) {
61
- qdev_prop_set_string(dev, "kernel-filename", machine->kernel_filename);
62
- }
63
qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
64
object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
65
+
66
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
67
+ FLASH_SIZE);
68
}
69
70
static void netduino2_machine_init(MachineClass *mc)
71
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/arm/stm32f205_soc.c
74
+++ b/hw/arm/stm32f205_soc.c
75
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_initfn(Object *obj)
76
STM32F205State *s = STM32F205_SOC(obj);
77
int i;
78
79
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
80
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
81
+
82
object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
83
qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
84
85
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
86
vmstate_register_ram_global(sram);
87
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
88
89
- nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
90
- s->kernel_filename, s->cpu_model);
91
+ nvic = DEVICE(&s->armv7m);
92
+ qdev_prop_set_uint32(nvic, "num-irq", 96);
93
+ qdev_prop_set_string(nvic, "cpu-model", s->cpu_model);
94
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
95
+ "memory", &error_abort);
96
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
97
+ if (err != NULL) {
98
+ error_propagate(errp, err);
99
+ return;
100
+ }
101
102
/* System configuration controller */
103
dev = DEVICE(&s->syscfg);
104
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
105
}
106
107
static Property stm32f205_soc_properties[] = {
108
- DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
109
DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
110
DEFINE_PROP_END_OF_LIST(),
111
};
112
--
50
--
113
2.7.4
51
2.20.1
114
52
115
53
diff view generated by jsdifflib
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
To Save and Restore ICC_SRE_EL1 register introduce vmstate
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
4
subsection and load only if non-zero.
4
plus one. Currently, it's counting the number of times these transitions
5
Also initialize icc_sre_el1 with to 0x7 in pre_load
5
do _not_ happen, plus one.
6
function.
7
6
8
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
7
Source:
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1487850673-26455-3-git-send-email-vijay.kilari@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
15
---
14
include/hw/intc/arm_gicv3_common.h | 1 +
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
15
hw/intc/arm_gicv3_common.c | 36 ++++++++++++++++++++++++++++++++++++
17
1 file changed, 1 insertion(+), 1 deletion(-)
16
2 files changed, 37 insertions(+)
17
18
18
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/arm_gicv3_common.h
21
--- a/tests/qtest/npcm7xx_rng-test.c
21
+++ b/include/hw/intc/arm_gicv3_common.h
22
+++ b/tests/qtest/npcm7xx_rng-test.c
22
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
23
uint8_t gicr_ipriorityr[GIC_INTERNAL];
24
pi = (double)nr_ones / nr_bits;
24
25
25
/* CPU interface */
26
for (k = 0; k < nr_bits - 1; k++) {
26
+ uint64_t icc_sre_el1;
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
27
uint64_t icc_ctlr_el1[2];
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
28
uint64_t icc_pmr_el1;
29
uint64_t icc_bpr[3];
30
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_common.c
33
+++ b/hw/intc/arm_gicv3_common.c
34
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu_virt = {
35
}
29
}
36
};
30
vn_obs += 1;
37
38
+static int icc_sre_el1_reg_pre_load(void *opaque)
39
+{
40
+ GICv3CPUState *cs = opaque;
41
+
42
+ /*
43
+ * If the sre_el1 subsection is not transferred this
44
+ * means SRE_EL1 is 0x7 (which might not be the same as
45
+ * our reset value).
46
+ */
47
+ cs->icc_sre_el1 = 0x7;
48
+ return 0;
49
+}
50
+
51
+static bool icc_sre_el1_reg_needed(void *opaque)
52
+{
53
+ GICv3CPUState *cs = opaque;
54
+
55
+ return cs->icc_sre_el1 != 7;
56
+}
57
+
58
+const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
59
+ .name = "arm_gicv3_cpu/sre_el1",
60
+ .version_id = 1,
61
+ .minimum_version_id = 1,
62
+ .pre_load = icc_sre_el1_reg_pre_load,
63
+ .needed = icc_sre_el1_reg_needed,
64
+ .fields = (VMStateField[]) {
65
+ VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
66
+ VMSTATE_END_OF_LIST()
67
+ }
68
+};
69
+
70
static const VMStateDescription vmstate_gicv3_cpu = {
71
.name = "arm_gicv3_cpu",
72
.version_id = 1,
73
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
74
.subsections = (const VMStateDescription * []) {
75
&vmstate_gicv3_cpu_virt,
76
NULL
77
+ },
78
+ .subsections = (const VMStateDescription * []) {
79
+ &vmstate_gicv3_cpu_sre_el1,
80
+ NULL
81
}
82
};
83
31
84
--
32
--
85
2.7.4
33
2.20.1
86
34
87
35
diff view generated by jsdifflib
1
The SysTick timer isn't really part of the NVIC proper;
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
2
we just modelled it that way back when we couldn't
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
easily have devices that only occupied a small chunk
3
trans function up above the access check.
4
of a memory region. Split it out into its own device.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1487604965-23220-10-git-send-email-peter.maydell@linaro.org
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
9
---
8
---
10
hw/timer/Makefile.objs | 1 +
9
target/arm/translate-neon.c.inc | 8 ++++----
11
include/hw/arm/armv7m_nvic.h | 10 +-
10
1 file changed, 4 insertions(+), 4 deletions(-)
12
include/hw/timer/armv7m_systick.h | 34 ++++++
13
hw/intc/armv7m_nvic.c | 160 ++++++-------------------
14
hw/timer/armv7m_systick.c | 240 ++++++++++++++++++++++++++++++++++++++
15
hw/timer/trace-events | 6 +
16
6 files changed, 318 insertions(+), 133 deletions(-)
17
create mode 100644 include/hw/timer/armv7m_systick.h
18
create mode 100644 hw/timer/armv7m_systick.c
19
11
20
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/Makefile.objs
14
--- a/target/arm/translate-neon.c.inc
23
+++ b/hw/timer/Makefile.objs
15
+++ b/target/arm/translate-neon.c.inc
24
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
25
common-obj-$(CONFIG_ARM_TIMER) += arm_timer.o
17
return false;
26
common-obj-$(CONFIG_ARM_MPTIMER) += arm_mptimer.o
18
}
27
+common-obj-$(CONFIG_ARM_V7M) += armv7m_systick.o
19
28
common-obj-$(CONFIG_A9_GTIMER) += a9gtimer.o
20
- if (!vfp_access_check(s)) {
29
common-obj-$(CONFIG_CADENCE) += cadence_ttc.o
21
- return true;
30
common-obj-$(CONFIG_DS1338) += ds1338.o
31
diff --git a/include/hw/arm/armv7m_nvic.h b/include/hw/arm/armv7m_nvic.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armv7m_nvic.h
34
+++ b/include/hw/arm/armv7m_nvic.h
35
@@ -XXX,XX +XXX,XX @@
36
37
#include "target/arm/cpu.h"
38
#include "hw/sysbus.h"
39
+#include "hw/timer/armv7m_systick.h"
40
41
#define TYPE_NVIC "armv7m_nvic"
42
43
@@ -XXX,XX +XXX,XX @@ typedef struct NVICState {
44
unsigned int vectpending; /* highest prio pending enabled exception */
45
int exception_prio; /* group prio of the highest prio active exception */
46
47
- struct {
48
- uint32_t control;
49
- uint32_t reload;
50
- int64_t tick;
51
- QEMUTimer *timer;
52
- } systick;
53
-
54
MemoryRegion sysregmem;
55
MemoryRegion container;
56
57
uint32_t num_irq;
58
qemu_irq excpout;
59
qemu_irq sysresetreq;
60
+
61
+ SysTickState systick;
62
} NVICState;
63
64
#endif
65
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
66
new file mode 100644
67
index XXXXXXX..XXXXXXX
68
--- /dev/null
69
+++ b/include/hw/timer/armv7m_systick.h
70
@@ -XXX,XX +XXX,XX @@
71
+/*
72
+ * ARMv7M SysTick timer
73
+ *
74
+ * Copyright (c) 2006-2007 CodeSourcery.
75
+ * Written by Paul Brook
76
+ * Copyright (c) 2017 Linaro Ltd
77
+ * Written by Peter Maydell
78
+ *
79
+ * This code is licensed under the GPL (version 2 or later).
80
+ */
81
+
82
+#ifndef HW_TIMER_ARMV7M_SYSTICK_H
83
+#define HW_TIMER_ARMV7M_SYSTICK_H
84
+
85
+#include "hw/sysbus.h"
86
+
87
+#define TYPE_SYSTICK "armv7m_systick"
88
+
89
+#define SYSTICK(obj) OBJECT_CHECK(SysTickState, (obj), TYPE_SYSTICK)
90
+
91
+typedef struct SysTickState {
92
+ /*< private >*/
93
+ SysBusDevice parent_obj;
94
+ /*< public >*/
95
+
96
+ uint32_t control;
97
+ uint32_t reload;
98
+ int64_t tick;
99
+ QEMUTimer *timer;
100
+ MemoryRegion iomem;
101
+ qemu_irq irq;
102
+} SysTickState;
103
+
104
+#endif
105
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/intc/armv7m_nvic.c
108
+++ b/hw/intc/armv7m_nvic.c
109
@@ -XXX,XX +XXX,XX @@ static const uint8_t nvic_id[] = {
110
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
111
};
112
113
-/* qemu timers run at 1GHz. We want something closer to 1MHz. */
114
-#define SYSTICK_SCALE 1000ULL
115
-
116
-#define SYSTICK_ENABLE (1 << 0)
117
-#define SYSTICK_TICKINT (1 << 1)
118
-#define SYSTICK_CLKSOURCE (1 << 2)
119
-#define SYSTICK_COUNTFLAG (1 << 16)
120
-
121
-int system_clock_scale;
122
-
123
-/* Conversion factor from qemu timer to SysTick frequencies. */
124
-static inline int64_t systick_scale(NVICState *s)
125
-{
126
- if (s->systick.control & SYSTICK_CLKSOURCE)
127
- return system_clock_scale;
128
- else
129
- return 1000;
130
-}
131
-
132
-static void systick_reload(NVICState *s, int reset)
133
-{
134
- /* The Cortex-M3 Devices Generic User Guide says that "When the
135
- * ENABLE bit is set to 1, the counter loads the RELOAD value from the
136
- * SYST RVR register and then counts down". So, we need to check the
137
- * ENABLE bit before reloading the value.
138
- */
139
- if ((s->systick.control & SYSTICK_ENABLE) == 0) {
140
- return;
141
- }
22
- }
142
-
23
-
143
- if (reset)
24
if ((a->vn + a->len + 1) > 32) {
144
- s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
25
/*
145
- s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
146
- timer_mod(s->systick.timer, s->systick.tick);
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
147
-}
28
return false;
148
-
149
-static void systick_timer_tick(void * opaque)
150
-{
151
- NVICState *s = (NVICState *)opaque;
152
- s->systick.control |= SYSTICK_COUNTFLAG;
153
- if (s->systick.control & SYSTICK_TICKINT) {
154
- /* Trigger the interrupt. */
155
- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
156
- }
157
- if (s->systick.reload == 0) {
158
- s->systick.control &= ~SYSTICK_ENABLE;
159
- } else {
160
- systick_reload(s, 0);
161
- }
162
-}
163
-
164
-static void systick_reset(NVICState *s)
165
-{
166
- s->systick.control = 0;
167
- s->systick.reload = 0;
168
- s->systick.tick = 0;
169
- timer_del(s->systick.timer);
170
-}
171
-
172
static int nvic_pending_prio(NVICState *s)
173
{
174
/* return the priority of the current pending interrupt,
175
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
176
switch (offset) {
177
case 4: /* Interrupt Control Type. */
178
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
179
- case 0x10: /* SysTick Control and Status. */
180
- val = s->systick.control;
181
- s->systick.control &= ~SYSTICK_COUNTFLAG;
182
- return val;
183
- case 0x14: /* SysTick Reload Value. */
184
- return s->systick.reload;
185
- case 0x18: /* SysTick Current Value. */
186
- {
187
- int64_t t;
188
- if ((s->systick.control & SYSTICK_ENABLE) == 0)
189
- return 0;
190
- t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
191
- if (t >= s->systick.tick)
192
- return 0;
193
- val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
194
- /* The interrupt in triggered when the timer reaches zero.
195
- However the counter is not reloaded until the next clock
196
- tick. This is a hack to return zero during the first tick. */
197
- if (val > s->systick.reload)
198
- val = 0;
199
- return val;
200
- }
201
- case 0x1c: /* SysTick Calibration Value. */
202
- return 10000;
203
case 0xd00: /* CPUID Base. */
204
return cpu->midr;
205
case 0xd04: /* Interrupt Control State. */
206
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset)
207
static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
208
{
209
ARMCPU *cpu = s->cpu;
210
- uint32_t oldval;
211
+
212
switch (offset) {
213
- case 0x10: /* SysTick Control and Status. */
214
- oldval = s->systick.control;
215
- s->systick.control &= 0xfffffff8;
216
- s->systick.control |= value & 7;
217
- if ((oldval ^ value) & SYSTICK_ENABLE) {
218
- int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
219
- if (value & SYSTICK_ENABLE) {
220
- if (s->systick.tick) {
221
- s->systick.tick += now;
222
- timer_mod(s->systick.timer, s->systick.tick);
223
- } else {
224
- systick_reload(s, 1);
225
- }
226
- } else {
227
- timer_del(s->systick.timer);
228
- s->systick.tick -= now;
229
- if (s->systick.tick < 0)
230
- s->systick.tick = 0;
231
- }
232
- } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
233
- /* This is a hack. Force the timer to be reloaded
234
- when the reference clock is changed. */
235
- systick_reload(s, 1);
236
- }
237
- break;
238
- case 0x14: /* SysTick Reload Value. */
239
- s->systick.reload = value;
240
- break;
241
- case 0x18: /* SysTick Current Value. Writes reload the timer. */
242
- systick_reload(s, 1);
243
- s->systick.control &= ~SYSTICK_COUNTFLAG;
244
- break;
245
case 0xd04: /* Interrupt Control State. */
246
if (value & (1 << 31)) {
247
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
248
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_VecInfo = {
249
250
static const VMStateDescription vmstate_nvic = {
251
.name = "armv7m_nvic",
252
- .version_id = 3,
253
- .minimum_version_id = 3,
254
+ .version_id = 4,
255
+ .minimum_version_id = 4,
256
.post_load = &nvic_post_load,
257
.fields = (VMStateField[]) {
258
VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
259
vmstate_VecInfo, VecInfo),
260
- VMSTATE_UINT32(systick.control, NVICState),
261
- VMSTATE_UINT32(systick.reload, NVICState),
262
- VMSTATE_INT64(systick.tick, NVICState),
263
- VMSTATE_TIMER_PTR(systick.timer, NVICState),
264
VMSTATE_UINT32(prigroup, NVICState),
265
VMSTATE_END_OF_LIST()
266
}
29
}
267
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
30
268
31
+ if (!vfp_access_check(s)) {
269
s->exception_prio = NVIC_NOEXC_PRIO;
32
+ return true;
270
s->vectpending = 0;
271
+}
272
273
- systick_reset(s);
274
+static void nvic_systick_trigger(void *opaque, int n, int level)
275
+{
276
+ NVICState *s = opaque;
277
+
278
+ if (level) {
279
+ /* SysTick just asked us to pend its exception.
280
+ * (This is different from an external interrupt line's
281
+ * behaviour.)
282
+ */
283
+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
284
+ }
285
}
286
287
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
288
{
289
NVICState *s = NVIC(dev);
290
+ SysBusDevice *systick_sbd;
291
+ Error *err = NULL;
292
293
s->cpu = ARM_CPU(qemu_get_cpu(0));
294
assert(s->cpu);
295
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
296
/* include space for internal exception vectors */
297
s->num_irq += NVIC_FIRST_IRQ;
298
299
+ object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
300
+ if (err != NULL) {
301
+ error_propagate(errp, err);
302
+ return;
303
+ }
304
+ systick_sbd = SYS_BUS_DEVICE(&s->systick);
305
+ sysbus_connect_irq(systick_sbd, 0,
306
+ qdev_get_gpio_in_named(dev, "systick-trigger", 0));
307
+
308
/* The NVIC and System Control Space (SCS) starts at 0xe000e000
309
* and looks like this:
310
* 0x004 - ICTR
311
- * 0x010 - 0x1c - systick
312
+ * 0x010 - 0xff - systick
313
* 0x100..0x7ec - NVIC
314
* 0x7f0..0xcff - Reserved
315
* 0xd00..0xd3c - SCS registers
316
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
317
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
318
"nvic_sysregs", 0x1000);
319
memory_region_add_subregion(&s->container, 0, &s->sysregmem);
320
+ memory_region_add_subregion_overlap(&s->container, 0x10,
321
+ sysbus_mmio_get_region(systick_sbd, 0),
322
+ 1);
323
324
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
325
-
326
- s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
327
}
328
329
static void armv7m_nvic_instance_init(Object *obj)
330
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_instance_init(Object *obj)
331
NVICState *nvic = NVIC(obj);
332
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
333
334
+ object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
335
+ qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
336
+
337
sysbus_init_irq(sbd, &nvic->excpout);
338
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
339
+ qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
340
}
341
342
static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
343
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
344
new file mode 100644
345
index XXXXXXX..XXXXXXX
346
--- /dev/null
347
+++ b/hw/timer/armv7m_systick.c
348
@@ -XXX,XX +XXX,XX @@
349
+/*
350
+ * ARMv7M SysTick timer
351
+ *
352
+ * Copyright (c) 2006-2007 CodeSourcery.
353
+ * Written by Paul Brook
354
+ * Copyright (c) 2017 Linaro Ltd
355
+ * Written by Peter Maydell
356
+ *
357
+ * This code is licensed under the GPL (version 2 or later).
358
+ */
359
+
360
+#include "qemu/osdep.h"
361
+#include "hw/timer/armv7m_systick.h"
362
+#include "qemu-common.h"
363
+#include "hw/sysbus.h"
364
+#include "qemu/timer.h"
365
+#include "qemu/log.h"
366
+#include "trace.h"
367
+
368
+/* qemu timers run at 1GHz. We want something closer to 1MHz. */
369
+#define SYSTICK_SCALE 1000ULL
370
+
371
+#define SYSTICK_ENABLE (1 << 0)
372
+#define SYSTICK_TICKINT (1 << 1)
373
+#define SYSTICK_CLKSOURCE (1 << 2)
374
+#define SYSTICK_COUNTFLAG (1 << 16)
375
+
376
+int system_clock_scale;
377
+
378
+/* Conversion factor from qemu timer to SysTick frequencies. */
379
+static inline int64_t systick_scale(SysTickState *s)
380
+{
381
+ if (s->control & SYSTICK_CLKSOURCE) {
382
+ return system_clock_scale;
383
+ } else {
384
+ return 1000;
385
+ }
386
+}
387
+
388
+static void systick_reload(SysTickState *s, int reset)
389
+{
390
+ /* The Cortex-M3 Devices Generic User Guide says that "When the
391
+ * ENABLE bit is set to 1, the counter loads the RELOAD value from the
392
+ * SYST RVR register and then counts down". So, we need to check the
393
+ * ENABLE bit before reloading the value.
394
+ */
395
+ trace_systick_reload();
396
+
397
+ if ((s->control & SYSTICK_ENABLE) == 0) {
398
+ return;
399
+ }
33
+ }
400
+
34
+
401
+ if (reset) {
35
desc = tcg_const_i32((a->vn << 2) | a->len);
402
+ s->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
36
def = tcg_temp_new_i64();
403
+ }
37
if (a->op) {
404
+ s->tick += (s->reload + 1) * systick_scale(s);
405
+ timer_mod(s->timer, s->tick);
406
+}
407
+
408
+static void systick_timer_tick(void *opaque)
409
+{
410
+ SysTickState *s = (SysTickState *)opaque;
411
+
412
+ trace_systick_timer_tick();
413
+
414
+ s->control |= SYSTICK_COUNTFLAG;
415
+ if (s->control & SYSTICK_TICKINT) {
416
+ /* Tell the NVIC to pend the SysTick exception */
417
+ qemu_irq_pulse(s->irq);
418
+ }
419
+ if (s->reload == 0) {
420
+ s->control &= ~SYSTICK_ENABLE;
421
+ } else {
422
+ systick_reload(s, 0);
423
+ }
424
+}
425
+
426
+static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size)
427
+{
428
+ SysTickState *s = opaque;
429
+ uint32_t val;
430
+
431
+ switch (addr) {
432
+ case 0x0: /* SysTick Control and Status. */
433
+ val = s->control;
434
+ s->control &= ~SYSTICK_COUNTFLAG;
435
+ break;
436
+ case 0x4: /* SysTick Reload Value. */
437
+ val = s->reload;
438
+ break;
439
+ case 0x8: /* SysTick Current Value. */
440
+ {
441
+ int64_t t;
442
+
443
+ if ((s->control & SYSTICK_ENABLE) == 0) {
444
+ val = 0;
445
+ break;
446
+ }
447
+ t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
448
+ if (t >= s->tick) {
449
+ val = 0;
450
+ break;
451
+ }
452
+ val = ((s->tick - (t + 1)) / systick_scale(s)) + 1;
453
+ /* The interrupt in triggered when the timer reaches zero.
454
+ However the counter is not reloaded until the next clock
455
+ tick. This is a hack to return zero during the first tick. */
456
+ if (val > s->reload) {
457
+ val = 0;
458
+ }
459
+ break;
460
+ }
461
+ case 0xc: /* SysTick Calibration Value. */
462
+ val = 10000;
463
+ break;
464
+ default:
465
+ val = 0;
466
+ qemu_log_mask(LOG_GUEST_ERROR,
467
+ "SysTick: Bad read offset 0x%" HWADDR_PRIx "\n", addr);
468
+ break;
469
+ }
470
+
471
+ trace_systick_read(addr, val, size);
472
+ return val;
473
+}
474
+
475
+static void systick_write(void *opaque, hwaddr addr,
476
+ uint64_t value, unsigned size)
477
+{
478
+ SysTickState *s = opaque;
479
+
480
+ trace_systick_write(addr, value, size);
481
+
482
+ switch (addr) {
483
+ case 0x0: /* SysTick Control and Status. */
484
+ {
485
+ uint32_t oldval = s->control;
486
+
487
+ s->control &= 0xfffffff8;
488
+ s->control |= value & 7;
489
+ if ((oldval ^ value) & SYSTICK_ENABLE) {
490
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
491
+ if (value & SYSTICK_ENABLE) {
492
+ if (s->tick) {
493
+ s->tick += now;
494
+ timer_mod(s->timer, s->tick);
495
+ } else {
496
+ systick_reload(s, 1);
497
+ }
498
+ } else {
499
+ timer_del(s->timer);
500
+ s->tick -= now;
501
+ if (s->tick < 0) {
502
+ s->tick = 0;
503
+ }
504
+ }
505
+ } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
506
+ /* This is a hack. Force the timer to be reloaded
507
+ when the reference clock is changed. */
508
+ systick_reload(s, 1);
509
+ }
510
+ break;
511
+ }
512
+ case 0x4: /* SysTick Reload Value. */
513
+ s->reload = value;
514
+ break;
515
+ case 0x8: /* SysTick Current Value. Writes reload the timer. */
516
+ systick_reload(s, 1);
517
+ s->control &= ~SYSTICK_COUNTFLAG;
518
+ break;
519
+ default:
520
+ qemu_log_mask(LOG_GUEST_ERROR,
521
+ "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr);
522
+ }
523
+}
524
+
525
+static const MemoryRegionOps systick_ops = {
526
+ .read = systick_read,
527
+ .write = systick_write,
528
+ .endianness = DEVICE_NATIVE_ENDIAN,
529
+ .valid.min_access_size = 4,
530
+ .valid.max_access_size = 4,
531
+};
532
+
533
+static void systick_reset(DeviceState *dev)
534
+{
535
+ SysTickState *s = SYSTICK(dev);
536
+
537
+ s->control = 0;
538
+ s->reload = 0;
539
+ s->tick = 0;
540
+ timer_del(s->timer);
541
+}
542
+
543
+static void systick_instance_init(Object *obj)
544
+{
545
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
546
+ SysTickState *s = SYSTICK(obj);
547
+
548
+ memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
549
+ sysbus_init_mmio(sbd, &s->iomem);
550
+ sysbus_init_irq(sbd, &s->irq);
551
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
552
+}
553
+
554
+static const VMStateDescription vmstate_systick = {
555
+ .name = "armv7m_systick",
556
+ .version_id = 1,
557
+ .minimum_version_id = 1,
558
+ .fields = (VMStateField[]) {
559
+ VMSTATE_UINT32(control, SysTickState),
560
+ VMSTATE_UINT32(reload, SysTickState),
561
+ VMSTATE_INT64(tick, SysTickState),
562
+ VMSTATE_TIMER_PTR(timer, SysTickState),
563
+ VMSTATE_END_OF_LIST()
564
+ }
565
+};
566
+
567
+static void systick_class_init(ObjectClass *klass, void *data)
568
+{
569
+ DeviceClass *dc = DEVICE_CLASS(klass);
570
+
571
+ dc->vmsd = &vmstate_systick;
572
+ dc->reset = systick_reset;
573
+}
574
+
575
+static const TypeInfo armv7m_systick_info = {
576
+ .name = TYPE_SYSTICK,
577
+ .parent = TYPE_SYS_BUS_DEVICE,
578
+ .instance_init = systick_instance_init,
579
+ .instance_size = sizeof(SysTickState),
580
+ .class_init = systick_class_init,
581
+};
582
+
583
+static void armv7m_systick_register_types(void)
584
+{
585
+ type_register_static(&armv7m_systick_info);
586
+}
587
+
588
+type_init(armv7m_systick_register_types)
589
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
590
index XXXXXXX..XXXXXXX 100644
591
--- a/hw/timer/trace-events
592
+++ b/hw/timer/trace-events
593
@@ -XXX,XX +XXX,XX @@ aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d"
594
aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32
595
aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32
596
aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64
597
+
598
+# hw/timer/armv7m_systick.c
599
+systick_reload(void) "systick reload"
600
+systick_timer_tick(void) "systick reload"
601
+systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
602
+systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
603
--
38
--
604
2.7.4
39
2.20.1
605
40
606
41
diff view generated by jsdifflib
Deleted patch
1
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
2
1
3
This actually implements pre_save and post_load methods for in-kernel
4
vGICv3.
5
6
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
10
Message-id: 1487850673-26455-4-git-send-email-vijay.kilari@gmail.com
11
[PMM:
12
* use decimal, not 0bnnn
13
* fixed typo in names of ICC_APR0R_EL1 and ICC_AP1R_EL1
14
* completely rearranged the get and put functions to read and write
15
the state in a natural order, rather than mixing distributor and
16
redistributor state together]
17
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
18
[Vijay:
19
* Update macro KVM_VGIC_ATTR
20
* Use 32 bit access for gicd and gicr
21
* GICD_IROUTER, GICD_TYPER, GICR_PROPBASER and GICR_PENDBASER reg
22
access are changed from 64-bit to 32-bit access
23
* Add ICC_SRE_EL1 save and restore
24
* Dropped translate_fn mechanism and coded functions to handle
25
save and restore of edge_trigger and priority
26
* Number of APnR register saved/restored based on number of
27
priority bits supported]
28
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
---
30
hw/intc/gicv3_internal.h | 1 +
31
hw/intc/arm_gicv3_kvm.c | 573 +++++++++++++++++++++++++++++++++++++++++++++--
32
2 files changed, 558 insertions(+), 16 deletions(-)
33
34
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/intc/gicv3_internal.h
37
+++ b/hw/intc/gicv3_internal.h
38
@@ -XXX,XX +XXX,XX @@
39
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
40
#define ICC_CTLR_EL1_PMHE (1U << 6)
41
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
42
+#define ICC_CTLR_EL1_PRIBITS_MASK (7U << ICC_CTLR_EL1_PRIBITS_SHIFT)
43
#define ICC_CTLR_EL1_IDBITS_SHIFT 11
44
#define ICC_CTLR_EL1_SEIS (1U << 14)
45
#define ICC_CTLR_EL1_A3V (1U << 15)
46
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/intc/arm_gicv3_kvm.c
49
+++ b/hw/intc/arm_gicv3_kvm.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "qapi/error.h"
52
#include "hw/intc/arm_gicv3_common.h"
53
#include "hw/sysbus.h"
54
+#include "qemu/error-report.h"
55
#include "sysemu/kvm.h"
56
#include "kvm_arm.h"
57
+#include "gicv3_internal.h"
58
#include "vgic_common.h"
59
#include "migration/migration.h"
60
61
@@ -XXX,XX +XXX,XX @@
62
#define KVM_ARM_GICV3_GET_CLASS(obj) \
63
OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
64
65
+#define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \
66
+ (ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
67
+ ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
68
+ ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
69
+ ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
70
+ ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
71
+
72
+#define ICC_PMR_EL1 \
73
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 4, 6, 0)
74
+#define ICC_BPR0_EL1 \
75
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 3)
76
+#define ICC_AP0R_EL1(n) \
77
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 8, 4 | n)
78
+#define ICC_AP1R_EL1(n) \
79
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 9, n)
80
+#define ICC_BPR1_EL1 \
81
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3)
82
+#define ICC_CTLR_EL1 \
83
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4)
84
+#define ICC_SRE_EL1 \
85
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5)
86
+#define ICC_IGRPEN0_EL1 \
87
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6)
88
+#define ICC_IGRPEN1_EL1 \
89
+ KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
90
+
91
typedef struct KVMARMGICv3Class {
92
ARMGICv3CommonClass parent_class;
93
DeviceRealize parent_realize;
94
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
95
kvm_arm_gic_set_irq(s->num_irq, irq, level);
96
}
97
98
+#define KVM_VGIC_ATTR(reg, typer) \
99
+ ((typer & KVM_DEV_ARM_VGIC_V3_MPIDR_MASK) | (reg))
100
+
101
+static inline void kvm_gicd_access(GICv3State *s, int offset,
102
+ uint32_t *val, bool write)
103
+{
104
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
105
+ KVM_VGIC_ATTR(offset, 0),
106
+ val, write);
107
+}
108
+
109
+static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
110
+ uint32_t *val, bool write)
111
+{
112
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
113
+ KVM_VGIC_ATTR(offset, s->cpu[cpu].gicr_typer),
114
+ val, write);
115
+}
116
+
117
+static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
118
+ uint64_t *val, bool write)
119
+{
120
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
121
+ KVM_VGIC_ATTR(reg, s->cpu[cpu].gicr_typer),
122
+ val, write);
123
+}
124
+
125
+static inline void kvm_gic_line_level_access(GICv3State *s, int irq, int cpu,
126
+ uint32_t *val, bool write)
127
+{
128
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
129
+ KVM_VGIC_ATTR(irq, s->cpu[cpu].gicr_typer) |
130
+ (VGIC_LEVEL_INFO_LINE_LEVEL <<
131
+ KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT),
132
+ val, write);
133
+}
134
+
135
+/* Loop through each distributor IRQ related register; since bits
136
+ * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
137
+ * is enabled, we skip those.
138
+ */
139
+#define for_each_dist_irq_reg(_irq, _max, _field_width) \
140
+ for (_irq = GIC_INTERNAL; _irq < _max; _irq += (32 / _field_width))
141
+
142
+static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
143
+{
144
+ uint32_t reg, *field;
145
+ int irq;
146
+
147
+ field = (uint32_t *)bmp;
148
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
149
+ kvm_gicd_access(s, offset, &reg, false);
150
+ *field = reg;
151
+ offset += 4;
152
+ field++;
153
+ }
154
+}
155
+
156
+static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp)
157
+{
158
+ uint32_t reg, *field;
159
+ int irq;
160
+
161
+ field = (uint32_t *)bmp;
162
+ for_each_dist_irq_reg(irq, s->num_irq, 8) {
163
+ reg = *field;
164
+ kvm_gicd_access(s, offset, &reg, true);
165
+ offset += 4;
166
+ field++;
167
+ }
168
+}
169
+
170
+static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
171
+ uint32_t *bmp)
172
+{
173
+ uint32_t reg;
174
+ int irq;
175
+
176
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
177
+ kvm_gicd_access(s, offset, &reg, false);
178
+ reg = half_unshuffle32(reg >> 1);
179
+ if (irq % 32 != 0) {
180
+ reg = (reg << 16);
181
+ }
182
+ *gic_bmp_ptr32(bmp, irq) |= reg;
183
+ offset += 4;
184
+ }
185
+}
186
+
187
+static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
188
+ uint32_t *bmp)
189
+{
190
+ uint32_t reg;
191
+ int irq;
192
+
193
+ for_each_dist_irq_reg(irq, s->num_irq, 2) {
194
+ reg = *gic_bmp_ptr32(bmp, irq);
195
+ if (irq % 32 != 0) {
196
+ reg = (reg & 0xffff0000) >> 16;
197
+ } else {
198
+ reg = reg & 0xffff;
199
+ }
200
+ reg = half_shuffle32(reg) << 1;
201
+ kvm_gicd_access(s, offset, &reg, true);
202
+ offset += 4;
203
+ }
204
+}
205
+
206
+static void kvm_gic_get_line_level_bmp(GICv3State *s, uint32_t *bmp)
207
+{
208
+ uint32_t reg;
209
+ int irq;
210
+
211
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
212
+ kvm_gic_line_level_access(s, irq, 0, &reg, false);
213
+ *gic_bmp_ptr32(bmp, irq) = reg;
214
+ }
215
+}
216
+
217
+static void kvm_gic_put_line_level_bmp(GICv3State *s, uint32_t *bmp)
218
+{
219
+ uint32_t reg;
220
+ int irq;
221
+
222
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
223
+ reg = *gic_bmp_ptr32(bmp, irq);
224
+ kvm_gic_line_level_access(s, irq, 0, &reg, true);
225
+ }
226
+}
227
+
228
+/* Read a bitmap register group from the kernel VGIC. */
229
+static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
230
+{
231
+ uint32_t reg;
232
+ int irq;
233
+
234
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
235
+ kvm_gicd_access(s, offset, &reg, false);
236
+ *gic_bmp_ptr32(bmp, irq) = reg;
237
+ offset += 4;
238
+ }
239
+}
240
+
241
+static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
242
+ uint32_t clroffset, uint32_t *bmp)
243
+{
244
+ uint32_t reg;
245
+ int irq;
246
+
247
+ for_each_dist_irq_reg(irq, s->num_irq, 1) {
248
+ /* If this bitmap is a set/clear register pair, first write to the
249
+ * clear-reg to clear all bits before using the set-reg to write
250
+ * the 1 bits.
251
+ */
252
+ if (clroffset != 0) {
253
+ reg = 0;
254
+ kvm_gicd_access(s, clroffset, &reg, true);
255
+ }
256
+ reg = *gic_bmp_ptr32(bmp, irq);
257
+ kvm_gicd_access(s, offset, &reg, true);
258
+ offset += 4;
259
+ }
260
+}
261
+
262
+static void kvm_arm_gicv3_check(GICv3State *s)
263
+{
264
+ uint32_t reg;
265
+ uint32_t num_irq;
266
+
267
+ /* Sanity checking s->num_irq */
268
+ kvm_gicd_access(s, GICD_TYPER, &reg, false);
269
+ num_irq = ((reg & 0x1f) + 1) * 32;
270
+
271
+ if (num_irq < s->num_irq) {
272
+ error_report("Model requests %u IRQs, but kernel supports max %u",
273
+ s->num_irq, num_irq);
274
+ abort();
275
+ }
276
+}
277
+
278
static void kvm_arm_gicv3_put(GICv3State *s)
279
{
280
- /* TODO */
281
- DPRINTF("Cannot put kernel gic state, no kernel interface\n");
282
+ uint32_t regl, regh, reg;
283
+ uint64_t reg64, redist_typer;
284
+ int ncpu, i;
285
+
286
+ kvm_arm_gicv3_check(s);
287
+
288
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
289
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
290
+ redist_typer = ((uint64_t)regh << 32) | regl;
291
+
292
+ reg = s->gicd_ctlr;
293
+ kvm_gicd_access(s, GICD_CTLR, &reg, true);
294
+
295
+ if (redist_typer & GICR_TYPER_PLPIS) {
296
+ /* Set base addresses before LPIs are enabled by GICR_CTLR write */
297
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
298
+ GICv3CPUState *c = &s->cpu[ncpu];
299
+
300
+ reg64 = c->gicr_propbaser;
301
+ regl = (uint32_t)reg64;
302
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, true);
303
+ regh = (uint32_t)(reg64 >> 32);
304
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, true);
305
+
306
+ reg64 = c->gicr_pendbaser;
307
+ if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
308
+ /* Setting PTZ is advised if LPIs are disabled, to reduce
309
+ * GIC initialization time.
310
+ */
311
+ reg64 |= GICR_PENDBASER_PTZ;
312
+ }
313
+ regl = (uint32_t)reg64;
314
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, true);
315
+ regh = (uint32_t)(reg64 >> 32);
316
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, true);
317
+ }
318
+ }
319
+
320
+ /* Redistributor state (one per CPU) */
321
+
322
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
323
+ GICv3CPUState *c = &s->cpu[ncpu];
324
+
325
+ reg = c->gicr_ctlr;
326
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, true);
327
+
328
+ reg = c->gicr_statusr[GICV3_NS];
329
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, true);
330
+
331
+ reg = c->gicr_waker;
332
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, true);
333
+
334
+ reg = c->gicr_igroupr0;
335
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, true);
336
+
337
+ reg = ~0;
338
+ kvm_gicr_access(s, GICR_ICENABLER0, ncpu, &reg, true);
339
+ reg = c->gicr_ienabler0;
340
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, true);
341
+
342
+ /* Restore config before pending so we treat level/edge correctly */
343
+ reg = half_shuffle32(c->edge_trigger >> 16) << 1;
344
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, true);
345
+
346
+ reg = c->level;
347
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, true);
348
+
349
+ reg = ~0;
350
+ kvm_gicr_access(s, GICR_ICPENDR0, ncpu, &reg, true);
351
+ reg = c->gicr_ipendr0;
352
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, true);
353
+
354
+ reg = ~0;
355
+ kvm_gicr_access(s, GICR_ICACTIVER0, ncpu, &reg, true);
356
+ reg = c->gicr_iactiver0;
357
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, true);
358
+
359
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
360
+ reg = c->gicr_ipriorityr[i] |
361
+ (c->gicr_ipriorityr[i + 1] << 8) |
362
+ (c->gicr_ipriorityr[i + 2] << 16) |
363
+ (c->gicr_ipriorityr[i + 3] << 24);
364
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, true);
365
+ }
366
+ }
367
+
368
+ /* Distributor state (shared between all CPUs */
369
+ reg = s->gicd_statusr[GICV3_NS];
370
+ kvm_gicd_access(s, GICD_STATUSR, &reg, true);
371
+
372
+ /* s->enable bitmap -> GICD_ISENABLERn */
373
+ kvm_dist_putbmp(s, GICD_ISENABLER, GICD_ICENABLER, s->enabled);
374
+
375
+ /* s->group bitmap -> GICD_IGROUPRn */
376
+ kvm_dist_putbmp(s, GICD_IGROUPR, 0, s->group);
377
+
378
+ /* Restore targets before pending to ensure the pending state is set on
379
+ * the appropriate CPU interfaces in the kernel
380
+ */
381
+
382
+ /* s->gicd_irouter[irq] -> GICD_IROUTERn
383
+ * We can't use kvm_dist_put() here because the registers are 64-bit
384
+ */
385
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
386
+ uint32_t offset;
387
+
388
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
389
+ reg = (uint32_t)s->gicd_irouter[i];
390
+ kvm_gicd_access(s, offset, &reg, true);
391
+
392
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
393
+ reg = (uint32_t)(s->gicd_irouter[i] >> 32);
394
+ kvm_gicd_access(s, offset, &reg, true);
395
+ }
396
+
397
+ /* s->trigger bitmap -> GICD_ICFGRn
398
+ * (restore configuration registers before pending IRQs so we treat
399
+ * level/edge correctly)
400
+ */
401
+ kvm_dist_put_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
402
+
403
+ /* s->level bitmap -> line_level */
404
+ kvm_gic_put_line_level_bmp(s, s->level);
405
+
406
+ /* s->pending bitmap -> GICD_ISPENDRn */
407
+ kvm_dist_putbmp(s, GICD_ISPENDR, GICD_ICPENDR, s->pending);
408
+
409
+ /* s->active bitmap -> GICD_ISACTIVERn */
410
+ kvm_dist_putbmp(s, GICD_ISACTIVER, GICD_ICACTIVER, s->active);
411
+
412
+ /* s->gicd_ipriority[] -> GICD_IPRIORITYRn */
413
+ kvm_dist_put_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
414
+
415
+ /* CPU Interface state (one per CPU) */
416
+
417
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
418
+ GICv3CPUState *c = &s->cpu[ncpu];
419
+ int num_pri_bits;
420
+
421
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true);
422
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
423
+ &c->icc_ctlr_el1[GICV3_NS], true);
424
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
425
+ &c->icc_igrpen[GICV3_G0], true);
426
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
427
+ &c->icc_igrpen[GICV3_G1NS], true);
428
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, true);
429
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], true);
430
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], true);
431
+
432
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
433
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
434
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
435
+
436
+ switch (num_pri_bits) {
437
+ case 7:
438
+ reg64 = c->icc_apr[GICV3_G0][3];
439
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, true);
440
+ reg64 = c->icc_apr[GICV3_G0][2];
441
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, true);
442
+ case 6:
443
+ reg64 = c->icc_apr[GICV3_G0][1];
444
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, true);
445
+ default:
446
+ reg64 = c->icc_apr[GICV3_G0][0];
447
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, true);
448
+ }
449
+
450
+ switch (num_pri_bits) {
451
+ case 7:
452
+ reg64 = c->icc_apr[GICV3_G1NS][3];
453
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true);
454
+ reg64 = c->icc_apr[GICV3_G1NS][2];
455
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true);
456
+ case 6:
457
+ reg64 = c->icc_apr[GICV3_G1NS][1];
458
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true);
459
+ default:
460
+ reg64 = c->icc_apr[GICV3_G1NS][0];
461
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true);
462
+ }
463
+ }
464
}
465
466
static void kvm_arm_gicv3_get(GICv3State *s)
467
{
468
- /* TODO */
469
- DPRINTF("Cannot get kernel gic state, no kernel interface\n");
470
+ uint32_t regl, regh, reg;
471
+ uint64_t reg64, redist_typer;
472
+ int ncpu, i;
473
+
474
+ kvm_arm_gicv3_check(s);
475
+
476
+ kvm_gicr_access(s, GICR_TYPER, 0, &regl, false);
477
+ kvm_gicr_access(s, GICR_TYPER + 4, 0, &regh, false);
478
+ redist_typer = ((uint64_t)regh << 32) | regl;
479
+
480
+ kvm_gicd_access(s, GICD_CTLR, &reg, false);
481
+ s->gicd_ctlr = reg;
482
+
483
+ /* Redistributor state (one per CPU) */
484
+
485
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
486
+ GICv3CPUState *c = &s->cpu[ncpu];
487
+
488
+ kvm_gicr_access(s, GICR_CTLR, ncpu, &reg, false);
489
+ c->gicr_ctlr = reg;
490
+
491
+ kvm_gicr_access(s, GICR_STATUSR, ncpu, &reg, false);
492
+ c->gicr_statusr[GICV3_NS] = reg;
493
+
494
+ kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, false);
495
+ c->gicr_waker = reg;
496
+
497
+ kvm_gicr_access(s, GICR_IGROUPR0, ncpu, &reg, false);
498
+ c->gicr_igroupr0 = reg;
499
+ kvm_gicr_access(s, GICR_ISENABLER0, ncpu, &reg, false);
500
+ c->gicr_ienabler0 = reg;
501
+ kvm_gicr_access(s, GICR_ICFGR1, ncpu, &reg, false);
502
+ c->edge_trigger = half_unshuffle32(reg >> 1) << 16;
503
+ kvm_gic_line_level_access(s, 0, ncpu, &reg, false);
504
+ c->level = reg;
505
+ kvm_gicr_access(s, GICR_ISPENDR0, ncpu, &reg, false);
506
+ c->gicr_ipendr0 = reg;
507
+ kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, &reg, false);
508
+ c->gicr_iactiver0 = reg;
509
+
510
+ for (i = 0; i < GIC_INTERNAL; i += 4) {
511
+ kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, &reg, false);
512
+ c->gicr_ipriorityr[i] = extract32(reg, 0, 8);
513
+ c->gicr_ipriorityr[i + 1] = extract32(reg, 8, 8);
514
+ c->gicr_ipriorityr[i + 2] = extract32(reg, 16, 8);
515
+ c->gicr_ipriorityr[i + 3] = extract32(reg, 24, 8);
516
+ }
517
+ }
518
+
519
+ if (redist_typer & GICR_TYPER_PLPIS) {
520
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
521
+ GICv3CPUState *c = &s->cpu[ncpu];
522
+
523
+ kvm_gicr_access(s, GICR_PROPBASER, ncpu, &regl, false);
524
+ kvm_gicr_access(s, GICR_PROPBASER + 4, ncpu, &regh, false);
525
+ c->gicr_propbaser = ((uint64_t)regh << 32) | regl;
526
+
527
+ kvm_gicr_access(s, GICR_PENDBASER, ncpu, &regl, false);
528
+ kvm_gicr_access(s, GICR_PENDBASER + 4, ncpu, &regh, false);
529
+ c->gicr_pendbaser = ((uint64_t)regh << 32) | regl;
530
+ }
531
+ }
532
+
533
+ /* Distributor state (shared between all CPUs */
534
+
535
+ kvm_gicd_access(s, GICD_STATUSR, &reg, false);
536
+ s->gicd_statusr[GICV3_NS] = reg;
537
+
538
+ /* GICD_IGROUPRn -> s->group bitmap */
539
+ kvm_dist_getbmp(s, GICD_IGROUPR, s->group);
540
+
541
+ /* GICD_ISENABLERn -> s->enabled bitmap */
542
+ kvm_dist_getbmp(s, GICD_ISENABLER, s->enabled);
543
+
544
+ /* Line level of irq */
545
+ kvm_gic_get_line_level_bmp(s, s->level);
546
+ /* GICD_ISPENDRn -> s->pending bitmap */
547
+ kvm_dist_getbmp(s, GICD_ISPENDR, s->pending);
548
+
549
+ /* GICD_ISACTIVERn -> s->active bitmap */
550
+ kvm_dist_getbmp(s, GICD_ISACTIVER, s->active);
551
+
552
+ /* GICD_ICFGRn -> s->trigger bitmap */
553
+ kvm_dist_get_edge_trigger(s, GICD_ICFGR, s->edge_trigger);
554
+
555
+ /* GICD_IPRIORITYRn -> s->gicd_ipriority[] */
556
+ kvm_dist_get_priority(s, GICD_IPRIORITYR, s->gicd_ipriority);
557
+
558
+ /* GICD_IROUTERn -> s->gicd_irouter[irq] */
559
+ for (i = GIC_INTERNAL; i < s->num_irq; i++) {
560
+ uint32_t offset;
561
+
562
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i);
563
+ kvm_gicd_access(s, offset, &regl, false);
564
+ offset = GICD_IROUTER + (sizeof(uint32_t) * i) + 4;
565
+ kvm_gicd_access(s, offset, &regh, false);
566
+ s->gicd_irouter[i] = ((uint64_t)regh << 32) | regl;
567
+ }
568
+
569
+ /*****************************************************************
570
+ * CPU Interface(s) State
571
+ */
572
+
573
+ for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
574
+ GICv3CPUState *c = &s->cpu[ncpu];
575
+ int num_pri_bits;
576
+
577
+ kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false);
578
+ kvm_gicc_access(s, ICC_CTLR_EL1, ncpu,
579
+ &c->icc_ctlr_el1[GICV3_NS], false);
580
+ kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu,
581
+ &c->icc_igrpen[GICV3_G0], false);
582
+ kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu,
583
+ &c->icc_igrpen[GICV3_G1NS], false);
584
+ kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &c->icc_pmr_el1, false);
585
+ kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &c->icc_bpr[GICV3_G0], false);
586
+ kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &c->icc_bpr[GICV3_G1NS], false);
587
+ num_pri_bits = ((c->icc_ctlr_el1[GICV3_NS] &
588
+ ICC_CTLR_EL1_PRIBITS_MASK) >>
589
+ ICC_CTLR_EL1_PRIBITS_SHIFT) + 1;
590
+
591
+ switch (num_pri_bits) {
592
+ case 7:
593
+ kvm_gicc_access(s, ICC_AP0R_EL1(3), ncpu, &reg64, false);
594
+ c->icc_apr[GICV3_G0][3] = reg64;
595
+ kvm_gicc_access(s, ICC_AP0R_EL1(2), ncpu, &reg64, false);
596
+ c->icc_apr[GICV3_G0][2] = reg64;
597
+ case 6:
598
+ kvm_gicc_access(s, ICC_AP0R_EL1(1), ncpu, &reg64, false);
599
+ c->icc_apr[GICV3_G0][1] = reg64;
600
+ default:
601
+ kvm_gicc_access(s, ICC_AP0R_EL1(0), ncpu, &reg64, false);
602
+ c->icc_apr[GICV3_G0][0] = reg64;
603
+ }
604
+
605
+ switch (num_pri_bits) {
606
+ case 7:
607
+ kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false);
608
+ c->icc_apr[GICV3_G1NS][3] = reg64;
609
+ kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false);
610
+ c->icc_apr[GICV3_G1NS][2] = reg64;
611
+ case 6:
612
+ kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false);
613
+ c->icc_apr[GICV3_G1NS][1] = reg64;
614
+ default:
615
+ kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);
616
+ c->icc_apr[GICV3_G1NS][0] = reg64;
617
+ }
618
+ }
619
}
620
621
static void kvm_arm_gicv3_reset(DeviceState *dev)
622
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
623
DPRINTF("Reset\n");
624
625
kgc->parent_reset(dev);
626
+
627
+ if (s->migration_blocker) {
628
+ DPRINTF("Cannot put kernel gic state, no kernel interface\n");
629
+ return;
630
+ }
631
+
632
kvm_arm_gicv3_put(s);
633
}
634
635
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
636
637
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
638
639
- /* Block migration of a KVM GICv3 device: the API for saving and restoring
640
- * the state in the kernel is not yet finalised in the kernel or
641
- * implemented in QEMU.
642
- */
643
- error_setg(&s->migration_blocker, "vGICv3 migration is not implemented");
644
- migrate_add_blocker(s->migration_blocker, &local_err);
645
- if (local_err) {
646
- error_propagate(errp, local_err);
647
- error_free(s->migration_blocker);
648
- return;
649
- }
650
-
651
/* Try to create the device via the device control API */
652
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
653
if (s->dev_fd < 0) {
654
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
655
656
kvm_irqchip_commit_routes(kvm_state);
657
}
658
+
659
+ if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
660
+ GICD_CTLR)) {
661
+ error_setg(&s->migration_blocker, "This operating system kernel does "
662
+ "not support vGICv3 migration");
663
+ migrate_add_blocker(s->migration_blocker, &local_err);
664
+ if (local_err) {
665
+ error_propagate(errp, local_err);
666
+ error_free(s->migration_blocker);
667
+ return;
668
+ }
669
+ }
670
}
671
672
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
673
--
674
2.7.4
675
676
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