[Qemu-devel] [PULL 00/27] target-arm queue
[PULL 00/12] target-arm queue
1
v1->v2 changes: drop the sd card-reparenting patch
1
The following changes since commit 131c58469f6fb68c89b38fee6aba8bbb20c7f4bf:
2
and the 2 raspi2 patches that depend on it.
3
2
4
-- PMM
3
rust: add --rust-target option for bindgen (2025-02-06 13:51:46 -0500)
5
4
6
The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
5
are available in the Git repository at:
7
6
8
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250210
9
8
10
are available in the git repository at:
9
for you to fetch changes up to 27a8d899c7a100fd5aa040a8b993bb257687c393:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
11
linux-user: Do not define struct sched_attr if libc headers do (2025-02-07 16:09:20 +0000)
13
14
for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
15
16
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* raspi2: implement RNG module
15
* Deprecate pxa2xx CPUs, iwMMXt emulation, -old-param option
21
* raspi2: implement new SD card controller (but don't wire it up)
16
* Drop unused AArch64DecodeTable typedefs
22
* sdhci: bugfixes for block transfers
17
* Minor code cleanups
23
* virt: fix cpu object reference leak
18
* hw/net/cadence_gem: Fix the mask/compare/disable-mask logic
24
* Add missing fp_access_check() to aarch64 crypto instructions
19
* linux-user: Do not define struct sched_attr if libc headers do
25
* cputlb: Don't assume do_unassigned_access() never returns
26
* virt: Add a user option to disallow ITS instantiation
27
* i.MX timers: fix reset handling
28
* ARMv7M NVIC: rewrite to fix broken priority handling and masking
29
* exynos: Fix proper mapping of CPUs by providing real cluster ID
30
* exynos: Fix Linux kernel division by zero for PLLs
31
20
32
----------------------------------------------------------------
21
----------------------------------------------------------------
33
Clement Deschamps (1):
22
Andrew Yuan (1):
34
bcm2835_sdhost: add bcm2835 sdhost controller
23
hw/net/cadence_gem: Fix the mask/compare/disable-mask logic
35
24
36
Eric Auger (1):
25
Khem Raj (1):
37
hw/arm/virt: Add a user option to disallow ITS instantiation
26
linux-user: Do not define struct sched_attr if libc headers do
38
27
39
Igor Mammedov (1):
28
Peter Maydell (4):
40
hw/arm/virt: fix cpu object reference leak
29
target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation
30
tests/tcg/arm: Remove test-arm-iwmmxt test
31
target/arm: Drop unused AArch64DecodeTable typedefs
32
qemu-options: Deprecate -old-param command line option
41
33
42
Krzysztof Kozlowski (2):
34
Philippe Mathieu-Daudé (6):
43
hw/arm/exynos: Fix Linux kernel division by zero for PLLs
35
hw/arm/boot: Propagate vCPU to arm_load_dtb()
44
hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
36
hw/arm/fsl-imx6: Add local 'mpcore/gic' variables
37
hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables
38
hw/arm/fsl-imx7: Add local 'mpcore/gic' variables
39
hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE
40
hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro
45
41
46
Kurban Mallachiev (1):
42
docs/about/deprecated.rst | 34 ++++++++++++++++++++++
47
ARM i.MX timers: fix reset handling
43
include/hw/arm/boot.h | 4 ++-
44
target/arm/cpu.h | 1 +
45
hw/arm/boot.c | 11 +++----
46
hw/arm/fsl-imx6.c | 52 ++++++++++++++-------------------
47
hw/arm/fsl-imx6ul.c | 64 +++++++++++++++++------------------------
48
hw/arm/fsl-imx7.c | 52 +++++++++++++++------------------
49
hw/arm/virt.c | 2 +-
50
hw/cpu/a15mpcore.c | 21 ++++++--------
51
hw/cpu/a9mpcore.c | 21 ++++++--------
52
hw/cpu/arm11mpcore.c | 21 ++++++--------
53
hw/cpu/realview_mpcore.c | 29 +++++++------------
54
hw/net/cadence_gem.c | 26 +++++++++++++----
55
linux-user/syscall.c | 4 ++-
56
system/vl.c | 1 +
57
target/arm/cpu.c | 3 ++
58
target/arm/tcg/cpu32.c | 36 +++++++++++++++--------
59
target/arm/tcg/translate-a64.c | 11 -------
60
tests/tcg/arm/Makefile.target | 7 -----
61
tests/tcg/arm/README | 5 ----
62
tests/tcg/arm/test-arm-iwmmxt.S | 49 -------------------------------
63
21 files changed, 205 insertions(+), 249 deletions(-)
64
delete mode 100644 tests/tcg/arm/test-arm-iwmmxt.S
48
65
49
Marcin Chojnacki (1):
50
target-arm: Implement BCM2835 hardware RNG
51
52
Michael Davidsaver (5):
53
armv7m: Rewrite NVIC to not use any GIC code
54
arm: gic: Remove references to NVIC
55
armv7m: Escalate exceptions to HardFault if necessary
56
armv7m: Simpler and faster exception start
57
armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
58
59
Nick Reilly (1):
60
Add missing fp_access_check() to aarch64 crypto instructions
61
62
Peter Maydell (10):
63
bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
64
cputlb: Don't assume do_unassigned_access() never returns
65
armv7m: Rename nvic_state to NVICState
66
armv7m: Implement reading and writing of PRIGROUP
67
armv7m: Fix condition check for taking exceptions
68
armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
69
armv7m: Extract "exception taken" code into functions
70
armv7m: Check exception return consistency
71
armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
72
armv7m: Allow SHCSR writes to change pending and active bits
73
74
Prasad J Pandit (4):
75
sd: sdhci: mask transfer mode register value
76
sd: sdhci: check transfer mode register in multi block transfer
77
sd: sdhci: conditionally invoke multi block transfer
78
sd: sdhci: Remove block count enable check in single block transfers
79
80
hw/misc/Makefile.objs | 3 +-
81
hw/sd/Makefile.objs | 1 +
82
hw/intc/gic_internal.h | 7 +-
83
include/hw/arm/bcm2835_peripherals.h | 2 +
84
include/hw/arm/virt.h | 1 +
85
include/hw/misc/bcm2835_rng.h | 27 ++
86
include/hw/sd/bcm2835_sdhost.h | 48 ++
87
target/arm/cpu.h | 23 +-
88
cputlb.c | 15 +-
89
hw/arm/bcm2835_peripherals.c | 15 +
90
hw/arm/exynos4210.c | 18 +
91
hw/arm/virt.c | 32 +-
92
hw/intc/arm_gic.c | 31 +-
93
hw/intc/arm_gic_common.c | 23 +-
94
hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++-------
95
hw/misc/bcm2835_rng.c | 149 ++++++
96
hw/misc/exynos4210_clk.c | 164 +++++++
97
hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++
98
hw/sd/sdhci.c | 25 +-
99
hw/timer/imx_gpt.c | 33 +-
100
linux-user/main.c | 1 +
101
target/arm/cpu.c | 16 +-
102
target/arm/helper.c | 245 +++++++---
103
target/arm/translate-a64.c | 12 +
104
target/arm/translate.c | 8 +-
105
hw/intc/trace-events | 15 +
106
26 files changed, 1897 insertions(+), 331 deletions(-)
107
create mode 100644 include/hw/misc/bcm2835_rng.h
108
create mode 100644 include/hw/sd/bcm2835_sdhost.h
109
create mode 100644 hw/misc/bcm2835_rng.c
110
create mode 100644 hw/misc/exynos4210_clk.c
111
create mode 100644 hw/sd/bcm2835_sdhost.c
112
diff view generated by jsdifflib
New patch
[PULL 01/12] target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation
1
The pxa2xx CPUs are now only useful with user-mode emulation, because
2
we dropped all the machine types that used them in 9.2. (Technically
3
you could alse use "-cpu pxa270" with a board model like versatilepb
4
which doesn't sanity-check the CPU type, but that has never been a
5
supported config.)
1
6
7
To use them (or iwMMXt emulation) with QEMU user-mode you would need
8
to explicitly select them with the -cpu option or the QEMU_CPU
9
environment variable. A google search finds no examples of anybody
10
doing this in the last decade; I don't believe the GCC folks are
11
using QEMU to test their iwMMXt codegen either. In fact, GCC is in
12
the process of dropping support for iwMMXT entirely.
13
14
The iwMMXt emulation is thousands of lines of code in QEMU, and
15
is now the only bit of Arm insn decode which doesn't use decodetree.
16
We have no way to test or validate changes to it. This code is
17
just dead weight that is almost certainly not being used by anybody.
18
Mark it as deprecated.
19
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
23
Message-id: 20250127112715.2936555-2-peter.maydell@linaro.org
24
---
25
docs/about/deprecated.rst | 21 +++++++++++++++++++++
26
target/arm/cpu.h | 1 +
27
target/arm/cpu.c | 3 +++
28
target/arm/tcg/cpu32.c | 36 ++++++++++++++++++++++++------------
29
4 files changed, 49 insertions(+), 12 deletions(-)
30
31
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
32
index XXXXXXX..XXXXXXX 100644
33
--- a/docs/about/deprecated.rst
34
+++ b/docs/about/deprecated.rst
35
@@ -XXX,XX +XXX,XX @@ is going to be so much slower it wouldn't make sense for any serious
36
instrumentation. Due to implementation differences there will also be
37
anomalies in things like memory instrumentation.
38
39
+linux-user mode CPUs
40
+--------------------
41
+
42
+iwMMXt emulation and the ``pxa`` CPUs (since 10.0)
43
+''''''''''''''''''''''''''''''''''''''''''''''''''
44
+
45
+The ``pxa`` CPU family (``pxa250``, ``pxa255``, ``pxa260``,
46
+``pxa261``, ``pxa262``, ``pxa270-a0``, ``pxa270-a1``, ``pxa270``,
47
+``pxa270-b0``, ``pxa270-b1``, ``pxa270-c0``, ``pxa270-c5``) are no
48
+longer used in system emulation, because all the machine types which
49
+used these CPUs were removed in the QEMU 9.2 release. These CPUs can
50
+now only be used in linux-user mode, and to do that you would have to
51
+explicitly select one of these CPUs with the ``-cpu`` command line
52
+option or the ``QEMU_CPU`` environment variable.
53
+
54
+We don't believe that anybody is using the iwMMXt emulation, and we do
55
+not have any tests to validate it or any real hardware or similar
56
+known-good implementation to test against. GCC is in the process of
57
+dropping their support for iwMMXt codegen. These CPU types are
58
+therefore deprecated in QEMU, and will be removed in a future release.
59
+
60
System emulator CPUs
61
--------------------
62
63
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/cpu.h
66
+++ b/target/arm/cpu.h
67
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
68
69
typedef struct ARMCPUInfo {
70
const char *name;
71
+ const char *deprecation_note;
72
void (*initfn)(Object *obj);
73
void (*class_init)(ObjectClass *oc, void *data);
74
} ARMCPUInfo;
75
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/cpu.c
78
+++ b/target/arm/cpu.c
79
@@ -XXX,XX +XXX,XX @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
80
81
acc->info = data;
82
cc->gdb_core_xml_file = "arm-core.xml";
83
+ if (acc->info->deprecation_note) {
84
+ cc->deprecation_note = acc->info->deprecation_note;
85
+ }
86
}
87
88
void arm_cpu_register(const ARMCPUInfo *info)
89
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/tcg/cpu32.c
92
+++ b/target/arm/tcg/cpu32.c
93
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
94
{ .name = "ti925t", .initfn = ti925t_initfn },
95
{ .name = "sa1100", .initfn = sa1100_initfn },
96
{ .name = "sa1110", .initfn = sa1110_initfn },
97
- { .name = "pxa250", .initfn = pxa250_initfn },
98
- { .name = "pxa255", .initfn = pxa255_initfn },
99
- { .name = "pxa260", .initfn = pxa260_initfn },
100
- { .name = "pxa261", .initfn = pxa261_initfn },
101
- { .name = "pxa262", .initfn = pxa262_initfn },
102
+ { .name = "pxa250", .initfn = pxa250_initfn,
103
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
104
+ { .name = "pxa255", .initfn = pxa255_initfn,
105
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
106
+ { .name = "pxa260", .initfn = pxa260_initfn,
107
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
108
+ { .name = "pxa261", .initfn = pxa261_initfn,
109
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
110
+ { .name = "pxa262", .initfn = pxa262_initfn,
111
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
112
/* "pxa270" is an alias for "pxa270-a0" */
113
- { .name = "pxa270", .initfn = pxa270a0_initfn },
114
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
115
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
116
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
117
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
118
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
119
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
120
+ { .name = "pxa270", .initfn = pxa270a0_initfn,
121
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
122
+ { .name = "pxa270-a0", .initfn = pxa270a0_initfn,
123
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
124
+ { .name = "pxa270-a1", .initfn = pxa270a1_initfn,
125
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
126
+ { .name = "pxa270-b0", .initfn = pxa270b0_initfn,
127
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
128
+ { .name = "pxa270-b1", .initfn = pxa270b1_initfn,
129
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
130
+ { .name = "pxa270-c0", .initfn = pxa270c0_initfn,
131
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
132
+ { .name = "pxa270-c5", .initfn = pxa270c5_initfn,
133
+ .deprecation_note = "iwMMXt CPUs are no longer supported", },
134
#ifndef TARGET_AARCH64
135
{ .name = "max", .initfn = arm_max_initfn },
136
#endif
137
--
138
2.34.1
139
140
diff view generated by jsdifflib
New patch
[PULL 02/12] tests/tcg/arm: Remove test-arm-iwmmxt test
1
The test-arm-iwmmmxt test isn't testing what it thinks it's testing.
1
2
3
If you run it with a CPU type that supports iwMMXt then it will crash
4
immediately with a SIGILL, because (even with -marm) GCC will link it
5
against startup code that is in Thumb mode, and no iwMMXt CPU has
6
Thumb:
7
8
00010338 <_start>:
9
10338: f04f 0b00 mov.w fp, #0
10
1033c: f04f 0e00 mov.w lr, #0
11
12
If you run it with a CPU type which does *not* support iwMMXt, which
13
is what 'make check-tcg' does, then QEMU will not try to handle the
14
insns as iwMMXt. Instead the translator turns them into illegal
15
instructions. Then in the linux-user cpu_loop() code we identify
16
them as FPA11 instructions inside emulate_arm_fpa11(), because the
17
FPA11 happened to use the same coprocessor number as these iwMMXt
18
insns. So we execute a completely different set of FPA11 insns,
19
which means we don't crash, but we will print garbage to stdout.
20
Then the test binary always exits with a 0 return code, so 'make
21
check-tcg' thinks the test passes.
22
23
Modern gnueabihf toolchains assume in their startup code that the CPU
24
is not so old as to not support Thumb, so there's no way to get them
25
to generate a binary that actually does what the test wants. Since
26
we're deprecating iwMMXt emulation anyway, it's not worth trying to
27
salvage the test case to get it to really test the iwMMXt insns.
28
29
Delete the test entirely.
30
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
34
Message-id: 20250127112715.2936555-3-peter.maydell@linaro.org
35
---
36
tests/tcg/arm/Makefile.target | 7 -----
37
tests/tcg/arm/README | 5 ----
38
tests/tcg/arm/test-arm-iwmmxt.S | 49 ---------------------------------
39
3 files changed, 61 deletions(-)
40
delete mode 100644 tests/tcg/arm/test-arm-iwmmxt.S
41
42
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tests/tcg/arm/Makefile.target
45
+++ b/tests/tcg/arm/Makefile.target
46
@@ -XXX,XX +XXX,XX @@ ARM_TESTS = hello-arm
47
hello-arm: CFLAGS+=-marm -ffreestanding -fno-stack-protector
48
hello-arm: LDFLAGS+=-nostdlib
49
50
-# IWMXT floating point extensions
51
-ARM_TESTS += test-arm-iwmmxt
52
-# Clang assembler does not support IWMXT, so use the external assembler.
53
-test-arm-iwmmxt: CFLAGS += -marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 $(CROSS_CC_HAS_FNIA)
54
-test-arm-iwmmxt: test-arm-iwmmxt.S
55
-    $(CC) $(CFLAGS) -Wa,--noexecstack $< -o $@ $(LDFLAGS)
56
-
57
# Float-convert Tests
58
ARM_TESTS += fcvt
59
fcvt: LDFLAGS += -lm
60
diff --git a/tests/tcg/arm/README b/tests/tcg/arm/README
61
index XXXXXXX..XXXXXXX 100644
62
--- a/tests/tcg/arm/README
63
+++ b/tests/tcg/arm/README
64
@@ -XXX,XX +XXX,XX @@ hello-arm
65
---------
66
67
A very simple inline assembly, write syscall based hello world
68
-
69
-test-arm-iwmmxt
70
----------------
71
-
72
-A simple test case for older iwmmxt extended ARMs
73
diff --git a/tests/tcg/arm/test-arm-iwmmxt.S b/tests/tcg/arm/test-arm-iwmmxt.S
74
deleted file mode 100644
75
index XXXXXXX..XXXXXXX
76
--- a/tests/tcg/arm/test-arm-iwmmxt.S
77
+++ /dev/null
78
@@ -XXX,XX +XXX,XX @@
79
-@ Checks whether iwMMXt is functional.
80
-.code    32
81
-.globl    main
82
-
83
-main:
84
-ldr    r0, =data0
85
-ldr    r1, =data1
86
-ldr    r2, =data2
87
-#ifndef FPA
88
-wldrd    wr0, [r0, #0]
89
-wldrd    wr1, [r0, #8]
90
-wldrd    wr2, [r1, #0]
91
-wldrd    wr3, [r1, #8]
92
-wsubb    wr2, wr2, wr0
93
-wsubb    wr3, wr3, wr1
94
-wldrd    wr0, [r2, #0]
95
-wldrd    wr1, [r2, #8]
96
-waddb    wr0, wr0, wr2
97
-waddb    wr1, wr1, wr3
98
-wstrd    wr0, [r2, #0]
99
-wstrd    wr1, [r2, #8]
100
-#else
101
-ldfe    f0, [r0, #0]
102
-ldfe    f1, [r0, #8]
103
-ldfe    f2, [r1, #0]
104
-ldfe    f3, [r1, #8]
105
-adfdp    f2, f2, f0
106
-adfdp    f3, f3, f1
107
-ldfe    f0, [r2, #0]
108
-ldfe    f1, [r2, #8]
109
-adfd    f0, f0, f2
110
-adfd    f1, f1, f3
111
-stfe    f0, [r2, #0]
112
-stfe    f1, [r2, #8]
113
-#endif
114
-mov    r0, #1
115
-mov    r1, r2
116
-mov    r2, #0x11
117
-swi    #0x900004
118
-mov    r0, #0
119
-swi    #0x900001
120
-
121
-.data
122
-data0:
123
-.string    "aaaabbbbccccdddd"
124
-data1:
125
-.string    "bbbbccccddddeeee"
126
-data2:
127
-.string    "hvLLWs\x1fsdrs9\x1fNJ-\n"
128
--
129
2.34.1
130
131
diff view generated by jsdifflib
New patch
[PULL 03/12] target/arm: Drop unused AArch64DecodeTable typedefs
1
We removed the old table-based decoder in favour of decodetree, but
2
we left a couple of typedefs that are now unused; delete them.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20250128135046.4108775-1-peter.maydell@linaro.org
7
---
8
target/arm/tcg/translate-a64.c | 11 -----------
9
1 file changed, 11 deletions(-)
10
11
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/tcg/translate-a64.c
14
+++ b/target/arm/tcg/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static int scale_by_log2_tag_granule(DisasContext *s, int x)
16
#include "decode-sme-fa64.c.inc"
17
#include "decode-a64.c.inc"
18
19
-/* Table based decoder typedefs - used when the relevant bits for decode
20
- * are too awkwardly scattered across the instruction (eg SIMD).
21
- */
22
-typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
23
-
24
-typedef struct AArch64DecodeTable {
25
- uint32_t pattern;
26
- uint32_t mask;
27
- AArch64DecodeFn *disas_fn;
28
-} AArch64DecodeTable;
29
-
30
/* initialize TCG globals. */
31
void a64_translate_init(void)
32
{
33
--
34
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/12] hw/arm/boot: Propagate vCPU to arm_load_dtb()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
In heterogeneous setup the first vCPU might not be
4
the one expected, better pass it explicitly.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20250130112615.3219-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/boot.h | 4 +++-
12
hw/arm/boot.c | 11 ++++++-----
13
hw/arm/virt.c | 2 +-
14
3 files changed, 10 insertions(+), 7 deletions(-)
15
16
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/boot.h
19
+++ b/include/hw/arm/boot.h
20
@@ -XXX,XX +XXX,XX @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
21
* @binfo: struct describing the boot environment
22
* @addr_limit: upper limit of the available memory area at @addr
23
* @as: address space to load image to
24
+ * @cpu: ARM CPU object
25
*
26
* Load a device tree supplied by the machine or by the user with the
27
* '-dtb' command line option, and put it at offset @addr in target
28
@@ -XXX,XX +XXX,XX @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
29
* Note: Must not be called unless have_dtb(binfo) is true.
30
*/
31
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
32
- hwaddr addr_limit, AddressSpace *as, MachineState *ms);
33
+ hwaddr addr_limit, AddressSpace *as, MachineState *ms,
34
+ ARMCPU *cpu);
35
36
/* Write a secure board setup routine with a dummy handler for SMCs */
37
void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
38
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/boot.c
41
+++ b/hw/arm/boot.c
42
@@ -XXX,XX +XXX,XX @@ out:
43
return ret;
44
}
45
46
-static void fdt_add_psci_node(void *fdt)
47
+static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu)
48
{
49
uint32_t cpu_suspend_fn;
50
uint32_t cpu_off_fn;
51
uint32_t cpu_on_fn;
52
uint32_t migrate_fn;
53
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
54
const char *psci_method;
55
int64_t psci_conduit;
56
int rc;
57
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
58
}
59
60
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
61
- hwaddr addr_limit, AddressSpace *as, MachineState *ms)
62
+ hwaddr addr_limit, AddressSpace *as, MachineState *ms,
63
+ ARMCPU *cpu)
64
{
65
void *fdt = NULL;
66
int size, rc, n = 0;
67
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
68
}
69
}
70
71
- fdt_add_psci_node(fdt);
72
+ fdt_add_psci_node(fdt, cpu);
73
74
if (binfo->modify_dtb) {
75
binfo->modify_dtb(binfo, fdt);
76
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
77
* decided whether to enable PSCI and set the psci-conduit CPU properties.
78
*/
79
if (!info->skip_dtb_autoload && have_dtb(info)) {
80
- if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
81
+ if (arm_load_dtb(info->dtb_start, info, info->dtb_limit,
82
+ as, ms, cpu) < 0) {
83
exit(1);
84
}
85
}
86
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/arm/virt.c
89
+++ b/hw/arm/virt.c
90
@@ -XXX,XX +XXX,XX @@ void virt_machine_done(Notifier *notifier, void *data)
91
vms->memmap[VIRT_PLATFORM_BUS].size,
92
vms->irqmap[VIRT_PLATFORM_BUS]);
93
}
94
- if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
95
+ if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
96
exit(1);
97
}
98
99
--
100
2.34.1
101
102
diff view generated by jsdifflib
New patch
[PULL 05/12] hw/arm/fsl-imx6: Add local 'mpcore/gic' variables
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
The A9MPCore forward the IRQs from its internal GIC.
4
To make the code clearer, add the 'mpcore' and 'gic'
5
variables.
6
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20250130112615.3219-3-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/fsl-imx6.c | 52 +++++++++++++++++++----------------------------
13
1 file changed, 21 insertions(+), 31 deletions(-)
14
15
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/fsl-imx6.c
18
+++ b/hw/arm/fsl-imx6.c
19
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
20
uint16_t i;
21
qemu_irq irq;
22
unsigned int smp_cpus = ms->smp.cpus;
23
+ DeviceState *mpcore = DEVICE(&s->a9mpcore);
24
+ DeviceState *gic;
25
26
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
27
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
28
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
29
}
30
}
31
32
- object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus,
33
- &error_abort);
34
+ object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
35
36
- object_property_set_int(OBJECT(&s->a9mpcore), "num-irq",
37
+ object_property_set_int(OBJECT(mpcore), "num-irq",
38
FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
39
40
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) {
41
+ if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) {
42
return;
43
}
44
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
45
+ sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
46
47
+ gic = mpcore;
48
for (i = 0; i < smp_cpus; i++) {
49
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
50
+ sysbus_connect_irq(SYS_BUS_DEVICE(gic), i,
51
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
52
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
53
+ sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus,
54
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
55
}
56
57
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
58
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
61
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
62
- serial_table[i].irq));
63
+ qdev_get_gpio_in(gic, serial_table[i].irq));
64
}
65
66
s->gpt.ccm = IMX_CCM(&s->ccm);
67
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
68
69
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
70
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
71
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
72
- FSL_IMX6_GPT_IRQ));
73
+ qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ));
74
75
/* Initialize all EPIT timers */
76
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
77
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
78
79
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
80
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
81
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
82
- epit_table[i].irq));
83
+ qdev_get_gpio_in(gic, epit_table[i].irq));
84
}
85
86
/* Initialize all I2C */
87
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
88
89
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
90
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
91
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
92
- i2c_table[i].irq));
93
+ qdev_get_gpio_in(gic, i2c_table[i].irq));
94
}
95
96
/* Initialize all GPIOs */
97
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
98
99
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
100
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
101
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
102
- gpio_table[i].irq_low));
103
+ qdev_get_gpio_in(gic, gpio_table[i].irq_low));
104
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
105
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
106
- gpio_table[i].irq_high));
107
+ qdev_get_gpio_in(gic, gpio_table[i].irq_high));
108
}
109
110
/* Initialize all SDHC */
111
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
112
}
113
sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
114
sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
115
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
116
- esdhc_table[i].irq));
117
+ qdev_get_gpio_in(gic, esdhc_table[i].irq));
118
}
119
120
/* USB */
121
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
122
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
123
FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
124
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
125
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
126
- FSL_IMX6_USBn_IRQ[i]));
127
+ qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i]));
128
}
129
130
/* Initialize all ECSPI */
131
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
132
133
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
134
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
135
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
136
- spi_table[i].irq));
137
+ qdev_get_gpio_in(gic, spi_table[i].irq));
138
}
139
140
object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
141
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
142
}
143
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
144
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
145
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
146
- FSL_IMX6_ENET_MAC_IRQ));
147
+ qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ));
148
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
149
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
150
- FSL_IMX6_ENET_MAC_1588_IRQ));
151
+ qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ));
152
153
/*
154
* SNVS
155
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
156
157
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
158
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
159
- qdev_get_gpio_in(DEVICE(&s->a9mpcore),
160
- FSL_IMX6_WDOGn_IRQ[i]));
161
+ qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i]));
162
}
163
164
/*
165
--
166
2.34.1
167
168
diff view generated by jsdifflib
New patch
[PULL 06/12] hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
The A7MPCore forward the IRQs from its internal GIC.
4
To make the code clearer, add the 'mpcore' and 'gic'
5
variables. Rename 'd' variable as 'cpu'.
6
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20250130112615.3219-4-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/fsl-imx6ul.c | 64 +++++++++++++++++++--------------------------
13
1 file changed, 27 insertions(+), 37 deletions(-)
14
15
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/fsl-imx6ul.c
18
+++ b/hw/arm/fsl-imx6ul.c
19
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
20
{
21
MachineState *ms = MACHINE(qdev_get_machine());
22
FslIMX6ULState *s = FSL_IMX6UL(dev);
23
+ DeviceState *mpcore = DEVICE(&s->a7mpcore);
24
int i;
25
char name[NAME_SIZE];
26
- SysBusDevice *sbd;
27
- DeviceState *d;
28
+ DeviceState *gic;
29
+ SysBusDevice *gicsbd;
30
+ DeviceState *cpu;
31
32
if (ms->smp.cpus > 1) {
33
error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
34
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
35
/*
36
* A7MPCORE
37
*/
38
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort);
39
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
40
+ object_property_set_int(OBJECT(mpcore), "num-cpu", 1, &error_abort);
41
+ object_property_set_int(OBJECT(mpcore), "num-irq",
42
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort);
43
- sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
44
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
45
+ sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
46
+ sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
47
48
- sbd = SYS_BUS_DEVICE(&s->a7mpcore);
49
- d = DEVICE(&s->cpu);
50
-
51
- sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ));
52
- sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ));
53
- sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ));
54
- sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ));
55
+ gic = mpcore;
56
+ gicsbd = SYS_BUS_DEVICE(gic);
57
+ cpu = DEVICE(&s->cpu);
58
+ sysbus_connect_irq(gicsbd, 0, qdev_get_gpio_in(cpu, ARM_CPU_IRQ));
59
+ sysbus_connect_irq(gicsbd, 1, qdev_get_gpio_in(cpu, ARM_CPU_FIQ));
60
+ sysbus_connect_irq(gicsbd, 2, qdev_get_gpio_in(cpu, ARM_CPU_VIRQ));
61
+ sysbus_connect_irq(gicsbd, 3, qdev_get_gpio_in(cpu, ARM_CPU_VFIQ));
62
63
/*
64
* A7MPCORE DAP
65
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
66
FSL_IMX6UL_GPTn_ADDR[i]);
67
68
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
69
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
70
- FSL_IMX6UL_GPTn_IRQ[i]));
71
+ qdev_get_gpio_in(gic, FSL_IMX6UL_GPTn_IRQ[i]));
72
}
73
74
/*
75
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
76
FSL_IMX6UL_EPITn_ADDR[i]);
77
78
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
79
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
80
- FSL_IMX6UL_EPITn_IRQ[i]));
81
+ qdev_get_gpio_in(gic, FSL_IMX6UL_EPITn_IRQ[i]));
82
}
83
84
/*
85
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
86
FSL_IMX6UL_GPIOn_ADDR[i]);
87
88
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
89
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
90
- FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
91
+ qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
92
93
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
94
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
95
- FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
96
+ qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
97
}
98
99
/*
100
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
101
FSL_IMX6UL_SPIn_ADDR[i]);
102
103
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
104
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
105
- FSL_IMX6UL_SPIn_IRQ[i]));
106
+ qdev_get_gpio_in(gic, FSL_IMX6UL_SPIn_IRQ[i]));
107
}
108
109
/*
110
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
111
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
112
113
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
114
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
115
- FSL_IMX6UL_I2Cn_IRQ[i]));
116
+ qdev_get_gpio_in(gic, FSL_IMX6UL_I2Cn_IRQ[i]));
117
}
118
119
/*
120
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
121
FSL_IMX6UL_UARTn_ADDR[i]);
122
123
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
124
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
125
- FSL_IMX6UL_UARTn_IRQ[i]));
126
+ qdev_get_gpio_in(gic, FSL_IMX6UL_UARTn_IRQ[i]));
127
}
128
129
/*
130
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
131
FSL_IMX6UL_ENETn_ADDR[i]);
132
133
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
134
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
135
- FSL_IMX6UL_ENETn_IRQ[i]));
136
+ qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_IRQ[i]));
137
138
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
139
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
140
- FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
141
+ qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
142
}
143
144
/*
145
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
146
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
147
FSL_IMX6UL_USB02_USBn_ADDR[i]);
148
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
149
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
150
- FSL_IMX6UL_USBn_IRQ[i]));
151
+ qdev_get_gpio_in(gic, FSL_IMX6UL_USBn_IRQ[i]));
152
}
153
154
/*
155
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
156
FSL_IMX6UL_USDHCn_ADDR[i]);
157
158
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
159
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
160
- FSL_IMX6UL_USDHCn_IRQ[i]));
161
+ qdev_get_gpio_in(gic, FSL_IMX6UL_USDHCn_IRQ[i]));
162
}
163
164
/*
165
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
166
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
167
FSL_IMX6UL_WDOGn_ADDR[i]);
168
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
169
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
170
- FSL_IMX6UL_WDOGn_IRQ[i]));
171
+ qdev_get_gpio_in(gic, FSL_IMX6UL_WDOGn_IRQ[i]));
172
}
173
174
/*
175
--
176
2.34.1
177
178
diff view generated by jsdifflib
New patch
[PULL 07/12] hw/arm/fsl-imx7: Add local 'mpcore/gic' variables
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
The A7MPCore forward the IRQs from its internal GIC.
4
To make the code clearer, add the 'mpcore' and 'gic'
5
variables.
6
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20250130112615.3219-5-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/fsl-imx7.c | 52 +++++++++++++++++++++--------------------------
13
1 file changed, 23 insertions(+), 29 deletions(-)
14
15
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/fsl-imx7.c
18
+++ b/hw/arm/fsl-imx7.c
19
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
20
{
21
MachineState *ms = MACHINE(qdev_get_machine());
22
FslIMX7State *s = FSL_IMX7(dev);
23
- Object *o;
24
+ DeviceState *mpcore = DEVICE(&s->a7mpcore);
25
+ DeviceState *gic;
26
int i;
27
qemu_irq irq;
28
char name[NAME_SIZE];
29
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
30
* CPUs
31
*/
32
for (i = 0; i < smp_cpus; i++) {
33
- o = OBJECT(&s->cpu[i]);
34
+ Object *o = OBJECT(&s->cpu[i]);
35
36
/* On uniprocessor, the CBAR is set to 0 */
37
if (smp_cpus > 1) {
38
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
39
/*
40
* A7MPCORE
41
*/
42
- object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus,
43
- &error_abort);
44
- object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
45
+ object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
46
+ object_property_set_int(OBJECT(mpcore), "num-irq",
47
FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
48
+ sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
49
+ sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
50
51
- sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
52
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
53
-
54
+ gic = mpcore;
55
for (i = 0; i < smp_cpus; i++) {
56
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
57
+ SysBusDevice *sbd = SYS_BUS_DEVICE(gic);
58
DeviceState *d = DEVICE(qemu_get_cpu(i));
59
60
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
61
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
62
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
63
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
64
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
65
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
66
- FSL_IMX7_GPTn_IRQ[i]));
67
+ qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i]));
68
}
69
70
/*
71
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
72
FSL_IMX7_GPIOn_ADDR[i]);
73
74
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
75
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
76
- FSL_IMX7_GPIOn_LOW_IRQ[i]));
77
+ qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i]));
78
79
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
80
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
81
- FSL_IMX7_GPIOn_HIGH_IRQ[i]));
82
+ qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i]));
83
}
84
85
/*
86
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
87
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
88
FSL_IMX7_SPIn_ADDR[i]);
89
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
90
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
91
- FSL_IMX7_SPIn_IRQ[i]));
92
+ qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i]));
93
}
94
95
/*
96
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
97
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
98
99
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
100
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
101
- FSL_IMX7_I2Cn_IRQ[i]));
102
+ qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i]));
103
}
104
105
/*
106
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
107
108
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
109
110
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
111
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]);
112
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
113
}
114
115
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
116
117
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
118
119
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
120
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0));
121
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
122
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
123
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3));
124
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
125
}
126
127
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
128
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
129
FSL_IMX7_USDHCn_ADDR[i]);
130
131
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
132
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]);
133
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
134
}
135
136
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
137
138
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
139
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
140
- qdev_get_gpio_in(DEVICE(&s->a7mpcore),
141
- FSL_IMX7_WDOGn_IRQ[i]));
142
+ qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i]));
143
}
144
145
/*
146
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
147
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ);
148
qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
149
150
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
151
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ);
152
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
153
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
154
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ);
155
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
156
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
157
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ);
158
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
159
irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
160
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
161
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
162
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
163
FSL_IMX7_USBn_ADDR[i]);
164
165
- irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
166
+ irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]);
167
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
168
169
snprintf(name, NAME_SIZE, "usbmisc%d", i);
170
--
171
2.34.1
172
173
diff view generated by jsdifflib
New patch
[PULL 08/12] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
No need to duplicate and forward the 'num-cpu' property from
4
TYPE_ARM11MPCORE_PRIV to TYPE_REALVIEW_MPCORE, alias it with
5
QOM object_property_add_alias().
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Message-id: 20250130112615.3219-6-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/cpu/realview_mpcore.c | 8 +-------
13
1 file changed, 1 insertion(+), 7 deletions(-)
14
15
diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/cpu/realview_mpcore.c
18
+++ b/hw/cpu/realview_mpcore.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/cpu/arm11mpcore.h"
21
#include "hw/intc/realview_gic.h"
22
#include "hw/irq.h"
23
-#include "hw/qdev-properties.h"
24
#include "qom/object.h"
25
26
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
27
@@ -XXX,XX +XXX,XX @@ static void realview_mpcore_realize(DeviceState *dev, Error **errp)
28
int n;
29
int i;
30
31
- qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
32
if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) {
33
return;
34
}
35
@@ -XXX,XX +XXX,XX @@ static void mpcore_rirq_init(Object *obj)
36
int i;
37
38
object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
39
+ object_property_add_alias(obj, "num-cpu", OBJECT(&s->priv), "num-cpu");
40
privbusdev = SYS_BUS_DEVICE(&s->priv);
41
sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
42
43
@@ -XXX,XX +XXX,XX @@ static void mpcore_rirq_init(Object *obj)
44
}
45
}
46
47
-static const Property mpcore_rirq_properties[] = {
48
- DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
49
-};
50
-
51
static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
52
{
53
DeviceClass *dc = DEVICE_CLASS(klass);
54
55
dc->realize = realview_mpcore_realize;
56
- device_class_set_props(dc, mpcore_rirq_properties);
57
}
58
59
static const TypeInfo mpcore_rirq_info = {
60
--
61
2.34.1
62
63
diff view generated by jsdifflib
New patch
[PULL 09/12] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
When multiple QOM types are registered in the same file,
4
it is simpler to use the the DEFINE_TYPES() macro. In
5
particular because type array declared with such macro
6
are easier to review.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
Message-id: 20250130112615.3219-7-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/cpu/a15mpcore.c | 21 +++++++++------------
14
hw/cpu/a9mpcore.c | 21 +++++++++------------
15
hw/cpu/arm11mpcore.c | 21 +++++++++------------
16
hw/cpu/realview_mpcore.c | 21 +++++++++------------
17
4 files changed, 36 insertions(+), 48 deletions(-)
18
19
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/cpu/a15mpcore.c
22
+++ b/hw/cpu/a15mpcore.c
23
@@ -XXX,XX +XXX,XX @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
24
/* We currently have no saveable state */
25
}
26
27
-static const TypeInfo a15mp_priv_info = {
28
- .name = TYPE_A15MPCORE_PRIV,
29
- .parent = TYPE_SYS_BUS_DEVICE,
30
- .instance_size = sizeof(A15MPPrivState),
31
- .instance_init = a15mp_priv_initfn,
32
- .class_init = a15mp_priv_class_init,
33
+static const TypeInfo a15mp_types[] = {
34
+ {
35
+ .name = TYPE_A15MPCORE_PRIV,
36
+ .parent = TYPE_SYS_BUS_DEVICE,
37
+ .instance_size = sizeof(A15MPPrivState),
38
+ .instance_init = a15mp_priv_initfn,
39
+ .class_init = a15mp_priv_class_init,
40
+ },
41
};
42
43
-static void a15mp_register_types(void)
44
-{
45
- type_register_static(&a15mp_priv_info);
46
-}
47
-
48
-type_init(a15mp_register_types)
49
+DEFINE_TYPES(a15mp_types)
50
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/cpu/a9mpcore.c
53
+++ b/hw/cpu/a9mpcore.c
54
@@ -XXX,XX +XXX,XX @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data)
55
device_class_set_props(dc, a9mp_priv_properties);
56
}
57
58
-static const TypeInfo a9mp_priv_info = {
59
- .name = TYPE_A9MPCORE_PRIV,
60
- .parent = TYPE_SYS_BUS_DEVICE,
61
- .instance_size = sizeof(A9MPPrivState),
62
- .instance_init = a9mp_priv_initfn,
63
- .class_init = a9mp_priv_class_init,
64
+static const TypeInfo a9mp_types[] = {
65
+ {
66
+ .name = TYPE_A9MPCORE_PRIV,
67
+ .parent = TYPE_SYS_BUS_DEVICE,
68
+ .instance_size = sizeof(A9MPPrivState),
69
+ .instance_init = a9mp_priv_initfn,
70
+ .class_init = a9mp_priv_class_init,
71
+ },
72
};
73
74
-static void a9mp_register_types(void)
75
-{
76
- type_register_static(&a9mp_priv_info);
77
-}
78
-
79
-type_init(a9mp_register_types)
80
+DEFINE_TYPES(a9mp_types)
81
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/cpu/arm11mpcore.c
84
+++ b/hw/cpu/arm11mpcore.c
85
@@ -XXX,XX +XXX,XX @@ static void mpcore_priv_class_init(ObjectClass *klass, void *data)
86
device_class_set_props(dc, mpcore_priv_properties);
87
}
88
89
-static const TypeInfo mpcore_priv_info = {
90
- .name = TYPE_ARM11MPCORE_PRIV,
91
- .parent = TYPE_SYS_BUS_DEVICE,
92
- .instance_size = sizeof(ARM11MPCorePriveState),
93
- .instance_init = mpcore_priv_initfn,
94
- .class_init = mpcore_priv_class_init,
95
+static const TypeInfo arm11mp_types[] = {
96
+ {
97
+ .name = TYPE_ARM11MPCORE_PRIV,
98
+ .parent = TYPE_SYS_BUS_DEVICE,
99
+ .instance_size = sizeof(ARM11MPCorePriveState),
100
+ .instance_init = mpcore_priv_initfn,
101
+ .class_init = mpcore_priv_class_init,
102
+ },
103
};
104
105
-static void arm11mpcore_register_types(void)
106
-{
107
- type_register_static(&mpcore_priv_info);
108
-}
109
-
110
-type_init(arm11mpcore_register_types)
111
+DEFINE_TYPES(arm11mp_types)
112
diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/hw/cpu/realview_mpcore.c
115
+++ b/hw/cpu/realview_mpcore.c
116
@@ -XXX,XX +XXX,XX @@ static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
117
dc->realize = realview_mpcore_realize;
118
}
119
120
-static const TypeInfo mpcore_rirq_info = {
121
- .name = TYPE_REALVIEW_MPCORE_RIRQ,
122
- .parent = TYPE_SYS_BUS_DEVICE,
123
- .instance_size = sizeof(mpcore_rirq_state),
124
- .instance_init = mpcore_rirq_init,
125
- .class_init = mpcore_rirq_class_init,
126
+static const TypeInfo realview_mpcore_types[] = {
127
+ {
128
+ .name = TYPE_REALVIEW_MPCORE_RIRQ,
129
+ .parent = TYPE_SYS_BUS_DEVICE,
130
+ .instance_size = sizeof(mpcore_rirq_state),
131
+ .instance_init = mpcore_rirq_init,
132
+ .class_init = mpcore_rirq_class_init,
133
+ },
134
};
135
136
-static void realview_mpcore_register_types(void)
137
-{
138
- type_register_static(&mpcore_rirq_info);
139
-}
140
-
141
-type_init(realview_mpcore_register_types)
142
+DEFINE_TYPES(realview_mpcore_types)
143
--
144
2.34.1
145
146
diff view generated by jsdifflib
New patch
[PULL 10/12] hw/net/cadence_gem: Fix the mask/compare/disable-mask logic
1
From: Andrew Yuan <andrew.yuan@jaguarmicro.com>
1
2
3
Our current handling of the mask/compare logic in the Cadence
4
GEM ethernet device is wrong:
5
(1) we load the same byte twice from rx_buf when
6
creating the compare value
7
(2) we ignore the DISABLE_MASK flag
8
9
The "Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev:
10
R1p12 - Doc Rev: 1.3 User Guide" states that if the DISABLE_MASK bit
11
in type2_compare_x_word_1 is set, the mask_value field in
12
type2_compare_x_word_0 is used as an additional 2 byte Compare Value.
13
14
Correct these bugs:
15
* in the !disable_mask codepath, use lduw_le_p() so we
16
correctly load a 16-bit value for comparison
17
* in the disable_mask codepath, we load a full 4-byte value
18
from rx_buf for the comparison, set the compare value to
19
the whole of the cr0 register (i.e. the concatenation of
20
the mask and compare fields), and set mask to 0xffffffff
21
to force a 32-bit comparison
22
23
Signed-off-by: Andrew Yuan <andrew.yuan@jaguarmicro.com>
24
Message-id: 20241219061658.805-1-andrew.yuan@jaguarmicro.com
25
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
[PMM: Expand commit message and comment]
27
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
---
31
hw/net/cadence_gem.c | 26 +++++++++++++++++++++-----
32
1 file changed, 21 insertions(+), 5 deletions(-)
33
34
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/net/cadence_gem.c
37
+++ b/hw/net/cadence_gem.c
38
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
39
40
/* Compare A, B, C */
41
for (j = 0; j < 3; j++) {
42
- uint32_t cr0, cr1, mask, compare;
43
- uint16_t rx_cmp;
44
+ uint32_t cr0, cr1, mask, compare, disable_mask;
45
+ uint32_t rx_cmp;
46
int offset;
47
int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
48
R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
49
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
50
break;
51
}
52
53
- rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
54
- mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
55
- compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
56
+ disable_mask =
57
+ FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, DISABLE_MASK);
58
+ if (disable_mask) {
59
+ /*
60
+ * If disable_mask is set, mask_value is used as an
61
+ * additional 2 byte Compare Value; that is equivalent
62
+ * to using the whole cr0 register as the comparison value.
63
+ * Load 32 bits of data from rx_buf, and set mask to
64
+ * all-ones so we compare all 32 bits.
65
+ */
66
+ rx_cmp = ldl_le_p(rxbuf_ptr + offset);
67
+ mask = 0xFFFFFFFF;
68
+ compare = cr0;
69
+ } else {
70
+ rx_cmp = lduw_le_p(rxbuf_ptr + offset);
71
+ mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
72
+ compare =
73
+ FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
74
+ }
75
76
if ((rx_cmp & mask) == (compare & mask)) {
77
matched = true;
78
--
79
2.34.1
80
81
diff view generated by jsdifflib
New patch
[PULL 11/12] qemu-options: Deprecate -old-param command line option
1
The '-old-param' command line option is specific to Arm targets; it
2
is very briefly documented as "old param mode". What this option
3
actually does is change the behaviour when directly booting a guest
4
kernel, so that command line arguments are passed to the kernel using
5
the extremely old "param_struct" ABI, rather than the newer ATAGS or
6
even newer DTB mechanisms.
1
7
8
This support was added back in 2007 to support an old vendor kernel
9
on the akita/terrier board types:
10
https://mail.gnu.org/archive/html/qemu-devel/2007-07/msg00344.html
11
Even then, it was an out-of-date mechanism from the kernel's
12
point of view -- the kernel has had a comment since 2001 marking
13
it as deprecated. As of mid-2024, the kernel only retained
14
param_struct support for the RiscPC and Footbridge platforms:
15
https://lore.kernel.org/linux-arm-kernel/2831c5a6-cfbf-4fe0-b51c-0396e5b0aeb7@app.fastmail.com/
16
17
None of the board types QEMU supports need param_struct support;
18
mark this option as deprecated.
19
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
22
Message-id: 20250127123113.2947620-1-peter.maydell@linaro.org
23
---
24
docs/about/deprecated.rst | 13 +++++++++++++
25
system/vl.c | 1 +
26
2 files changed, 14 insertions(+)
27
28
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
29
index XXXXXXX..XXXXXXX 100644
30
--- a/docs/about/deprecated.rst
31
+++ b/docs/about/deprecated.rst
32
@@ -XXX,XX +XXX,XX @@ configurations (e.g. -smp drawers=1,books=1,clusters=1 for x86 PC machine) is
33
marked deprecated since 9.0, users have to ensure that all the topology members
34
described with -smp are supported by the target machine.
35
36
+``-old-param`` option for booting Arm kernels via param_struct (since 10.0)
37
+'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
38
+
39
+The ``-old-param`` command line option is specific to Arm targets:
40
+it is used when directly booting a guest kernel to pass it the
41
+command line and other information via the old ``param_struct`` ABI,
42
+rather than the newer ATAGS or DTB mechanisms. This option was only
43
+ever needed to support ancient kernels on some old board types
44
+like the ``akita`` or ``terrier``; it has been deprecated in the
45
+kernel since 2001. None of the board types QEMU supports need
46
+``param_struct`` support, so this option has been deprecated and will
47
+be removed in a future QEMU version.
48
+
49
User-mode emulator command line arguments
50
-----------------------------------------
51
52
diff --git a/system/vl.c b/system/vl.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/system/vl.c
55
+++ b/system/vl.c
56
@@ -XXX,XX +XXX,XX @@ void qemu_init(int argc, char **argv)
57
nb_prom_envs++;
58
break;
59
case QEMU_OPTION_old_param:
60
+ warn_report("-old-param is deprecated");
61
old_param = 1;
62
break;
63
case QEMU_OPTION_rtc:
64
--
65
2.34.1
66
67
diff view generated by jsdifflib
New patch
[PULL 12/12] linux-user: Do not define struct sched_attr if libc headers do
1
From: Khem Raj <raj.khem@gmail.com>
1
2
3
glibc 2.41+ has added [1] definitions for sched_setattr and
4
sched_getattr functions and struct sched_attr. Therefore, it needs
5
to be checked for here as well before defining sched_attr, to avoid
6
a compilation failure.
7
8
Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0 is
9
not defined.
10
11
[1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72707b2a7736cf12190a0;hp=298bc488fdc047da37482f4003023cb9adef78f8
12
13
Signed-off-by: Khem Raj <raj.khem@gmail.com>
14
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2799
15
Cc: qemu-stable@nongnu.org
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
linux-user/syscall.c | 4 +++-
20
1 file changed, 3 insertions(+), 1 deletion(-)
21
22
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/linux-user/syscall.c
25
+++ b/linux-user/syscall.c
26
@@ -XXX,XX +XXX,XX @@ _syscall3(int, sys_sched_getaffinity, pid_t, pid, unsigned int, len,
27
#define __NR_sys_sched_setaffinity __NR_sched_setaffinity
28
_syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len,
29
unsigned long *, user_mask_ptr);
30
-/* sched_attr is not defined in glibc */
31
+/* sched_attr is not defined in glibc < 2.41 */
32
+#ifndef SCHED_ATTR_SIZE_VER0
33
struct sched_attr {
34
uint32_t size;
35
uint32_t sched_policy;
36
@@ -XXX,XX +XXX,XX @@ struct sched_attr {
37
uint32_t sched_util_min;
38
uint32_t sched_util_max;
39
};
40
+#endif
41
#define __NR_sys_sched_getattr __NR_sched_getattr
42
_syscall4(int, sys_sched_getattr, pid_t, pid, struct sched_attr *, attr,
43
unsigned int, size, unsigned int, flags);
44
--
45
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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