[Qemu-devel] [PULL 00/27] target-arm queue
[PULL 0/1] target-arm queue
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v1->v2 changes: drop the sd card-reparenting patch
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The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
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and the 2 raspi2 patches that depend on it.
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-- PMM
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Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
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The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
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are available in the Git repository at:
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Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
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are available in the git repository at:
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for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
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target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
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for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
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hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* raspi2: implement RNG module
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* fix part of the "TCG-disabled builds are broken" issue
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* raspi2: implement new SD card controller (but don't wire it up)
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* sdhci: bugfixes for block transfers
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* virt: fix cpu object reference leak
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* Add missing fp_access_check() to aarch64 crypto instructions
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* cputlb: Don't assume do_unassigned_access() never returns
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* virt: Add a user option to disallow ITS instantiation
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* i.MX timers: fix reset handling
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* ARMv7M NVIC: rewrite to fix broken priority handling and masking
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* exynos: Fix proper mapping of CPUs by providing real cluster ID
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* exynos: Fix Linux kernel division by zero for PLLs
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----------------------------------------------------------------
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----------------------------------------------------------------
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Clement Deschamps (1):
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Philippe Mathieu-Daudé (1):
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bcm2835_sdhost: add bcm2835 sdhost controller
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target/arm/gdbstub: Only advertise M-profile features if TCG available
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Eric Auger (1):
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target/arm/gdbstub.c | 5 +++--
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hw/arm/virt: Add a user option to disallow ITS instantiation
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1 file changed, 3 insertions(+), 2 deletions(-)
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Igor Mammedov (1):
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hw/arm/virt: fix cpu object reference leak
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Krzysztof Kozlowski (2):
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hw/arm/exynos: Fix Linux kernel division by zero for PLLs
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hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
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Kurban Mallachiev (1):
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ARM i.MX timers: fix reset handling
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Marcin Chojnacki (1):
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target-arm: Implement BCM2835 hardware RNG
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Michael Davidsaver (5):
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armv7m: Rewrite NVIC to not use any GIC code
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arm: gic: Remove references to NVIC
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armv7m: Escalate exceptions to HardFault if necessary
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armv7m: Simpler and faster exception start
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armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
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Nick Reilly (1):
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Add missing fp_access_check() to aarch64 crypto instructions
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Peter Maydell (10):
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bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
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cputlb: Don't assume do_unassigned_access() never returns
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armv7m: Rename nvic_state to NVICState
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armv7m: Implement reading and writing of PRIGROUP
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armv7m: Fix condition check for taking exceptions
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armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
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armv7m: Extract "exception taken" code into functions
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armv7m: Check exception return consistency
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armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
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armv7m: Allow SHCSR writes to change pending and active bits
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Prasad J Pandit (4):
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sd: sdhci: mask transfer mode register value
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sd: sdhci: check transfer mode register in multi block transfer
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sd: sdhci: conditionally invoke multi block transfer
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sd: sdhci: Remove block count enable check in single block transfers
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hw/misc/Makefile.objs | 3 +-
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hw/sd/Makefile.objs | 1 +
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hw/intc/gic_internal.h | 7 +-
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include/hw/arm/bcm2835_peripherals.h | 2 +
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include/hw/arm/virt.h | 1 +
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include/hw/misc/bcm2835_rng.h | 27 ++
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include/hw/sd/bcm2835_sdhost.h | 48 ++
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target/arm/cpu.h | 23 +-
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cputlb.c | 15 +-
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hw/arm/bcm2835_peripherals.c | 15 +
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hw/arm/exynos4210.c | 18 +
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hw/arm/virt.c | 32 +-
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hw/intc/arm_gic.c | 31 +-
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hw/intc/arm_gic_common.c | 23 +-
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hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++-------
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hw/misc/bcm2835_rng.c | 149 ++++++
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hw/misc/exynos4210_clk.c | 164 +++++++
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hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++
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hw/sd/sdhci.c | 25 +-
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hw/timer/imx_gpt.c | 33 +-
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linux-user/main.c | 1 +
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target/arm/cpu.c | 16 +-
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target/arm/helper.c | 245 +++++++---
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target/arm/translate-a64.c | 12 +
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target/arm/translate.c | 8 +-
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hw/intc/trace-events | 15 +
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26 files changed, 1897 insertions(+), 331 deletions(-)
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create mode 100644 include/hw/misc/bcm2835_rng.h
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create mode 100644 include/hw/sd/bcm2835_sdhost.h
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create mode 100644 hw/misc/bcm2835_rng.c
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create mode 100644 hw/misc/exynos4210_clk.c
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create mode 100644 hw/sd/bcm2835_sdhost.c
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diff view generated by jsdifflib
New patch
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
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From: Philippe Mathieu-Daudé <philmd@linaro.org>
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Cortex-M profile is only emulable from TCG accelerator. Restrict
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the GDBstub features to its availability in order to avoid a link
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error when TCG is not enabled:
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Undefined symbols for architecture arm64:
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"_arm_v7m_get_sp_ptr", referenced from:
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_m_sysreg_get in target_arm_gdbstub.c.o
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"_arm_v7m_mrs_control", referenced from:
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_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
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ld: symbol(s) not found for architecture arm64
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clang: error: linker command failed with exit code 1 (use -v to see invocation)
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Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20230322142902.69511-3-philmd@linaro.org
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[PMM: add #include since I cherry-picked this patch from the series]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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+#include "sysemu/tcg.h"
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#include "internals.h"
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#include "cpregs.h"
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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2, "arm-vfp-sysregs.xml", 0);
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}
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}
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- if (cpu_isar_feature(aa32_mve, cpu)) {
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+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
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gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
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1, "arm-m-profile-mve.xml", 0);
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}
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
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"system-registers.xml", 0);
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- if (arm_feature(env, ARM_FEATURE_M)) {
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+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
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gdb_register_coprocessor(cs,
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arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
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arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
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--
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2.34.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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