[Qemu-devel] [PULL 00/27] target-arm queue
[PULL 0/3] target-arm queue
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v1->v2 changes: drop the sd card-reparenting patch
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Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code.
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and the 2 raspi2 patches that depend on it.
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2
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-- PMM
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-- PMM
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The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
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The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236:
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Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
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Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801
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for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
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for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc:
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hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
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target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* raspi2: implement RNG module
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* Fix KVM SVE ID register probe code
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* raspi2: implement new SD card controller (but don't wire it up)
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* sdhci: bugfixes for block transfers
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* virt: fix cpu object reference leak
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* Add missing fp_access_check() to aarch64 crypto instructions
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* cputlb: Don't assume do_unassigned_access() never returns
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* virt: Add a user option to disallow ITS instantiation
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* i.MX timers: fix reset handling
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* ARMv7M NVIC: rewrite to fix broken priority handling and masking
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* exynos: Fix proper mapping of CPUs by providing real cluster ID
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* exynos: Fix Linux kernel division by zero for PLLs
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----------------------------------------------------------------
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----------------------------------------------------------------
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Clement Deschamps (1):
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Richard Henderson (3):
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bcm2835_sdhost: add bcm2835 sdhost controller
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target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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target/arm: Move sve probe inside kvm >= 4.15 branch
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Eric Auger (1):
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target/arm/kvm64.c | 45 ++++++++++++++++++++++-----------------------
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hw/arm/virt: Add a user option to disallow ITS instantiation
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1 file changed, 22 insertions(+), 23 deletions(-)
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Igor Mammedov (1):
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hw/arm/virt: fix cpu object reference leak
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Krzysztof Kozlowski (2):
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hw/arm/exynos: Fix Linux kernel division by zero for PLLs
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hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
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Kurban Mallachiev (1):
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ARM i.MX timers: fix reset handling
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Marcin Chojnacki (1):
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target-arm: Implement BCM2835 hardware RNG
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Michael Davidsaver (5):
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armv7m: Rewrite NVIC to not use any GIC code
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arm: gic: Remove references to NVIC
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armv7m: Escalate exceptions to HardFault if necessary
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armv7m: Simpler and faster exception start
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armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
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Nick Reilly (1):
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Add missing fp_access_check() to aarch64 crypto instructions
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Peter Maydell (10):
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bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
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cputlb: Don't assume do_unassigned_access() never returns
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armv7m: Rename nvic_state to NVICState
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armv7m: Implement reading and writing of PRIGROUP
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armv7m: Fix condition check for taking exceptions
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armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
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armv7m: Extract "exception taken" code into functions
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armv7m: Check exception return consistency
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armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
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armv7m: Allow SHCSR writes to change pending and active bits
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Prasad J Pandit (4):
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sd: sdhci: mask transfer mode register value
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sd: sdhci: check transfer mode register in multi block transfer
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sd: sdhci: conditionally invoke multi block transfer
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sd: sdhci: Remove block count enable check in single block transfers
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hw/misc/Makefile.objs | 3 +-
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hw/sd/Makefile.objs | 1 +
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hw/intc/gic_internal.h | 7 +-
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include/hw/arm/bcm2835_peripherals.h | 2 +
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include/hw/arm/virt.h | 1 +
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include/hw/misc/bcm2835_rng.h | 27 ++
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include/hw/sd/bcm2835_sdhost.h | 48 ++
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target/arm/cpu.h | 23 +-
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cputlb.c | 15 +-
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hw/arm/bcm2835_peripherals.c | 15 +
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hw/arm/exynos4210.c | 18 +
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hw/arm/virt.c | 32 +-
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hw/intc/arm_gic.c | 31 +-
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hw/intc/arm_gic_common.c | 23 +-
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hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++-------
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hw/misc/bcm2835_rng.c | 149 ++++++
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hw/misc/exynos4210_clk.c | 164 +++++++
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hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++
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hw/sd/sdhci.c | 25 +-
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hw/timer/imx_gpt.c | 33 +-
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linux-user/main.c | 1 +
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target/arm/cpu.c | 16 +-
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target/arm/helper.c | 245 +++++++---
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target/arm/translate-a64.c | 12 +
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target/arm/translate.c | 8 +-
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hw/intc/trace-events | 15 +
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26 files changed, 1897 insertions(+), 331 deletions(-)
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create mode 100644 include/hw/misc/bcm2835_rng.h
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create mode 100644 include/hw/sd/bcm2835_sdhost.h
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create mode 100644 hw/misc/bcm2835_rng.c
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create mode 100644 hw/misc/exynos4210_clk.c
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create mode 100644 hw/sd/bcm2835_sdhost.c
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diff view generated by jsdifflib
New patch
[PULL 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features
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From: Richard Henderson <richard.henderson@linaro.org>
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2
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Indication for support for SVE will not depend on whether we
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perform the query on the main kvm_state or the temp vcpu.
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-2-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
19
}
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}
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- sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
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+ sve_supported = kvm_arm_sve_supported();
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/* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host
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From: Richard Henderson <richard.henderson@linaro.org>
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2
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Because we weren't setting this flag, our probe of ID_AA64ZFR0
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was always returning zero. This also obviates the adjustment
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of ID_AA64PFR0, which had sanitized the SVE field.
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The effects of the bug are not visible, because the only thing that
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ID_AA64ZFR0 is used for within qemu at present is tcg translation.
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The other tests for SVE within KVM are via ID_AA64PFR0.SVE.
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Reported-by: Zenghui Yu <yuzenghui@huawei.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-3-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 27 +++++++++++++--------------
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1 file changed, 13 insertions(+), 14 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
23
+++ b/target/arm/kvm64.c
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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- uint64_t t;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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- * Ask for Pointer Authentication if supported. We can't play the
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- * SVE trick of synthesising the ID reg as KVM won't tell us
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- * whether we have the architected or IMPDEF version of PAuth, so
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- * we have to use the actual ID regs.
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+ * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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+ * which is otherwise RAZ.
42
+ */
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+ sve_supported = kvm_arm_sve_supported();
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+ if (sve_supported) {
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+ init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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+ }
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+
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+ /*
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+ * Ask for Pointer Authentication if supported, so that we get
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+ * the unsanitized field values for AA64ISAR1_EL1.
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*/
52
if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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}
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}
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- sve_supported = kvm_arm_sve_supported();
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-
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- /* Add feature bits that can't appear until after VCPU init. */
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if (sve_supported) {
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- t = ahcf->isar.id_aa64pfr0;
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- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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- ahcf->isar.id_aa64pfr0 = t;
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-
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, so we only read it here, rather than together with all
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- * the other ID registers earlier.
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+ * SVE support, which resulted in an error rather than RAZ.
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+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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--
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2.25.1
diff view generated by jsdifflib
New patch
[PULL 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch
1
From: Richard Henderson <richard.henderson@linaro.org>
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2
3
The test for the IF block indicates no ID registers are exposed, much
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less host support for SVE. Move the SVE probe into the ELSE block.
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6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20220726045828.53697-4-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/kvm64.c | 22 +++++++++++-----------
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1 file changed, 11 insertions(+), 11 deletions(-)
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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- }
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- if (sve_supported) {
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- /*
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- * There is a range of kernels between kernel commit 73433762fcae
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- * and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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- * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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- * SVE support, which resulted in an error rather than RAZ.
30
- * So only read the register if we set KVM_ARM_VCPU_SVE above.
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- */
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- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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- ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ if (sve_supported) {
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+ /*
36
+ * There is a range of kernels between kernel commit 73433762fcae
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+ * and f81cb2c3ad41 which have a bug where the kernel doesn't
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+ * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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+ * enabled SVE support, which resulted in an error rather than RAZ.
40
+ * So only read the register if we set KVM_ARM_VCPU_SVE above.
41
+ */
42
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
43
+ ARM64_SYS_REG(3, 0, 0, 4, 4));
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+ }
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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