Series comparison

-[Qemu-devel] [PULL 00/27] target-arm queue
+[PULL v2 00/11] target-arm queue
-v1->v2 changes: drop the sd card-reparenting patch
+Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
-and the 2 raspi2 patches that depend on it.
+ethernet device failed 'make check' on big-endian hosts.
 -- PMM
-The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
+The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:
-  Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
+  Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)
-are available in the git repository at:
+are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1
-for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
+for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:
-  hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
+  target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * raspi2: implement RNG module
+ * Correctly initialize MDCR_EL2.HPMN
- * raspi2: implement new SD card controller (but don't wire it up)
+ * versal: Use nr_apu_cpus in favor of hard coding 2
- * sdhci: bugfixes for block transfers
+ * accel/tcg: Add URL of clang bug to comment about our workaround
- * virt: fix cpu object reference leak
+ * Add support for FEAT_DIT, Data Independent Timing
- * Add missing fp_access_check() to aarch64 crypto instructions
+ * Remove GPIO from unimplemented NPCM7XX
- * cputlb: Don't assume do_unassigned_access() never returns
+ * Fix SCR RES1 handling
- * virt: Add a user option to disallow ITS instantiation
+ * Don't migrate CPUARMState.features
  * i.MX timers: fix reset handling
  * ARMv7M NVIC: rewrite to fix broken priority handling and masking
  * exynos: Fix proper mapping of CPUs by providing real cluster ID
  * exynos: Fix Linux kernel division by zero for PLLs
 ----------------------------------------------------------------
-Clement Deschamps (1):
+Aaron Lindsay (1):
-      bcm2835_sdhost: add bcm2835 sdhost controller
+      target/arm: Don't migrate CPUARMState.features
-Eric Auger (1):
+Daniel Müller (1):
-      hw/arm/virt: Add a user option to disallow ITS instantiation
+      target/arm: Correctly initialize MDCR_EL2.HPMN
-Igor Mammedov (1):
+Edgar E. Iglesias (1):
-      hw/arm/virt: fix cpu object reference leak
+      hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
-Krzysztof Kozlowski (2):
+Hao Wu (1):
-      hw/arm/exynos: Fix Linux kernel division by zero for PLLs
+      hw/arm: Remove GPIO from unimplemented NPCM7XX
       hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
-Kurban Mallachiev (1):
+Mike Nawrocki (1):
-      ARM i.MX timers: fix reset handling
+      target/arm: Fix SCR RES1 handling
-Marcin Chojnacki (1):
+Peter Maydell (2):
-      target-arm: Implement BCM2835 hardware RNG
+      arm: Update infocenter.arm.com URLs
       accel/tcg: Add URL of clang bug to comment about our workaround
-Michael Davidsaver (5):
+Rebecca Cran (4):
-      armv7m: Rewrite NVIC to not use any GIC code
+      target/arm: Add support for FEAT_DIT, Data Independent Timing
-      arm: gic: Remove references to NVIC
+      target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
-      armv7m: Escalate exceptions to HardFault if necessary
+      target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
-      armv7m: Simpler and faster exception start
+      target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
       armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
-Nick Reilly (1):
+ include/hw/dma/pl080.h                 |  7 ++--
-      Add missing fp_access_check() to aarch64 crypto instructions
+ include/hw/misc/arm_integrator_debug.h |  2 +-
  include/hw/ssi/pl022.h                 |  5 ++-
  target/arm/cpu.h                       | 17 ++++++++
  target/arm/internals.h                 |  6 +++
  accel/tcg/cpu-exec.c                   | 25 +++++++++---
  hw/arm/aspeed_ast2600.c                |  2 +-
  hw/arm/musca.c                         |  4 +-
  hw/arm/npcm7xx.c                       |  8 ----
  hw/arm/xlnx-versal.c                   |  4 +-
  hw/misc/arm_integrator_debug.c         |  2 +-
  hw/timer/arm_timer.c                   |  7 ++--
  target/arm/cpu.c                       |  4 ++
  target/arm/cpu64.c                     |  5 +++
  target/arm/helper-a64.c                | 27 +++++++++++--
  target/arm/helper.c                    | 71 +++++++++++++++++++++++++++-------
  target/arm/machine.c                   |  2 +-
  target/arm/op_helper.c                 |  9 +----
  target/arm/translate-a64.c             | 12 ++++++
 files changed, 164 insertions(+), 55 deletions(-)
-Peter Maydell (10):
-      bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
-      cputlb: Don't assume do_unassigned_access() never returns
-      armv7m: Rename nvic_state to NVICState
-      armv7m: Implement reading and writing of PRIGROUP
-      armv7m: Fix condition check for taking exceptions
-      armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
-      armv7m: Extract "exception taken" code into functions
-      armv7m: Check exception return consistency
-      armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
-      armv7m: Allow SHCSR writes to change pending and active bits
-Prasad J Pandit (4):
-      sd: sdhci: mask transfer mode register value
-      sd: sdhci: check transfer mode register in multi block transfer
-      sd: sdhci: conditionally invoke multi block transfer
-      sd: sdhci: Remove block count enable check in single block transfers
- hw/misc/Makefile.objs                |   3 +-
- hw/sd/Makefile.objs                  |   1 +
- hw/intc/gic_internal.h               |   7 +-
- include/hw/arm/bcm2835_peripherals.h |   2 +
- include/hw/arm/virt.h                |   1 +
- include/hw/misc/bcm2835_rng.h        |  27 ++
- include/hw/sd/bcm2835_sdhost.h       |  48 ++
- target/arm/cpu.h                     |  23 +-
- cputlb.c                             |  15 +-
- hw/arm/bcm2835_peripherals.c         |  15 +
- hw/arm/exynos4210.c                  |  18 +
- hw/arm/virt.c                        |  32 +-
- hw/intc/arm_gic.c                    |  31 +-
- hw/intc/arm_gic_common.c             |  23 +-
- hw/intc/armv7m_nvic.c                | 885 ++++++++++++++++++++++++++++-------
- hw/misc/bcm2835_rng.c                | 149 ++++++
- hw/misc/exynos4210_clk.c             | 164 +++++++
- hw/sd/bcm2835_sdhost.c               | 429 +++++++++++++++++
- hw/sd/sdhci.c                        |  25 +-
- hw/timer/imx_gpt.c                   |  33 +-
- linux-user/main.c                    |   1 +
- target/arm/cpu.c                     |  16 +-
- target/arm/helper.c                  | 245 +++++++---
- target/arm/translate-a64.c           |  12 +
- target/arm/translate.c               |   8 +-
- hw/intc/trace-events                 |  15 +
-files changed, 1897 insertions(+), 331 deletions(-)
- create mode 100644 include/hw/misc/bcm2835_rng.h
- create mode 100644 include/hw/sd/bcm2835_sdhost.h
- create mode 100644 hw/misc/bcm2835_rng.c
- create mode 100644 hw/misc/exynos4210_clk.c
- create mode 100644 hw/sd/bcm2835_sdhost.c

v1->v2 changes: drop the sd card-reparenting patch
and the 2 raspi2 patches that depend on it.

-- PMM

The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:

Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228

for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:

hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)

----------------------------------------------------------------
target-arm queue:
 * raspi2: implement RNG module
 * raspi2: implement new SD card controller (but don't wire it up)
 * sdhci: bugfixes for block transfers
 * virt: fix cpu object reference leak
 * Add missing fp_access_check() to aarch64 crypto instructions
 * cputlb: Don't assume do_unassigned_access() never returns
 * virt: Add a user option to disallow ITS instantiation
 * i.MX timers: fix reset handling
 * ARMv7M NVIC: rewrite to fix broken priority handling and masking
 * exynos: Fix proper mapping of CPUs by providing real cluster ID
 * exynos: Fix Linux kernel division by zero for PLLs

----------------------------------------------------------------
Clement Deschamps (1):
      bcm2835_sdhost: add bcm2835 sdhost controller

Eric Auger (1):
      hw/arm/virt: Add a user option to disallow ITS instantiation

Igor Mammedov (1):
      hw/arm/virt: fix cpu object reference leak

Krzysztof Kozlowski (2):
      hw/arm/exynos: Fix Linux kernel division by zero for PLLs
      hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID

Kurban Mallachiev (1):
      ARM i.MX timers: fix reset handling

Marcin Chojnacki (1):
      target-arm: Implement BCM2835 hardware RNG

Michael Davidsaver (5):
      armv7m: Rewrite NVIC to not use any GIC code
      arm: gic: Remove references to NVIC
      armv7m: Escalate exceptions to HardFault if necessary
      armv7m: Simpler and faster exception start
      armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE

Nick Reilly (1):
      Add missing fp_access_check() to aarch64 crypto instructions

Peter Maydell (10):
      bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
      cputlb: Don't assume do_unassigned_access() never returns
      armv7m: Rename nvic_state to NVICState
      armv7m: Implement reading and writing of PRIGROUP
      armv7m: Fix condition check for taking exceptions
      armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
      armv7m: Extract "exception taken" code into functions
      armv7m: Check exception return consistency
      armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
      armv7m: Allow SHCSR writes to change pending and active bits

Prasad J Pandit (4):
      sd: sdhci: mask transfer mode register value
      sd: sdhci: check transfer mode register in multi block transfer
      sd: sdhci: conditionally invoke multi block transfer
      sd: sdhci: Remove block count enable check in single block transfers

Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx
ethernet device failed 'make check' on big-endian hosts.

-- PMM

The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf:

Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1

for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621:

target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000)

----------------------------------------------------------------
target-arm queue:
 * Correctly initialize MDCR_EL2.HPMN
 * versal: Use nr_apu_cpus in favor of hard coding 2
 * accel/tcg: Add URL of clang bug to comment about our workaround
 * Add support for FEAT_DIT, Data Independent Timing
 * Remove GPIO from unimplemented NPCM7XX
 * Fix SCR RES1 handling
 * Don't migrate CPUARMState.features

----------------------------------------------------------------
Aaron Lindsay (1):
      target/arm: Don't migrate CPUARMState.features

Daniel Müller (1):
      target/arm: Correctly initialize MDCR_EL2.HPMN

Edgar E. Iglesias (1):
      hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2

Hao Wu (1):
      hw/arm: Remove GPIO from unimplemented NPCM7XX

Mike Nawrocki (1):
      target/arm: Fix SCR RES1 handling

Peter Maydell (2):
      arm: Update infocenter.arm.com URLs
      accel/tcg: Add URL of clang bug to comment about our workaround

Rebecca Cran (4):
      target/arm: Add support for FEAT_DIT, Data Independent Timing
      target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
      target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
      target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU