| 1 | v1->v2 changes: drop the sd card-reparenting patch | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | and the 2 raspi2 patches that depend on it. | ||
| 3 | 2 | ||
| 4 | -- PMM | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 5 | 4 | ||
| 6 | The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606: | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 7 | 6 | ||
| 8 | Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000) | 7 | are available in the Git repository at: |
| 9 | 8 | ||
| 10 | are available in the git repository at: | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 11 | 10 | ||
| 12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228 | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 13 | 12 | ||
| 14 | for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61: | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 15 | |||
| 16 | hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000) | ||
| 17 | 14 | ||
| 18 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 16 | target-arm queue: |
| 20 | * raspi2: implement RNG module | 17 | * Implement IMPDEF pauth algorithm |
| 21 | * raspi2: implement new SD card controller (but don't wire it up) | 18 | * Support ARMv8.4-SEL2 |
| 22 | * sdhci: bugfixes for block transfers | 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns |
| 23 | * virt: fix cpu object reference leak | 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 24 | * Add missing fp_access_check() to aarch64 crypto instructions | 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 25 | * cputlb: Don't assume do_unassigned_access() never returns | 22 | * docs: Build and install all the docs in a single manual |
| 26 | * virt: Add a user option to disallow ITS instantiation | ||
| 27 | * i.MX timers: fix reset handling | ||
| 28 | * ARMv7M NVIC: rewrite to fix broken priority handling and masking | ||
| 29 | * exynos: Fix proper mapping of CPUs by providing real cluster ID | ||
| 30 | * exynos: Fix Linux kernel division by zero for PLLs | ||
| 31 | 23 | ||
| 32 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 33 | Clement Deschamps (1): | 25 | Gan Qixin (1): |
| 34 | bcm2835_sdhost: add bcm2835 sdhost controller | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 35 | 27 | ||
| 36 | Eric Auger (1): | 28 | Peter Maydell (1): |
| 37 | hw/arm/virt: Add a user option to disallow ITS instantiation | 29 | docs: Build and install all the docs in a single manual |
| 38 | 30 | ||
| 39 | Igor Mammedov (1): | 31 | Philippe Mathieu-Daudé (1): |
| 40 | hw/arm/virt: fix cpu object reference leak | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 41 | 33 | ||
| 42 | Krzysztof Kozlowski (2): | 34 | Richard Henderson (7): |
| 43 | hw/arm/exynos: Fix Linux kernel division by zero for PLLs | 35 | target/arm: Implement an IMPDEF pauth algorithm |
| 44 | hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID | 36 | target/arm: Add cpu properties to control pauth |
| 37 | target/arm: Use object_property_add_bool for "sve" property | ||
| 38 | target/arm: Introduce PREDDESC field definitions | ||
| 39 | target/arm: Update PFIRST, PNEXT for pred_desc | ||
| 40 | target/arm: Update ZIP, UZP, TRN for pred_desc | ||
| 41 | target/arm: Update REV, PUNPK for pred_desc | ||
| 45 | 42 | ||
| 46 | Kurban Mallachiev (1): | 43 | Rémi Denis-Courmont (19): |
| 47 | ARM i.MX timers: fix reset handling | 44 | target/arm: remove redundant tests |
| 45 | target/arm: add arm_is_el2_enabled() helper | ||
| 46 | target/arm: use arm_is_el2_enabled() where applicable | ||
| 47 | target/arm: use arm_hcr_el2_eff() where applicable | ||
| 48 | target/arm: factor MDCR_EL2 common handling | ||
| 49 | target/arm: Define isar_feature function to test for presence of SEL2 | ||
| 50 | target/arm: add 64-bit S-EL2 to EL exception table | ||
| 51 | target/arm: add MMU stage 1 for Secure EL2 | ||
| 52 | target/arm: add ARMv8.4-SEL2 system registers | ||
| 53 | target/arm: handle VMID change in secure state | ||
| 54 | target/arm: do S1_ptw_translate() before address space lookup | ||
| 55 | target/arm: translate NS bit in page-walks | ||
| 56 | target/arm: generalize 2-stage page-walk condition | ||
| 57 | target/arm: secure stage 2 translation regime | ||
| 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | ||
| 59 | target/arm: revector to run-time pick target EL | ||
| 60 | target/arm: Implement SCR_EL2.EEL2 | ||
| 61 | target/arm: enable Secure EL2 in max CPU | ||
| 62 | target/arm: refactor vae1_tlbmask() | ||
| 48 | 63 | ||
| 49 | Marcin Chojnacki (1): | 64 | docs/conf.py | 46 ++++- |
| 50 | target-arm: Implement BCM2835 hardware RNG | 65 | docs/devel/conf.py | 15 -- |
| 66 | docs/index.html.in | 17 -- | ||
| 67 | docs/interop/conf.py | 28 --- | ||
| 68 | docs/meson.build | 64 +++--- | ||
| 69 | docs/specs/conf.py | 16 -- | ||
| 70 | docs/system/arm/cpu-features.rst | 21 ++ | ||
| 71 | docs/system/conf.py | 28 --- | ||
| 72 | docs/tools/conf.py | 37 ---- | ||
| 73 | docs/user/conf.py | 15 -- | ||
| 74 | include/qemu/xxhash.h | 98 +++++++++ | ||
| 75 | target/arm/cpu-param.h | 2 +- | ||
| 76 | target/arm/cpu.h | 107 ++++++++-- | ||
| 77 | target/arm/internals.h | 45 +++++ | ||
| 78 | target/arm/cpu.c | 23 ++- | ||
| 79 | target/arm/cpu64.c | 65 ++++-- | ||
| 80 | target/arm/helper-a64.c | 8 +- | ||
| 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- | ||
| 82 | target/arm/m_helper.c | 2 +- | ||
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 51 | 102 | ||
| 52 | Michael Davidsaver (5): | ||
| 53 | armv7m: Rewrite NVIC to not use any GIC code | ||
| 54 | arm: gic: Remove references to NVIC | ||
| 55 | armv7m: Escalate exceptions to HardFault if necessary | ||
| 56 | armv7m: Simpler and faster exception start | ||
| 57 | armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE | ||
| 58 | |||
| 59 | Nick Reilly (1): | ||
| 60 | Add missing fp_access_check() to aarch64 crypto instructions | ||
| 61 | |||
| 62 | Peter Maydell (10): | ||
| 63 | bcm2835_rng: Use qcrypto_random_bytes() rather than rand() | ||
| 64 | cputlb: Don't assume do_unassigned_access() never returns | ||
| 65 | armv7m: Rename nvic_state to NVICState | ||
| 66 | armv7m: Implement reading and writing of PRIGROUP | ||
| 67 | armv7m: Fix condition check for taking exceptions | ||
| 68 | armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value | ||
| 69 | armv7m: Extract "exception taken" code into functions | ||
| 70 | armv7m: Check exception return consistency | ||
| 71 | armv7m: Raise correct kind of UsageFault for attempts to execute ARM code | ||
| 72 | armv7m: Allow SHCSR writes to change pending and active bits | ||
| 73 | |||
| 74 | Prasad J Pandit (4): | ||
| 75 | sd: sdhci: mask transfer mode register value | ||
| 76 | sd: sdhci: check transfer mode register in multi block transfer | ||
| 77 | sd: sdhci: conditionally invoke multi block transfer | ||
| 78 | sd: sdhci: Remove block count enable check in single block transfers | ||
| 79 | |||
| 80 | hw/misc/Makefile.objs | 3 +- | ||
| 81 | hw/sd/Makefile.objs | 1 + | ||
| 82 | hw/intc/gic_internal.h | 7 +- | ||
| 83 | include/hw/arm/bcm2835_peripherals.h | 2 + | ||
| 84 | include/hw/arm/virt.h | 1 + | ||
| 85 | include/hw/misc/bcm2835_rng.h | 27 ++ | ||
| 86 | include/hw/sd/bcm2835_sdhost.h | 48 ++ | ||
| 87 | target/arm/cpu.h | 23 +- | ||
| 88 | cputlb.c | 15 +- | ||
| 89 | hw/arm/bcm2835_peripherals.c | 15 + | ||
| 90 | hw/arm/exynos4210.c | 18 + | ||
| 91 | hw/arm/virt.c | 32 +- | ||
| 92 | hw/intc/arm_gic.c | 31 +- | ||
| 93 | hw/intc/arm_gic_common.c | 23 +- | ||
| 94 | hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++------- | ||
| 95 | hw/misc/bcm2835_rng.c | 149 ++++++ | ||
| 96 | hw/misc/exynos4210_clk.c | 164 +++++++ | ||
| 97 | hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++ | ||
| 98 | hw/sd/sdhci.c | 25 +- | ||
| 99 | hw/timer/imx_gpt.c | 33 +- | ||
| 100 | linux-user/main.c | 1 + | ||
| 101 | target/arm/cpu.c | 16 +- | ||
| 102 | target/arm/helper.c | 245 +++++++--- | ||
| 103 | target/arm/translate-a64.c | 12 + | ||
| 104 | target/arm/translate.c | 8 +- | ||
| 105 | hw/intc/trace-events | 15 + | ||
| 106 | 26 files changed, 1897 insertions(+), 331 deletions(-) | ||
| 107 | create mode 100644 include/hw/misc/bcm2835_rng.h | ||
| 108 | create mode 100644 include/hw/sd/bcm2835_sdhost.h | ||
| 109 | create mode 100644 hw/misc/bcm2835_rng.c | ||
| 110 | create mode 100644 hw/misc/exynos4210_clk.c | ||
| 111 | create mode 100644 hw/sd/bcm2835_sdhost.c | ||
| 112 | diff view generated by jsdifflib |