[Qemu-devel] [PULL 00/27] target-arm queue
[Qemu-devel] [PULL 00/17] target-arm queue
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v1->v2 changes: drop the sd card-reparenting patch
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v2: dropped a couple of cadence_gem changes to ID regs that
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and the 2 raspi2 patches that depend on it.
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caused new clang sanitizer warnings.
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-- PMM
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-- PMM
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The following changes since commit 6181478f6395cdd9d6ffd99623d0c9f39ea53606:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2017-02-28 08:46:03 +0000)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170228
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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for you to fetch changes up to f3a6339a5bbc160d327299c67bb68c6d07fa4a61:
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID (2017-02-28 12:08:20 +0000)
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* raspi2: implement RNG module
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* raspi2: implement new SD card controller (but don't wire it up)
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* sdhci: bugfixes for block transfers
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* target/arm: Define fields of ISAR registers
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* virt: fix cpu object reference leak
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* target/arm: Align cortex-r5 id_isar0
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* Add missing fp_access_check() to aarch64 crypto instructions
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* target/arm: Fix cortex-a7 id_isar0
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* cputlb: Don't assume do_unassigned_access() never returns
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* net/cadence_gem: Fix various bugs, add support for new
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* virt: Add a user option to disallow ITS instantiation
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features that will be used by the Xilinx Versal board
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* i.MX timers: fix reset handling
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* ARMv7M NVIC: rewrite to fix broken priority handling and masking
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* target/arm: Add the Cortex-A72
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* exynos: Fix proper mapping of CPUs by providing real cluster ID
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* exynos: Fix Linux kernel division by zero for PLLs
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Clement Deschamps (1):
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Aaron Lindsay (2):
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bcm2835_sdhost: add bcm2835 sdhost controller
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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target/arm: Mask PMOVSR writes based on supported counters
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Eric Auger (1):
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Edgar E. Iglesias (8):
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hw/arm/virt: Add a user option to disallow ITS instantiation
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net: cadence_gem: Disable TSU feature bit
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Igor Mammedov (1):
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Jerome Forissier (1):
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hw/arm/virt: fix cpu object reference leak
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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Krzysztof Kozlowski (2):
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Peter Maydell (2):
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hw/arm/exynos: Fix Linux kernel division by zero for PLLs
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Kurban Mallachiev (1):
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Richard Henderson (4):
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ARM i.MX timers: fix reset handling
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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Marcin Chojnacki (1):
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include/hw/net/cadence_gem.h | 7 +-
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target-arm: Implement BCM2835 hardware RNG
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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Michael Davidsaver (5):
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armv7m: Rewrite NVIC to not use any GIC code
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arm: gic: Remove references to NVIC
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armv7m: Escalate exceptions to HardFault if necessary
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armv7m: Simpler and faster exception start
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armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
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Nick Reilly (1):
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Add missing fp_access_check() to aarch64 crypto instructions
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Peter Maydell (10):
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bcm2835_rng: Use qcrypto_random_bytes() rather than rand()
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cputlb: Don't assume do_unassigned_access() never returns
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armv7m: Rename nvic_state to NVICState
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armv7m: Implement reading and writing of PRIGROUP
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armv7m: Fix condition check for taking exceptions
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armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
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armv7m: Extract "exception taken" code into functions
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armv7m: Check exception return consistency
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armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
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armv7m: Allow SHCSR writes to change pending and active bits
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Prasad J Pandit (4):
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sd: sdhci: mask transfer mode register value
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sd: sdhci: check transfer mode register in multi block transfer
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sd: sdhci: conditionally invoke multi block transfer
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sd: sdhci: Remove block count enable check in single block transfers
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hw/misc/Makefile.objs | 3 +-
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hw/sd/Makefile.objs | 1 +
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hw/intc/gic_internal.h | 7 +-
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include/hw/arm/bcm2835_peripherals.h | 2 +
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include/hw/arm/virt.h | 1 +
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include/hw/misc/bcm2835_rng.h | 27 ++
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include/hw/sd/bcm2835_sdhost.h | 48 ++
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target/arm/cpu.h | 23 +-
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cputlb.c | 15 +-
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hw/arm/bcm2835_peripherals.c | 15 +
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hw/arm/exynos4210.c | 18 +
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hw/arm/virt.c | 32 +-
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hw/intc/arm_gic.c | 31 +-
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hw/intc/arm_gic_common.c | 23 +-
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hw/intc/armv7m_nvic.c | 885 ++++++++++++++++++++++++++++-------
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hw/misc/bcm2835_rng.c | 149 ++++++
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hw/misc/exynos4210_clk.c | 164 +++++++
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hw/sd/bcm2835_sdhost.c | 429 +++++++++++++++++
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hw/sd/sdhci.c | 25 +-
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hw/timer/imx_gpt.c | 33 +-
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linux-user/main.c | 1 +
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target/arm/cpu.c | 16 +-
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target/arm/helper.c | 245 +++++++---
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target/arm/translate-a64.c | 12 +
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target/arm/translate.c | 8 +-
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hw/intc/trace-events | 15 +
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26 files changed, 1897 insertions(+), 331 deletions(-)
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create mode 100644 include/hw/misc/bcm2835_rng.h
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create mode 100644 include/hw/sd/bcm2835_sdhost.h
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create mode 100644 hw/misc/bcm2835_rng.c
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create mode 100644 hw/misc/exynos4210_clk.c
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create mode 100644 hw/sd/bcm2835_sdhost.c
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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