[Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15

Nikunj A Dadhania posted 10 patches 7 years, 2 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/1487763883-4877-1-git-send-email-nikunj@linux.vnet.ibm.com
Test checkpatch passed
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There is a newer version of this series
target/ppc/Makefile.objs    |   1 +
target/ppc/cpu.c            |  51 ++++++++++++++++++
target/ppc/cpu.h            |  21 ++++----
target/ppc/int_helper.c     |  53 +++++++-----------
target/ppc/translate.c      | 128 ++++++++++++++++++++++++++++++++++++++------
target/ppc/translate_init.c |   4 +-
6 files changed, 194 insertions(+), 64 deletions(-)
create mode 100644 target/ppc/cpu.c
[Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15
Posted by Nikunj A Dadhania 7 years, 2 months ago
This series contains implentation of CA32 and OV32 bits added to the 
ISA 3.0. Various fixed-point arithmetic instructions are updated to take
care of the newer flags. 

Finally the last patch adds new instruction mcrxrx, that helps reading 
the carry (CA and CA32) and the overflow (OV and OV32) flags

Changelog:
v2: 
* Add missing condition in narrow mode(add/subf), multiply and divide
* Drop nego patch, subf implementation is sufficient for setting OV and OV32
* Retaining neg[.], as the code is simplified.
* Fix OV resetting in compute_ov()

v1: 
* Use these ISA 3.0 flag to enable CA32 and OV32
* Re-write ca32 compute routine
* Add setting of flags for "neg." and "nego."

Nikunj A Dadhania (10):
  target/ppc: move cpu_[read, write]_xer to cpu.c
  target/ppc: optimize gen_write_xer()
  target/ppc: support for 32-bit carry and overflow
  target/ppc: update ca32 in arithmetic add
  target/ppc: update ca32 in arithmetic substract
  target/ppc: update overflow flags for add/sub
  target/ppc: use tcg ops for neg instruction
  target/ppc: add ov32 flag for multiply low insns
  target/ppc: add ov32 flag in divide operations
  target/ppc: add mcrxrx instruction

 target/ppc/Makefile.objs    |   1 +
 target/ppc/cpu.c            |  51 ++++++++++++++++++
 target/ppc/cpu.h            |  21 ++++----
 target/ppc/int_helper.c     |  53 +++++++-----------
 target/ppc/translate.c      | 128 ++++++++++++++++++++++++++++++++++++++------
 target/ppc/translate_init.c |   4 +-
 6 files changed, 194 insertions(+), 64 deletions(-)
 create mode 100644 target/ppc/cpu.c

-- 
2.7.4


Re: [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15
Posted by David Gibson 7 years, 2 months ago
On Wed, Feb 22, 2017 at 05:14:33PM +0530, Nikunj A Dadhania wrote:
> This series contains implentation of CA32 and OV32 bits added to the 
> ISA 3.0. Various fixed-point arithmetic instructions are updated to take
> care of the newer flags. 
> 
> Finally the last patch adds new instruction mcrxrx, that helps reading 
> the carry (CA and CA32) and the overflow (OV and OV32) flags

I've applied patches 1 & 2 to ppc-for-2.9.

The rest I've left for a resend pending my comments and rth's.

> 
> Changelog:
> v2: 
> * Add missing condition in narrow mode(add/subf), multiply and divide
> * Drop nego patch, subf implementation is sufficient for setting OV and OV32
> * Retaining neg[.], as the code is simplified.
> * Fix OV resetting in compute_ov()
> 
> v1: 
> * Use these ISA 3.0 flag to enable CA32 and OV32
> * Re-write ca32 compute routine
> * Add setting of flags for "neg." and "nego."
> 
> Nikunj A Dadhania (10):
>   target/ppc: move cpu_[read, write]_xer to cpu.c
>   target/ppc: optimize gen_write_xer()
>   target/ppc: support for 32-bit carry and overflow
>   target/ppc: update ca32 in arithmetic add
>   target/ppc: update ca32 in arithmetic substract
>   target/ppc: update overflow flags for add/sub
>   target/ppc: use tcg ops for neg instruction
>   target/ppc: add ov32 flag for multiply low insns
>   target/ppc: add ov32 flag in divide operations
>   target/ppc: add mcrxrx instruction
> 
>  target/ppc/Makefile.objs    |   1 +
>  target/ppc/cpu.c            |  51 ++++++++++++++++++
>  target/ppc/cpu.h            |  21 ++++----
>  target/ppc/int_helper.c     |  53 +++++++-----------
>  target/ppc/translate.c      | 128 ++++++++++++++++++++++++++++++++++++++------
>  target/ppc/translate_init.c |   4 +-
>  6 files changed, 194 insertions(+), 64 deletions(-)
>  create mode 100644 target/ppc/cpu.c
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson