docs/devel/loads-stores.rst | 40 +-

docs/system/arm/emulation.rst | 2 +

contrib/elf2dmp/addrspace.h | 1 +

contrib/elf2dmp/pdb.h | 2 +-

contrib/elf2dmp/qemu_elf.h | 2 +

target/arm/cpu.h | 35 ++

target/arm/internals.h | 55 +++

target/arm/syndrome.h | 12 +

target/arm/tcg/helper-a64.h | 14 +

target/arm/tcg/translate.h | 4 +-

target/arm/tcg/a64.decode | 38 +-

audio/jackaudio.c | 21 +-

contrib/elf2dmp/addrspace.c | 31 +-

contrib/elf2dmp/main.c | 154 ++++----

contrib/elf2dmp/pdb.c | 15 +-

contrib/elf2dmp/qemu_elf.c | 68 +++-

hw/arm/boot.c | 4 +

hw/arm/sbsa-ref.c | 2 +

linux-user/elfload.c | 72 +++-

target/arm/helper.c | 39 +-

target/arm/tcg/cpu64.c | 5 +

target/arm/tcg/helper-a64.c | 878 +++++++++++++++++++++++++++++++++++++++++

target/arm/tcg/hflags.c | 21 +

target/arm/tcg/mte_helper.c | 281 +++++++++++--

target/arm/tcg/translate-a64.c | 164 +++++++-

target/m68k/m68k-semi.c | 4 +

tests/tcg/aarch64/sysregs.c | 4 +-

27 files changed, 1768 insertions(+), 200 deletions(-)

The spec for m68k semihosting is documented in the libgloss

sources. Add a comment with the URL for it, as we already

have for nios2 semihosting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20230801154451.3505492-1-peter.maydell@linaro.org

---

target/m68k/m68k-semi.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c

index XXXXXXX..XXXXXXX 100644

--- a/target/m68k/m68k-semi.c

+++ b/target/m68k/m68k-semi.c

@@ -XXX,XX +XXX,XX @@

*

* You should have received a copy of the GNU General Public License

* along with this program; if not, see <http://www.gnu.org/licenses/>.

+ *

+ * The semihosting protocol implemented here is described in the

+ * libgloss sources:

+ * https://sourceware.org/git/?p=newlib-cygwin.git;a=blob;f=libgloss/m68k/m68k-semi.txt;hb=HEAD

*/

#include "qemu/osdep.h"

--

2.34.1

The loads-and-stores documentation includes git grep regexes to find

occurrences of the various functions. Some of these regexes have

errors, typically failing to escape the '?', '(' and ')' when they

should be metacharacters (since these are POSIX basic REs). We also

weren't consistent about whether to have a ':' on the end of the

line introducing the list of regexes in each section.

Fix the errors.

The following shell rune will complain about any REs in the

file which don't have any matches in the codebase:

for re in $(sed -ne 's/ - ``\(\\<.*\)``/\1/p' docs/devel/loads-stores.rst); do git grep -q "$re" || echo "no matches for re $re"; done

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Message-id: 20230904161703.3996734-1-peter.maydell@linaro.org

---

docs/devel/loads-stores.rst | 40 ++++++++++++++++++-------------------

1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/devel/loads-stores.rst

+++ b/docs/devel/loads-stores.rst

@@ -XXX,XX +XXX,XX @@ which stores ``val`` to ``ptr`` as an ``{endian}`` order value

of size ``sz`` bytes.

-Regexes for git grep

+Regexes for git grep:

- ``\<ld[us]\?[bwlq]\(_[hbl]e\)\?_p\>``

- ``\<st[bwlq]\(_[hbl]e\)\?_p\>``

- ``\<st24\(_[hbl]e\)\?_p\>``

- - ``\<ldn_\([hbl]e\)?_p\>``

- - ``\<stn_\([hbl]e\)?_p\>``

+ - ``\<ldn_\([hbl]e\)\?_p\>``

+ - ``\<stn_\([hbl]e\)\?_p\>``

``cpu_{ld,st}*_mmu``

~~~~~~~~~~~~~~~~~~~~

@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)``

- ``_le`` : little endian

Regexes for git grep:

- - ``\<cpu_ld[bwlq](_[bl]e)\?_mmu\>``

- - ``\<cpu_st[bwlq](_[bl]e)\?_mmu\>``

+ - ``\<cpu_ld[bwlq]\(_[bl]e\)\?_mmu\>``

+ - ``\<cpu_st[bwlq]\(_[bl]e\)\?_mmu\>``

``cpu_{ld,st}*_mmuidx_ra``

@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``

- ``_le`` : little endian

Regexes for git grep:

- - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_mmuidx_ra\>``

- - ``\<cpu_st[bwlq](_[bl]e)\?_mmuidx_ra\>``

+ - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``

+ - ``\<cpu_st[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``

``cpu_{ld,st}*_data_ra``

~~~~~~~~~~~~~~~~~~~~~~~~

@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``

- ``_le`` : little endian

Regexes for git grep:

- - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data_ra\>``

- - ``\<cpu_st[bwlq](_[bl]e)\?_data_ra\>``

+ - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data_ra\>``

+ - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data_ra\>``

``cpu_{ld,st}*_data``

~~~~~~~~~~~~~~~~~~~~~

@@ -XXX,XX +XXX,XX @@ store: ``cpu_st{size}{end}_data(env, ptr, val)``

- ``_be`` : big endian

- ``_le`` : little endian

-Regexes for git grep

- - ``\<cpu_ld[us]\?[bwlq](_[bl]e)\?_data\>``

- - ``\<cpu_st[bwlq](_[bl]e)\?_data\+\>``

+Regexes for git grep:

+ - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data\>``

+ - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data\+\>``

``cpu_ld*_code``

~~~~~~~~~~~~~~~~

@@ -XXX,XX +XXX,XX @@ swap: ``translator_ld{sign}{size}_swap(env, ptr, swap)``

- ``l`` : 32 bits

- ``q`` : 64 bits

-Regexes for git grep

+Regexes for git grep:

- ``\<translator_ld[us]\?[bwlq]\(_swap\)\?\>``

``helper_{ld,st}*_mmu``

@@ -XXX,XX +XXX,XX @@ store: ``helper_{size}_mmu(env, addr, val, opindex, retaddr)``

- ``l`` : 32 bits

- ``q`` : 64 bits

-Regexes for git grep

+Regexes for git grep:

- ``\<helper_ld[us]\?[bwlq]_mmu\>``

- ``\<helper_st[bwlq]_mmu\>``

@@ -XXX,XX +XXX,XX @@ succeeded using a MemTxResult return code.

The ``_{endian}`` suffix is omitted for byte accesses.

-Regexes for git grep

+Regexes for git grep:

- ``\<address_space_\(read\|write\|rw\)\>``

- ``\<address_space_ldu\?[bwql]\(_[lb]e\)\?\>``

- ``\<address_space_st[bwql]\(_[lb]e\)\?\>``

@@ -XXX,XX +XXX,XX @@ Note that portions of the write which attempt to write data to a

device will be silently ignored -- only real RAM and ROM will

be written to.

-Regexes for git grep

+Regexes for git grep:

- ``address_space_write_rom``

``{ld,st}*_phys``

@@ -XXX,XX +XXX,XX @@ device doing the access has no way to report such an error.

The ``_{endian}_`` infix is omitted for byte accesses.

-Regexes for git grep

+Regexes for git grep:

- ``\<ldu\?[bwlq]\(_[bl]e\)\?_phys\>``

- ``\<st[bwlq]\(_[bl]e\)\?_phys\>``

@@ -XXX,XX +XXX,XX @@ For new code they are better avoided:

``cpu_physical_memory_rw``

-Regexes for git grep

+Regexes for git grep:

- ``\<cpu_physical_memory_\(read\|write\|rw\)\>``

``cpu_memory_rw_debug``

@@ -XXX,XX +XXX,XX @@ make sure our existing code is doing things correctly.

``dma_memory_rw``

-Regexes for git grep

+Regexes for git grep:

- ``\<dma_memory_\(read\|write\|rw\)\>``

- ``\<ldu\?[bwlq]\(_[bl]e\)\?_dma\>``

- ``\<st[bwlq]\(_[bl]e\)\?_dma\>``

@@ -XXX,XX +XXX,XX @@ correct address space for that device.

The ``_{endian}_`` infix is omitted for byte accesses.

-Regexes for git grep

+Regexes for git grep:

- ``\<pci_dma_\(read\|write\|rw\)\>``

- ``\<ldu\?[bwlq]\(_[bl]e\)\?_pci_dma\>``

- ``\<st[bwlq]\(_[bl]e\)\?_pci_dma\>``

--

2.34.1

From: Fabian Vogt <fvogt@suse.de>

Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit

handles SCR_EL3.FGTEn for FEAT_FGT:

When we direct boot a kernel on a CPU which emulates EL3, we need to

set up the EL3 system registers as the Linux kernel documentation

specifies:

https://www.kernel.org/doc/Documentation/arm64/booting.rst

> For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:

> - If EL3 is present and the kernel is entered at EL2:

> - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.

Cc: qemu-stable@nongnu.org

Signed-off-by: Fabian Vogt <fvogt@suse.de>

Message-id: 4831384.GXAFRqVoOG@linux-e202.suse.de

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/boot.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/boot.c

+++ b/hw/arm/boot.c

@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)

if (cpu_isar_feature(aa64_hcx, cpu)) {

env->cp15.scr_el3 |= SCR_HXEN;

}

+ if (cpu_isar_feature(aa64_fgt, cpu)) {

+ env->cp15.scr_el3 |= SCR_FGTEN;

+ }

+

/* AArch64 kernels never boot in secure mode */

assert(!info->secure_boot);

/* This hook is only supported for AArch32 currently:

--

2.34.1

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Add the code to report the arm32 hwcaps we were previously missing:

ss, ssbs, fphp, asimdhp, asimddp, asimdfhm, asimdbf16, i8mm

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

linux-user/elfload.c | 12 ++++++++++++

1 file changed, 12 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/elfload.c

+++ b/linux-user/elfload.c

@@ -XXX,XX +XXX,XX @@ uint32_t get_elf_hwcap(void)

}

}

GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);

+ /*

+ * MVFR1.FPHP and .SIMDHP must be in sync, and QEMU uses the same

+ * isar_feature function for both. The kernel reports them as two hwcaps.

+ */

+ GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_FPHP);

+ GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_ASIMDHP);

+ GET_FEATURE_ID(aa32_dp, ARM_HWCAP_ARM_ASIMDDP);

+ GET_FEATURE_ID(aa32_fhm, ARM_HWCAP_ARM_ASIMDFHM);

+ GET_FEATURE_ID(aa32_bf16, ARM_HWCAP_ARM_ASIMDBF16);

+ GET_FEATURE_ID(aa32_i8mm, ARM_HWCAP_ARM_I8MM);

return hwcaps;

}

@@ -XXX,XX +XXX,XX @@ uint32_t get_elf_hwcap2(void)

GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);

GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);

GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);

+ GET_FEATURE_ID(aa32_sb, ARM_HWCAP2_ARM_SB);

+ GET_FEATURE_ID(aa32_ssbs, ARM_HWCAP2_ARM_SSBS);

return hwcaps;

}

--

2.34.1

Update our AArch64 ID register field definitions from the 2023-06

system register XML release:

https://developer.arm.com/documentation/ddi0601/2023-06/

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

target/arm/cpu.h | 23 +++++++++++++++++++++++

1 file changed, 23 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR0, SHA1, 8, 4)

FIELD(ID_AA64ISAR0, SHA2, 12, 4)

FIELD(ID_AA64ISAR0, CRC32, 16, 4)

FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)

+FIELD(ID_AA64ISAR0, TME, 24, 4)

FIELD(ID_AA64ISAR0, RDM, 28, 4)

FIELD(ID_AA64ISAR0, SHA3, 32, 4)

FIELD(ID_AA64ISAR0, SM3, 36, 4)

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR2, APA3, 12, 4)

FIELD(ID_AA64ISAR2, MOPS, 16, 4)

FIELD(ID_AA64ISAR2, BC, 20, 4)

FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)

+FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)

+FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)

+FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)

+FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)

+FIELD(ID_AA64ISAR2, RPRFM, 48, 4)

+FIELD(ID_AA64ISAR2, CSSC, 52, 4)

+FIELD(ID_AA64ISAR2, ATS1A, 60, 4)

FIELD(ID_AA64PFR0, EL0, 0, 4)

FIELD(ID_AA64PFR0, EL1, 4, 4)

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR1, SME, 24, 4)

FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)

FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)

FIELD(ID_AA64PFR1, NMI, 36, 4)

+FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)

+FIELD(ID_AA64PFR1, GCS, 44, 4)

+FIELD(ID_AA64PFR1, THE, 48, 4)

+FIELD(ID_AA64PFR1, MTEX, 52, 4)

+FIELD(ID_AA64PFR1, DF2, 56, 4)

+FIELD(ID_AA64PFR1, PFAR, 60, 4)

FIELD(ID_AA64MMFR0, PARANGE, 0, 4)

FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, AFP, 44, 4)

FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)

FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)

FIELD(ID_AA64MMFR1, CMOW, 56, 4)

+FIELD(ID_AA64MMFR1, ECBHB, 60, 4)

FIELD(ID_AA64MMFR2, CNP, 0, 4)

FIELD(ID_AA64MMFR2, UAO, 4, 4)

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)

FIELD(ID_AA64DFR0, TRACEVER, 4, 4)

FIELD(ID_AA64DFR0, PMUVER, 8, 4)

FIELD(ID_AA64DFR0, BRPS, 12, 4)

+FIELD(ID_AA64DFR0, PMSS, 16, 4)

FIELD(ID_AA64DFR0, WRPS, 20, 4)

+FIELD(ID_AA64DFR0, SEBEP, 24, 4)

FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)

FIELD(ID_AA64DFR0, PMSVER, 32, 4)

FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)

FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)

FIELD(ID_AA64DFR0, MTPMU, 48, 4)

FIELD(ID_AA64DFR0, BRBE, 52, 4)

+FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)

FIELD(ID_AA64DFR0, HPMN0, 60, 4)

FIELD(ID_AA64ZFR0, SVEVER, 0, 4)

FIELD(ID_AA64ZFR0, AES, 4, 4)

FIELD(ID_AA64ZFR0, BITPERM, 16, 4)

FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)

+FIELD(ID_AA64ZFR0, B16B16, 24, 4)

FIELD(ID_AA64ZFR0, SHA3, 32, 4)

FIELD(ID_AA64ZFR0, SM4, 40, 4)

FIELD(ID_AA64ZFR0, I8MM, 44, 4)

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ZFR0, F32MM, 52, 4)

FIELD(ID_AA64ZFR0, F64MM, 56, 4)

FIELD(ID_AA64SMFR0, F32F32, 32, 1)

+FIELD(ID_AA64SMFR0, BI32I32, 33, 1)

FIELD(ID_AA64SMFR0, B16F32, 34, 1)

FIELD(ID_AA64SMFR0, F16F32, 35, 1)

FIELD(ID_AA64SMFR0, I8I32, 36, 4)

+FIELD(ID_AA64SMFR0, F16F16, 42, 1)

+FIELD(ID_AA64SMFR0, B16B16, 43, 1)

+FIELD(ID_AA64SMFR0, I16I32, 44, 4)

FIELD(ID_AA64SMFR0, F64F64, 48, 1)

FIELD(ID_AA64SMFR0, I16I64, 52, 4)

FIELD(ID_AA64SMFR0, SMEVER, 56, 4)

--

2.34.1

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/arm/emulation.rst

+++ b/docs/system/arm/emulation.rst

@@ -XXX,XX +XXX,XX @@ the following architecture extensions:

- FEAT_FlagM2 (Enhancements to flag manipulation instructions)

- FEAT_GTG (Guest translation granule size)

- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)

+- FEAT_HBC (Hinted conditional branches)

- FEAT_HCX (Support for the HCRX_EL2 register)

- FEAT_HPDS (Hierarchical permission disables)

- FEAT_HPDS2 (Translation table page-based hardware attributes)

The LDRT/STRT "unprivileged load/store" instructions behave like

normal ones if executed at EL0. We handle this correctly for

the load/store semantics, but get the MTE checking wrong.

We always look at s->mte_active[is_unpriv] to see whether we should

be doing MTE checks, but in hflags.c when we set the TB flags that

will be used to fill the mte_active[] array we only set the

MTE0_ACTIVE bit if UNPRIV is true (i.e. we are not at EL0).

This means that a LDRT at EL0 will see s->mte_active[1] as 0,

and will not do MTE checks even when MTE is enabled.

To avoid the translate-time code having to do an explicit check on

s->unpriv to see if it is OK to index into the mte_active[] array,

duplicate MTE_ACTIVE into MTE0_ACTIVE when UNPRIV is false.

(This isn't a very serious bug because generally nobody executes

LDRT/STRT at EL0, because they have no use there.)

Cc: qemu-stable@nongnu.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20230912140434.1333369-2-peter.maydell@linaro.org

---

target/arm/tcg/hflags.c | 9 +++++++++

1 file changed, 9 insertions(+)

diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/tcg/hflags.c

+++ b/target/arm/tcg/hflags.c

@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

&& !(env->pstate & PSTATE_TCO)

&& (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {

DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);

+ if (!EX_TBFLAG_A64(flags, UNPRIV)) {

+ /*

+ * In non-unpriv contexts (eg EL0), unpriv load/stores

+ * act like normal ones; duplicate the MTE info to

+ * avoid translate-a64.c having to check UNPRIV to see

+ * whether it is OK to index into MTE_ACTIVE[].

+ */

+ DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);

+ }

}

}

/* And again for unprivileged accesses, if required. */

--

2.34.1

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20230912140434.1333369-3-peter.maydell@linaro.org

In every place that we call the get_a64_user_mem_index() function

we do it like this:

memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);

Refactor so the caller passes in the bool that says whether they

want the 'unpriv' or 'normal' mem_index rather than having to

do the ?: themselves.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20230912140434.1333369-4-peter.maydell@linaro.org

---

target/arm/tcg/translate-a64.c | 20 ++++++++++++++------

1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/tcg/translate-a64.c

+++ b/target/arm/tcg/translate-a64.c

@@ -XXX,XX +XXX,XX @@ void a64_translate_init(void)

}

/*

- * Return the core mmu_idx to use for A64 "unprivileged load/store" insns

+ * Return the core mmu_idx to use for A64 load/store insns which

+ * have a "unprivileged load/store" variant. Those insns access

+ * EL0 if executed from an EL which has control over EL0 (usually

+ * EL1) but behave like normal loads and stores if executed from

+ * elsewhere (eg EL3).

+ *

+ * @unpriv : true for the unprivileged encoding; false for the

+ * normal encoding (in which case we will return the same

+ * thing as get_mem_index().

*/