[Qemu-devel] [PULL 00/12] target-arm queue
[PULL v2 00/57] target-arm queue
1
ARM queue: nothing particularly exciting here, but no
1
Squashed in a trivial fix for 32-bit hosts:
2
reason to sit on them for another week.
3
2
4
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
5
-- PMM
15
-- PMM
6
16
7
The following changes since commit 61eedf7aec0e2395aabd628cc055096909a3ea15:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
8
18
9
tests/prom-env: Ease time-out problems on slow hosts (2017-02-10 15:44:53 +0000)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
10
20
11
are available in the git repository at:
21
are available in the Git repository at:
12
22
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170210
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
14
24
15
for you to fetch changes up to b4cc583f0285a2e1e78621dfba142f00ca47414a:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
16
26
17
aspeed/smc: use a modulo to check segment limits (2017-02-10 17:40:30 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
18
28
19
----------------------------------------------------------------
29
----------------------------------------------------------------
20
target-arm queue:
30
target-arm queue:
21
* aspeed: minor fixes
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
22
* virt: declare fwcfg and virtio-mmio as DMA coherent in DT & ACPI
32
* docs: Document which architecture extensions we emulate
23
* arm: enable basic TCG emulation of PMU for AArch64
33
* Fix bugs in M-profile FPCXT_NS accesses
34
* First slice of MVE patches
35
* Implement MTE3
36
* docs/system: arm: Add nRF boards description
24
37
25
----------------------------------------------------------------
38
----------------------------------------------------------------
26
Alexander Graf (4):
39
Alexandre Iooss (1):
27
target-arm: Declare virtio-mmio as dma-coherent in dt
40
docs/system: arm: Add nRF boards description
28
hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
29
hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
30
hw/arm/virt: Declare fwcfg as dma cache coherent in dt
31
41
32
Cédric Le Goater (4):
42
Peter Collingbourne (1):
33
aspeed: check for negative values returned by blk_getlength()
43
target/arm: Implement MTE3
34
aspeed: remove useless comment on controller segment size
35
aspeed/smc: handle dummies only in fast read mode
36
aspeed/smc: use a modulo to check segment limits
37
44
38
Wei Huang (4):
45
Peter Maydell (55):
39
target-arm: Add support for PMU register PMSELR_EL0
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
40
target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
47
hw/acpi: Provide function acpi_ghes_present()
41
target-arm: Add support for PMU register PMINTENSET_EL1
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
42
target-arm: Enable vPMU support under TCG mode
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
43
101
44
target/arm/cpu.h | 4 +--
102
docs/system/arm/emulation.rst | 103 ++++
45
hw/arm/aspeed.c | 22 +++++++++-----
103
docs/system/arm/nrf.rst | 51 ++
46
hw/arm/vexpress.c | 1 +
104
docs/system/target-arm.rst | 7 +
47
hw/arm/virt-acpi-build.c | 2 ++
105
include/hw/acpi/ghes.h | 9 +
48
hw/arm/virt.c | 4 ++-
106
include/tcg/tcg-op.h | 8 +
49
hw/ssi/aspeed_smc.c | 13 +++++----
107
include/tcg/tcg.h | 1 -
50
target/arm/cpu.c | 2 +-
108
target/arm/helper-mve.h | 357 +++++++++++++
51
target/arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++------------
109
target/arm/helper.h | 2 +
52
8 files changed, 88 insertions(+), 34 deletions(-)
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
53
135
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/12] target-arm: Add support for PMU register PMSELR_EL0
Deleted patch
1
From: Wei Huang <wei@redhat.com>
2
1
3
This patch adds support for AArch64 register PMSELR_EL0. The existing
4
PMSELR definition is revised accordingly.
5
6
Signed-off-by: Wei Huang <wei@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
[PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs]
9
Message-id: 1486504171-26807-2-git-send-email-wei@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.h | 1 +
13
target/arm/helper.c | 27 +++++++++++++++++++++------
14
2 files changed, 22 insertions(+), 6 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
21
uint32_t c9_pmovsr; /* perf monitor overflow status */
22
uint32_t c9_pmxevtyper; /* perf monitor event type */
23
uint32_t c9_pmuserenr; /* perf monitor user enable */
24
+ uint64_t c9_pmselr; /* perf monitor counter selection register */
25
uint32_t c9_pminten; /* perf monitor interrupt enables */
26
union { /* Memory attribute redirection */
27
struct {
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
33
return total_ticks - env->cp15.c15_ccnt;
34
}
35
36
+static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
+ uint64_t value)
38
+{
39
+ /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
40
+ * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
41
+ * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
42
+ * accessed.
43
+ */
44
+ env->cp15.c9_pmselr = value & 0x1f;
45
+}
46
+
47
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
48
uint64_t value)
49
{
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
51
/* Unimplemented so WI. */
52
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
53
.access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
54
- /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
55
- * We choose to RAZ/WI.
56
- */
57
- { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
58
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
59
- .accessfn = pmreg_access },
60
#ifndef CONFIG_USER_ONLY
61
+ { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
62
+ .access = PL0_RW, .type = ARM_CP_ALIAS,
63
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
64
+ .accessfn = pmreg_access, .writefn = pmselr_write,
65
+ .raw_writefn = raw_write},
66
+ { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
67
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
68
+ .access = PL0_RW, .accessfn = pmreg_access,
69
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
70
+ .writefn = pmselr_write, .raw_writefn = raw_write, },
71
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
72
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
73
.readfn = pmccntr_read, .writefn = pmccntr_write32,
74
--
75
2.7.4
76
77
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
Deleted patch
1
From: Wei Huang <wei@redhat.com>
2
1
3
In order to support Linux perf, which uses PMXEVTYPER register,
4
this patch adds read/write access support for PMXEVTYPER. The access
5
is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally
6
this patch adds support for PMXEVTYPER_EL0.
7
8
Signed-off-by: Wei Huang <wei@redhat.com>
9
Message-id: 1486504171-26807-3-git-send-email-wei@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 1 -
14
target/arm/helper.c | 30 +++++++++++++++++++++++++-----
15
2 files changed, 25 insertions(+), 6 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
22
uint64_t c9_pmcr; /* performance monitor control register */
23
uint64_t c9_pmcnten; /* perf monitor counter enables */
24
uint32_t c9_pmovsr; /* perf monitor overflow status */
25
- uint32_t c9_pmxevtyper; /* perf monitor event type */
26
uint32_t c9_pmuserenr; /* perf monitor user enable */
27
uint64_t c9_pmselr; /* perf monitor counter selection register */
28
uint32_t c9_pminten; /* perf monitor interrupt enables */
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper.c
32
+++ b/target/arm/helper.c
33
@@ -XXX,XX +XXX,XX @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
34
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
35
uint64_t value)
36
{
37
- env->cp15.c9_pmxevtyper = value & 0xff;
38
+ /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
39
+ * PMSELR value is equal to or greater than the number of implemented
40
+ * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
41
+ */
42
+ if (env->cp15.c9_pmselr == 0x1f) {
43
+ pmccfiltr_write(env, ri, value);
44
+ }
45
+}
46
+
47
+static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
48
+{
49
+ /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
50
+ * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
51
+ */
52
+ if (env->cp15.c9_pmselr == 0x1f) {
53
+ return env->cp15.pmccfiltr_el0;
54
+ } else {
55
+ return 0;
56
+ }
57
}
58
59
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
60
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
61
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
62
.resetvalue = 0, },
63
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
64
- .access = PL0_RW,
65
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
66
- .accessfn = pmreg_access, .writefn = pmxevtyper_write,
67
- .raw_writefn = raw_write },
68
+ .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
69
+ .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
70
+ { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
71
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
72
+ .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
73
+ .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
74
/* Unimplemented, RAZ/WI. */
75
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
76
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
77
--
78
2.7.4
79
80
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1
Deleted patch
1
From: Wei Huang <wei@redhat.com>
2
1
3
This patch adds access support for PMINTENSET_EL1.
4
5
Signed-off-by: Wei Huang <wei@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 1486504171-26807-4-git-send-email-wei@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 2 +-
11
target/arm/helper.c | 10 +++++++++-
12
2 files changed, 10 insertions(+), 2 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
uint32_t c9_pmovsr; /* perf monitor overflow status */
20
uint32_t c9_pmuserenr; /* perf monitor user enable */
21
uint64_t c9_pmselr; /* perf monitor counter selection register */
22
- uint32_t c9_pminten; /* perf monitor interrupt enables */
23
+ uint64_t c9_pminten; /* perf monitor interrupt enables */
24
union { /* Memory attribute redirection */
25
struct {
26
#ifdef HOST_WORDS_BIGENDIAN
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
32
.writefn = pmuserenr_write, .raw_writefn = raw_write },
33
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
34
.access = PL1_RW, .accessfn = access_tpm,
35
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
36
+ .type = ARM_CP_ALIAS,
37
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
38
.resetvalue = 0,
39
.writefn = pmintenset_write, .raw_writefn = raw_write },
40
+ { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
41
+ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
42
+ .access = PL1_RW, .accessfn = access_tpm,
43
+ .type = ARM_CP_IO,
44
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
45
+ .writefn = pmintenset_write, .raw_writefn = raw_write,
46
+ .resetvalue = 0x0 },
47
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
48
.access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
49
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
50
--
51
2.7.4
52
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode
Deleted patch
1
From: Wei Huang <wei@redhat.com>
2
1
3
This patch contains several fixes to enable vPMU under TCG mode. It
4
first removes the checking of kvm_enabled() while unsetting
5
ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU
6
under TCG mode. Secondly the PMU node of DT table is now created under TCG.
7
The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1.
8
9
Signed-off-by: Wei Huang <wei@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 1486504171-26807-5-git-send-email-wei@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/virt.c | 2 +-
15
target/arm/cpu.c | 2 +-
16
target/arm/helper.c | 7 +------
17
3 files changed, 3 insertions(+), 8 deletions(-)
18
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
22
+++ b/hw/arm/virt.c
23
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
24
CPU_FOREACH(cpu) {
25
armcpu = ARM_CPU(cpu);
26
if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) ||
27
- !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {
28
+ (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) {
29
return;
30
}
31
}
32
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/cpu.c
35
+++ b/target/arm/cpu.c
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
37
unset_feature(env, ARM_FEATURE_EL2);
38
}
39
40
- if (!cpu->has_pmu || !kvm_enabled()) {
41
+ if (!cpu->has_pmu) {
42
cpu->has_pmu = false;
43
unset_feature(env, ARM_FEATURE_PMU);
44
}
45
diff --git a/target/arm/helper.c b/target/arm/helper.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/helper.c
48
+++ b/target/arm/helper.c
49
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
50
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
51
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
52
.access = PL1_R, .type = ARM_CP_CONST,
53
- /* We mask out the PMUVer field, because we don't currently
54
- * implement the PMU. Not advertising it prevents the guest
55
- * from trying to use it and getting UNDEFs on registers we
56
- * don't implement.
57
- */
58
- .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
59
+ .resetvalue = cpu->id_aa64dfr0 },
60
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
61
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
62
.access = PL1_R, .type = ARM_CP_CONST,
63
--
64
2.7.4
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt
Deleted patch
1
From: Alexander Graf <agraf@suse.de>
2
1
3
QEMU emulated hardware is always dma coherent with its guest. We do
4
annotate that correctly on the PCI host controller, but left out
5
virtio-mmio.
6
7
Recent kernels have started to interpret that flag rather than take
8
dma coherency as granted with virtio-mmio. While that is considered
9
a kernel bug, as it breaks previously working systems, it showed that
10
our dt description is incomplete.
11
12
This patch adds the respective marker that allows guest OSs to evaluate
13
that our virtio-mmio devices are indeed cache coherent.
14
15
Signed-off-by: Alexander Graf <agraf@suse.de>
16
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
17
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
18
Message-id: 1486644810-33181-2-git-send-email-agraf@suse.de
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/arm/vexpress.c | 1 +
22
hw/arm/virt.c | 1 +
23
2 files changed, 2 insertions(+)
24
25
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/vexpress.c
28
+++ b/hw/arm/vexpress.c
29
@@ -XXX,XX +XXX,XX @@ static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
30
acells, addr, scells, size);
31
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
32
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
33
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
34
g_free(nodename);
35
if (rc) {
36
return -1;
37
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/virt.c
40
+++ b/hw/arm/virt.c
41
@@ -XXX,XX +XXX,XX @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
42
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
43
GIC_FDT_IRQ_TYPE_SPI, irq,
44
GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
45
+ qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
46
g_free(nodename);
47
}
48
}
49
--
50
2.7.4
51
52
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
Deleted patch
1
From: Alexander Graf <agraf@suse.de>
2
1
3
Virtio-mmio devices can directly access guest memory and do so in cache
4
coherent fashion. Tell the guest about that fact when it's using ACPI.
5
6
Signed-off-by: Alexander Graf <agraf@suse.de>
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
8
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
9
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
10
Message-id: 1486644810-33181-3-git-send-email-agraf@suse.de
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/virt-acpi-build.c | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
19
+++ b/hw/arm/virt-acpi-build.c
20
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_virtio(Aml *scope,
21
Aml *dev = aml_device("VR%02u", i);
22
aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
23
aml_append(dev, aml_name_decl("_UID", aml_int(i)));
24
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
25
26
Aml *crs = aml_resource_template();
27
aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
28
--
29
2.7.4
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
Deleted patch
1
From: Alexander Graf <agraf@suse.de>
2
1
3
Fw-cfg recently learned how to directly access guest memory and does so in
4
cache coherent fashion. Tell the guest about that fact when it's using ACPI.
5
6
Signed-off-by: Alexander Graf <agraf@suse.de>
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
8
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
9
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
10
Message-id: 1486644810-33181-4-git-send-email-agraf@suse.de
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/virt-acpi-build.c | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
19
+++ b/hw/arm/virt-acpi-build.c
20
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
21
aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
22
/* device present, functioning, decoding, not shown in UI */
23
aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
24
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
25
26
Aml *crs = aml_resource_template();
27
aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
28
--
29
2.7.4
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/12] hw/arm/virt: Declare fwcfg as dma cache coherent in dt
Deleted patch
1
From: Alexander Graf <agraf@suse.de>
2
1
3
Fw-cfg recently learned how to directly access guest memory and does so in
4
cache coherent fashion. Tell the guest about that fact when it's using DT.
5
6
Signed-off-by: Alexander Graf <agraf@suse.de>
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
8
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
9
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
10
Message-id: 1486644810-33181-5-git-send-email-agraf@suse.de
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/virt.c | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt.c
19
+++ b/hw/arm/virt.c
20
@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
21
"compatible", "qemu,fw-cfg-mmio");
22
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
23
2, base, 2, size);
24
+ qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
25
g_free(nodename);
26
return fw_cfg;
27
}
28
--
29
2.7.4
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength()
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
write_boot_rom() does not check for negative values. This is more a
4
problem for coverity than the actual code as the size of the flash
5
device is checked when the m25p80 object is created. If there is
6
anything wrong with the backing file, we should not even reach that
7
path.
8
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
Message-id: 1486648058-520-2-git-send-email-clg@kaod.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/aspeed.c | 14 ++++++++++++--
15
1 file changed, 12 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/aspeed.c
20
+++ b/hw/arm/aspeed.c
21
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
22
{
23
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
24
uint8_t *storage;
25
+ int64_t size;
26
27
- if (rom_size > blk_getlength(blk)) {
28
- rom_size = blk_getlength(blk);
29
+ /* The block backend size should have already been 'validated' by
30
+ * the creation of the m25p80 object.
31
+ */
32
+ size = blk_getlength(blk);
33
+ if (size <= 0) {
34
+ error_setg(errp, "failed to get flash size");
35
+ return;
36
+ }
37
+
38
+ if (rom_size > size) {
39
+ rom_size = size;
40
}
41
42
storage = g_new0(uint8_t, rom_size);
43
--
44
2.7.4
45
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/12] aspeed: remove useless comment on controller segment size
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The flash devices used for the FMC controller (BMC firmware) are well
4
defined for each Aspeed machine and are all smaller than the default
5
mapping window size, at least for CE0 which is the chip the SoC boots
6
from.
7
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1486648058-520-3-git-send-email-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/aspeed.c | 8 +++-----
14
1 file changed, 3 insertions(+), 5 deletions(-)
15
16
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/aspeed.c
19
+++ b/hw/arm/aspeed.c
20
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
21
DriveInfo *dinfo = drive_get_next(IF_MTD);
22
qemu_irq cs_line;
23
24
- /*
25
- * FIXME: check that we are not using a flash module exceeding
26
- * the controller segment size
27
- */
28
fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
29
if (dinfo) {
30
qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
32
33
/*
34
* create a ROM region using the default mapping window size of
35
- * the flash module.
36
+ * the flash module. The window size is 64MB for the AST2400
37
+ * SoC and 128MB for the AST2500 SoC, which is twice as big as
38
+ * needed by the flash modules of the Aspeed machines.
39
*/
40
memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
41
fl->size, &error_abort);
42
--
43
2.7.4
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
HW works fine in normal read mode with dummy bytes being set. So let's
4
check this case to not transfer bytes.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 1486648058-520-4-git-send-email-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/ssi/aspeed_smc.c | 9 ++++++---
11
1 file changed, 6 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/ssi/aspeed_smc.c
16
+++ b/hw/ssi/aspeed_smc.c
17
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
18
/*
19
* Use fake transfers to model dummy bytes. The value should
20
* be configured to some non-zero value in fast read mode and
21
- * zero in read mode.
22
+ * zero in read mode. But, as the HW allows inconsistent
23
+ * settings, let's check for fast read mode.
24
*/
25
- for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
26
- ssi_transfer(fl->controller->spi, 0xFF);
27
+ if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
28
+ for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
29
+ ssi_transfer(fl->controller->spi, 0xFF);
30
+ }
31
}
32
33
for (i = 0; i < size; i++) {
34
--
35
2.7.4
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The size of a segment is not necessarily a power of 2.
4
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 1486648058-520-5-git-send-email-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/ssi/aspeed_smc.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/ssi/aspeed_smc.c
16
+++ b/hw/ssi/aspeed_smc.c
17
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
18
AspeedSegments seg;
19
20
aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);
21
- if ((addr & (seg.size - 1)) != addr) {
22
+ if ((addr % seg.size) != addr) {
23
qemu_log_mask(LOG_GUEST_ERROR,
24
"%s: invalid address 0x%08x for CS%d segment : "
25
"[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
26
s->ctrl->name, addr, fl->id, seg.addr,
27
seg.addr + seg.size);
28
+ addr %= seg.size;
29
}
30
31
- addr &= seg.size - 1;
32
return addr;
33
}
34
35
--
36
2.7.4
37
38
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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