Nothing too exciting, but does include the last bits of v8.1M support work.

The following changes since commit e79de63ab1bd1f6550e7b915e433bec1ad1a870a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210107' into staging (2021-01-07 20:34:05 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210108

for you to fetch changes up to c9f8511ea8d2b80723af0fea1f716d752c1b5208:

docs/system: arm: Add sabrelite board description (2021-01-08 15:13:39 +0000)

* intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

* target/arm: Fix MTE0_ACTIVE

* target/arm: Implement v8.1M and Cortex-M55 model

* hw/arm/highbank: Drop dead KVM support code

* util/qemu-timer: Make timer_free() imply timer_del()

* various devices: Use ptimer_free() in finalize function

* docs/system: arm: Add sabrelite board description

* sabrelite: Minor fixes to allow booting U-Boot

Andrew Jones (1):

hw/arm/virt: Remove virt machine state 'smp_cpus'

Bin Meng (4):

hw/misc: imx6_ccm: Update PMU_MISC0 reset value

hw/msic: imx6_ccm: Correct register value for silicon type

hw/arm: sabrelite: Connect the Ethernet PHY at address 6

docs/system: arm: Add sabrelite board description

Edgar E. Iglesias (1):

intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs

Gan Qixin (7):

digic-timer: Use ptimer_free() in the finalize function to avoid memleaks

allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_rtc: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks

mss-timer: Use ptimer_free() in the finalize function to avoid memleaks

musicpal: Use ptimer_free() in the finalize function to avoid memleaks

exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks

From: Andrew Jones <drjones@redhat.com>

virt machine's 'smp_cpus' and machine->smp.cpus must always have the

same value. And, anywhere we have virt machine state we have machine

state. So let's remove the redundancy. Also, to make it easier to see

that machine->smp is the true source for "smp_cpus" and "max_cpus",

avoid passing them in function parameters, preferring instead to get

them from the state.

No functional change intended.

Signed-off-by: Andrew Jones <drjones@redhat.com>

Reviewed-by: David Edmondson <david.edmondson@oracle.com>

Reviewed-by: Ying Fang <fangying1@huawei.com>

Message-id: 20201215174815.51520-1-drjones@redhat.com

[PMM: minor formatting tweak to smp_cpus variable declaration]

include/hw/arm/virt.h | 3 +--

hw/arm/virt-acpi-build.c | 9 +++++----

hw/arm/virt.c | 21 ++++++++++-----------

3 files changed, 16 insertions(+), 17 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)

if (vms->gic_version == VIRT_GIC_VERSION_2) {

irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

GIC_FDT_IRQ_PPI_CPU_WIDTH,

- (1 << vms->smp_cpus) - 1);

+ (1 << MACHINE(vms)->smp.cpus) - 1);

}

qemu_fdt_add_subnode(vms->fdt, "/timer");

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

int cpu;

int addr_cells = 1;

const MachineState *ms = MACHINE(vms);

+ int smp_cpus = ms->smp.cpus;

/*

* From Documentation/devicetree/bindings/arm/cpus.txt

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

* The simplest way to go is to examine affinity IDs of all our CPUs. If

* at least one of them has Aff3 populated, we set #address-cells to 2.

*/

- for (cpu = 0; cpu < vms->smp_cpus; cpu++) {

+ for (cpu = 0; cpu < smp_cpus; cpu++) {

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));

if (armcpu->mp_affinity & ARM_AFF3_MASK) {

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);

qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);

- for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {

+ for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {

char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);

ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));

CPUState *cs = CPU(armcpu);

@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)

qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",

armcpu->dtb_compatible);

- if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED

- && vms->smp_cpus > 1) {

+ if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {

qemu_fdt_setprop_string(vms->fdt, nodename,

"enable-method", "psci");

}

@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)

if (vms->gic_version == VIRT_GIC_VERSION_2) {

irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

GIC_FDT_IRQ_PPI_CPU_WIDTH,

- (1 << vms->smp_cpus) - 1);

+ (1 << MACHINE(vms)->smp.cpus) - 1);

}

qemu_fdt_add_subnode(vms->fdt, "/pmu");

@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)

* virt_cpu_post_init() must be called after the CPUs have

* been realized and the GIC has been created.

*/

-static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,

- MemoryRegion *sysmem)

+static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)

{

+ int max_cpus = MACHINE(vms)->smp.max_cpus;

bool aarch64, pmu, steal_time;

CPUState *cpu;

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

exit(1);

}

- vms->smp_cpus = smp_cpus;

-

if (vms->virt && kvm_enabled()) {

error_report("mach-virt: KVM does not support providing "

"Virtualization extensions to the guest CPU");

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

create_fdt(vms);

possible_cpus = mc->possible_cpu_arch_ids(machine);

+ assert(possible_cpus->len == max_cpus);

for (n = 0; n < possible_cpus->len; n++) {

Object *cpuobj;

CPUState *cs;

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

create_gic(vms);

- virt_cpu_post_init(vms, possible_cpus->len, sysmem);

+ virt_cpu_post_init(vms, sysmem);

fdt_add_pmu_nodes(vms);

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

In 50244cc76abc we updated mte_check_fail to match the ARM

pseudocode, using the correct EL to select the TCF field.

But we failed to update MTE0_ACTIVE the same way, which led

to g_assert_not_reached().

Cc: qemu-stable@nongnu.org

Buglink: https://bugs.launchpad.net/bugs/1907137

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201221204426.88514-1-richard.henderson@linaro.org

target/arm/helper.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,

if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)

&& tbid

&& !(env->pstate & PSTATE_TCO)

- && (sctlr & SCTLR_TCF0)

+ && (sctlr & SCTLR_TCF)

&& allocation_tag_access_enabled(env, 0, sctlr)) {

flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);

}

2.20.1

The CCR is a register most of whose bits are banked between security

states but where BFHFNMIGN is not, and we keep it in the non-secure

entry of the v7m.ccr[] array. The logic which tries to handle this

bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS

is zero" requirement; correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201210201433.26262-2-peter.maydell@linaro.org

---

hw/intc/armv7m_nvic.c | 15 +++++++++++++++

1 file changed, 15 insertions(+)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

val = cpu->env.v7m.ccr[attrs.secure];

val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;

+ /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */

+ if (!attrs.secure) {

+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {

+ val &= ~R_V7M_CCR_BFHFNMIGN_MASK;

+ }

+ }

return val;

case 0xd24: /* System Handler Control and State (SHCSR) */

if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {

@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,

(cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK)

| (value & R_V7M_CCR_BFHFNMIGN_MASK);

value &= ~R_V7M_CCR_BFHFNMIGN_MASK;

+ } else {

+ /*

+ * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so

+ * preserve the state currently in the NS element of the array

+ */

+ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {

+ value &= ~R_V7M_CCR_BFHFNMIGN_MASK;

+ value |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;

cpu->env.v7m.ccr[attrs.secure] = value;

2.20.1