1 | ARM queue: nothing particularly exciting here, but no | 1 | Arm queue; bugfixes only. |
---|---|---|---|
2 | reason to sit on them for another week. | ||
3 | 2 | ||
4 | thanks | 3 | thanks |
5 | -- PMM | 4 | -- PMM |
6 | 5 | ||
7 | The following changes since commit 61eedf7aec0e2395aabd628cc055096909a3ea15: | 6 | The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739: |
8 | 7 | ||
9 | tests/prom-env: Ease time-out problems on slow hosts (2017-02-10 15:44:53 +0000) | 8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000) |
10 | 9 | ||
11 | are available in the git repository at: | 10 | are available in the Git repository at: |
12 | 11 | ||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170210 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117 |
14 | 13 | ||
15 | for you to fetch changes up to b4cc583f0285a2e1e78621dfba142f00ca47414a: | 14 | for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42: |
16 | 15 | ||
17 | aspeed/smc: use a modulo to check segment limits (2017-02-10 17:40:30 +0000) | 16 | tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000) |
18 | 17 | ||
19 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
20 | target-arm queue: | 19 | target-arm queue: |
21 | * aspeed: minor fixes | 20 | * hw/arm/virt: ARM_VIRT must select ARM_GIC |
22 | * virt: declare fwcfg and virtio-mmio as DMA coherent in DT & ACPI | 21 | * exynos: Fix bad printf format specifiers |
23 | * arm: enable basic TCG emulation of PMU for AArch64 | 22 | * hw/input/ps2.c: Remove remnants of printf debug |
23 | * target/openrisc: Remove dead code attempting to check "is timer disabled" | ||
24 | * register: Remove unnecessary NULL check | ||
25 | * util/cutils: Fix Coverity array overrun in freq_to_str() | ||
26 | * configure: Make "does libgio work" test pull in some actual functions | ||
27 | * tmp105: reset the T_low and T_High registers | ||
28 | * tmp105: Correct handling of temperature limit checks | ||
24 | 29 | ||
25 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
26 | Alexander Graf (4): | 31 | Alex Chen (1): |
27 | target-arm: Declare virtio-mmio as dma-coherent in dt | 32 | exynos: Fix bad printf format specifiers |
28 | hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI | ||
29 | hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI | ||
30 | hw/arm/virt: Declare fwcfg as dma cache coherent in dt | ||
31 | 33 | ||
32 | Cédric Le Goater (4): | 34 | Alistair Francis (1): |
33 | aspeed: check for negative values returned by blk_getlength() | 35 | register: Remove unnecessary NULL check |
34 | aspeed: remove useless comment on controller segment size | ||
35 | aspeed/smc: handle dummies only in fast read mode | ||
36 | aspeed/smc: use a modulo to check segment limits | ||
37 | 36 | ||
38 | Wei Huang (4): | 37 | Andrew Jones (1): |
39 | target-arm: Add support for PMU register PMSELR_EL0 | 38 | hw/arm/virt: ARM_VIRT must select ARM_GIC |
40 | target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0 | ||
41 | target-arm: Add support for PMU register PMINTENSET_EL1 | ||
42 | target-arm: Enable vPMU support under TCG mode | ||
43 | 39 | ||
44 | target/arm/cpu.h | 4 +-- | 40 | Peter Maydell (5): |
45 | hw/arm/aspeed.c | 22 +++++++++----- | 41 | hw/input/ps2.c: Remove remnants of printf debug |
46 | hw/arm/vexpress.c | 1 + | 42 | target/openrisc: Remove dead code attempting to check "is timer disabled" |
47 | hw/arm/virt-acpi-build.c | 2 ++ | 43 | configure: Make "does libgio work" test pull in some actual functions |
48 | hw/arm/virt.c | 4 ++- | 44 | hw/misc/tmp105: reset the T_low and T_High registers |
49 | hw/ssi/aspeed_smc.c | 13 +++++---- | 45 | tmp105: Correct handling of temperature limit checks |
50 | target/arm/cpu.c | 2 +- | ||
51 | target/arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++------------ | ||
52 | 8 files changed, 88 insertions(+), 34 deletions(-) | ||
53 | 46 | ||
47 | Philippe Mathieu-Daudé (1): | ||
48 | util/cutils: Fix Coverity array overrun in freq_to_str() | ||
49 | |||
50 | configure | 11 +++++-- | ||
51 | hw/misc/tmp105.h | 7 +++++ | ||
52 | hw/core/register.c | 4 --- | ||
53 | hw/input/ps2.c | 9 ------ | ||
54 | hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------ | ||
55 | hw/timer/exynos4210_mct.c | 4 +-- | ||
56 | hw/timer/exynos4210_pwm.c | 8 ++--- | ||
57 | target/openrisc/sys_helper.c | 3 -- | ||
58 | util/cutils.c | 3 +- | ||
59 | hw/arm/Kconfig | 1 + | ||
60 | 10 files changed, 89 insertions(+), 34 deletions(-) | ||
61 | diff view generated by jsdifflib |
1 | From: Alexander Graf <agraf@suse.de> | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Fw-cfg recently learned how to directly access guest memory and does so in | 3 | The removal of the selection of A15MPCORE from ARM_VIRT also |
4 | cache coherent fashion. Tell the guest about that fact when it's using DT. | 4 | removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC. |
5 | 5 | ||
6 | Signed-off-by: Alexander Graf <agraf@suse.de> | 6 | Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals") |
7 | Reviewed-by: Laszlo Ersek <lersek@redhat.com> | 7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> |
8 | Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> | 8 | Signed-off-by: Andrew Jones <drjones@redhat.com> |
9 | Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> | 9 | Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com> |
10 | Message-id: 1486644810-33181-5-git-send-email-agraf@suse.de | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
11 | Message-id: 20201111143440.112763-1-drjones@redhat.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | hw/arm/virt.c | 1 + | 14 | hw/arm/Kconfig | 1 + |
14 | 1 file changed, 1 insertion(+) | 15 | 1 file changed, 1 insertion(+) |
15 | 16 | ||
16 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 17 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/virt.c | 19 | --- a/hw/arm/Kconfig |
19 | +++ b/hw/arm/virt.c | 20 | +++ b/hw/arm/Kconfig |
20 | @@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) | 21 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT |
21 | "compatible", "qemu,fw-cfg-mmio"); | 22 | imply VFIO_PLATFORM |
22 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | 23 | imply VFIO_XGMAC |
23 | 2, base, 2, size); | 24 | imply TPM_TIS_SYSBUS |
24 | + qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); | 25 | + select ARM_GIC |
25 | g_free(nodename); | 26 | select ACPI |
26 | return fw_cfg; | 27 | select ARM_SMMUV3 |
27 | } | 28 | select GPIO_KEY |
28 | -- | 29 | -- |
29 | 2.7.4 | 30 | 2.20.1 |
30 | 31 | ||
31 | 32 | diff view generated by jsdifflib |
1 | From: Wei Huang <wei@redhat.com> | 1 | From: Alex Chen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | In order to support Linux perf, which uses PMXEVTYPER register, | 3 | We should use printf format specifier "%u" instead of "%d" for |
4 | this patch adds read/write access support for PMXEVTYPER. The access | 4 | argument of type "unsigned int". |
5 | is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally | ||
6 | this patch adds support for PMXEVTYPER_EL0. | ||
7 | 5 | ||
8 | Signed-off-by: Wei Huang <wei@redhat.com> | 6 | Reported-by: Euler Robot <euler.robot@huawei.com> |
9 | Message-id: 1486504171-26807-3-git-send-email-wei@redhat.com | 7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> |
8 | Message-id: 20201111073651.72804-1-alex.chen@huawei.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | target/arm/cpu.h | 1 - | 12 | hw/timer/exynos4210_mct.c | 4 ++-- |
14 | target/arm/helper.c | 30 +++++++++++++++++++++++++----- | 13 | hw/timer/exynos4210_pwm.c | 8 ++++---- |
15 | 2 files changed, 25 insertions(+), 6 deletions(-) | 14 | 2 files changed, 6 insertions(+), 6 deletions(-) |
16 | 15 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 18 | --- a/hw/timer/exynos4210_mct.c |
20 | +++ b/target/arm/cpu.h | 19 | +++ b/hw/timer/exynos4210_mct.c |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id) |
22 | uint64_t c9_pmcr; /* performance monitor control register */ | 21 | /* If CSTAT is pending and IRQ is enabled */ |
23 | uint64_t c9_pmcnten; /* perf monitor counter enables */ | 22 | if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && |
24 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | 23 | (s->reg.int_enb & G_INT_ENABLE(id))) { |
25 | - uint32_t c9_pmxevtyper; /* perf monitor event type */ | 24 | - DPRINTF("gcmp timer[%d] IRQ\n", id); |
26 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | 25 | + DPRINTF("gcmp timer[%u] IRQ\n", id); |
27 | uint64_t c9_pmselr; /* perf monitor counter selection register */ | 26 | qemu_irq_raise(s->irq[id]); |
28 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | 27 | } |
29 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 28 | } |
29 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | ||
30 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); | ||
31 | |||
32 | if (freq != s->freq) { | ||
33 | - DPRINTF("freq=%dHz\n", s->freq); | ||
34 | + DPRINTF("freq=%uHz\n", s->freq); | ||
35 | |||
36 | /* global timer */ | ||
37 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
38 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/helper.c | 40 | --- a/hw/timer/exynos4210_pwm.c |
32 | +++ b/target/arm/helper.c | 41 | +++ b/hw/timer/exynos4210_pwm.c |
33 | @@ -XXX,XX +XXX,XX @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) |
34 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | 43 | |
35 | uint64_t value) | 44 | if (freq != s->timer[id].freq) { |
36 | { | 45 | ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); |
37 | - env->cp15.c9_pmxevtyper = value & 0xff; | 46 | - DPRINTF("freq=%dHz\n", s->timer[id].freq); |
38 | + /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when | 47 | + DPRINTF("freq=%uHz\n", s->timer[id].freq); |
39 | + * PMSELR value is equal to or greater than the number of implemented | 48 | } |
40 | + * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | ||
41 | + */ | ||
42 | + if (env->cp15.c9_pmselr == 0x1f) { | ||
43 | + pmccfiltr_write(env, ri, value); | ||
44 | + } | ||
45 | +} | ||
46 | + | ||
47 | +static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
48 | +{ | ||
49 | + /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | ||
50 | + * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). | ||
51 | + */ | ||
52 | + if (env->cp15.c9_pmselr == 0x1f) { | ||
53 | + return env->cp15.pmccfiltr_el0; | ||
54 | + } else { | ||
55 | + return 0; | ||
56 | + } | ||
57 | } | 49 | } |
58 | 50 | ||
59 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) |
60 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | 52 | uint32_t id = s->id; |
61 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | 53 | bool cmp; |
62 | .resetvalue = 0, }, | 54 | |
63 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, | 55 | - DPRINTF("timer %d tick\n", id); |
64 | - .access = PL0_RW, | 56 | + DPRINTF("timer %u tick\n", id); |
65 | - .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), | 57 | |
66 | - .accessfn = pmreg_access, .writefn = pmxevtyper_write, | 58 | /* set irq status */ |
67 | - .raw_writefn = raw_write }, | 59 | p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); |
68 | + .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, | 60 | |
69 | + .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | 61 | /* raise IRQ */ |
70 | + { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | 62 | if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { |
71 | + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | 63 | - DPRINTF("timer %d IRQ\n", id); |
72 | + .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, | 64 | + DPRINTF("timer %u IRQ\n", id); |
73 | + .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | 65 | qemu_irq_raise(p->timer[id].irq); |
74 | /* Unimplemented, RAZ/WI. */ | 66 | } |
75 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, | 67 | |
76 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, | 68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) |
69 | } | ||
70 | |||
71 | if (cmp) { | ||
72 | - DPRINTF("auto reload timer %d count to %x\n", id, | ||
73 | + DPRINTF("auto reload timer %u count to %x\n", id, | ||
74 | p->timer[id].reg_tcntb); | ||
75 | ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); | ||
76 | ptimer_run(p->timer[id].ptimer, 1); | ||
77 | -- | 77 | -- |
78 | 2.7.4 | 78 | 2.20.1 |
79 | 79 | ||
80 | 80 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | In commit 5edab03d4040 we added tracepoints to the ps2 keyboard |
---|---|---|---|
2 | and mouse emulation. However we didn't remove all the debug-by-printf | ||
3 | support. In fact there is only one printf() remaining, and it is | ||
4 | redundant with the trace_ps2_write_mouse() event next to it. | ||
5 | Remove the printf() and the now-unused DEBUG* macros. | ||
2 | 6 | ||
3 | HW works fine in normal read mode with dummy bytes being set. So let's | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | check this case to not transfer bytes. | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
9 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
10 | Message-id: 20201101133258.4240-1-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/input/ps2.c | 9 --------- | ||
13 | 1 file changed, 9 deletions(-) | ||
5 | 14 | ||
6 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 15 | diff --git a/hw/input/ps2.c b/hw/input/ps2.c |
7 | Message-id: 1486648058-520-4-git-send-email-clg@kaod.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/ssi/aspeed_smc.c | 9 ++++++--- | ||
11 | 1 file changed, 6 insertions(+), 3 deletions(-) | ||
12 | |||
13 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/ssi/aspeed_smc.c | 17 | --- a/hw/input/ps2.c |
16 | +++ b/hw/ssi/aspeed_smc.c | 18 | +++ b/hw/input/ps2.c |
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) | 19 | @@ -XXX,XX +XXX,XX @@ |
18 | /* | 20 | |
19 | * Use fake transfers to model dummy bytes. The value should | 21 | #include "trace.h" |
20 | * be configured to some non-zero value in fast read mode and | 22 | |
21 | - * zero in read mode. | 23 | -/* debug PC keyboard */ |
22 | + * zero in read mode. But, as the HW allows inconsistent | 24 | -//#define DEBUG_KBD |
23 | + * settings, let's check for fast read mode. | 25 | - |
24 | */ | 26 | -/* debug PC keyboard : only mouse */ |
25 | - for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { | 27 | -//#define DEBUG_MOUSE |
26 | - ssi_transfer(fl->controller->spi, 0xFF); | 28 | - |
27 | + if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { | 29 | /* Keyboard Commands */ |
28 | + for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { | 30 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ |
29 | + ssi_transfer(fl->controller->spi, 0xFF); | 31 | #define KBD_CMD_ECHO 0xEE |
30 | + } | 32 | @@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val) |
31 | } | 33 | PS2MouseState *s = (PS2MouseState *)opaque; |
32 | 34 | ||
33 | for (i = 0; i < size; i++) { | 35 | trace_ps2_write_mouse(opaque, val); |
36 | -#ifdef DEBUG_MOUSE | ||
37 | - printf("kbd: write mouse 0x%02x\n", val); | ||
38 | -#endif | ||
39 | switch(s->common.write_cmd) { | ||
40 | default: | ||
41 | case -1: | ||
34 | -- | 42 | -- |
35 | 2.7.4 | 43 | 2.20.1 |
36 | 44 | ||
37 | 45 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | In the mtspr helper we attempt to check for "is the timer disabled" |
---|---|---|---|
2 | with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE | ||
3 | is zero and the condition is always false (Coverity complains about | ||
4 | the dead code.) | ||
2 | 5 | ||
3 | The flash devices used for the FMC controller (BMC firmware) are well | 6 | The correct check would be to test whether the TTMR_M field in the |
4 | defined for each Aspeed machine and are all smaller than the default | 7 | register is equal to TIMER_NONE instead. However, the |
5 | mapping window size, at least for CE0 which is the chip the SoC boots | 8 | cpu_openrisc_timer_update() function checks whether the timer is |
6 | from. | 9 | enabled (it looks at cpu->env.is_counting, which is set to 0 via |
10 | cpu_openrisc_count_stop() when the TTMR_M field is set to | ||
11 | TIMER_NONE), so there's no need to check for "timer disabled" in the | ||
12 | target/openrisc code. Instead, simply remove the dead code. | ||
7 | 13 | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 14 | Fixes: Coverity CID 1005812 |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 1486648058-520-3-git-send-email-clg@kaod.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Acked-by: Stafford Horne <shorne@gmail.com> | ||
17 | Message-id: 20201103114654.18540-1-peter.maydell@linaro.org | ||
12 | --- | 18 | --- |
13 | hw/arm/aspeed.c | 8 +++----- | 19 | target/openrisc/sys_helper.c | 3 --- |
14 | 1 file changed, 3 insertions(+), 5 deletions(-) | 20 | 1 file changed, 3 deletions(-) |
15 | 21 | ||
16 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 22 | diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/aspeed.c | 24 | --- a/target/openrisc/sys_helper.c |
19 | +++ b/hw/arm/aspeed.c | 25 | +++ b/target/openrisc/sys_helper.c |
20 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, | 26 | @@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) |
21 | DriveInfo *dinfo = drive_get_next(IF_MTD); | 27 | |
22 | qemu_irq cs_line; | 28 | case TO_SPR(10, 1): /* TTCR */ |
23 | 29 | cpu_openrisc_count_set(cpu, rb); | |
24 | - /* | 30 | - if (env->ttmr & TIMER_NONE) { |
25 | - * FIXME: check that we are not using a flash module exceeding | 31 | - return; |
26 | - * the controller segment size | 32 | - } |
27 | - */ | 33 | cpu_openrisc_timer_update(cpu); |
28 | fl->flash = ssi_create_slave_no_init(s->spi, flashtype); | 34 | break; |
29 | if (dinfo) { | 35 | #endif |
30 | qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo), | ||
31 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
32 | |||
33 | /* | ||
34 | * create a ROM region using the default mapping window size of | ||
35 | - * the flash module. | ||
36 | + * the flash module. The window size is 64MB for the AST2400 | ||
37 | + * SoC and 128MB for the AST2500 SoC, which is twice as big as | ||
38 | + * needed by the flash modules of the Aspeed machines. | ||
39 | */ | ||
40 | memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom", | ||
41 | fl->size, &error_abort); | ||
42 | -- | 36 | -- |
43 | 2.7.4 | 37 | 2.20.1 |
44 | 38 | ||
45 | 39 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
---|---|---|---|
2 | 2 | ||
3 | write_boot_rom() does not check for negative values. This is more a | 3 | This patch fixes CID 1432800 by removing an unnecessary check. |
4 | problem for coverity than the actual code as the size of the flash | ||
5 | device is checked when the m25p80 object is created. If there is | ||
6 | anything wrong with the backing file, we should not even reach that | ||
7 | path. | ||
8 | 4 | ||
9 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 5 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
10 | Message-id: 1486648058-520-2-git-send-email-clg@kaod.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 8 | --- |
14 | hw/arm/aspeed.c | 14 ++++++++++++-- | 9 | hw/core/register.c | 4 ---- |
15 | 1 file changed, 12 insertions(+), 2 deletions(-) | 10 | 1 file changed, 4 deletions(-) |
16 | 11 | ||
17 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 12 | diff --git a/hw/core/register.c b/hw/core/register.c |
18 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/aspeed.c | 14 | --- a/hw/core/register.c |
20 | +++ b/hw/arm/aspeed.c | 15 | +++ b/hw/core/register.c |
21 | @@ -XXX,XX +XXX,XX @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, | 16 | @@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner, |
22 | { | 17 | int index = rae[i].addr / data_size; |
23 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); | 18 | RegisterInfo *r = &ri[index]; |
24 | uint8_t *storage; | 19 | |
25 | + int64_t size; | 20 | - if (data + data_size * index == 0 || !&rae[i]) { |
26 | 21 | - continue; | |
27 | - if (rom_size > blk_getlength(blk)) { | 22 | - } |
28 | - rom_size = blk_getlength(blk); | 23 | - |
29 | + /* The block backend size should have already been 'validated' by | 24 | /* Init the register, this will zero it. */ |
30 | + * the creation of the m25p80 object. | 25 | object_initialize((void *)r, sizeof(*r), TYPE_REGISTER); |
31 | + */ | 26 | |
32 | + size = blk_getlength(blk); | ||
33 | + if (size <= 0) { | ||
34 | + error_setg(errp, "failed to get flash size"); | ||
35 | + return; | ||
36 | + } | ||
37 | + | ||
38 | + if (rom_size > size) { | ||
39 | + rom_size = size; | ||
40 | } | ||
41 | |||
42 | storage = g_new0(uint8_t, rom_size); | ||
43 | -- | 27 | -- |
44 | 2.7.4 | 28 | 2.20.1 |
45 | 29 | ||
46 | 30 | diff view generated by jsdifflib |
1 | From: Alexander Graf <agraf@suse.de> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | QEMU emulated hardware is always dma coherent with its guest. We do | 3 | Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN): |
4 | annotate that correctly on the PCI host controller, but left out | ||
5 | virtio-mmio. | ||
6 | 4 | ||
7 | Recent kernels have started to interpret that flag rather than take | 5 | >>> Overrunning array "suffixes" of 7 8-byte elements at element |
8 | dma coherency as granted with virtio-mmio. While that is considered | 6 | index 7 (byte offset 63) using index "idx" (which evaluates to 7). |
9 | a kernel bug, as it breaks previously working systems, it showed that | ||
10 | our dt description is incomplete. | ||
11 | 7 | ||
12 | This patch adds the respective marker that allows guest OSs to evaluate | 8 | Note, the biggest input value freq_to_str() can accept is UINT64_MAX, |
13 | that our virtio-mmio devices are indeed cache coherent. | 9 | which is ~18.446 EHz, less than 1000 EHz. |
14 | 10 | ||
15 | Signed-off-by: Alexander Graf <agraf@suse.de> | 11 | Reported-by: Eduardo Habkost <ehabkost@redhat.com> |
16 | Reviewed-by: Laszlo Ersek <lersek@redhat.com> | 12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
17 | Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Message-id: 1486644810-33181-2-git-send-email-agraf@suse.de | 14 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> |
15 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
16 | Message-id: 20201101215755.2021421-1-f4bug@amsat.org | ||
17 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 20 | --- |
21 | hw/arm/vexpress.c | 1 + | 21 | util/cutils.c | 3 ++- |
22 | hw/arm/virt.c | 1 + | 22 | 1 file changed, 2 insertions(+), 1 deletion(-) |
23 | 2 files changed, 2 insertions(+) | ||
24 | 23 | ||
25 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | 24 | diff --git a/util/cutils.c b/util/cutils.c |
26 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/arm/vexpress.c | 26 | --- a/util/cutils.c |
28 | +++ b/hw/arm/vexpress.c | 27 | +++ b/util/cutils.c |
29 | @@ -XXX,XX +XXX,XX @@ static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells, | 28 | @@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz) |
30 | acells, addr, scells, size); | 29 | double freq = freq_hz; |
31 | qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc); | 30 | size_t idx = 0; |
32 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1); | 31 | |
33 | + qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); | 32 | - while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) { |
34 | g_free(nodename); | 33 | + while (freq >= 1000.0) { |
35 | if (rc) { | 34 | freq /= 1000.0; |
36 | return -1; | 35 | idx++; |
37 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/arm/virt.c | ||
40 | +++ b/hw/arm/virt.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) | ||
42 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", | ||
43 | GIC_FDT_IRQ_TYPE_SPI, irq, | ||
44 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | ||
45 | + qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); | ||
46 | g_free(nodename); | ||
47 | } | 36 | } |
37 | + assert(idx < ARRAY_SIZE(suffixes)); | ||
38 | |||
39 | return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]); | ||
48 | } | 40 | } |
49 | -- | 41 | -- |
50 | 2.7.4 | 42 | 2.20.1 |
51 | 43 | ||
52 | 44 | diff view generated by jsdifflib |
1 | From: Alexander Graf <agraf@suse.de> | 1 | In commit 76346b6264a9b01979 we tried to add a configure check that |
---|---|---|---|
2 | the libgio pkg-config data was correct, which builds an executable | ||
3 | linked against it. Unfortunately this doesn't catch the problem | ||
4 | (missing static library dependency info), because a "do nothing" test | ||
5 | source file doesn't have any symbol references that cause the linker | ||
6 | to pull in .o files from libgio.a, and so we don't see the "missing | ||
7 | symbols from libmount" error that a full QEMU link triggers. | ||
2 | 8 | ||
3 | Fw-cfg recently learned how to directly access guest memory and does so in | 9 | (The ineffective test went unnoticed because of a typo that |
4 | cache coherent fashion. Tell the guest about that fact when it's using ACPI. | 10 | effectively disabled libgio unconditionally, but after commit |
11 | 3569a5dfc11f2 fixed that, a static link of the system emulator on | ||
12 | Ubuntu stopped working again.) | ||
5 | 13 | ||
6 | Signed-off-by: Alexander Graf <agraf@suse.de> | 14 | Improve the gio test by having the test source fragment reference a |
7 | Reviewed-by: Laszlo Ersek <lersek@redhat.com> | 15 | g_dbus function (which is what is indirectly causing us to end up |
8 | Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> | 16 | wanting functions from libmount). |
9 | Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> | 17 | |
10 | Message-id: 1486644810-33181-4-git-send-email-agraf@suse.de | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
20 | Message-id: 20201116104617.18333-1-peter.maydell@linaro.org | ||
12 | --- | 21 | --- |
13 | hw/arm/virt-acpi-build.c | 1 + | 22 | configure | 11 +++++++++-- |
14 | 1 file changed, 1 insertion(+) | 23 | 1 file changed, 9 insertions(+), 2 deletions(-) |
15 | 24 | ||
16 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | 25 | diff --git a/configure b/configure |
17 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100755 |
18 | --- a/hw/arm/virt-acpi-build.c | 27 | --- a/configure |
19 | +++ b/hw/arm/virt-acpi-build.c | 28 | +++ b/configure |
20 | @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap) | 29 | @@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then |
21 | aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002"))); | 30 | # Check that the libraries actually work -- Ubuntu 18.04 ships |
22 | /* device present, functioning, decoding, not shown in UI */ | 31 | # with pkg-config --static --libs data for gio-2.0 that is missing |
23 | aml_append(dev, aml_name_decl("_STA", aml_int(0xB))); | 32 | # -lblkid and will give a link error. |
24 | + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); | 33 | - write_c_skeleton |
25 | 34 | - if compile_prog "" "$gio_libs" ; then | |
26 | Aml *crs = aml_resource_template(); | 35 | + cat > $TMPC <<EOF |
27 | aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base, | 36 | +#include <gio/gio.h> |
37 | +int main(void) | ||
38 | +{ | ||
39 | + g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0); | ||
40 | + return 0; | ||
41 | +} | ||
42 | +EOF | ||
43 | + if compile_prog "$gio_cflags" "$gio_libs" ; then | ||
44 | gio=yes | ||
45 | else | ||
46 | gio=no | ||
28 | -- | 47 | -- |
29 | 2.7.4 | 48 | 2.20.1 |
30 | 49 | ||
31 | 50 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the |
---|---|---|---|
2 | power-up reset values for the T_low and T_high registers are 80 degrees C | ||
3 | and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These | ||
4 | values are then shifted right by four bits to give the register reset | ||
5 | values, since both registers store the 12 bits of temperature data in bits | ||
6 | [15..4] of a 16 bit register. | ||
2 | 7 | ||
3 | The size of a segment is not necessarily a power of 2. | 8 | We were resetting these registers to zero, which is problematic for Linux |
9 | guests which enable the alert interrupt and then immediately take an | ||
10 | unexpected overtemperature alert because the current temperature is above | ||
11 | freezing... | ||
4 | 12 | ||
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Message-id: 1486648058-520-5-git-send-email-clg@kaod.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Message-id: 20201110150023.25533-2-peter.maydell@linaro.org | ||
9 | --- | 16 | --- |
10 | hw/ssi/aspeed_smc.c | 4 ++-- | 17 | hw/misc/tmp105.c | 3 +++ |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 18 | 1 file changed, 3 insertions(+) |
12 | 19 | ||
13 | diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c | 20 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c |
14 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/ssi/aspeed_smc.c | 22 | --- a/hw/misc/tmp105.c |
16 | +++ b/hw/ssi/aspeed_smc.c | 23 | +++ b/hw/misc/tmp105.c |
17 | @@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, | 24 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) |
18 | AspeedSegments seg; | 25 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; |
19 | 26 | s->alarm = 0; | |
20 | aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg); | 27 | |
21 | - if ((addr & (seg.size - 1)) != addr) { | 28 | + s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ |
22 | + if ((addr % seg.size) != addr) { | 29 | + s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ |
23 | qemu_log_mask(LOG_GUEST_ERROR, | 30 | + |
24 | "%s: invalid address 0x%08x for CS%d segment : " | 31 | tmp105_interrupt_update(s); |
25 | "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n", | ||
26 | s->ctrl->name, addr, fl->id, seg.addr, | ||
27 | seg.addr + seg.size); | ||
28 | + addr %= seg.size; | ||
29 | } | ||
30 | |||
31 | - addr &= seg.size - 1; | ||
32 | return addr; | ||
33 | } | 32 | } |
34 | 33 | ||
35 | -- | 34 | -- |
36 | 2.7.4 | 35 | 2.20.1 |
37 | 36 | ||
38 | 37 | diff view generated by jsdifflib |
1 | From: Wei Huang <wei@redhat.com> | 1 | The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device |
---|---|---|---|
2 | signals an alert when the temperature equals or exceeds the T_high value and | ||
3 | then remains high until a device register is read or the device responds to | ||
4 | the SMBUS Alert Response address, or the device is put into Shutdown Mode. | ||
5 | Thereafter the Alert pin will only be re-signalled when temperature falls | ||
6 | below T_low; alert can then be cleared in the same set of ways, and the | ||
7 | device returns to its initial "alert when temperature goes above T_high" | ||
8 | mode. (If this textual description is confusing, see figure 3 in the | ||
9 | TI datasheet at https://www.ti.com/lit/gpn/tmp105 .) | ||
2 | 10 | ||
3 | This patch adds support for AArch64 register PMSELR_EL0. The existing | 11 | We were misimplementing this as a simple "always alert if temperature is |
4 | PMSELR definition is revised accordingly. | 12 | above T_high or below T_low" condition, which gives a spurious alert on |
13 | startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset | ||
14 | limit values. | ||
5 | 15 | ||
6 | Signed-off-by: Wei Huang <wei@redhat.com> | 16 | Implement the correct (hysteresis) behaviour by tracking whether we |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | are currently looking for the temperature to rise over T_high or |
8 | [PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs] | 18 | for it to fall below T_low. Our implementation of the comparator |
9 | Message-id: 1486504171-26807-2-git-send-email-wei@redhat.com | 19 | mode (TM==0) wasn't wrong, but rephrase it to match the way that |
20 | interrupt mode is now handled for clarity. | ||
21 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
24 | Message-id: 20201110150023.25533-3-peter.maydell@linaro.org | ||
11 | --- | 25 | --- |
12 | target/arm/cpu.h | 1 + | 26 | hw/misc/tmp105.h | 7 +++++ |
13 | target/arm/helper.c | 27 +++++++++++++++++++++------ | 27 | hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++------- |
14 | 2 files changed, 22 insertions(+), 6 deletions(-) | 28 | 2 files changed, 68 insertions(+), 9 deletions(-) |
15 | 29 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 30 | diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h |
17 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 32 | --- a/hw/misc/tmp105.h |
19 | +++ b/target/arm/cpu.h | 33 | +++ b/hw/misc/tmp105.h |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 34 | @@ -XXX,XX +XXX,XX @@ struct TMP105State { |
21 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | 35 | int16_t limit[2]; |
22 | uint32_t c9_pmxevtyper; /* perf monitor event type */ | 36 | int faults; |
23 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | 37 | uint8_t alarm; |
24 | + uint64_t c9_pmselr; /* perf monitor counter selection register */ | 38 | + /* |
25 | uint32_t c9_pminten; /* perf monitor interrupt enables */ | 39 | + * The TMP105 initially looks for a temperature rising above T_high; |
26 | union { /* Memory attribute redirection */ | 40 | + * once this is detected, the condition it looks for next is the |
27 | struct { | 41 | + * temperature falling below T_low. This flag is false when initially |
28 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 42 | + * looking for T_high, true when looking for T_low. |
43 | + */ | ||
44 | + bool detect_falling; | ||
45 | }; | ||
46 | |||
47 | #endif | ||
48 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 49 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/helper.c | 50 | --- a/hw/misc/tmp105.c |
31 | +++ b/target/arm/helper.c | 51 | +++ b/hw/misc/tmp105.c |
32 | @@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 52 | @@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s) |
33 | return total_ticks - env->cp15.c15_ccnt; | 53 | return; |
54 | } | ||
55 | |||
56 | - if ((s->config >> 1) & 1) { /* TM */ | ||
57 | - if (s->temperature >= s->limit[1]) | ||
58 | - s->alarm = 1; | ||
59 | - else if (s->temperature < s->limit[0]) | ||
60 | - s->alarm = 1; | ||
61 | + if (s->config >> 1 & 1) { | ||
62 | + /* | ||
63 | + * TM == 1 : Interrupt mode. We signal Alert when the | ||
64 | + * temperature rises above T_high, and expect the guest to clear | ||
65 | + * it (eg by reading a device register). | ||
66 | + */ | ||
67 | + if (s->detect_falling) { | ||
68 | + if (s->temperature < s->limit[0]) { | ||
69 | + s->alarm = 1; | ||
70 | + s->detect_falling = false; | ||
71 | + } | ||
72 | + } else { | ||
73 | + if (s->temperature >= s->limit[1]) { | ||
74 | + s->alarm = 1; | ||
75 | + s->detect_falling = true; | ||
76 | + } | ||
77 | + } | ||
78 | } else { | ||
79 | - if (s->temperature >= s->limit[1]) | ||
80 | - s->alarm = 1; | ||
81 | - else if (s->temperature < s->limit[0]) | ||
82 | - s->alarm = 0; | ||
83 | + /* | ||
84 | + * TM == 0 : Comparator mode. We signal Alert when the temperature | ||
85 | + * rises above T_high, and stop signalling it when the temperature | ||
86 | + * falls below T_low. | ||
87 | + */ | ||
88 | + if (s->detect_falling) { | ||
89 | + if (s->temperature < s->limit[0]) { | ||
90 | + s->alarm = 0; | ||
91 | + s->detect_falling = false; | ||
92 | + } | ||
93 | + } else { | ||
94 | + if (s->temperature >= s->limit[1]) { | ||
95 | + s->alarm = 1; | ||
96 | + s->detect_falling = true; | ||
97 | + } | ||
98 | + } | ||
99 | } | ||
100 | |||
101 | tmp105_interrupt_update(s); | ||
102 | @@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id) | ||
103 | return 0; | ||
34 | } | 104 | } |
35 | 105 | ||
36 | +static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 106 | +static bool detect_falling_needed(void *opaque) |
37 | + uint64_t value) | ||
38 | +{ | 107 | +{ |
39 | + /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | 108 | + TMP105State *s = opaque; |
40 | + * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | 109 | + |
41 | + * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | 110 | + /* |
42 | + * accessed. | 111 | + * We only need to migrate the detect_falling bool if it's set; |
112 | + * for migration from older machines we assume that it is false | ||
113 | + * (ie temperature is not out of range). | ||
43 | + */ | 114 | + */ |
44 | + env->cp15.c9_pmselr = value & 0x1f; | 115 | + return s->detect_falling; |
45 | +} | 116 | +} |
46 | + | 117 | + |
47 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 118 | +static const VMStateDescription vmstate_tmp105_detect_falling = { |
48 | uint64_t value) | 119 | + .name = "TMP105/detect-falling", |
49 | { | 120 | + .version_id = 1, |
50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | 121 | + .minimum_version_id = 1, |
51 | /* Unimplemented so WI. */ | 122 | + .needed = detect_falling_needed, |
52 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, | 123 | + .fields = (VMStateField[]) { |
53 | .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, | 124 | + VMSTATE_BOOL(detect_falling, TMP105State), |
54 | - /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE. | 125 | + VMSTATE_END_OF_LIST() |
55 | - * We choose to RAZ/WI. | 126 | + } |
56 | - */ | 127 | +}; |
57 | - { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | 128 | + |
58 | - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, | 129 | static const VMStateDescription vmstate_tmp105 = { |
59 | - .accessfn = pmreg_access }, | 130 | .name = "TMP105", |
60 | #ifndef CONFIG_USER_ONLY | 131 | .version_id = 0, |
61 | + { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | 132 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = { |
62 | + .access = PL0_RW, .type = ARM_CP_ALIAS, | 133 | VMSTATE_UINT8(alarm, TMP105State), |
63 | + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | 134 | VMSTATE_I2C_SLAVE(i2c, TMP105State), |
64 | + .accessfn = pmreg_access, .writefn = pmselr_write, | 135 | VMSTATE_END_OF_LIST() |
65 | + .raw_writefn = raw_write}, | 136 | + }, |
66 | + { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | 137 | + .subsections = (const VMStateDescription*[]) { |
67 | + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | 138 | + &vmstate_tmp105_detect_falling, |
68 | + .access = PL0_RW, .accessfn = pmreg_access, | 139 | + NULL |
69 | + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), | 140 | } |
70 | + .writefn = pmselr_write, .raw_writefn = raw_write, }, | 141 | }; |
71 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, | 142 | |
72 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, | 143 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) |
73 | .readfn = pmccntr_read, .writefn = pmccntr_write32, | 144 | s->config = 0; |
145 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | ||
146 | s->alarm = 0; | ||
147 | + s->detect_falling = false; | ||
148 | |||
149 | s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | ||
150 | s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | ||
74 | -- | 151 | -- |
75 | 2.7.4 | 152 | 2.20.1 |
76 | 153 | ||
77 | 154 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Wei Huang <wei@redhat.com> | ||
2 | 1 | ||
3 | This patch adds access support for PMINTENSET_EL1. | ||
4 | |||
5 | Signed-off-by: Wei Huang <wei@redhat.com> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Message-id: 1486504171-26807-4-git-send-email-wei@redhat.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.h | 2 +- | ||
11 | target/arm/helper.c | 10 +++++++++- | ||
12 | 2 files changed, 10 insertions(+), 2 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
19 | uint32_t c9_pmovsr; /* perf monitor overflow status */ | ||
20 | uint32_t c9_pmuserenr; /* perf monitor user enable */ | ||
21 | uint64_t c9_pmselr; /* perf monitor counter selection register */ | ||
22 | - uint32_t c9_pminten; /* perf monitor interrupt enables */ | ||
23 | + uint64_t c9_pminten; /* perf monitor interrupt enables */ | ||
24 | union { /* Memory attribute redirection */ | ||
25 | struct { | ||
26 | #ifdef HOST_WORDS_BIGENDIAN | ||
27 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/helper.c | ||
30 | +++ b/target/arm/helper.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
32 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | ||
33 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, | ||
34 | .access = PL1_RW, .accessfn = access_tpm, | ||
35 | - .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
36 | + .type = ARM_CP_ALIAS, | ||
37 | + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), | ||
38 | .resetvalue = 0, | ||
39 | .writefn = pmintenset_write, .raw_writefn = raw_write }, | ||
40 | + { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, | ||
41 | + .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | ||
42 | + .access = PL1_RW, .accessfn = access_tpm, | ||
43 | + .type = ARM_CP_IO, | ||
44 | + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
45 | + .writefn = pmintenset_write, .raw_writefn = raw_write, | ||
46 | + .resetvalue = 0x0 }, | ||
47 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, | ||
48 | .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, | ||
49 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
50 | -- | ||
51 | 2.7.4 | ||
52 | |||
53 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Wei Huang <wei@redhat.com> | ||
2 | 1 | ||
3 | This patch contains several fixes to enable vPMU under TCG mode. It | ||
4 | first removes the checking of kvm_enabled() while unsetting | ||
5 | ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU | ||
6 | under TCG mode. Secondly the PMU node of DT table is now created under TCG. | ||
7 | The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1. | ||
8 | |||
9 | Signed-off-by: Wei Huang <wei@redhat.com> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 1486504171-26807-5-git-send-email-wei@redhat.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/virt.c | 2 +- | ||
15 | target/arm/cpu.c | 2 +- | ||
16 | target/arm/helper.c | 7 +------ | ||
17 | 3 files changed, 3 insertions(+), 8 deletions(-) | ||
18 | |||
19 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/arm/virt.c | ||
22 | +++ b/hw/arm/virt.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms) | ||
24 | CPU_FOREACH(cpu) { | ||
25 | armcpu = ARM_CPU(cpu); | ||
26 | if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || | ||
27 | - !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { | ||
28 | + (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) { | ||
29 | return; | ||
30 | } | ||
31 | } | ||
32 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/cpu.c | ||
35 | +++ b/target/arm/cpu.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
37 | unset_feature(env, ARM_FEATURE_EL2); | ||
38 | } | ||
39 | |||
40 | - if (!cpu->has_pmu || !kvm_enabled()) { | ||
41 | + if (!cpu->has_pmu) { | ||
42 | cpu->has_pmu = false; | ||
43 | unset_feature(env, ARM_FEATURE_PMU); | ||
44 | } | ||
45 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/helper.c | ||
48 | +++ b/target/arm/helper.c | ||
49 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
50 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
51 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | ||
52 | .access = PL1_R, .type = ARM_CP_CONST, | ||
53 | - /* We mask out the PMUVer field, because we don't currently | ||
54 | - * implement the PMU. Not advertising it prevents the guest | ||
55 | - * from trying to use it and getting UNDEFs on registers we | ||
56 | - * don't implement. | ||
57 | - */ | ||
58 | - .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, | ||
59 | + .resetvalue = cpu->id_aa64dfr0 }, | ||
60 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
61 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | ||
62 | .access = PL1_R, .type = ARM_CP_CONST, | ||
63 | -- | ||
64 | 2.7.4 | ||
65 | |||
66 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alexander Graf <agraf@suse.de> | ||
2 | 1 | ||
3 | Virtio-mmio devices can directly access guest memory and do so in cache | ||
4 | coherent fashion. Tell the guest about that fact when it's using ACPI. | ||
5 | |||
6 | Signed-off-by: Alexander Graf <agraf@suse.de> | ||
7 | Reviewed-by: Laszlo Ersek <lersek@redhat.com> | ||
8 | Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> | ||
9 | Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> | ||
10 | Message-id: 1486644810-33181-3-git-send-email-agraf@suse.de | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/arm/virt-acpi-build.c | 1 + | ||
14 | 1 file changed, 1 insertion(+) | ||
15 | |||
16 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/arm/virt-acpi-build.c | ||
19 | +++ b/hw/arm/virt-acpi-build.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_virtio(Aml *scope, | ||
21 | Aml *dev = aml_device("VR%02u", i); | ||
22 | aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005"))); | ||
23 | aml_append(dev, aml_name_decl("_UID", aml_int(i))); | ||
24 | + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); | ||
25 | |||
26 | Aml *crs = aml_resource_template(); | ||
27 | aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE)); | ||
28 | -- | ||
29 | 2.7.4 | ||
30 | |||
31 | diff view generated by jsdifflib |