[Qemu-devel] [PULL 00/12] target-arm queue
[Qemu-devel] [PULL 00/16] target-arm queue
1
ARM queue: nothing particularly exciting here, but no
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
2
reason to sit on them for another week.
3
2
4
thanks
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
5
-- PMM
6
4
7
The following changes since commit 61eedf7aec0e2395aabd628cc055096909a3ea15:
5
are available in the Git repository at:
8
6
9
tests/prom-env: Ease time-out problems on slow hosts (2017-02-10 15:44:53 +0000)
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
10
8
11
are available in the git repository at:
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
12
10
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170210
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
14
15
for you to fetch changes up to b4cc583f0285a2e1e78621dfba142f00ca47414a:
16
17
aspeed/smc: use a modulo to check segment limits (2017-02-10 17:40:30 +0000)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* aspeed: minor fixes
15
* Fix coverity nit in int_to_float code
22
* virt: declare fwcfg and virtio-mmio as DMA coherent in DT & ACPI
16
* Don't set Invalid for float-to-int(MAXINT)
23
* arm: enable basic TCG emulation of PMU for AArch64
17
* Fix fp_status_f16 tininess before rounding
18
* Add various missing insns from the v8.2-FP16 extension
19
* Fix sqrt_f16 exception raising
20
* sdcard: Correct CRC16 offset in sd_function_switch()
21
* tcg: Optionally log FPU state in TCG -d cpu logging
24
22
25
----------------------------------------------------------------
23
----------------------------------------------------------------
26
Alexander Graf (4):
24
Alex Bennée (5):
27
target-arm: Declare virtio-mmio as dma-coherent in dt
25
fpu/softfloat: int_to_float ensure r fully initialised
28
hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
26
target/arm: Implement FCMP for fp16
29
hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
27
target/arm: Implement FCSEL for fp16
30
hw/arm/virt: Declare fwcfg as dma cache coherent in dt
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
31
30
32
Cédric Le Goater (4):
31
Peter Maydell (3):
33
aspeed: check for negative values returned by blk_getlength()
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
34
aspeed: remove useless comment on controller segment size
33
target/arm: Fix fp_status_f16 tininess before rounding
35
aspeed/smc: handle dummies only in fast read mode
34
tcg: Optionally log FPU state in TCG -d cpu logging
36
aspeed/smc: use a modulo to check segment limits
37
35
38
Wei Huang (4):
36
Philippe Mathieu-Daudé (1):
39
target-arm: Add support for PMU register PMSELR_EL0
37
sdcard: Correct CRC16 offset in sd_function_switch()
40
target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
41
target-arm: Add support for PMU register PMINTENSET_EL1
42
target-arm: Enable vPMU support under TCG mode
43
38
44
target/arm/cpu.h | 4 +--
39
Richard Henderson (7):
45
hw/arm/aspeed.c | 22 +++++++++-----
40
target/arm: Implement FMOV (general) for fp16
46
hw/arm/vexpress.c | 1 +
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
47
hw/arm/virt-acpi-build.c | 2 ++
42
target/arm: Implement FCVT (scalar, integer) for fp16
48
hw/arm/virt.c | 4 ++-
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
49
hw/ssi/aspeed_smc.c | 13 +++++----
44
target/arm: Introduce and use read_fp_hreg
50
target/arm/cpu.c | 2 +-
45
target/arm: Implement FP data-processing (2 source) for fp16
51
target/arm/helper.c | 74 ++++++++++++++++++++++++++++++++++++------------
46
target/arm: Implement FP data-processing (3 source) for fp16
52
8 files changed, 88 insertions(+), 34 deletions(-)
53
47
48
include/qemu/log.h | 1 +
49
target/arm/helper-a64.h | 2 +
50
target/arm/helper.h | 6 +
51
accel/tcg/cpu-exec.c | 9 +-
52
fpu/softfloat.c | 6 +-
53
hw/sd/sd.c | 2 +-
54
target/arm/cpu.c | 2 +
55
target/arm/helper-a64.c | 10 ++
56
target/arm/helper.c | 38 +++-
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
58
util/log.c | 2 +
59
11 files changed, 428 insertions(+), 71 deletions(-)
60
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
4
later on so we might as well mirror that.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
fpu/softfloat.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
17
+++ b/fpu/softfloat.c
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
19
20
static FloatParts int_to_float(int64_t a, float_status *status)
21
{
22
- FloatParts r;
23
+ FloatParts r = {};
24
if (a == 0) {
25
r.cls = float_class_zero;
26
r.sign = false;
27
--
28
2.17.0
29
30
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
1
In float-to-integer conversion, if the floating point input
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
1
8
9
Fix the boundary case to take the right half of the if()
10
statements.
11
12
This fixes a regression from 2.11 introduced by the softfloat
13
refactoring.
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
20
---
21
fpu/softfloat.c | 4 ++--
22
1 file changed, 2 insertions(+), 2 deletions(-)
23
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
27
+++ b/fpu/softfloat.c
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
29
r = UINT64_MAX;
30
}
31
if (p.sign) {
32
- if (r < -(uint64_t) min) {
33
+ if (r <= -(uint64_t) min) {
34
return -r;
35
} else {
36
s->float_exception_flags = orig_flags | float_flag_invalid;
37
return min;
38
}
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
45
--
46
2.17.0
47
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/12] target-arm: Enable vPMU support under TCG mode
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
1
From: Wei Huang <wei@redhat.com>
1
In commit d81ce0ef2c4f105 we added an extra float_status field
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
2
8
3
This patch contains several fixes to enable vPMU under TCG mode. It
9
Add the missing initialization.
4
first removes the checking of kvm_enabled() while unsetting
5
ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU
6
under TCG mode. Secondly the PMU node of DT table is now created under TCG.
7
The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1.
8
10
9
Signed-off-by: Wei Huang <wei@redhat.com>
11
Fixes: d81ce0ef2c4f105
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Cc: qemu-stable@nongnu.org
11
Message-id: 1486504171-26807-5-git-send-email-wei@redhat.com
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
13
---
17
---
14
hw/arm/virt.c | 2 +-
18
target/arm/cpu.c | 2 ++
15
target/arm/cpu.c | 2 +-
19
1 file changed, 2 insertions(+)
16
target/arm/helper.c | 7 +------
17
3 files changed, 3 insertions(+), 8 deletions(-)
18
20
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
22
+++ b/hw/arm/virt.c
23
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
24
CPU_FOREACH(cpu) {
25
armcpu = ARM_CPU(cpu);
26
if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) ||
27
- !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) {
28
+ (kvm_enabled() && !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ)))) {
29
return;
30
}
31
}
32
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
33
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/cpu.c
23
--- a/target/arm/cpu.c
35
+++ b/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
37
unset_feature(env, ARM_FEATURE_EL2);
26
&env->vfp.fp_status);
38
}
27
set_float_detect_tininess(float_tininess_before_rounding,
39
28
&env->vfp.standard_fp_status);
40
- if (!cpu->has_pmu || !kvm_enabled()) {
29
+ set_float_detect_tininess(float_tininess_before_rounding,
41
+ if (!cpu->has_pmu) {
30
+ &env->vfp.fp_status_f16);
42
cpu->has_pmu = false;
31
#ifndef CONFIG_USER_ONLY
43
unset_feature(env, ARM_FEATURE_PMU);
32
if (kvm_enabled()) {
44
}
33
kvm_arm_reset_vcpu(cpu);
45
diff --git a/target/arm/helper.c b/target/arm/helper.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/helper.c
48
+++ b/target/arm/helper.c
49
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
50
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
51
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
52
.access = PL1_R, .type = ARM_CP_CONST,
53
- /* We mask out the PMUVer field, because we don't currently
54
- * implement the PMU. Not advertising it prevents the guest
55
- * from trying to use it and getting UNDEFs on registers we
56
- * don't implement.
57
- */
58
- .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
59
+ .resetvalue = cpu->id_aa64dfr0 },
60
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
61
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
62
.access = PL1_R, .type = ARM_CP_CONST,
63
--
34
--
64
2.7.4
35
2.17.0
65
36
66
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/12] target-arm: Declare virtio-mmio as dma-coherent in dt
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
1
From: Alexander Graf <agraf@suse.de>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
QEMU emulated hardware is always dma coherent with its guest. We do
3
Adding the fp16 moves to/from general registers.
4
annotate that correctly on the PCI host controller, but left out
5
virtio-mmio.
6
4
7
Recent kernels have started to interpret that flag rather than take
5
Cc: qemu-stable@nongnu.org
8
dma coherency as granted with virtio-mmio. While that is considered
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
a kernel bug, as it breaks previously working systems, it showed that
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
our dt description is incomplete.
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
11
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
This patch adds the respective marker that allows guest OSs to evaluate
13
that our virtio-mmio devices are indeed cache coherent.
14
15
Signed-off-by: Alexander Graf <agraf@suse.de>
16
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
17
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
18
Message-id: 1486644810-33181-2-git-send-email-agraf@suse.de
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
11
---
21
hw/arm/vexpress.c | 1 +
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
22
hw/arm/virt.c | 1 +
13
1 file changed, 21 insertions(+)
23
2 files changed, 2 insertions(+)
24
14
25
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/vexpress.c
17
--- a/target/arm/translate-a64.c
28
+++ b/hw/arm/vexpress.c
18
+++ b/target/arm/translate-a64.c
29
@@ -XXX,XX +XXX,XX @@ static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
30
acells, addr, scells, size);
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
31
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
21
clear_vec_high(s, true, rd);
32
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
22
break;
33
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
23
+ case 3:
34
g_free(nodename);
24
+ /* 16 bit */
35
if (rc) {
25
+ tmp = tcg_temp_new_i64();
36
return -1;
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
37
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
27
+ write_fp_dreg(s, rd, tmp);
38
index XXXXXXX..XXXXXXX 100644
28
+ tcg_temp_free_i64(tmp);
39
--- a/hw/arm/virt.c
29
+ break;
40
+++ b/hw/arm/virt.c
30
+ default:
41
@@ -XXX,XX +XXX,XX @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
31
+ g_assert_not_reached();
42
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
32
}
43
GIC_FDT_IRQ_TYPE_SPI, irq,
33
} else {
44
GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
45
+ qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
46
g_free(nodename);
36
/* 64 bits from top half */
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
47
}
46
}
48
}
47
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
49
case 0xa: /* 64 bit */
50
case 0xd: /* 64 bit to top half of quad */
51
break;
52
+ case 0x6: /* 16-bit float, 32-bit int */
53
+ case 0xe: /* 16-bit float, 64-bit int */
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
55
+ break;
56
+ }
57
+ /* fallthru */
58
default:
59
/* all other sf/type/rmode combinations are invalid */
60
unallocated_encoding(s);
49
--
61
--
50
2.7.4
62
2.17.0
51
63
52
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/12] aspeed/smc: handle dummies only in fast read mode
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
HW works fine in normal read mode with dummy bytes being set. So let's
3
No sense in emitting code after the exception.
4
check this case to not transfer bytes.
5
4
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 1486648058-520-4-git-send-email-clg@kaod.org
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
hw/ssi/aspeed_smc.c | 9 ++++++---
11
target/arm/translate-a64.c | 2 +-
11
1 file changed, 6 insertions(+), 3 deletions(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
13
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/ssi/aspeed_smc.c
16
--- a/target/arm/translate-a64.c
16
+++ b/hw/ssi/aspeed_smc.c
17
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
18
/*
19
default:
19
* Use fake transfers to model dummy bytes. The value should
20
/* all other sf/type/rmode combinations are invalid */
20
* be configured to some non-zero value in fast read mode and
21
unallocated_encoding(s);
21
- * zero in read mode.
22
- break;
22
+ * zero in read mode. But, as the HW allows inconsistent
23
+ return;
23
+ * settings, let's check for fast read mode.
24
*/
25
- for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
26
- ssi_transfer(fl->controller->spi, 0xFF);
27
+ if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
28
+ for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
29
+ ssi_transfer(fl->controller->spi, 0xFF);
30
+ }
31
}
24
}
32
25
33
for (i = 0; i < size; i++) {
26
if (!fp_access_check(s)) {
34
--
27
--
35
2.7.4
28
2.17.0
36
29
37
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
1
From: Wei Huang <wei@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch adds access support for PMINTENSET_EL1.
3
Cc: qemu-stable@nongnu.org
4
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Wei Huang <wei@redhat.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1486504171-26807-4-git-send-email-wei@redhat.com
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
target/arm/cpu.h | 2 +-
10
target/arm/helper.h | 6 +++
11
target/arm/helper.c | 10 +++++++++-
11
target/arm/helper.c | 38 ++++++++++++++-
12
2 files changed, 10 insertions(+), 2 deletions(-)
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
13
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
--- a/target/arm/helper.h
17
+++ b/target/arm/cpu.h
18
+++ b/target/arm/helper.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
19
uint32_t c9_pmovsr; /* perf monitor overflow status */
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
20
uint32_t c9_pmuserenr; /* perf monitor user enable */
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
21
uint64_t c9_pmselr; /* perf monitor counter selection register */
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
22
- uint32_t c9_pminten; /* perf monitor interrupt enables */
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
23
+ uint64_t c9_pminten; /* perf monitor interrupt enables */
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
24
union { /* Memory attribute redirection */
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
25
struct {
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
26
#ifdef HOST_WORDS_BIGENDIAN
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
32
.writefn = pmuserenr_write, .raw_writefn = raw_write },
44
#undef VFP_CONV_FIX_A64
33
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
45
34
.access = PL1_RW, .accessfn = access_tpm,
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
35
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
47
- * Therefore we convert to f64 (which does not round), scale,
36
+ .type = ARM_CP_ALIAS,
48
- * and then convert f64 to f16 (which may round).
37
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
38
.resetvalue = 0,
50
+ * vice versa for conversion to integer.
39
.writefn = pmintenset_write, .raw_writefn = raw_write },
51
+ *
40
+ { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
41
+ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
53
+ * For 64-bit integers, any integer that would cause rounding will also
42
+ .access = PL1_RW, .accessfn = access_tpm,
54
+ * overflow to f16 infinity, so there is no double rounding problem.
43
+ .type = ARM_CP_IO,
55
*/
44
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
56
45
+ .writefn = pmintenset_write, .raw_writefn = raw_write,
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
46
+ .resetvalue = 0x0 },
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
47
{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
48
.access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
60
}
49
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
61
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
65
+}
66
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
68
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
70
+}
71
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
50
--
265
--
51
2.7.4
266
2.17.0
52
267
53
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/12] aspeed: remove useless comment on controller segment size
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The flash devices used for the FMC controller (BMC firmware) are well
3
Cc: qemu-stable@nongnu.org
4
defined for each Aspeed machine and are all smaller than the default
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
mapping window size, at least for CE0 which is the chip the SoC boots
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
from.
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 1486648058-520-3-git-send-email-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
hw/arm/aspeed.c | 8 +++-----
10
target/arm/translate-a64.c | 17 +++++++++++++++--
14
1 file changed, 3 insertions(+), 5 deletions(-)
11
1 file changed, 15 insertions(+), 2 deletions(-)
15
12
16
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/aspeed.c
15
--- a/target/arm/translate-a64.c
19
+++ b/hw/arm/aspeed.c
16
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
21
DriveInfo *dinfo = drive_get_next(IF_MTD);
18
bool sf = extract32(insn, 31, 1);
22
qemu_irq cs_line;
19
bool itof;
23
20
24
- /*
21
- if (sbit || (type > 1)
25
- * FIXME: check that we are not using a flash module exceeding
22
- || (!sf && scale < 32)) {
26
- * the controller segment size
23
+ if (sbit || (!sf && scale < 32)) {
27
- */
24
+ unallocated_encoding(s);
28
fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
25
+ return;
29
if (dinfo) {
26
+ }
30
qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
27
+
31
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
28
+ switch (type) {
32
29
+ case 0: /* float32 */
33
/*
30
+ case 1: /* float64 */
34
* create a ROM region using the default mapping window size of
31
+ break;
35
- * the flash module.
32
+ case 3: /* float16 */
36
+ * the flash module. The window size is 64MB for the AST2400
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
37
+ * SoC and 128MB for the AST2500 SoC, which is twice as big as
34
+ break;
38
+ * needed by the flash modules of the Aspeed machines.
35
+ }
39
*/
36
+ /* fallthru */
40
memory_region_init_rom(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
37
+ default:
41
fl->size, &error_abort);
38
unallocated_encoding(s);
39
return;
40
}
42
--
41
--
43
2.7.4
42
2.17.0
44
43
45
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/12] aspeed/smc: use a modulo to check segment limits
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The size of a segment is not necessarily a power of 2.
3
Cc: qemu-stable@nongnu.org
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1486648058-520-5-git-send-email-clg@kaod.org
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
hw/ssi/aspeed_smc.c | 4 ++--
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
11
1 file changed, 2 insertions(+), 2 deletions(-)
11
1 file changed, 14 insertions(+), 16 deletions(-)
12
12
13
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/ssi/aspeed_smc.c
15
--- a/target/arm/translate-a64.c
16
+++ b/hw/ssi/aspeed_smc.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
18
AspeedSegments seg;
18
return v;
19
19
}
20
aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);
20
21
- if ((addr & (seg.size - 1)) != addr) {
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
22
+ if ((addr % seg.size) != addr) {
22
+{
23
qemu_log_mask(LOG_GUEST_ERROR,
23
+ TCGv_i32 v = tcg_temp_new_i32();
24
"%s: invalid address 0x%08x for CS%d segment : "
24
+
25
"[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]\n",
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
26
s->ctrl->name, addr, fl->id, seg.addr,
26
+ return v;
27
seg.addr + seg.size);
27
+}
28
+ addr %= seg.size;
28
+
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
30
* If SVE is not enabled, then there are only 128 bits in the vector.
31
*/
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
34
{
35
TCGv_ptr fpst = NULL;
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
39
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
41
-
42
switch (opcode) {
43
case 0x0: /* FMOV */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
48
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
29
}
78
}
30
79
31
- addr &= seg.size - 1;
80
if (is_scalar) {
32
return addr;
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
33
}
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
34
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
35
--
90
--
36
2.7.4
91
2.17.0
37
92
38
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/12] hw/arm/virt: Declare fwcfg as dma cache coherent in dt
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
1
From: Alexander Graf <agraf@suse.de>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fw-cfg recently learned how to directly access guest memory and does so in
3
We missed all of the scalar fp16 binary operations.
4
cache coherent fashion. Tell the guest about that fact when it's using DT.
5
4
6
Signed-off-by: Alexander Graf <agraf@suse.de>
5
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 1486644810-33181-5-git-send-email-agraf@suse.de
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
hw/arm/virt.c | 1 +
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
14
1 file changed, 1 insertion(+)
13
1 file changed, 65 insertions(+)
15
14
16
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt.c
17
--- a/target/arm/translate-a64.c
19
+++ b/hw/arm/virt.c
18
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
21
"compatible", "qemu,fw-cfg-mmio");
20
tcg_temp_free_i64(tcg_res);
22
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
23
2, base, 2, size);
24
+ qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
25
g_free(nodename);
26
return fw_cfg;
27
}
21
}
22
23
+/* Floating-point data-processing (2 source) - half precision */
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
25
+ int rd, int rn, int rm)
26
+{
27
+ TCGv_i32 tcg_op1;
28
+ TCGv_i32 tcg_op2;
29
+ TCGv_i32 tcg_res;
30
+ TCGv_ptr fpst;
31
+
32
+ tcg_res = tcg_temp_new_i32();
33
+ fpst = get_fpstatus_ptr(true);
34
+ tcg_op1 = read_fp_hreg(s, rn);
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
77
+
78
/* Floating point data-processing (2 source)
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
82
}
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
84
break;
85
+ case 3:
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
87
+ unallocated_encoding(s);
88
+ return;
89
+ }
90
+ if (!fp_access_check(s)) {
91
+ return;
92
+ }
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
94
+ break;
95
default:
96
unallocated_encoding(s);
97
}
28
--
98
--
29
2.7.4
99
2.17.0
30
100
31
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/12] target-arm: Add support for PMU register PMSELR_EL0
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
1
From: Wei Huang <wei@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This patch adds support for AArch64 register PMSELR_EL0. The existing
3
We missed all of the scalar fp16 fma operations.
4
PMSELR definition is revised accordingly.
5
4
6
Signed-off-by: Wei Huang <wei@redhat.com>
5
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
[PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs]
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 1486504171-26807-2-git-send-email-wei@redhat.com
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/cpu.h | 1 +
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
13
target/arm/helper.c | 27 +++++++++++++++++++++------
13
1 file changed, 48 insertions(+)
14
2 files changed, 22 insertions(+), 6 deletions(-)
15
14
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
17
--- a/target/arm/translate-a64.c
19
+++ b/target/arm/cpu.h
18
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
21
uint32_t c9_pmovsr; /* perf monitor overflow status */
20
tcg_temp_free_i64(tcg_res);
22
uint32_t c9_pmxevtyper; /* perf monitor event type */
23
uint32_t c9_pmuserenr; /* perf monitor user enable */
24
+ uint64_t c9_pmselr; /* perf monitor counter selection register */
25
uint32_t c9_pminten; /* perf monitor interrupt enables */
26
union { /* Memory attribute redirection */
27
struct {
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
33
return total_ticks - env->cp15.c15_ccnt;
34
}
21
}
35
22
36
+static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
23
+/* Floating-point data-processing (3 source) - half precision */
37
+ uint64_t value)
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
25
+ int rd, int rn, int rm, int ra)
38
+{
26
+{
39
+ /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
40
+ * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
41
+ * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
42
+ * accessed.
30
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
32
+ tcg_op2 = read_fp_hreg(s, rm);
33
+ tcg_op3 = read_fp_hreg(s, ra);
34
+
35
+ /* These are fused multiply-add, and must be done as one
36
+ * floating point operation with no rounding between the
37
+ * multiplication and addition steps.
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
43
+ */
41
+ */
44
+ env->cp15.c9_pmselr = value & 0x1f;
42
+ if (o1 == true) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
44
+ }
45
+
46
+ if (o0 != o1) {
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
48
+ }
49
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
51
+
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
45
+}
59
+}
46
+
60
+
47
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
61
/* Floating point data-processing (3 source)
48
uint64_t value)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
49
{
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
51
/* Unimplemented so WI. */
65
}
52
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
53
.access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
67
break;
54
- /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
68
+ case 3:
55
- * We choose to RAZ/WI.
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
56
- */
70
+ unallocated_encoding(s);
57
- { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
71
+ return;
58
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
72
+ }
59
- .accessfn = pmreg_access },
73
+ if (!fp_access_check(s)) {
60
#ifndef CONFIG_USER_ONLY
74
+ return;
61
+ { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
75
+ }
62
+ .access = PL0_RW, .type = ARM_CP_ALIAS,
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
63
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
77
+ break;
64
+ .accessfn = pmreg_access, .writefn = pmselr_write,
78
default:
65
+ .raw_writefn = raw_write},
79
unallocated_encoding(s);
66
+ { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
80
}
67
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
68
+ .access = PL0_RW, .accessfn = pmreg_access,
69
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
70
+ .writefn = pmselr_write, .raw_writefn = raw_write, },
71
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
72
.access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
73
.readfn = pmccntr_read, .writefn = pmccntr_write32,
74
--
81
--
75
2.7.4
82
2.17.0
76
83
77
84
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
1
1
From: Alex Bennée <alex.bennee@linaro.org>
2
3
These where missed out from the rest of the half-precision work.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/helper-a64.h | 2 +
16
target/arm/helper-a64.c | 10 +++++
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
23
+++ b/target/arm/helper-a64.h
24
@@ -XXX,XX +XXX,XX @@
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
36
+++ b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
38
return flags;
39
}
40
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
42
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
44
+}
45
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
52
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
60
}
61
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
63
+static void handle_fp_compare(DisasContext *s, int size,
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
165
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
215
2.17.0
216
217
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/12] aspeed: check for negative values returned by blk_getlength()
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
write_boot_rom() does not check for negative values. This is more a
3
These were missed out from the rest of the half-precision work.
4
problem for coverity than the actual code as the size of the flash
5
device is checked when the m25p80 object is created. If there is
6
anything wrong with the backing file, we should not even reach that
7
path.
8
4
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5
Cc: qemu-stable@nongnu.org
10
Message-id: 1486648058-520-2-git-send-email-clg@kaod.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
hw/arm/aspeed.c | 14 ++++++++++++--
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
15
1 file changed, 12 insertions(+), 2 deletions(-)
16
1 file changed, 25 insertions(+), 6 deletions(-)
16
17
17
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/aspeed.c
20
--- a/target/arm/translate-a64.c
20
+++ b/hw/arm/aspeed.c
21
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
22
{
23
unsigned int mos, type, rm, cond, rn, rd;
23
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
24
TCGv_i64 t_true, t_false, t_zero;
24
uint8_t *storage;
25
DisasCompare64 c;
25
+ int64_t size;
26
+ TCGMemOp sz;
26
27
27
- if (rom_size > blk_getlength(blk)) {
28
mos = extract32(insn, 29, 3);
28
- rom_size = blk_getlength(blk);
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
29
+ /* The block backend size should have already been 'validated' by
30
+ type = extract32(insn, 22, 2);
30
+ * the creation of the m25p80 object.
31
rm = extract32(insn, 16, 5);
31
+ */
32
cond = extract32(insn, 12, 4);
32
+ size = blk_getlength(blk);
33
rn = extract32(insn, 5, 5);
33
+ if (size <= 0) {
34
rd = extract32(insn, 0, 5);
34
+ error_setg(errp, "failed to get flash size");
35
36
- if (mos || type > 1) {
37
+ if (mos) {
38
+ unallocated_encoding(s);
35
+ return;
39
+ return;
36
+ }
40
+ }
37
+
41
+
38
+ if (rom_size > size) {
42
+ switch (type) {
39
+ rom_size = size;
43
+ case 0:
44
+ sz = MO_32;
45
+ break;
46
+ case 1:
47
+ sz = MO_64;
48
+ break;
49
+ case 3:
50
+ sz = MO_16;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
52
+ break;
53
+ }
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
57
return;
40
}
58
}
41
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
42
storage = g_new0(uint8_t, rom_size);
60
return;
61
}
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
43
--
83
--
44
2.7.4
84
2.17.0
45
85
46
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/12] hw/arm/virt: Declare fwcfg as dma cache coherent in ACPI
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
1
From: Alexander Graf <agraf@suse.de>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Fw-cfg recently learned how to directly access guest memory and does so in
3
All the hard work is already done by vfp_expand_imm, we just need to
4
cache coherent fashion. Tell the guest about that fact when it's using ACPI.
4
make sure we pick up the correct size.
5
5
6
Signed-off-by: Alexander Graf <agraf@suse.de>
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 1486644810-33181-4-git-send-email-agraf@suse.de
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
15
---
13
hw/arm/virt-acpi-build.c | 1 +
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
14
1 file changed, 1 insertion(+)
17
1 file changed, 17 insertions(+), 3 deletions(-)
15
18
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
21
--- a/target/arm/translate-a64.c
19
+++ b/hw/arm/virt-acpi-build.c
22
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
21
aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
24
{
22
/* device present, functioning, decoding, not shown in UI */
25
int rd = extract32(insn, 0, 5);
23
aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
26
int imm8 = extract32(insn, 13, 8);
24
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
27
- int is_double = extract32(insn, 22, 2);
25
28
+ int type = extract32(insn, 22, 2);
26
Aml *crs = aml_resource_template();
29
uint64_t imm;
27
aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
30
TCGv_i64 tcg_res;
31
+ TCGMemOp sz;
32
33
- if (is_double > 1) {
34
+ switch (type) {
35
+ case 0:
36
+ sz = MO_32;
37
+ break;
38
+ case 1:
39
+ sz = MO_64;
40
+ break;
41
+ case 3:
42
+ sz = MO_16;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
44
+ break;
45
+ }
46
+ /* fallthru */
47
+ default:
48
unallocated_encoding(s);
49
return;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
52
return;
53
}
54
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
56
+ imm = vfp_expand_imm(sz, imm8);
57
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
28
--
60
--
29
2.7.4
61
2.17.0
30
62
31
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/12] hw/arm/virt: Declare virtio-mmio as dma cache coherent in ACPI
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
1
From: Alexander Graf <agraf@suse.de>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Virtio-mmio devices can directly access guest memory and do so in cache
3
We are meant to explicitly pass fpst, not cpu_env.
4
coherent fashion. Tell the guest about that fact when it's using ACPI.
5
4
6
Signed-off-by: Alexander Graf <agraf@suse.de>
5
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1486644810-33181-3-git-send-email-agraf@suse.de
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
hw/arm/virt-acpi-build.c | 1 +
13
target/arm/translate-a64.c | 3 ++-
14
1 file changed, 1 insertion(+)
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
15
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/virt-acpi-build.c
18
--- a/target/arm/translate-a64.c
19
+++ b/hw/arm/virt-acpi-build.c
19
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_virtio(Aml *scope,
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
21
Aml *dev = aml_device("VR%02u", i);
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
22
aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
22
break;
23
aml_append(dev, aml_name_decl("_UID", aml_int(i)));
23
case 0x3: /* FSQRT */
24
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
25
25
+ fpst = get_fpstatus_ptr(true);
26
Aml *crs = aml_resource_template();
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
27
aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
27
break;
28
case 0x8: /* FRINTN */
29
case 0x9: /* FRINTP */
28
--
30
--
29
2.7.4
31
2.17.0
30
32
31
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/12] target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
1
From: Wei Huang <wei@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
In order to support Linux perf, which uses PMXEVTYPER register,
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
4
this patch adds read/write access support for PMXEVTYPER. The access
5
is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally
6
this patch adds support for PMXEVTYPER_EL0.
7
4
8
Signed-off-by: Wei Huang <wei@redhat.com>
5
The block length is predefined to 512 bits
9
Message-id: 1486504171-26807-3-git-send-email-wei@redhat.com
6
7
and "4.10.2 SD Status":
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
20
---
13
target/arm/cpu.h | 1 -
21
hw/sd/sd.c | 2 +-
14
target/arm/helper.c | 30 +++++++++++++++++++++++++-----
22
1 file changed, 1 insertion(+), 1 deletion(-)
15
2 files changed, 25 insertions(+), 6 deletions(-)
16
23
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
18
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
26
--- a/hw/sd/sd.c
20
+++ b/target/arm/cpu.h
27
+++ b/hw/sd/sd.c
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
22
uint64_t c9_pmcr; /* performance monitor control register */
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
23
uint64_t c9_pmcnten; /* perf monitor counter enables */
30
}
24
uint32_t c9_pmovsr; /* perf monitor overflow status */
31
memset(&sd->data[17], 0, 47);
25
- uint32_t c9_pmxevtyper; /* perf monitor event type */
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
26
uint32_t c9_pmuserenr; /* perf monitor user enable */
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
27
uint64_t c9_pmselr; /* perf monitor counter selection register */
28
uint32_t c9_pminten; /* perf monitor interrupt enables */
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper.c
32
+++ b/target/arm/helper.c
33
@@ -XXX,XX +XXX,XX @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
34
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
35
uint64_t value)
36
{
37
- env->cp15.c9_pmxevtyper = value & 0xff;
38
+ /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
39
+ * PMSELR value is equal to or greater than the number of implemented
40
+ * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
41
+ */
42
+ if (env->cp15.c9_pmselr == 0x1f) {
43
+ pmccfiltr_write(env, ri, value);
44
+ }
45
+}
46
+
47
+static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
48
+{
49
+ /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
50
+ * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
51
+ */
52
+ if (env->cp15.c9_pmselr == 0x1f) {
53
+ return env->cp15.pmccfiltr_el0;
54
+ } else {
55
+ return 0;
56
+ }
57
}
34
}
58
35
59
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
60
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
61
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
62
.resetvalue = 0, },
63
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
64
- .access = PL0_RW,
65
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
66
- .accessfn = pmreg_access, .writefn = pmxevtyper_write,
67
- .raw_writefn = raw_write },
68
+ .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
69
+ .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
70
+ { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
71
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
72
+ .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
73
+ .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
74
/* Unimplemented, RAZ/WI. */
75
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
76
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
77
--
37
--
78
2.7.4
38
2.17.0
79
39
80
40
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
1
Usually the logging of the CPU state produced by -d cpu is sufficient
2
to diagnose problems, but sometimes you want to see the state of
3
the floating point registers as well. We don't want to enable that
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
10
---
11
include/qemu/log.h | 1 +
12
accel/tcg/cpu-exec.c | 9 ++++++---
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
19
+++ b/include/qemu/log.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
21
#define CPU_LOG_PAGE (1 << 14)
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
23
#define CPU_LOG_TB_OP_IND (1 << 16)
24
+#define CPU_LOG_TB_FPU (1 << 17)
25
26
/* Lock output for a series of related logs. Since this is not needed
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/cpu-exec.c
31
+++ b/accel/tcg/cpu-exec.c
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
34
&& qemu_log_in_addr_range(itb->pc)) {
35
qemu_log_lock();
36
+ int flags = 0;
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
38
+ flags |= CPU_DUMP_FPU;
39
+ }
40
#if defined(TARGET_I386)
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
42
-#else
43
- log_cpu_state(cpu, 0);
44
+ flags |= CPU_DUMP_CCOP;
45
#endif
46
+ log_cpu_state(cpu, flags);
47
qemu_log_unlock();
48
}
49
#endif /* DEBUG_DISAS */
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
63
--
64
2.17.0
65
66
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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