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A random mix of items here, nothing very major. v2 is just
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v2: drop pvpanic-pci patches.
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squashing in the fix for the clang unused-function error.
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2
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thanks
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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-- PMM
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:
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are available in the Git repository at:
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Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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are available in the git repository at:
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207-1
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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for you to fetch changes up to aecfbbc97a2e52bbee34a53c32f961a182046a95:
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stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:55:15 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm:
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target-arm queue:
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* new "unimplemented" device for stubbing out devices in a
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* Implement IMPDEF pauth algorithm
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system model so accesses can be logged
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* Support ARMv8.4-SEL2
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* stellaris: document the SoC memory map
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* arm: create instruction syndromes for AArch32 data aborts
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* arm: Correctly handle watchpoints for BE32 CPUs
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* Fix Thumb-1 BE32 execution and disassembly
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* docs: Build and install all the docs in a single manual
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* arm: Add cfgend parameter for ARM CPU selection
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* sd: sdhci: check data length during dma_memory_read
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* aspeed: add a watchdog controller
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* integratorcp: adding vmstate for save/restore
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----------------------------------------------------------------
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----------------------------------------------------------------
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Cédric Le Goater (2):
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Gan Qixin (1):
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wdt: Add Aspeed watchdog device model
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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aspeed: add a watchdog controller
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Julian Brown (4):
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Peter Maydell (1):
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hw/arm/integratorcp: Support specifying features via -cpu
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docs: Build and install all the docs in a single manual
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target/arm: Add cfgend parameter for ARM CPU selection.
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Fix Thumb-1 BE32 execution and disassembly.
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arm: Correctly handle watchpoints for BE32 CPUs
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Pavel Dovgalyuk (1):
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Philippe Mathieu-Daudé (1):
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integratorcp: adding vmstate for save/restore
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Peter Maydell (5):
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Richard Henderson (7):
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target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
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target/arm: Implement an IMPDEF pauth algorithm
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target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
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target/arm: Add cpu properties to control pauth
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stellaris: Document memory map and which SoC devices are unimplemented
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target/arm: Use object_property_add_bool for "sve" property
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hw/misc: New "unimplemented" sysbus device
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target/arm: Introduce PREDDESC field definitions
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stellaris: Use the 'unimplemented' device for parts we don't implement
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Prasad J Pandit (1):
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Rémi Denis-Courmont (19):
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sd: sdhci: check data length during dma_memory_read
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target/arm: remove redundant tests
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target/arm: add arm_is_el2_enabled() helper
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm: factor MDCR_EL2 common handling
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm: add 64-bit S-EL2 to EL exception table
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target/arm: add MMU stage 1 for Secure EL2
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm: handle VMID change in secure state
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm: translate NS bit in page-walks
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target/arm: generalize 2-stage page-walk condition
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target/arm: secure stage 2 translation regime
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm: revector to run-time pick target EL
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target/arm: Implement SCR_EL2.EEL2
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target/arm: enable Secure EL2 in max CPU
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target/arm: refactor vae1_tlbmask()
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hw/misc/Makefile.objs | 2 +
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docs/conf.py | 46 ++++-
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hw/watchdog/Makefile.objs | 1 +
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docs/devel/conf.py | 15 --
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include/disas/bfd.h | 7 ++
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docs/index.html.in | 17 --
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include/hw/arm/aspeed_soc.h | 2 +
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docs/interop/conf.py | 28 ---
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include/hw/misc/unimp.h | 39 +++++++
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docs/meson.build | 64 +++---
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include/hw/watchdog/wdt_aspeed.h | 32 ++++++
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docs/specs/conf.py | 16 --
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include/qom/cpu.h | 3 +
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docs/system/arm/cpu-features.rst | 21 ++
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target/arm/arm_ldst.h | 10 +-
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docs/system/conf.py | 28 ---
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target/arm/cpu.h | 7 ++
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docs/tools/conf.py | 37 ----
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target/arm/internals.h | 5 +
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docs/user/conf.py | 15 --
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target/arm/translate.h | 14 +++
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include/qemu/xxhash.h | 98 +++++++++
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disas.c | 1 +
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target/arm/cpu-param.h | 2 +-
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exec.c | 1 +
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target/arm/cpu.h | 107 ++++++++--
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hw/arm/aspeed_soc.c | 13 +++
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target/arm/internals.h | 45 +++++
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hw/arm/integratorcp.c | 78 +++++++++++++-
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target/arm/cpu.c | 23 ++-
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hw/arm/stellaris.c | 48 +++++++++
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target/arm/cpu64.c | 65 ++++--
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hw/misc/unimp.c | 107 +++++++++++++++++++
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target/arm/helper-a64.c | 8 +-
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hw/sd/sdhci.c | 2 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++
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target/arm/m_helper.c | 2 +-
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qom/cpu.c | 6 ++
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target/arm/monitor.c | 1 +
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target/arm/cpu.c | 39 +++++++
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target/arm/op_helper.c | 4 +-
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target/arm/op_helper.c | 22 ++++
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target/arm/pauth_helper.c | 27 ++-
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target/arm/translate-a64.c | 14 ---
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target/arm/sve_helper.c | 33 ++--
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target/arm/translate.c | 193 ++++++++++++++++++++++++---------
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target/arm/tlb_helper.c | 3 +
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24 files changed, 801 insertions(+), 70 deletions(-)
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target/arm/translate-a64.c | 4 +
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create mode 100644 include/hw/misc/unimp.h
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target/arm/translate-sve.c | 31 ++-
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create mode 100644 include/hw/watchdog/wdt_aspeed.h
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target/arm/translate.c | 36 +++-
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create mode 100644 hw/misc/unimp.c
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tests/qtest/arm-cpu-features.c | 13 ++
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create mode 100644 hw/watchdog/wdt_aspeed.c
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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