1 | A random mix of items here, nothing very major. | 1 | The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9: |
---|---|---|---|
2 | 2 | ||
3 | thanks | 3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000) |
4 | -- PMM | ||
5 | 4 | ||
5 | are available in the Git repository at: | ||
6 | 6 | ||
7 | The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b: | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216 |
8 | 8 | ||
9 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000) | 9 | for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8: |
10 | 10 | ||
11 | are available in the git repository at: | 11 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000) |
12 | |||
13 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207 | ||
14 | |||
15 | for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd: | ||
16 | |||
17 | stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000) | ||
18 | 12 | ||
19 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
20 | target-arm: | 14 | target-arm queue: |
21 | * new "unimplemented" device for stubbing out devices in a | 15 | * Some mostly M-profile-related code cleanups |
22 | system model so accesses can be logged | 16 | * avocado: Retire the boot_linux.py AArch64 TCG tests |
23 | * stellaris: document the SoC memory map | 17 | * hw/arm/smmuv3: Add GBPA register |
24 | * arm: create instruction syndromes for AArch32 data aborts | 18 | * arm/virt: don't try to spell out the accelerator |
25 | * arm: Correctly handle watchpoints for BE32 CPUs | 19 | * hw/arm: Attach PSPI module to NPCM7XX SoC |
26 | * Fix Thumb-1 BE32 execution and disassembly | 20 | * Some cleanup/refactoring patches aiming towards |
27 | * arm: Add cfgend parameter for ARM CPU selection | 21 | allowing building Arm targets without CONFIG_TCG |
28 | * sd: sdhci: check data length during dma_memory_read | ||
29 | * aspeed: add a watchdog controller | ||
30 | * integratorcp: adding vmstate for save/restore | ||
31 | 22 | ||
32 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
33 | Cédric Le Goater (2): | 24 | Alex Bennée (1): |
34 | wdt: Add Aspeed watchdog device model | 25 | tests/avocado: retire the Aarch64 TCG tests from boot_linux.py |
35 | aspeed: add a watchdog controller | ||
36 | 26 | ||
37 | Julian Brown (4): | 27 | Claudio Fontana (3): |
38 | hw/arm/integratorcp: Support specifying features via -cpu | 28 | target/arm: rename handle_semihosting to tcg_handle_semihosting |
39 | target/arm: Add cfgend parameter for ARM CPU selection. | 29 | target/arm: wrap psci call with tcg_enabled |
40 | Fix Thumb-1 BE32 execution and disassembly. | 30 | target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() |
41 | arm: Correctly handle watchpoints for BE32 CPUs | ||
42 | 31 | ||
43 | Pavel Dovgalyuk (1): | 32 | Cornelia Huck (1): |
44 | integratorcp: adding vmstate for save/restore | 33 | arm/virt: don't try to spell out the accelerator |
45 | 34 | ||
46 | Peter Maydell (5): | 35 | Fabiano Rosas (7): |
47 | target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode | 36 | target/arm: Move PC alignment check |
48 | target/arm: A32, T32: Create Instruction Syndromes for Data Aborts | 37 | target/arm: Move cpregs code out of cpu.h |
49 | stellaris: Document memory map and which SoC devices are unimplemented | 38 | tests/avocado: Skip tests that require a missing accelerator |
50 | hw/misc: New "unimplemented" sysbus device | 39 | tests/avocado: Tag TCG tests with accel:tcg |
51 | stellaris: Use the 'unimplemented' device for parts we don't implement | 40 | target/arm: Use "max" as default cpu for the virt machine with KVM |
41 | tests/qtest: arm-cpu-features: Match tests to required accelerators | ||
42 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG | ||
52 | 43 | ||
53 | Prasad J Pandit (1): | 44 | Hao Wu (3): |
54 | sd: sdhci: check data length during dma_memory_read | 45 | MAINTAINERS: Add myself to maintainers and remove Havard |
46 | hw/ssi: Add Nuvoton PSPI Module | ||
47 | hw/arm: Attach PSPI module to NPCM7XX SoC | ||
55 | 48 | ||
56 | hw/misc/Makefile.objs | 2 + | 49 | Jean-Philippe Brucker (2): |
57 | hw/watchdog/Makefile.objs | 1 + | 50 | hw/arm/smmu-common: Support 64-bit addresses |
58 | include/disas/bfd.h | 7 ++ | 51 | hw/arm/smmu-common: Fix TTB1 handling |
59 | include/hw/arm/aspeed_soc.h | 2 + | ||
60 | include/hw/misc/unimp.h | 39 +++++++ | ||
61 | include/hw/watchdog/wdt_aspeed.h | 32 ++++++ | ||
62 | include/qom/cpu.h | 3 + | ||
63 | target/arm/arm_ldst.h | 10 +- | ||
64 | target/arm/cpu.h | 7 ++ | ||
65 | target/arm/internals.h | 5 + | ||
66 | target/arm/translate.h | 14 +++ | ||
67 | disas.c | 1 + | ||
68 | exec.c | 1 + | ||
69 | hw/arm/aspeed_soc.c | 13 +++ | ||
70 | hw/arm/integratorcp.c | 78 +++++++++++++- | ||
71 | hw/arm/stellaris.c | 48 +++++++++ | ||
72 | hw/misc/unimp.c | 107 +++++++++++++++++++ | ||
73 | hw/sd/sdhci.c | 2 +- | ||
74 | hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++ | ||
75 | qom/cpu.c | 6 ++ | ||
76 | target/arm/cpu.c | 39 +++++++ | ||
77 | target/arm/op_helper.c | 22 ++++ | ||
78 | target/arm/translate-a64.c | 14 --- | ||
79 | target/arm/translate.c | 193 ++++++++++++++++++++++++--------- | ||
80 | 24 files changed, 801 insertions(+), 70 deletions(-) | ||
81 | create mode 100644 include/hw/misc/unimp.h | ||
82 | create mode 100644 include/hw/watchdog/wdt_aspeed.h | ||
83 | create mode 100644 hw/misc/unimp.c | ||
84 | create mode 100644 hw/watchdog/wdt_aspeed.c | ||
85 | 52 | ||
53 | Mostafa Saleh (1): | ||
54 | hw/arm/smmuv3: Add GBPA register | ||
55 | |||
56 | Philippe Mathieu-Daudé (12): | ||
57 | hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro | ||
58 | target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation | ||
59 | target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope | ||
60 | target/arm: Constify ID_PFR1 on user emulation | ||
61 | target/arm: Convert CPUARMState::eabi to boolean | ||
62 | target/arm: Avoid resetting CPUARMState::eabi field | ||
63 | target/arm: Restrict CPUARMState::gicv3state to sysemu | ||
64 | target/arm: Restrict CPUARMState::arm_boot_info to sysemu | ||
65 | target/arm: Restrict CPUARMState::nvic to sysemu | ||
66 | target/arm: Store CPUARMState::nvic as NVICState* | ||
67 | target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' | ||
68 | hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency | ||
69 | |||
70 | MAINTAINERS | 8 +- | ||
71 | docs/system/arm/nuvoton.rst | 2 +- | ||
72 | hw/arm/smmuv3-internal.h | 7 + | ||
73 | include/hw/arm/npcm7xx.h | 2 + | ||
74 | include/hw/arm/smmu-common.h | 2 - | ||
75 | include/hw/arm/smmuv3.h | 1 + | ||
76 | include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++- | ||
77 | include/hw/ssi/npcm_pspi.h | 53 ++++++++ | ||
78 | linux-user/user-internals.h | 2 +- | ||
79 | target/arm/cpregs.h | 98 ++++++++++++++ | ||
80 | target/arm/cpu.h | 228 ++------------------------------- | ||
81 | target/arm/internals.h | 14 -- | ||
82 | hw/arm/npcm7xx.c | 25 +++- | ||
83 | hw/arm/smmu-common.c | 4 +- | ||
84 | hw/arm/smmuv3.c | 43 ++++++- | ||
85 | hw/arm/virt.c | 10 +- | ||
86 | hw/intc/armv7m_nvic.c | 38 ++---- | ||
87 | hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++ | ||
88 | linux-user/arm/cpu_loop.c | 4 +- | ||
89 | target/arm/cpu.c | 5 +- | ||
90 | target/arm/cpu_tcg.c | 3 + | ||
91 | target/arm/helper.c | 31 +++-- | ||
92 | target/arm/m_helper.c | 86 +++++++------ | ||
93 | target/arm/machine.c | 18 +-- | ||
94 | tests/qtest/arm-cpu-features.c | 28 ++-- | ||
95 | hw/arm/Kconfig | 1 + | ||
96 | hw/ssi/meson.build | 2 +- | ||
97 | hw/ssi/trace-events | 5 + | ||
98 | tests/avocado/avocado_qemu/__init__.py | 4 + | ||
99 | tests/avocado/boot_linux.py | 48 ++----- | ||
100 | tests/avocado/boot_linux_console.py | 1 + | ||
101 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++- | ||
102 | tests/avocado/reverse_debugging.py | 8 ++ | ||
103 | tests/qtest/meson.build | 4 +- | ||
104 | 34 files changed, 798 insertions(+), 399 deletions(-) | ||
105 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
106 | create mode 100644 hw/ssi/npcm_pspi.c | ||
107 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, | ||
4 | similarly to automatic conversion from commit 8063396bf3 | ||
5 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-2-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/intc/armv7m_nvic.h | 5 +---- | ||
13 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/intc/armv7m_nvic.h | ||
18 | +++ b/include/hw/intc/armv7m_nvic.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "qom/object.h" | ||
21 | |||
22 | #define TYPE_NVIC "armv7m_nvic" | ||
23 | - | ||
24 | -typedef struct NVICState NVICState; | ||
25 | -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, | ||
26 | - TYPE_NVIC) | ||
27 | +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) | ||
28 | |||
29 | /* Highest permitted number of exceptions (architectural limit) */ | ||
30 | #define NVIC_MAX_VECTORS 512 | ||
31 | -- | ||
32 | 2.34.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
1 | Add support for generating the ISS (Instruction Specific Syndrome) | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | for Data Abort exceptions taken from AArch32. These syndromes are | ||
3 | used by hypervisors for example to trap and emulate memory accesses. | ||
4 | 2 | ||
5 | This is the equivalent for AArch32 guests of the work done for AArch64 | 3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
6 | guests in commit aaa1f954d4cab243. | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230206223502.25122-3-philmd@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | target/arm/m_helper.c | 11 ++++++++--- | ||
10 | 1 file changed, 8 insertions(+), 3 deletions(-) | ||
7 | 11 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
9 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
10 | --- | ||
11 | target/arm/translate.h | 14 ++++ | ||
12 | target/arm/translate-a64.c | 14 ---- | ||
13 | target/arm/translate.c | 184 +++++++++++++++++++++++++++++++++------------ | ||
14 | 3 files changed, 149 insertions(+), 63 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate.h | 14 | --- a/target/arm/m_helper.c |
19 | +++ b/target/arm/translate.h | 15 | +++ b/target/arm/m_helper.c |
20 | @@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s) | 16 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
21 | ? 3 : MAX(1, s->current_el); | 17 | return 0; |
22 | } | 18 | } |
23 | 19 | ||
24 | +static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) | 20 | -#else |
21 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
25 | +{ | 22 | +{ |
26 | + /* We don't need to save all of the syndrome so we mask and shift | 23 | + return ARMMMUIdx_MUser; |
27 | + * out unneeded bits to help the sleb128 encoder do a better job. | ||
28 | + */ | ||
29 | + syn &= ARM_INSN_START_WORD2_MASK; | ||
30 | + syn >>= ARM_INSN_START_WORD2_SHIFT; | ||
31 | + | ||
32 | + /* We check and clear insn_start_idx to catch multiple updates. */ | ||
33 | + assert(s->insn_start_idx != 0); | ||
34 | + tcg_set_insn_param(s->insn_start_idx, 2, syn); | ||
35 | + s->insn_start_idx = 0; | ||
36 | +} | 24 | +} |
37 | + | 25 | + |
38 | /* target-specific extra values for is_jmp */ | 26 | +#else /* !CONFIG_USER_ONLY */ |
39 | /* These instructions trap after executing, so the A32/T32 decoder must | 27 | |
40 | * defer them until after the conditional execution state has been updated. | 28 | /* |
41 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 29 | * What kind of stack write are we doing? This affects how exceptions |
42 | index XXXXXXX..XXXXXXX 100644 | 30 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
43 | --- a/target/arm/translate-a64.c | 31 | return tt_resp; |
44 | +++ b/target/arm/translate-a64.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | ||
46 | } | ||
47 | } | 32 | } |
48 | 33 | ||
49 | -static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) | 34 | -#endif /* !CONFIG_USER_ONLY */ |
50 | -{ | ||
51 | - /* We don't need to save all of the syndrome so we mask and shift | ||
52 | - * out uneeded bits to help the sleb128 encoder do a better job. | ||
53 | - */ | ||
54 | - syn &= ARM_INSN_START_WORD2_MASK; | ||
55 | - syn >>= ARM_INSN_START_WORD2_SHIFT; | ||
56 | - | 35 | - |
57 | - /* We check and clear insn_start_idx to catch multiple updates. */ | 36 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
58 | - assert(s->insn_start_idx != 0); | 37 | bool secstate, bool priv, bool negpri) |
59 | - tcg_set_insn_param(s->insn_start_idx, 2, syn); | ||
60 | - s->insn_start_idx = 0; | ||
61 | -} | ||
62 | - | ||
63 | static void unallocated_encoding(DisasContext *s) | ||
64 | { | 38 | { |
65 | /* Unallocated and reserved encodings are uncategorized */ | 39 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
66 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 40 | |
67 | index XXXXXXX..XXXXXXX 100644 | 41 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
68 | --- a/target/arm/translate.c | ||
69 | +++ b/target/arm/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
71 | a64_translate_init(); | ||
72 | } | 42 | } |
73 | |||
74 | +/* Flags for the disas_set_da_iss info argument: | ||
75 | + * lower bits hold the Rt register number, higher bits are flags. | ||
76 | + */ | ||
77 | +typedef enum ISSInfo { | ||
78 | + ISSNone = 0, | ||
79 | + ISSRegMask = 0x1f, | ||
80 | + ISSInvalid = (1 << 5), | ||
81 | + ISSIsAcqRel = (1 << 6), | ||
82 | + ISSIsWrite = (1 << 7), | ||
83 | + ISSIs16Bit = (1 << 8), | ||
84 | +} ISSInfo; | ||
85 | + | 43 | + |
86 | +/* Save the syndrome information for a Data Abort */ | 44 | +#endif /* !CONFIG_USER_ONLY */ |
87 | +static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo) | ||
88 | +{ | ||
89 | + uint32_t syn; | ||
90 | + int sas = memop & MO_SIZE; | ||
91 | + bool sse = memop & MO_SIGN; | ||
92 | + bool is_acqrel = issinfo & ISSIsAcqRel; | ||
93 | + bool is_write = issinfo & ISSIsWrite; | ||
94 | + bool is_16bit = issinfo & ISSIs16Bit; | ||
95 | + int srt = issinfo & ISSRegMask; | ||
96 | + | ||
97 | + if (issinfo & ISSInvalid) { | ||
98 | + /* Some callsites want to conditionally provide ISS info, | ||
99 | + * eg "only if this was not a writeback" | ||
100 | + */ | ||
101 | + return; | ||
102 | + } | ||
103 | + | ||
104 | + if (srt == 15) { | ||
105 | + /* For AArch32, insns where the src/dest is R15 never generate | ||
106 | + * ISS information. Catching that here saves checking at all | ||
107 | + * the call sites. | ||
108 | + */ | ||
109 | + return; | ||
110 | + } | ||
111 | + | ||
112 | + syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel, | ||
113 | + 0, 0, 0, is_write, 0, is_16bit); | ||
114 | + disas_set_insn_syndrome(s, syn); | ||
115 | +} | ||
116 | + | ||
117 | static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s) | ||
118 | { | ||
119 | /* Return the mmu_idx to use for A32/T32 "unprivileged load/store" | ||
120 | @@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ | ||
121 | TCGv_i32 a32, int index) \ | ||
122 | { \ | ||
123 | gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ | ||
124 | +} \ | ||
125 | +static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ | ||
126 | + TCGv_i32 val, \ | ||
127 | + TCGv_i32 a32, int index, \ | ||
128 | + ISSInfo issinfo) \ | ||
129 | +{ \ | ||
130 | + gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ | ||
131 | + disas_set_da_iss(s, OPC, issinfo); \ | ||
132 | } | ||
133 | |||
134 | #define DO_GEN_ST(SUFF, OPC) \ | ||
135 | @@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ | ||
136 | TCGv_i32 a32, int index) \ | ||
137 | { \ | ||
138 | gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ | ||
139 | +} \ | ||
140 | +static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ | ||
141 | + TCGv_i32 val, \ | ||
142 | + TCGv_i32 a32, int index, \ | ||
143 | + ISSInfo issinfo) \ | ||
144 | +{ \ | ||
145 | + gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ | ||
146 | + disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ | ||
147 | } | ||
148 | |||
149 | static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) | ||
150 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
151 | tmp = tcg_temp_new_i32(); | ||
152 | switch (op1) { | ||
153 | case 0: /* lda */ | ||
154 | - gen_aa32_ld32u(s, tmp, addr, | ||
155 | - get_mem_index(s)); | ||
156 | + gen_aa32_ld32u_iss(s, tmp, addr, | ||
157 | + get_mem_index(s), | ||
158 | + rd | ISSIsAcqRel); | ||
159 | break; | ||
160 | case 2: /* ldab */ | ||
161 | - gen_aa32_ld8u(s, tmp, addr, | ||
162 | - get_mem_index(s)); | ||
163 | + gen_aa32_ld8u_iss(s, tmp, addr, | ||
164 | + get_mem_index(s), | ||
165 | + rd | ISSIsAcqRel); | ||
166 | break; | ||
167 | case 3: /* ldah */ | ||
168 | - gen_aa32_ld16u(s, tmp, addr, | ||
169 | - get_mem_index(s)); | ||
170 | + gen_aa32_ld16u_iss(s, tmp, addr, | ||
171 | + get_mem_index(s), | ||
172 | + rd | ISSIsAcqRel); | ||
173 | break; | ||
174 | default: | ||
175 | abort(); | ||
176 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
177 | tmp = load_reg(s, rm); | ||
178 | switch (op1) { | ||
179 | case 0: /* stl */ | ||
180 | - gen_aa32_st32(s, tmp, addr, | ||
181 | - get_mem_index(s)); | ||
182 | + gen_aa32_st32_iss(s, tmp, addr, | ||
183 | + get_mem_index(s), | ||
184 | + rm | ISSIsAcqRel); | ||
185 | break; | ||
186 | case 2: /* stlb */ | ||
187 | - gen_aa32_st8(s, tmp, addr, | ||
188 | - get_mem_index(s)); | ||
189 | + gen_aa32_st8_iss(s, tmp, addr, | ||
190 | + get_mem_index(s), | ||
191 | + rm | ISSIsAcqRel); | ||
192 | break; | ||
193 | case 3: /* stlh */ | ||
194 | - gen_aa32_st16(s, tmp, addr, | ||
195 | - get_mem_index(s)); | ||
196 | + gen_aa32_st16_iss(s, tmp, addr, | ||
197 | + get_mem_index(s), | ||
198 | + rm | ISSIsAcqRel); | ||
199 | break; | ||
200 | default: | ||
201 | abort(); | ||
202 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
203 | bool wbit = insn & (1 << 21); | ||
204 | bool pbit = insn & (1 << 24); | ||
205 | bool doubleword = false; | ||
206 | + ISSInfo issinfo; | ||
207 | + | ||
208 | /* Misc load/store */ | ||
209 | rn = (insn >> 16) & 0xf; | ||
210 | rd = (insn >> 12) & 0xf; | ||
211 | |||
212 | + /* ISS not valid if writeback */ | ||
213 | + issinfo = (pbit & !wbit) ? rd : ISSInvalid; | ||
214 | + | ||
215 | if (!load && (sh & 2)) { | ||
216 | /* doubleword */ | ||
217 | ARCH(5TE); | ||
218 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
219 | tmp = tcg_temp_new_i32(); | ||
220 | switch (sh) { | ||
221 | case 1: | ||
222 | - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
223 | + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), | ||
224 | + issinfo); | ||
225 | break; | ||
226 | case 2: | ||
227 | - gen_aa32_ld8s(s, tmp, addr, get_mem_index(s)); | ||
228 | + gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), | ||
229 | + issinfo); | ||
230 | break; | ||
231 | default: | ||
232 | case 3: | ||
233 | - gen_aa32_ld16s(s, tmp, addr, get_mem_index(s)); | ||
234 | + gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), | ||
235 | + issinfo); | ||
236 | break; | ||
237 | } | ||
238 | } else { | ||
239 | /* store */ | ||
240 | tmp = load_reg(s, rd); | ||
241 | - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
242 | + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo); | ||
243 | tcg_temp_free_i32(tmp); | ||
244 | } | ||
245 | /* Perform base writeback before the loaded value to | ||
246 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
247 | /* load */ | ||
248 | tmp = tcg_temp_new_i32(); | ||
249 | if (insn & (1 << 22)) { | ||
250 | - gen_aa32_ld8u(s, tmp, tmp2, i); | ||
251 | + gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); | ||
252 | } else { | ||
253 | - gen_aa32_ld32u(s, tmp, tmp2, i); | ||
254 | + gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); | ||
255 | } | ||
256 | } else { | ||
257 | /* store */ | ||
258 | tmp = load_reg(s, rd); | ||
259 | if (insn & (1 << 22)) { | ||
260 | - gen_aa32_st8(s, tmp, tmp2, i); | ||
261 | + gen_aa32_st8_iss(s, tmp, tmp2, i, rd); | ||
262 | } else { | ||
263 | - gen_aa32_st32(s, tmp, tmp2, i); | ||
264 | + gen_aa32_st32_iss(s, tmp, tmp2, i, rd); | ||
265 | } | ||
266 | tcg_temp_free_i32(tmp); | ||
267 | } | ||
268 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | ||
269 | tmp = tcg_temp_new_i32(); | ||
270 | switch (op) { | ||
271 | case 0: /* ldab */ | ||
272 | - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); | ||
273 | + gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), | ||
274 | + rs | ISSIsAcqRel); | ||
275 | break; | ||
276 | case 1: /* ldah */ | ||
277 | - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
278 | + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), | ||
279 | + rs | ISSIsAcqRel); | ||
280 | break; | ||
281 | case 2: /* lda */ | ||
282 | - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
283 | + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), | ||
284 | + rs | ISSIsAcqRel); | ||
285 | break; | ||
286 | default: | ||
287 | abort(); | ||
288 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | ||
289 | tmp = load_reg(s, rs); | ||
290 | switch (op) { | ||
291 | case 0: /* stlb */ | ||
292 | - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); | ||
293 | + gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), | ||
294 | + rs | ISSIsAcqRel); | ||
295 | break; | ||
296 | case 1: /* stlh */ | ||
297 | - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
298 | + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), | ||
299 | + rs | ISSIsAcqRel); | ||
300 | break; | ||
301 | case 2: /* stl */ | ||
302 | - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
303 | + gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), | ||
304 | + rs | ISSIsAcqRel); | ||
305 | break; | ||
306 | default: | ||
307 | abort(); | ||
308 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | ||
309 | int postinc = 0; | ||
310 | int writeback = 0; | ||
311 | int memidx; | ||
312 | + ISSInfo issinfo; | ||
313 | + | ||
314 | if ((insn & 0x01100000) == 0x01000000) { | ||
315 | if (disas_neon_ls_insn(s, insn)) { | ||
316 | goto illegal_op; | ||
317 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | ||
318 | } | ||
319 | } | ||
320 | } | ||
321 | + | ||
322 | + issinfo = writeback ? ISSInvalid : rs; | ||
323 | + | ||
324 | if (insn & (1 << 20)) { | ||
325 | /* Load. */ | ||
326 | tmp = tcg_temp_new_i32(); | ||
327 | switch (op) { | ||
328 | case 0: | ||
329 | - gen_aa32_ld8u(s, tmp, addr, memidx); | ||
330 | + gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); | ||
331 | break; | ||
332 | case 4: | ||
333 | - gen_aa32_ld8s(s, tmp, addr, memidx); | ||
334 | + gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); | ||
335 | break; | ||
336 | case 1: | ||
337 | - gen_aa32_ld16u(s, tmp, addr, memidx); | ||
338 | + gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); | ||
339 | break; | ||
340 | case 5: | ||
341 | - gen_aa32_ld16s(s, tmp, addr, memidx); | ||
342 | + gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); | ||
343 | break; | ||
344 | case 2: | ||
345 | - gen_aa32_ld32u(s, tmp, addr, memidx); | ||
346 | + gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); | ||
347 | break; | ||
348 | default: | ||
349 | tcg_temp_free_i32(tmp); | ||
350 | @@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw | ||
351 | tmp = load_reg(s, rs); | ||
352 | switch (op) { | ||
353 | case 0: | ||
354 | - gen_aa32_st8(s, tmp, addr, memidx); | ||
355 | + gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); | ||
356 | break; | ||
357 | case 1: | ||
358 | - gen_aa32_st16(s, tmp, addr, memidx); | ||
359 | + gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); | ||
360 | break; | ||
361 | case 2: | ||
362 | - gen_aa32_st32(s, tmp, addr, memidx); | ||
363 | + gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); | ||
364 | break; | ||
365 | default: | ||
366 | tcg_temp_free_i32(tmp); | ||
367 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
368 | addr = tcg_temp_new_i32(); | ||
369 | tcg_gen_movi_i32(addr, val); | ||
370 | tmp = tcg_temp_new_i32(); | ||
371 | - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
372 | + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), | ||
373 | + rd | ISSIs16Bit); | ||
374 | tcg_temp_free_i32(addr); | ||
375 | store_reg(s, rd, tmp); | ||
376 | break; | ||
377 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
378 | |||
379 | switch (op) { | ||
380 | case 0: /* str */ | ||
381 | - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
382 | + gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
383 | break; | ||
384 | case 1: /* strh */ | ||
385 | - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
386 | + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
387 | break; | ||
388 | case 2: /* strb */ | ||
389 | - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); | ||
390 | + gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
391 | break; | ||
392 | case 3: /* ldrsb */ | ||
393 | - gen_aa32_ld8s(s, tmp, addr, get_mem_index(s)); | ||
394 | + gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
395 | break; | ||
396 | case 4: /* ldr */ | ||
397 | - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
398 | + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
399 | break; | ||
400 | case 5: /* ldrh */ | ||
401 | - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
402 | + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
403 | break; | ||
404 | case 6: /* ldrb */ | ||
405 | - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); | ||
406 | + gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
407 | break; | ||
408 | case 7: /* ldrsh */ | ||
409 | - gen_aa32_ld16s(s, tmp, addr, get_mem_index(s)); | ||
410 | + gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
411 | break; | ||
412 | } | ||
413 | if (op >= 3) { /* load */ | ||
414 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
415 | if (insn & (1 << 11)) { | ||
416 | /* load */ | ||
417 | tmp = tcg_temp_new_i32(); | ||
418 | - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); | ||
419 | + gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
420 | store_reg(s, rd, tmp); | ||
421 | } else { | ||
422 | /* store */ | ||
423 | tmp = load_reg(s, rd); | ||
424 | - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); | ||
425 | + gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
426 | tcg_temp_free_i32(tmp); | ||
427 | } | ||
428 | tcg_temp_free_i32(addr); | ||
429 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
430 | if (insn & (1 << 11)) { | ||
431 | /* load */ | ||
432 | tmp = tcg_temp_new_i32(); | ||
433 | - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
434 | + gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
435 | store_reg(s, rd, tmp); | ||
436 | } else { | ||
437 | /* store */ | ||
438 | tmp = load_reg(s, rd); | ||
439 | - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
440 | + gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
441 | tcg_temp_free_i32(tmp); | ||
442 | } | ||
443 | tcg_temp_free_i32(addr); | ||
444 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) | ||
445 | if (insn & (1 << 11)) { | ||
446 | /* load */ | ||
447 | tmp = tcg_temp_new_i32(); | ||
448 | - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
449 | + gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
450 | store_reg(s, rd, tmp); | ||
451 | } else { | ||
452 | /* store */ | ||
453 | tmp = load_reg(s, rd); | ||
454 | - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
455 | + gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); | ||
456 | tcg_temp_free_i32(tmp); | ||
457 | } | ||
458 | tcg_temp_free_i32(addr); | ||
459 | @@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) | ||
460 | store_cpu_field(tmp, condexec_bits); | ||
461 | } | ||
462 | do { | ||
463 | + dc->insn_start_idx = tcg_op_buf_count(); | ||
464 | tcg_gen_insn_start(dc->pc, | ||
465 | (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), | ||
466 | 0); | ||
467 | -- | 45 | -- |
468 | 2.7.4 | 46 | 2.34.1 |
469 | 47 | ||
470 | 48 | diff view generated by jsdifflib |
1 | From: Julian Brown <julian@codesourcery.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | In BE32 mode, sub-word size watchpoints can fail to trigger because the | 3 | arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() |
4 | address of the access is adjusted in the opcode helpers before being | 4 | are only used for system emulation in m_helper.c. |
5 | compared with the watchpoint registers. This patch reverses the address | 5 | Move the definitions to avoid prototype forward declarations. |
6 | adjustment before performing the comparison with the help of a new CPUClass | ||
7 | hook. | ||
8 | 6 | ||
9 | This version of the patch augments and tidies up comments a little. | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
11 | Signed-off-by: Julian Brown <julian@codesourcery.com> | 9 | Message-id: 20230206223502.25122-4-philmd@linaro.org |
12 | Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 11 | --- |
16 | include/qom/cpu.h | 3 +++ | 12 | target/arm/internals.h | 14 -------- |
17 | target/arm/internals.h | 5 +++++ | 13 | target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- |
18 | exec.c | 1 + | 14 | 2 files changed, 37 insertions(+), 51 deletions(-) |
19 | qom/cpu.c | 6 ++++++ | ||
20 | target/arm/cpu.c | 3 +++ | ||
21 | target/arm/op_helper.c | 22 ++++++++++++++++++++++ | ||
22 | 6 files changed, 40 insertions(+) | ||
23 | 15 | ||
24 | diff --git a/include/qom/cpu.h b/include/qom/cpu.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/include/qom/cpu.h | ||
27 | +++ b/include/qom/cpu.h | ||
28 | @@ -XXX,XX +XXX,XX @@ struct TranslationBlock; | ||
29 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | ||
30 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. | ||
31 | * @disas_set_info: Setup architecture specific components of disassembly info | ||
32 | + * @adjust_watchpoint_address: Perform a target-specific adjustment to an | ||
33 | + * address before attempting to match it against watchpoints. | ||
34 | * | ||
35 | * Represents a CPU family or model. | ||
36 | */ | ||
37 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUClass { | ||
38 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); | ||
39 | |||
40 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | ||
41 | + vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); | ||
42 | } CPUClass; | ||
43 | |||
44 | #ifdef HOST_WORDS_BIGENDIAN | ||
45 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
46 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/target/arm/internals.h | 18 | --- a/target/arm/internals.h |
48 | +++ b/target/arm/internals.h | 19 | +++ b/target/arm/internals.h |
49 | @@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu); | 20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
50 | /* Callback function for checking if a watchpoint should trigger. */ | 21 | |
51 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); | 22 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
52 | 23 | ||
53 | +/* Adjust addresses (in BE32 mode) before testing against watchpoint | 24 | -/* |
54 | + * addresses. | 25 | - * Return the MMU index for a v7M CPU with all relevant information |
55 | + */ | 26 | - * manually specified. |
56 | +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); | 27 | - */ |
28 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
29 | - bool secstate, bool priv, bool negpri); | ||
30 | - | ||
31 | -/* | ||
32 | - * Return the MMU index for a v7M CPU in the specified security and | ||
33 | - * privilege state. | ||
34 | - */ | ||
35 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
36 | - bool secstate, bool priv); | ||
37 | - | ||
38 | /* Return the MMU index for a v7M CPU in the specified security state */ | ||
39 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | ||
40 | |||
41 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/m_helper.c | ||
44 | +++ b/target/arm/m_helper.c | ||
45 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
46 | |||
47 | #else /* !CONFIG_USER_ONLY */ | ||
48 | |||
49 | +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
50 | + bool secstate, bool priv, bool negpri) | ||
51 | +{ | ||
52 | + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | ||
57 | + | 53 | + |
58 | /* Callback function for when a watchpoint or breakpoint triggers. */ | 54 | + if (priv) { |
59 | void arm_debug_excp_handler(CPUState *cs); | 55 | + mmu_idx |= ARM_MMU_IDX_M_PRIV; |
60 | 56 | + } | |
61 | diff --git a/exec.c b/exec.c | 57 | + |
62 | index XXXXXXX..XXXXXXX 100644 | 58 | + if (negpri) { |
63 | --- a/exec.c | 59 | + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; |
64 | +++ b/exec.c | 60 | + } |
65 | @@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) | 61 | + |
66 | return; | 62 | + if (secstate) { |
67 | } | 63 | + mmu_idx |= ARM_MMU_IDX_M_S; |
68 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; | 64 | + } |
69 | + vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); | 65 | + |
70 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | 66 | + return mmu_idx; |
71 | if (cpu_watchpoint_address_matches(wp, vaddr, len) | ||
72 | && (wp->flags & flags)) { | ||
73 | diff --git a/qom/cpu.c b/qom/cpu.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/qom/cpu.c | ||
76 | +++ b/qom/cpu.c | ||
77 | @@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) | ||
78 | return cpu->cpu_index; | ||
79 | } | ||
80 | |||
81 | +static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len) | ||
82 | +{ | ||
83 | + return addr; | ||
84 | +} | 67 | +} |
85 | + | 68 | + |
86 | static void cpu_class_init(ObjectClass *klass, void *data) | 69 | +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
87 | { | 70 | + bool secstate, bool priv) |
88 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
89 | @@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data) | ||
90 | k->cpu_exec_enter = cpu_common_noop; | ||
91 | k->cpu_exec_exit = cpu_common_noop; | ||
92 | k->cpu_exec_interrupt = cpu_common_exec_interrupt; | ||
93 | + k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; | ||
94 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); | ||
95 | dc->realize = cpu_common_realizefn; | ||
96 | dc->unrealize = cpu_common_unrealizefn; | ||
97 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
98 | index XXXXXXX..XXXXXXX 100644 | ||
99 | --- a/target/arm/cpu.c | ||
100 | +++ b/target/arm/cpu.c | ||
101 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) | ||
102 | cc->gdb_stop_before_watchpoint = true; | ||
103 | cc->debug_excp_handler = arm_debug_excp_handler; | ||
104 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; | ||
105 | +#if !defined(CONFIG_USER_ONLY) | ||
106 | + cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; | ||
107 | +#endif | ||
108 | |||
109 | cc->disas_set_info = arm_disas_set_info; | ||
110 | } | ||
111 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/op_helper.c | ||
114 | +++ b/target/arm/op_helper.c | ||
115 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) | ||
116 | return check_watchpoints(cpu); | ||
117 | } | ||
118 | |||
119 | +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) | ||
120 | +{ | 71 | +{ |
121 | + ARMCPU *cpu = ARM_CPU(cs); | 72 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); |
122 | + CPUARMState *env = &cpu->env; | ||
123 | + | 73 | + |
124 | + /* In BE32 system mode, target memory is stored byteswapped (on a | 74 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); |
125 | + * little-endian host system), and by the time we reach here (via an | ||
126 | + * opcode helper) the addresses of subword accesses have been adjusted | ||
127 | + * to account for that, which means that watchpoints will not match. | ||
128 | + * Undo the adjustment here. | ||
129 | + */ | ||
130 | + if (arm_sctlr_b(env)) { | ||
131 | + if (len == 1) { | ||
132 | + addr ^= 3; | ||
133 | + } else if (len == 2) { | ||
134 | + addr ^= 2; | ||
135 | + } | ||
136 | + } | ||
137 | + | ||
138 | + return addr; | ||
139 | +} | 75 | +} |
140 | + | 76 | + |
141 | void arm_debug_excp_handler(CPUState *cs) | 77 | +/* Return the MMU index for a v7M CPU in the specified security state */ |
142 | { | 78 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
143 | /* Called by core code when a watchpoint or breakpoint fires; | 79 | +{ |
80 | + bool priv = arm_v7m_is_handler_mode(env) || | ||
81 | + !(env->v7m.control[secstate] & 1); | ||
82 | + | ||
83 | + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
84 | +} | ||
85 | + | ||
86 | /* | ||
87 | * What kind of stack write are we doing? This affects how exceptions | ||
88 | * generated during the stacking are treated. | ||
89 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
90 | return tt_resp; | ||
91 | } | ||
92 | |||
93 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
94 | - bool secstate, bool priv, bool negpri) | ||
95 | -{ | ||
96 | - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | ||
97 | - | ||
98 | - if (priv) { | ||
99 | - mmu_idx |= ARM_MMU_IDX_M_PRIV; | ||
100 | - } | ||
101 | - | ||
102 | - if (negpri) { | ||
103 | - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
104 | - } | ||
105 | - | ||
106 | - if (secstate) { | ||
107 | - mmu_idx |= ARM_MMU_IDX_M_S; | ||
108 | - } | ||
109 | - | ||
110 | - return mmu_idx; | ||
111 | -} | ||
112 | - | ||
113 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
114 | - bool secstate, bool priv) | ||
115 | -{ | ||
116 | - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | ||
117 | - | ||
118 | - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | ||
119 | -} | ||
120 | - | ||
121 | -/* Return the MMU index for a v7M CPU in the specified security state */ | ||
122 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
123 | -{ | ||
124 | - bool priv = arm_v7m_is_handler_mode(env) || | ||
125 | - !(env->v7m.control[secstate] & 1); | ||
126 | - | ||
127 | - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
128 | -} | ||
129 | - | ||
130 | #endif /* !CONFIG_USER_ONLY */ | ||
144 | -- | 131 | -- |
145 | 2.7.4 | 132 | 2.34.1 |
146 | 133 | ||
147 | 134 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This enables reboot of a guest from U-Boot and Linux. | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
5 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 5 | Message-id: 20230206223502.25122-5-philmd@linaro.org |
6 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
7 | Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 7 | --- |
10 | include/hw/arm/aspeed_soc.h | 2 ++ | 8 | target/arm/helper.c | 12 ++++++++++-- |
11 | hw/arm/aspeed_soc.c | 13 +++++++++++++ | 9 | 1 file changed, 10 insertions(+), 2 deletions(-) |
12 | 2 files changed, 15 insertions(+) | ||
13 | 10 | ||
14 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | 11 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/aspeed_soc.h | 13 | --- a/target/arm/helper.c |
17 | +++ b/include/hw/arm/aspeed_soc.h | 14 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) |
19 | #include "hw/timer/aspeed_timer.h" | 16 | } |
20 | #include "hw/i2c/aspeed_i2c.h" | ||
21 | #include "hw/ssi/aspeed_smc.h" | ||
22 | +#include "hw/watchdog/wdt_aspeed.h" | ||
23 | |||
24 | #define ASPEED_SPIS_NUM 2 | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { | ||
27 | AspeedSMCState fmc; | ||
28 | AspeedSMCState spi[ASPEED_SPIS_NUM]; | ||
29 | AspeedSDMCState sdmc; | ||
30 | + AspeedWDTState wdt; | ||
31 | } AspeedSoCState; | ||
32 | |||
33 | #define TYPE_ASPEED_SOC "aspeed-soc" | ||
34 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/hw/arm/aspeed_soc.c | ||
37 | +++ b/hw/arm/aspeed_soc.c | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #define ASPEED_SOC_SCU_BASE 0x1E6E2000 | ||
40 | #define ASPEED_SOC_SRAM_BASE 0x1E720000 | ||
41 | #define ASPEED_SOC_TIMER_BASE 0x1E782000 | ||
42 | +#define ASPEED_SOC_WDT_BASE 0x1E785000 | ||
43 | #define ASPEED_SOC_I2C_BASE 0x1E78A000 | ||
44 | |||
45 | static const int uart_irqs[] = { 9, 32, 33, 34, 10 }; | ||
46 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
47 | sc->info->silicon_rev); | ||
48 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), | ||
49 | "ram-size", &error_abort); | ||
50 | + | ||
51 | + object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT); | ||
52 | + object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL); | ||
53 | + qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); | ||
54 | } | 17 | } |
55 | 18 | ||
56 | static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 19 | +#ifndef CONFIG_USER_ONLY |
57 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) | 20 | /* |
58 | return; | 21 | * We don't know until after realize whether there's a GICv3 |
59 | } | 22 | * attached, and that is what registers the gicv3 sysregs. |
60 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE); | 23 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
61 | + | 24 | return pfr1; |
62 | + /* Watch dog */ | ||
63 | + object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); | ||
64 | + if (err) { | ||
65 | + error_propagate(errp, err); | ||
66 | + return; | ||
67 | + } | ||
68 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE); | ||
69 | } | 25 | } |
70 | 26 | ||
71 | static void aspeed_soc_class_init(ObjectClass *oc, void *data) | 27 | -#ifndef CONFIG_USER_ONLY |
28 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
29 | { | ||
30 | ARMCPU *cpu = env_archcpu(env); | ||
31 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
32 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | ||
33 | .access = PL1_R, .type = ARM_CP_NO_RAW, | ||
34 | .accessfn = access_aa32_tid3, | ||
35 | +#ifdef CONFIG_USER_ONLY | ||
36 | + .type = ARM_CP_CONST, | ||
37 | + .resetvalue = cpu->isar.id_pfr1, | ||
38 | +#else | ||
39 | + .type = ARM_CP_NO_RAW, | ||
40 | + .accessfn = access_aa32_tid3, | ||
41 | .readfn = id_pfr1_read, | ||
42 | - .writefn = arm_cp_write_ignore }, | ||
43 | + .writefn = arm_cp_write_ignore | ||
44 | +#endif | ||
45 | + }, | ||
46 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
48 | .access = PL1_R, .type = ARM_CP_CONST, | ||
72 | -- | 49 | -- |
73 | 2.7.4 | 50 | 2.34.1 |
74 | 51 | ||
75 | 52 | diff view generated by jsdifflib |
1 | In the ARM ldr/str decode path, rather than directly testing | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | "insn & (1 << 21)" and "insn & (1 << 24)", abstract these | ||
3 | bits out into wbit and pbit local flags. (We will want to | ||
4 | do more tests against them to determine whether we need to | ||
5 | provide syndrome information.) | ||
6 | 2 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230206223502.25122-6-philmd@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
9 | --- | 8 | --- |
10 | target/arm/translate.c | 9 ++++++--- | 9 | linux-user/user-internals.h | 2 +- |
11 | 1 file changed, 6 insertions(+), 3 deletions(-) | 10 | target/arm/cpu.h | 2 +- |
11 | linux-user/arm/cpu_loop.c | 4 ++-- | ||
12 | 3 files changed, 4 insertions(+), 4 deletions(-) | ||
12 | 13 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 16 | --- a/linux-user/user-internals.h |
16 | +++ b/target/arm/translate.c | 17 | +++ b/linux-user/user-internals.h |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 18 | @@ -XXX,XX +XXX,XX @@ void print_termios(void *arg); |
18 | } else { | 19 | #ifdef TARGET_ARM |
19 | int address_offset; | 20 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) |
20 | bool load = insn & (1 << 20); | 21 | { |
21 | + bool wbit = insn & (1 << 21); | 22 | - return cpu_env->eabi == 1; |
22 | + bool pbit = insn & (1 << 24); | 23 | + return cpu_env->eabi; |
23 | bool doubleword = false; | 24 | } |
24 | /* Misc load/store */ | 25 | #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) |
25 | rn = (insn >> 16) & 0xf; | 26 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } |
26 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/cpu.h | ||
30 | +++ b/target/arm/cpu.h | ||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
32 | |||
33 | #if defined(CONFIG_USER_ONLY) | ||
34 | /* For usermode syscall translation. */ | ||
35 | - int eabi; | ||
36 | + bool eabi; | ||
37 | #endif | ||
38 | |||
39 | struct CPUBreakpoint *cpu_breakpoint[16]; | ||
40 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/linux-user/arm/cpu_loop.c | ||
43 | +++ b/linux-user/arm/cpu_loop.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
45 | break; | ||
46 | case EXCP_SWI: | ||
47 | { | ||
48 | - env->eabi = 1; | ||
49 | + env->eabi = true; | ||
50 | /* system call */ | ||
51 | if (env->thumb) { | ||
52 | /* Thumb is always EABI style with syscall number in r7 */ | ||
53 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
54 | * > 0xfffff and are handled below as out-of-range. | ||
55 | */ | ||
56 | n ^= ARM_SYSCALL_BASE; | ||
57 | - env->eabi = 0; | ||
58 | + env->eabi = false; | ||
59 | } | ||
27 | } | 60 | } |
28 | 61 | ||
29 | addr = load_reg(s, rn); | ||
30 | - if (insn & (1 << 24)) | ||
31 | + if (pbit) { | ||
32 | gen_add_datah_offset(s, insn, 0, addr); | ||
33 | + } | ||
34 | address_offset = 0; | ||
35 | |||
36 | if (doubleword) { | ||
37 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
38 | ensure correct behavior with overlapping index registers. | ||
39 | ldrd with base writeback is undefined if the | ||
40 | destination and index registers overlap. */ | ||
41 | - if (!(insn & (1 << 24))) { | ||
42 | + if (!pbit) { | ||
43 | gen_add_datah_offset(s, insn, address_offset, addr); | ||
44 | store_reg(s, rn, addr); | ||
45 | - } else if (insn & (1 << 21)) { | ||
46 | + } else if (wbit) { | ||
47 | if (address_offset) | ||
48 | tcg_gen_addi_i32(addr, addr, address_offset); | ||
49 | store_reg(s, rn, addr); | ||
50 | -- | 62 | -- |
51 | 2.7.4 | 63 | 2.34.1 |
52 | 64 | ||
53 | 65 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Although the 'eabi' field is only used in user emulation where | ||
4 | CPU reset doesn't occur, it doesn't belong to the area to reset. | ||
5 | Move it after the 'end_reset_fields' for consistency. | ||
6 | |||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Message-id: 20230206223502.25122-7-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/cpu.h | 9 ++++----- | ||
13 | 1 file changed, 4 insertions(+), 5 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/cpu.h | ||
18 | +++ b/target/arm/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
20 | ARMVectorReg zarray[ARM_MAX_VQ * 16]; | ||
21 | #endif | ||
22 | |||
23 | -#if defined(CONFIG_USER_ONLY) | ||
24 | - /* For usermode syscall translation. */ | ||
25 | - bool eabi; | ||
26 | -#endif | ||
27 | - | ||
28 | struct CPUBreakpoint *cpu_breakpoint[16]; | ||
29 | struct CPUWatchpoint *cpu_watchpoint[16]; | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
32 | const struct arm_boot_info *boot_info; | ||
33 | /* Store GICv3CPUState to access from this struct */ | ||
34 | void *gicv3state; | ||
35 | +#if defined(CONFIG_USER_ONLY) | ||
36 | + /* For usermode syscall translation. */ | ||
37 | + bool eabi; | ||
38 | +#endif /* CONFIG_USER_ONLY */ | ||
39 | |||
40 | #ifdef TARGET_TAGGED_ADDRESSES | ||
41 | /* Linux syscall tagged address support */ | ||
42 | -- | ||
43 | 2.34.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Message-id: 20230206223502.25122-8-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 3 ++- | ||
9 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
16 | |||
17 | void *nvic; | ||
18 | const struct arm_boot_info *boot_info; | ||
19 | +#if !defined(CONFIG_USER_ONLY) | ||
20 | /* Store GICv3CPUState to access from this struct */ | ||
21 | void *gicv3state; | ||
22 | -#if defined(CONFIG_USER_ONLY) | ||
23 | +#else /* CONFIG_USER_ONLY */ | ||
24 | /* For usermode syscall translation. */ | ||
25 | bool eabi; | ||
26 | #endif /* CONFIG_USER_ONLY */ | ||
27 | -- | ||
28 | 2.34.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Message-id: 20230206223502.25122-9-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 2 +- | ||
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
16 | } sau; | ||
17 | |||
18 | void *nvic; | ||
19 | - const struct arm_boot_info *boot_info; | ||
20 | #if !defined(CONFIG_USER_ONLY) | ||
21 | + const struct arm_boot_info *boot_info; | ||
22 | /* Store GICv3CPUState to access from this struct */ | ||
23 | void *gicv3state; | ||
24 | #else /* CONFIG_USER_ONLY */ | ||
25 | -- | ||
26 | 2.34.1 | ||
27 | |||
28 | diff view generated by jsdifflib |
1 | From: Prasad J Pandit <pjp@fedoraproject.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | While doing multi block SDMA transfer in routine | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | 'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | index 'begin' and data length 's->data_count' could end up to be same. | 5 | Message-id: 20230206223502.25122-10-philmd@linaro.org |
6 | This could lead to an OOB access issue. Correct transfer data length | ||
7 | to avoid it. | ||
8 | |||
9 | Cc: qemu-stable@nongnu.org | ||
10 | Reported-by: Jiang Xin <jiangxin1@huawei.com> | ||
11 | Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Message-id: 20170130064736.9236-1-ppandit@redhat.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 7 | --- |
16 | hw/sd/sdhci.c | 2 +- | 8 | target/arm/cpu.h | 2 +- |
17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
18 | 10 | ||
19 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
20 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/sd/sdhci.c | 13 | --- a/target/arm/cpu.h |
22 | +++ b/hw/sd/sdhci.c | 14 | +++ b/target/arm/cpu.h |
23 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
24 | boundary_count -= block_size - begin; | 16 | uint32_t ctrl; |
25 | } | 17 | } sau; |
26 | dma_memory_read(&address_space_memory, s->sdmasysad, | 18 | |
27 | - &s->fifo_buffer[begin], s->data_count); | 19 | - void *nvic; |
28 | + &s->fifo_buffer[begin], s->data_count - begin); | 20 | #if !defined(CONFIG_USER_ONLY) |
29 | s->sdmasysad += s->data_count - begin; | 21 | + void *nvic; |
30 | if (s->data_count == block_size) { | 22 | const struct arm_boot_info *boot_info; |
31 | for (n = 0; n < block_size; n++) { | 23 | /* Store GICv3CPUState to access from this struct */ |
24 | void *gicv3state; | ||
32 | -- | 25 | -- |
33 | 2.7.4 | 26 | 2.34.1 |
34 | 27 | ||
35 | 28 | diff view generated by jsdifflib |
1 | From: Julian Brown <julian@codesourcery.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Add a new "cfgend" property which selects whether the CPU resets into | 3 | There is no point in using a void pointer to access the NVIC. |
4 | big-endian mode or not. This setting affects whether we reset with | 4 | Use the real type to avoid casting it while debugging. |
5 | SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set. | 5 | |
6 | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
7 | Signed-off-by: Julian Brown <julian@codesourcery.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com | 8 | Message-id: 20230206223502.25122-11-philmd@linaro.org |
9 | [PMM: use error_report_err() rather than error_report(); | ||
10 | move the integratorcp changes to their own patch; | ||
11 | drop an unnecessary extra #include; | ||
12 | rephrase commit message accordingly; | ||
13 | move setting of reset_sctlr above registration of cpregs | ||
14 | so it actually has an effect] | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 10 | --- |
18 | target/arm/cpu.h | 7 +++++++ | 11 | target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- |
19 | target/arm/cpu.c | 13 +++++++++++++ | 12 | hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- |
20 | 2 files changed, 20 insertions(+) | 13 | target/arm/cpu.c | 1 + |
14 | target/arm/m_helper.c | 2 +- | ||
15 | 4 files changed, 39 insertions(+), 48 deletions(-) | ||
21 | 16 | ||
22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
23 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/cpu.h |
25 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/cpu.h |
26 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags { |
27 | int gic_vpribits; /* number of virtual priority bits */ | 22 | |
28 | int gic_vprebits; /* number of virtual preemption bits */ | 23 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; |
29 | 24 | ||
30 | + /* Whether the cfgend input is high (i.e. this CPU should reset into | 25 | +typedef struct NVICState NVICState; |
31 | + * big-endian mode). This setting isn't used directly: instead it modifies | ||
32 | + * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the | ||
33 | + * architecture version. | ||
34 | + */ | ||
35 | + bool cfgend; | ||
36 | + | 26 | + |
37 | ARMELChangeHook *el_change_hook; | 27 | typedef struct CPUArchState { |
38 | void *el_change_hook_opaque; | 28 | /* Regs for current mode. */ |
39 | }; | 29 | uint32_t regs[16]; |
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
31 | } sau; | ||
32 | |||
33 | #if !defined(CONFIG_USER_ONLY) | ||
34 | - void *nvic; | ||
35 | + NVICState *nvic; | ||
36 | const struct arm_boot_info *boot_info; | ||
37 | /* Store GICv3CPUState to access from this struct */ | ||
38 | void *gicv3state; | ||
39 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
40 | |||
41 | /* Interface between CPU and Interrupt controller. */ | ||
42 | #ifndef CONFIG_USER_ONLY | ||
43 | -bool armv7m_nvic_can_take_pending_exception(void *opaque); | ||
44 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
45 | #else | ||
46 | -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
47 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
48 | { | ||
49 | return true; | ||
50 | } | ||
51 | #endif | ||
52 | /** | ||
53 | * armv7m_nvic_set_pending: mark the specified exception as pending | ||
54 | - * @opaque: the NVIC | ||
55 | + * @s: the NVIC | ||
56 | * @irq: the exception number to mark pending | ||
57 | * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | * version of a banked exception, true for the secure version of a banked | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
60 | * if @secure is true and @irq does not specify one of the fixed set | ||
61 | * of architecturally banked exceptions. | ||
62 | */ | ||
63 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
64 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
65 | /** | ||
66 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
67 | - * @opaque: the NVIC | ||
68 | + * @s: the NVIC | ||
69 | * @irq: the exception number to mark pending | ||
70 | * @secure: false for non-banked exceptions or for the nonsecure | ||
71 | * version of a banked exception, true for the secure version of a banked | ||
72 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
73 | * exceptions (exceptions generated in the course of trying to take | ||
74 | * a different exception). | ||
75 | */ | ||
76 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
77 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
78 | /** | ||
79 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
80 | - * @opaque: the NVIC | ||
81 | + * @s: the NVIC | ||
82 | * @irq: the exception number to mark pending | ||
83 | * @secure: false for non-banked exceptions or for the nonsecure | ||
84 | * version of a banked exception, true for the secure version of a banked | ||
85 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
86 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
87 | * generated in the course of lazy stacking of FP registers. | ||
88 | */ | ||
89 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
90 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
91 | /** | ||
92 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
93 | * exception, and whether it targets Secure state | ||
94 | - * @opaque: the NVIC | ||
95 | + * @s: the NVIC | ||
96 | * @pirq: set to pending exception number | ||
97 | * @ptargets_secure: set to whether pending exception targets Secure | ||
98 | * | ||
99 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
100 | * to true if the current highest priority pending exception should | ||
101 | * be taken to Secure state, false for NS. | ||
102 | */ | ||
103 | -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | ||
104 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
105 | bool *ptargets_secure); | ||
106 | /** | ||
107 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
108 | - * @opaque: the NVIC | ||
109 | + * @s: the NVIC | ||
110 | * | ||
111 | * Move the current highest priority pending exception from the pending | ||
112 | * state to the active state, and update v7m.exception to indicate that | ||
113 | * it is the exception currently being handled. | ||
114 | */ | ||
115 | -void armv7m_nvic_acknowledge_irq(void *opaque); | ||
116 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
117 | /** | ||
118 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
119 | - * @opaque: the NVIC | ||
120 | + * @s: the NVIC | ||
121 | * @irq: the exception number to complete | ||
122 | * @secure: true if this exception was secure | ||
123 | * | ||
124 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
125 | * 0 if there is still an irq active after this one was completed | ||
126 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
127 | */ | ||
128 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
129 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
130 | /** | ||
131 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
132 | - * @opaque: the NVIC | ||
133 | + * @s: the NVIC | ||
134 | * @irq: the exception number to mark pending | ||
135 | * @secure: false for non-banked exceptions or for the nonsecure | ||
136 | * version of a banked exception, true for the secure version of a banked | ||
137 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
138 | * interrupt the current execution priority. This controls whether the | ||
139 | * RDY bit for it in the FPCCR is set. | ||
140 | */ | ||
141 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | ||
142 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
143 | /** | ||
144 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
145 | - * @opaque: the NVIC | ||
146 | + * @s: the NVIC | ||
147 | * | ||
148 | * Returns: the raw execution priority as defined by the v8M architecture. | ||
149 | * This is the execution priority minus the effects of AIRCR.PRIS, | ||
150 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
151 | * (v8M ARM ARM I_PKLD.) | ||
152 | */ | ||
153 | -int armv7m_nvic_raw_execution_priority(void *opaque); | ||
154 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
155 | /** | ||
156 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
157 | * priority is negative for the specified security state. | ||
158 | - * @opaque: the NVIC | ||
159 | + * @s: the NVIC | ||
160 | * @secure: the security state to test | ||
161 | * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
162 | */ | ||
163 | #ifndef CONFIG_USER_ONLY | ||
164 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | ||
165 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
166 | #else | ||
167 | -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
168 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
169 | { | ||
170 | return false; | ||
171 | } | ||
172 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
173 | index XXXXXXX..XXXXXXX 100644 | ||
174 | --- a/hw/intc/armv7m_nvic.c | ||
175 | +++ b/hw/intc/armv7m_nvic.c | ||
176 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
177 | return MIN(running, s->exception_prio); | ||
178 | } | ||
179 | |||
180 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
181 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
182 | { | ||
183 | /* Return true if the requested execution priority is negative | ||
184 | * for the specified security state, ie that security state | ||
185 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
186 | * mean we don't allow FAULTMASK_NS to actually make the execution | ||
187 | * priority negative). Compare pseudocode IsReqExcPriNeg(). | ||
188 | */ | ||
189 | - NVICState *s = opaque; | ||
190 | - | ||
191 | if (s->cpu->env.v7m.faultmask[secure]) { | ||
192 | return true; | ||
193 | } | ||
194 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
195 | return false; | ||
196 | } | ||
197 | |||
198 | -bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
199 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
200 | { | ||
201 | - NVICState *s = opaque; | ||
202 | - | ||
203 | return nvic_exec_prio(s) > nvic_pending_prio(s); | ||
204 | } | ||
205 | |||
206 | -int armv7m_nvic_raw_execution_priority(void *opaque) | ||
207 | +int armv7m_nvic_raw_execution_priority(NVICState *s) | ||
208 | { | ||
209 | - NVICState *s = opaque; | ||
210 | - | ||
211 | return s->exception_prio; | ||
212 | } | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s) | ||
215 | * if @secure is true and @irq does not specify one of the fixed set | ||
216 | * of architecturally banked exceptions. | ||
217 | */ | ||
218 | -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | ||
219 | +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) | ||
220 | { | ||
221 | - NVICState *s = (NVICState *)opaque; | ||
222 | VecInfo *vec; | ||
223 | |||
224 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
225 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, | ||
226 | } | ||
227 | } | ||
228 | |||
229 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) | ||
230 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) | ||
231 | { | ||
232 | - do_armv7m_nvic_set_pending(opaque, irq, secure, false); | ||
233 | + do_armv7m_nvic_set_pending(s, irq, secure, false); | ||
234 | } | ||
235 | |||
236 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | ||
237 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) | ||
238 | { | ||
239 | - do_armv7m_nvic_set_pending(opaque, irq, secure, true); | ||
240 | + do_armv7m_nvic_set_pending(s, irq, secure, true); | ||
241 | } | ||
242 | |||
243 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
244 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
245 | { | ||
246 | /* | ||
247 | * Pend an exception during lazy FP stacking. This differs | ||
248 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
249 | * whether we should escalate depends on the saved context | ||
250 | * in the FPCCR register, not on the current state of the CPU/NVIC. | ||
251 | */ | ||
252 | - NVICState *s = (NVICState *)opaque; | ||
253 | bool banked = exc_is_banked(irq); | ||
254 | VecInfo *vec; | ||
255 | bool targets_secure; | ||
256 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
257 | } | ||
258 | |||
259 | /* Make pending IRQ active. */ | ||
260 | -void armv7m_nvic_acknowledge_irq(void *opaque) | ||
261 | +void armv7m_nvic_acknowledge_irq(NVICState *s) | ||
262 | { | ||
263 | - NVICState *s = (NVICState *)opaque; | ||
264 | CPUARMState *env = &s->cpu->env; | ||
265 | const int pending = s->vectpending; | ||
266 | const int running = nvic_exec_prio(s); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s) | ||
268 | exc_targets_secure(s, s->vectpending); | ||
269 | } | ||
270 | |||
271 | -void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
272 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, | ||
273 | int *pirq, bool *ptargets_secure) | ||
274 | { | ||
275 | - NVICState *s = (NVICState *)opaque; | ||
276 | const int pending = s->vectpending; | ||
277 | bool targets_secure; | ||
278 | |||
279 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
280 | *pirq = pending; | ||
281 | } | ||
282 | |||
283 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
284 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) | ||
285 | { | ||
286 | - NVICState *s = (NVICState *)opaque; | ||
287 | VecInfo *vec = NULL; | ||
288 | int ret = 0; | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
295 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) | ||
296 | { | ||
297 | /* | ||
298 | * Return whether an exception is "ready", i.e. it is enabled and is | ||
299 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
300 | * for non-banked exceptions secure is always false; for banked exceptions | ||
301 | * it indicates which of the exceptions is required. | ||
302 | */ | ||
303 | - NVICState *s = (NVICState *)opaque; | ||
304 | bool banked = exc_is_banked(irq); | ||
305 | VecInfo *vec; | ||
306 | int running = nvic_exec_prio(s); | ||
40 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 307 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
41 | index XXXXXXX..XXXXXXX 100644 | 308 | index XXXXXXX..XXXXXXX 100644 |
42 | --- a/target/arm/cpu.c | 309 | --- a/target/arm/cpu.c |
43 | +++ b/target/arm/cpu.c | 310 | +++ b/target/arm/cpu.c |
44 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el2_property = | 311 | @@ -XXX,XX +XXX,XX @@ |
45 | static Property arm_cpu_has_el3_property = | 312 | #if !defined(CONFIG_USER_ONLY) |
46 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | 313 | #include "hw/loader.h" |
47 | 314 | #include "hw/boards.h" | |
48 | +static Property arm_cpu_cfgend_property = | 315 | +#include "hw/intc/armv7m_nvic.h" |
49 | + DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | 316 | #endif |
50 | + | 317 | #include "sysemu/tcg.h" |
51 | /* use property name "pmu" to match other archs and virt tools */ | 318 | #include "sysemu/qtest.h" |
52 | static Property arm_cpu_has_pmu_property = | 319 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
53 | DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); | 320 | index XXXXXXX..XXXXXXX 100644 |
54 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj) | 321 | --- a/target/arm/m_helper.c |
55 | } | 322 | +++ b/target/arm/m_helper.c |
56 | } | 323 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, |
57 | 324 | * that we will need later in order to do lazy FP reg stacking. | |
58 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, | 325 | */ |
59 | + &error_abort); | 326 | bool is_secure = env->v7m.secure; |
60 | } | 327 | - void *nvic = env->nvic; |
61 | 328 | + NVICState *nvic = env->nvic; | |
62 | static void arm_cpu_finalizefn(Object *obj) | 329 | /* |
63 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 330 | * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits |
64 | cpu->reset_sctlr |= (1 << 13); | 331 | * are banked and we want to update the bit in the bank for the |
65 | } | ||
66 | |||
67 | + if (cpu->cfgend) { | ||
68 | + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | ||
69 | + cpu->reset_sctlr |= SCTLR_EE; | ||
70 | + } else { | ||
71 | + cpu->reset_sctlr |= SCTLR_B; | ||
72 | + } | ||
73 | + } | ||
74 | + | ||
75 | if (!cpu->has_el3) { | ||
76 | /* If the has_el3 CPU property is disabled then we need to disable the | ||
77 | * feature. | ||
78 | -- | 332 | -- |
79 | 2.7.4 | 333 | 2.34.1 |
80 | 334 | ||
81 | 335 | diff view generated by jsdifflib |
1 | From: Julian Brown <julian@codesourcery.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Thumb-1 code has some issues in BE32 mode (as currently implemented). In | 3 | While dozens of files include "cpu.h", only 3 files require |
4 | short, since bytes are swapped within words at load time for BE32 | 4 | these NVIC helper declarations. |
5 | executables, this also swaps pairs of adjacent Thumb-1 instructions. | 5 | |
6 | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
7 | This patch un-swaps those pairs of instructions again, both for execution, | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | and for disassembly. (The previous version of the patch always read four | 8 | Message-id: 20230206223502.25122-12-philmd@linaro.org |
9 | bytes in arm_read_memory_func and then extracted the proper two bytes, | ||
10 | in a probably misguided attempt to match the behaviour of actual hardware | ||
11 | as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for | ||
12 | instruction fetches". It's less complicated to just read the correct | ||
13 | two bytes though.) | ||
14 | |||
15 | Signed-off-by: Julian Brown <julian@codesourcery.com> | ||
16 | Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 10 | --- |
20 | include/disas/bfd.h | 7 +++++++ | 11 | include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ |
21 | target/arm/arm_ldst.h | 10 +++++++++- | 12 | target/arm/cpu.h | 123 ---------------------------------- |
22 | disas.c | 1 + | 13 | target/arm/cpu.c | 4 +- |
23 | target/arm/cpu.c | 23 +++++++++++++++++++++++ | 14 | target/arm/cpu_tcg.c | 3 + |
24 | 4 files changed, 40 insertions(+), 1 deletion(-) | 15 | target/arm/m_helper.c | 3 + |
25 | 16 | 5 files changed, 132 insertions(+), 124 deletions(-) | |
26 | diff --git a/include/disas/bfd.h b/include/disas/bfd.h | 17 | |
27 | index XXXXXXX..XXXXXXX 100644 | 18 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h |
28 | --- a/include/disas/bfd.h | 19 | index XXXXXXX..XXXXXXX 100644 |
29 | +++ b/include/disas/bfd.h | 20 | --- a/include/hw/intc/armv7m_nvic.h |
30 | @@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info { | 21 | +++ b/include/hw/intc/armv7m_nvic.h |
31 | The bottom 16 bits are for the internal use of the disassembler. */ | 22 | @@ -XXX,XX +XXX,XX @@ struct NVICState { |
32 | unsigned long flags; | 23 | qemu_irq sysresetreq; |
33 | #define INSN_HAS_RELOC 0x80000000 | 24 | }; |
34 | +#define INSN_ARM_BE32 0x00010000 | 25 | |
35 | PTR private_data; | 26 | +/* Interface between CPU and Interrupt controller. */ |
36 | 27 | +/** | |
37 | /* Function used to get bytes to disassemble. MEMADDR is the | 28 | + * armv7m_nvic_set_pending: mark the specified exception as pending |
38 | @@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info { | 29 | + * @s: the NVIC |
39 | (bfd_vma memaddr, bfd_byte *myaddr, int length, | 30 | + * @irq: the exception number to mark pending |
40 | struct disassemble_info *info); | 31 | + * @secure: false for non-banked exceptions or for the nonsecure |
41 | 32 | + * version of a banked exception, true for the secure version of a banked | |
42 | + /* A place to stash the real read_memory_func if read_memory_func wants to | 33 | + * exception. |
43 | + do some funky address arithmetic or similar (e.g. for ARM BE32 mode). */ | 34 | + * |
44 | + int (*read_memory_inner_func) | 35 | + * Marks the specified exception as pending. Note that we will assert() |
45 | + (bfd_vma memaddr, bfd_byte *myaddr, int length, | 36 | + * if @secure is true and @irq does not specify one of the fixed set |
46 | + struct disassemble_info *info); | 37 | + * of architecturally banked exceptions. |
38 | + */ | ||
39 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
40 | +/** | ||
41 | + * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
42 | + * @s: the NVIC | ||
43 | + * @irq: the exception number to mark pending | ||
44 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
45 | + * version of a banked exception, true for the secure version of a banked | ||
46 | + * exception. | ||
47 | + * | ||
48 | + * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
49 | + * exceptions (exceptions generated in the course of trying to take | ||
50 | + * a different exception). | ||
51 | + */ | ||
52 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
53 | +/** | ||
54 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
55 | + * @s: the NVIC | ||
56 | + * @irq: the exception number to mark pending | ||
57 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | + * version of a banked exception, true for the secure version of a banked | ||
59 | + * exception. | ||
60 | + * | ||
61 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
62 | + * generated in the course of lazy stacking of FP registers. | ||
63 | + */ | ||
64 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
65 | +/** | ||
66 | + * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
67 | + * exception, and whether it targets Secure state | ||
68 | + * @s: the NVIC | ||
69 | + * @pirq: set to pending exception number | ||
70 | + * @ptargets_secure: set to whether pending exception targets Secure | ||
71 | + * | ||
72 | + * This function writes the number of the highest priority pending | ||
73 | + * exception (the one which would be made active by | ||
74 | + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
75 | + * to true if the current highest priority pending exception should | ||
76 | + * be taken to Secure state, false for NS. | ||
77 | + */ | ||
78 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
79 | + bool *ptargets_secure); | ||
80 | +/** | ||
81 | + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
82 | + * @s: the NVIC | ||
83 | + * | ||
84 | + * Move the current highest priority pending exception from the pending | ||
85 | + * state to the active state, and update v7m.exception to indicate that | ||
86 | + * it is the exception currently being handled. | ||
87 | + */ | ||
88 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
89 | +/** | ||
90 | + * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
91 | + * @s: the NVIC | ||
92 | + * @irq: the exception number to complete | ||
93 | + * @secure: true if this exception was secure | ||
94 | + * | ||
95 | + * Returns: -1 if the irq was not active | ||
96 | + * 1 if completing this irq brought us back to base (no active irqs) | ||
97 | + * 0 if there is still an irq active after this one was completed | ||
98 | + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
99 | + */ | ||
100 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
101 | +/** | ||
102 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
103 | + * @s: the NVIC | ||
104 | + * @irq: the exception number to mark pending | ||
105 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
106 | + * version of a banked exception, true for the secure version of a banked | ||
107 | + * exception. | ||
108 | + * | ||
109 | + * Return whether an exception is "ready", i.e. whether the exception is | ||
110 | + * enabled and is configured at a priority which would allow it to | ||
111 | + * interrupt the current execution priority. This controls whether the | ||
112 | + * RDY bit for it in the FPCCR is set. | ||
113 | + */ | ||
114 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
115 | +/** | ||
116 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
117 | + * @s: the NVIC | ||
118 | + * | ||
119 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
120 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
121 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
122 | + * (v8M ARM ARM I_PKLD.) | ||
123 | + */ | ||
124 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
125 | +/** | ||
126 | + * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
127 | + * priority is negative for the specified security state. | ||
128 | + * @s: the NVIC | ||
129 | + * @secure: the security state to test | ||
130 | + * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
131 | + */ | ||
132 | +#ifndef CONFIG_USER_ONLY | ||
133 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
134 | +#else | ||
135 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
136 | +{ | ||
137 | + return false; | ||
138 | +} | ||
139 | +#endif | ||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
142 | +#else | ||
143 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
144 | +{ | ||
145 | + return true; | ||
146 | +} | ||
147 | +#endif | ||
47 | + | 148 | + |
48 | /* Function which should be called if we get an error that we can't | 149 | #endif |
49 | recover from. STATUS is the errno value from read_memory_func and | 150 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
50 | MEMADDR is the address that we were trying to read. INFO is a | 151 | index XXXXXXX..XXXXXXX 100644 |
51 | diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h | 152 | --- a/target/arm/cpu.h |
52 | index XXXXXXX..XXXXXXX 100644 | 153 | +++ b/target/arm/cpu.h |
53 | --- a/target/arm/arm_ldst.h | 154 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); |
54 | +++ b/target/arm/arm_ldst.h | 155 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
55 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, | 156 | uint32_t cur_el, bool secure); |
56 | static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, | 157 | |
57 | bool sctlr_b) | 158 | -/* Interface between CPU and Interrupt controller. */ |
58 | { | 159 | -#ifndef CONFIG_USER_ONLY |
59 | - uint16_t insn = cpu_lduw_code(env, addr); | 160 | -bool armv7m_nvic_can_take_pending_exception(NVICState *s); |
60 | + uint16_t insn; | 161 | -#else |
61 | +#ifndef CONFIG_USER_ONLY | 162 | -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) |
62 | + /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped | 163 | -{ |
63 | + within each word. Undo that now. */ | 164 | - return true; |
64 | + if (sctlr_b) { | 165 | -} |
65 | + addr ^= 2; | 166 | -#endif |
66 | + } | 167 | -/** |
67 | +#endif | 168 | - * armv7m_nvic_set_pending: mark the specified exception as pending |
68 | + insn = cpu_lduw_code(env, addr); | 169 | - * @s: the NVIC |
69 | if (bswap_code(sctlr_b)) { | 170 | - * @irq: the exception number to mark pending |
70 | return bswap16(insn); | 171 | - * @secure: false for non-banked exceptions or for the nonsecure |
71 | } | 172 | - * version of a banked exception, true for the secure version of a banked |
72 | diff --git a/disas.c b/disas.c | 173 | - * exception. |
73 | index XXXXXXX..XXXXXXX 100644 | 174 | - * |
74 | --- a/disas.c | 175 | - * Marks the specified exception as pending. Note that we will assert() |
75 | +++ b/disas.c | 176 | - * if @secure is true and @irq does not specify one of the fixed set |
76 | @@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code, | 177 | - * of architecturally banked exceptions. |
77 | 178 | - */ | |
78 | s.cpu = cpu; | 179 | -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); |
79 | s.info.read_memory_func = target_read_memory; | 180 | -/** |
80 | + s.info.read_memory_inner_func = NULL; | 181 | - * armv7m_nvic_set_pending_derived: mark this derived exception as pending |
81 | s.info.buffer_vma = code; | 182 | - * @s: the NVIC |
82 | s.info.buffer_length = size; | 183 | - * @irq: the exception number to mark pending |
83 | s.info.print_address_func = generic_print_address; | 184 | - * @secure: false for non-banked exceptions or for the nonsecure |
185 | - * version of a banked exception, true for the secure version of a banked | ||
186 | - * exception. | ||
187 | - * | ||
188 | - * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
189 | - * exceptions (exceptions generated in the course of trying to take | ||
190 | - * a different exception). | ||
191 | - */ | ||
192 | -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
193 | -/** | ||
194 | - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
195 | - * @s: the NVIC | ||
196 | - * @irq: the exception number to mark pending | ||
197 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
198 | - * version of a banked exception, true for the secure version of a banked | ||
199 | - * exception. | ||
200 | - * | ||
201 | - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
202 | - * generated in the course of lazy stacking of FP registers. | ||
203 | - */ | ||
204 | -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
205 | -/** | ||
206 | - * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
207 | - * exception, and whether it targets Secure state | ||
208 | - * @s: the NVIC | ||
209 | - * @pirq: set to pending exception number | ||
210 | - * @ptargets_secure: set to whether pending exception targets Secure | ||
211 | - * | ||
212 | - * This function writes the number of the highest priority pending | ||
213 | - * exception (the one which would be made active by | ||
214 | - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
215 | - * to true if the current highest priority pending exception should | ||
216 | - * be taken to Secure state, false for NS. | ||
217 | - */ | ||
218 | -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
219 | - bool *ptargets_secure); | ||
220 | -/** | ||
221 | - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
222 | - * @s: the NVIC | ||
223 | - * | ||
224 | - * Move the current highest priority pending exception from the pending | ||
225 | - * state to the active state, and update v7m.exception to indicate that | ||
226 | - * it is the exception currently being handled. | ||
227 | - */ | ||
228 | -void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
229 | -/** | ||
230 | - * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
231 | - * @s: the NVIC | ||
232 | - * @irq: the exception number to complete | ||
233 | - * @secure: true if this exception was secure | ||
234 | - * | ||
235 | - * Returns: -1 if the irq was not active | ||
236 | - * 1 if completing this irq brought us back to base (no active irqs) | ||
237 | - * 0 if there is still an irq active after this one was completed | ||
238 | - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
239 | - */ | ||
240 | -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
241 | -/** | ||
242 | - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
243 | - * @s: the NVIC | ||
244 | - * @irq: the exception number to mark pending | ||
245 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
246 | - * version of a banked exception, true for the secure version of a banked | ||
247 | - * exception. | ||
248 | - * | ||
249 | - * Return whether an exception is "ready", i.e. whether the exception is | ||
250 | - * enabled and is configured at a priority which would allow it to | ||
251 | - * interrupt the current execution priority. This controls whether the | ||
252 | - * RDY bit for it in the FPCCR is set. | ||
253 | - */ | ||
254 | -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
255 | -/** | ||
256 | - * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
257 | - * @s: the NVIC | ||
258 | - * | ||
259 | - * Returns: the raw execution priority as defined by the v8M architecture. | ||
260 | - * This is the execution priority minus the effects of AIRCR.PRIS, | ||
261 | - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
262 | - * (v8M ARM ARM I_PKLD.) | ||
263 | - */ | ||
264 | -int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
265 | -/** | ||
266 | - * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
267 | - * priority is negative for the specified security state. | ||
268 | - * @s: the NVIC | ||
269 | - * @secure: the security state to test | ||
270 | - * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
271 | - */ | ||
272 | -#ifndef CONFIG_USER_ONLY | ||
273 | -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
274 | -#else | ||
275 | -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
276 | -{ | ||
277 | - return false; | ||
278 | -} | ||
279 | -#endif | ||
280 | - | ||
281 | /* Interface for defining coprocessor registers. | ||
282 | * Registers are defined in tables of arm_cp_reginfo structs | ||
283 | * which are passed to define_arm_cp_regs(). | ||
84 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 284 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
85 | index XXXXXXX..XXXXXXX 100644 | 285 | index XXXXXXX..XXXXXXX 100644 |
86 | --- a/target/arm/cpu.c | 286 | --- a/target/arm/cpu.c |
87 | +++ b/target/arm/cpu.c | 287 | +++ b/target/arm/cpu.c |
88 | @@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info) | 288 | @@ -XXX,XX +XXX,XX @@ |
89 | return print_insn_arm(pc | 1, info); | 289 | #if !defined(CONFIG_USER_ONLY) |
90 | } | 290 | #include "hw/loader.h" |
91 | 291 | #include "hw/boards.h" | |
92 | +static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b, | 292 | +#ifdef CONFIG_TCG |
93 | + int length, struct disassemble_info *info) | 293 | #include "hw/intc/armv7m_nvic.h" |
94 | +{ | 294 | -#endif |
95 | + assert(info->read_memory_inner_func); | 295 | +#endif /* CONFIG_TCG */ |
96 | + assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4); | 296 | +#endif /* !CONFIG_USER_ONLY */ |
97 | + | 297 | #include "sysemu/tcg.h" |
98 | + if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) { | 298 | #include "sysemu/qtest.h" |
99 | + assert(info->endian == BFD_ENDIAN_LITTLE); | 299 | #include "sysemu/hw_accel.h" |
100 | + return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2, | 300 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
101 | + info); | 301 | index XXXXXXX..XXXXXXX 100644 |
102 | + } else { | 302 | --- a/target/arm/cpu_tcg.c |
103 | + return info->read_memory_inner_func(memaddr, b, length, info); | 303 | +++ b/target/arm/cpu_tcg.c |
104 | + } | 304 | @@ -XXX,XX +XXX,XX @@ |
105 | +} | 305 | #include "hw/boards.h" |
106 | + | ||
107 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
108 | { | ||
109 | ARMCPU *ac = ARM_CPU(cpu); | ||
110 | @@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
111 | info->endian = BFD_ENDIAN_BIG; | ||
112 | #endif | 306 | #endif |
113 | } | 307 | #include "cpregs.h" |
114 | + if (info->read_memory_inner_func == NULL) { | 308 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) |
115 | + info->read_memory_inner_func = info->read_memory_func; | 309 | +#include "hw/intc/armv7m_nvic.h" |
116 | + info->read_memory_func = arm_read_memory_func; | 310 | +#endif |
117 | + } | 311 | |
118 | + info->flags &= ~INSN_ARM_BE32; | 312 | |
119 | + if (arm_sctlr_b(env)) { | 313 | /* Share AArch32 -cpu max features with AArch64. */ |
120 | + info->flags |= INSN_ARM_BE32; | 314 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
121 | + } | 315 | index XXXXXXX..XXXXXXX 100644 |
122 | } | 316 | --- a/target/arm/m_helper.c |
123 | 317 | +++ b/target/arm/m_helper.c | |
124 | static void arm_cpu_initfn(Object *obj) | 318 | @@ -XXX,XX +XXX,XX @@ |
319 | #include "exec/cpu_ldst.h" | ||
320 | #include "semihosting/common-semi.h" | ||
321 | #endif | ||
322 | +#if !defined(CONFIG_USER_ONLY) | ||
323 | +#include "hw/intc/armv7m_nvic.h" | ||
324 | +#endif | ||
325 | |||
326 | static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
327 | uint32_t reg, uint32_t val) | ||
125 | -- | 328 | -- |
126 | 2.7.4 | 329 | 2.34.1 |
127 | 330 | ||
128 | 331 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Alex Bennée <alex.bennee@linaro.org> | |
2 | |||
3 | The two TCG tests for GICv2 and GICv3 are very heavy weight distros | ||
4 | that take a long time to boot up, especially for an --enable-debug | ||
5 | build. The total code coverage they give is: | ||
6 | |||
7 | Overall coverage rate: | ||
8 | lines......: 11.2% (59584 of 530123 lines) | ||
9 | functions..: 15.0% (7436 of 49443 functions) | ||
10 | branches...: 6.3% (19273 of 303933 branches) | ||
11 | |||
12 | We already get pretty close to that with the machine_aarch64_virt | ||
13 | tests which only does one full boot (~120s vs ~600s) of alpine. We | ||
14 | expand the kernel+initrd boot (~8s) to test both GICs and also add an | ||
15 | RNG device and a block device to generate a few IRQs and exercise the | ||
16 | storage layer. With that we get to a coverage of: | ||
17 | |||
18 | Overall coverage rate: | ||
19 | lines......: 11.0% (58121 of 530123 lines) | ||
20 | functions..: 14.9% (7343 of 49443 functions) | ||
21 | branches...: 6.0% (18269 of 303933 branches) | ||
22 | |||
23 | which I feel is close enough given the massive time saving. If we want | ||
24 | to target any more sub-systems we can use lighter weight more directed | ||
25 | tests. | ||
26 | |||
27 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
29 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org | ||
31 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | --- | ||
34 | tests/avocado/boot_linux.py | 48 ++++---------------- | ||
35 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- | ||
36 | 2 files changed, 65 insertions(+), 46 deletions(-) | ||
37 | |||
38 | diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/tests/avocado/boot_linux.py | ||
41 | +++ b/tests/avocado/boot_linux.py | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self): | ||
43 | self.launch_and_wait(set_up_ssh_connection=False) | ||
44 | |||
45 | |||
46 | -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very | ||
47 | -# heavyweight. There are lighter weight distros which we use in the | ||
48 | -# machine_aarch64_virt.py tests. | ||
49 | +# For Aarch64 we only boot KVM tests in CI as booting the current | ||
50 | +# Fedora OS in TCG tests is very heavyweight. There are lighter weight | ||
51 | +# distros which we use in the machine_aarch64_virt.py tests. | ||
52 | class BootLinuxAarch64(LinuxTest): | ||
53 | """ | ||
54 | :avocado: tags=arch:aarch64 | ||
55 | :avocado: tags=machine:virt | ||
56 | - :avocado: tags=machine:gic-version=2 | ||
57 | """ | ||
58 | timeout = 720 | ||
59 | |||
60 | - def add_common_args(self): | ||
61 | - self.vm.add_args('-bios', | ||
62 | - os.path.join(BUILD_DIR, 'pc-bios', | ||
63 | - 'edk2-aarch64-code.fd')) | ||
64 | - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
65 | - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
66 | - | ||
67 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
68 | - def test_fedora_cloud_tcg_gicv2(self): | ||
69 | - """ | ||
70 | - :avocado: tags=accel:tcg | ||
71 | - :avocado: tags=cpu:max | ||
72 | - :avocado: tags=device:gicv2 | ||
73 | - """ | ||
74 | - self.require_accelerator("tcg") | ||
75 | - self.vm.add_args("-accel", "tcg") | ||
76 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
77 | - self.vm.add_args("-machine", "virt,gic-version=2") | ||
78 | - self.add_common_args() | ||
79 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
80 | - | ||
81 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
82 | - def test_fedora_cloud_tcg_gicv3(self): | ||
83 | - """ | ||
84 | - :avocado: tags=accel:tcg | ||
85 | - :avocado: tags=cpu:max | ||
86 | - :avocado: tags=device:gicv3 | ||
87 | - """ | ||
88 | - self.require_accelerator("tcg") | ||
89 | - self.vm.add_args("-accel", "tcg") | ||
90 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
91 | - self.vm.add_args("-machine", "virt,gic-version=3") | ||
92 | - self.add_common_args() | ||
93 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
94 | - | ||
95 | def test_virt_kvm(self): | ||
96 | """ | ||
97 | :avocado: tags=accel:kvm | ||
98 | @@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self): | ||
99 | self.require_accelerator("kvm") | ||
100 | self.vm.add_args("-accel", "kvm") | ||
101 | self.vm.add_args("-machine", "virt,gic-version=host") | ||
102 | - self.add_common_args() | ||
103 | + self.vm.add_args('-bios', | ||
104 | + os.path.join(BUILD_DIR, 'pc-bios', | ||
105 | + 'edk2-aarch64-code.fd')) | ||
106 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
107 | + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
108 | self.launch_and_wait(set_up_ssh_connection=False) | ||
109 | |||
110 | |||
111 | diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/tests/avocado/machine_aarch64_virt.py | ||
114 | +++ b/tests/avocado/machine_aarch64_virt.py | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | |||
117 | import time | ||
118 | import os | ||
119 | +import logging | ||
120 | |||
121 | from avocado_qemu import QemuSystemTest | ||
122 | from avocado_qemu import wait_for_console_pattern | ||
123 | from avocado_qemu import exec_command | ||
124 | from avocado_qemu import BUILD_DIR | ||
125 | +from avocado.utils import process | ||
126 | +from avocado.utils.path import find_command | ||
127 | |||
128 | class Aarch64VirtMachine(QemuSystemTest): | ||
129 | KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' | ||
130 | @@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self): | ||
131 | self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') | ||
132 | |||
133 | |||
134 | - def test_aarch64_virt(self): | ||
135 | + def common_aarch64_virt(self, machine): | ||
136 | """ | ||
137 | - :avocado: tags=arch:aarch64 | ||
138 | - :avocado: tags=machine:virt | ||
139 | - :avocado: tags=accel:tcg | ||
140 | - :avocado: tags=cpu:max | ||
141 | + Common code to launch basic virt machine with kernel+initrd | ||
142 | + and a scratch disk. | ||
143 | """ | ||
144 | + logger = logging.getLogger('aarch64_virt') | ||
145 | + | ||
146 | kernel_url = ('https://fileserver.linaro.org/s/' | ||
147 | 'z6B2ARM7DQT3HWN/download') | ||
148 | - | ||
149 | kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' | ||
150 | kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self): | ||
153 | 'console=ttyAMA0') | ||
154 | self.require_accelerator("tcg") | ||
155 | self.vm.add_args('-cpu', 'max,pauth-impdef=on', | ||
156 | + '-machine', machine, | ||
157 | '-accel', 'tcg', | ||
158 | '-kernel', kernel_path, | ||
159 | '-append', kernel_command_line) | ||
160 | + | ||
161 | + # A RNG offers an easy way to generate a few IRQs | ||
162 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
163 | + self.vm.add_args('-object', | ||
164 | + 'rng-random,id=rng0,filename=/dev/urandom') | ||
165 | + | ||
166 | + # Also add a scratch block device | ||
167 | + logger.info('creating scratch qcow2 image') | ||
168 | + image_path = os.path.join(self.workdir, 'scratch.qcow2') | ||
169 | + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') | ||
170 | + if not os.path.exists(qemu_img): | ||
171 | + qemu_img = find_command('qemu-img', False) | ||
172 | + if qemu_img is False: | ||
173 | + self.cancel('Could not find "qemu-img", which is required to ' | ||
174 | + 'create the temporary qcow2 image') | ||
175 | + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) | ||
176 | + process.run(cmd) | ||
177 | + | ||
178 | + # Add the device | ||
179 | + self.vm.add_args('-blockdev', | ||
180 | + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") | ||
181 | + self.vm.add_args('-device', | ||
182 | + 'virtio-blk-device,drive=scratch') | ||
183 | + | ||
184 | self.vm.launch() | ||
185 | self.wait_for_console_pattern('Welcome to Buildroot') | ||
186 | time.sleep(0.1) | ||
187 | exec_command(self, 'root') | ||
188 | time.sleep(0.1) | ||
189 | + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') | ||
190 | + time.sleep(0.1) | ||
191 | + exec_command(self, 'md5sum /dev/vda') | ||
192 | + time.sleep(0.1) | ||
193 | + exec_command(self, 'cat /proc/interrupts') | ||
194 | + time.sleep(0.1) | ||
195 | exec_command(self, 'cat /proc/self/maps') | ||
196 | time.sleep(0.1) | ||
197 | + | ||
198 | + def test_aarch64_virt_gicv3(self): | ||
199 | + """ | ||
200 | + :avocado: tags=arch:aarch64 | ||
201 | + :avocado: tags=machine:virt | ||
202 | + :avocado: tags=accel:tcg | ||
203 | + :avocado: tags=cpu:max | ||
204 | + """ | ||
205 | + self.common_aarch64_virt("virt,gic_version=3") | ||
206 | + | ||
207 | + def test_aarch64_virt_gicv2(self): | ||
208 | + """ | ||
209 | + :avocado: tags=arch:aarch64 | ||
210 | + :avocado: tags=machine:virt | ||
211 | + :avocado: tags=accel:tcg | ||
212 | + :avocado: tags=cpu:max | ||
213 | + """ | ||
214 | + self.common_aarch64_virt("virt,gic-version=2") | ||
215 | -- | ||
216 | 2.34.1 | ||
217 | |||
218 | diff view generated by jsdifflib |
1 | From: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> | 1 | From: Mostafa Saleh <smostafa@google.com> |
---|---|---|---|
2 | 2 | ||
3 | VMState added by this patch preserves correct | 3 | GBPA register can be used to globally abort all |
4 | loading of the integratorcp device state. | 4 | transactions. |
5 | 5 | ||
6 | Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> | 6 | It is described in the SMMU manual in "6.3.14 SMMU_GBPA". |
7 | Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP | 7 | ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to |
8 | [PMM: removed unnecessary minimum_version_id_old lines] | 8 | be zero(Do not abort incoming transactions). |
9 | |||
10 | Other fields have default values of Use Incoming. | ||
11 | |||
12 | If UPDATE is not set, the write is ignored. This is the only permitted | ||
13 | behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) | ||
14 | |||
15 | As this patch adds a new state to the SMMU (GBPA), it is added | ||
16 | in a new subsection for forward migration compatibility. | ||
17 | GBPA is only migrated if its value is different from the reset value. | ||
18 | It does this to be backward migration compatible if SW didn't write | ||
19 | the register. | ||
20 | |||
21 | Signed-off-by: Mostafa Saleh <smostafa@google.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Message-id: 20230214094009.2445653-1-smostafa@google.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 27 | --- |
12 | hw/arm/integratorcp.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++ | 28 | hw/arm/smmuv3-internal.h | 7 +++++++ |
13 | 1 file changed, 59 insertions(+) | 29 | include/hw/arm/smmuv3.h | 1 + |
30 | hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- | ||
31 | 3 files changed, 50 insertions(+), 1 deletion(-) | ||
14 | 32 | ||
15 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c | 33 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h |
16 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/integratorcp.c | 35 | --- a/hw/arm/smmuv3-internal.h |
18 | +++ b/hw/arm/integratorcp.c | 36 | +++ b/hw/arm/smmuv3-internal.h |
19 | @@ -XXX,XX +XXX,XX @@ static uint8_t integrator_spd[128] = { | 37 | @@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24) |
20 | 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 | 38 | REG32(CR1, 0x28) |
39 | REG32(CR2, 0x2c) | ||
40 | REG32(STATUSR, 0x40) | ||
41 | +REG32(GBPA, 0x44) | ||
42 | + FIELD(GBPA, ABORT, 20, 1) | ||
43 | + FIELD(GBPA, UPDATE, 31, 1) | ||
44 | + | ||
45 | +/* Use incoming. */ | ||
46 | +#define SMMU_GBPA_RESET_VAL 0x1000 | ||
47 | + | ||
48 | REG32(IRQ_CTRL, 0x50) | ||
49 | FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) | ||
50 | FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) | ||
51 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/include/hw/arm/smmuv3.h | ||
54 | +++ b/include/hw/arm/smmuv3.h | ||
55 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { | ||
56 | uint32_t cr[3]; | ||
57 | uint32_t cr0ack; | ||
58 | uint32_t statusr; | ||
59 | + uint32_t gbpa; | ||
60 | uint32_t irq_ctrl; | ||
61 | uint32_t gerror; | ||
62 | uint32_t gerrorn; | ||
63 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/arm/smmuv3.c | ||
66 | +++ b/hw/arm/smmuv3.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | ||
68 | s->gerror = 0; | ||
69 | s->gerrorn = 0; | ||
70 | s->statusr = 0; | ||
71 | + s->gbpa = SMMU_GBPA_RESET_VAL; | ||
72 | } | ||
73 | |||
74 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
76 | qemu_mutex_lock(&s->mutex); | ||
77 | |||
78 | if (!smmu_enabled(s)) { | ||
79 | - status = SMMU_TRANS_DISABLE; | ||
80 | + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { | ||
81 | + status = SMMU_TRANS_ABORT; | ||
82 | + } else { | ||
83 | + status = SMMU_TRANS_DISABLE; | ||
84 | + } | ||
85 | goto epilogue; | ||
86 | } | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, | ||
89 | case A_GERROR_IRQ_CFG2: | ||
90 | s->gerror_irq_cfg2 = data; | ||
91 | return MEMTX_OK; | ||
92 | + case A_GBPA: | ||
93 | + /* | ||
94 | + * If UPDATE is not set, the write is ignored. This is the only | ||
95 | + * permitted behavior in SMMUv3.2 and later. | ||
96 | + */ | ||
97 | + if (data & R_GBPA_UPDATE_MASK) { | ||
98 | + /* Ignore update bit as write is synchronous. */ | ||
99 | + s->gbpa = data & ~R_GBPA_UPDATE_MASK; | ||
100 | + } | ||
101 | + return MEMTX_OK; | ||
102 | case A_STRTAB_BASE: /* 64b */ | ||
103 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | ||
104 | return MEMTX_OK; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | ||
106 | case A_STATUSR: | ||
107 | *data = s->statusr; | ||
108 | return MEMTX_OK; | ||
109 | + case A_GBPA: | ||
110 | + *data = s->gbpa; | ||
111 | + return MEMTX_OK; | ||
112 | case A_IRQ_CTRL: | ||
113 | case A_IRQ_CTRL_ACK: | ||
114 | *data = s->irq_ctrl; | ||
115 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = { | ||
116 | }, | ||
21 | }; | 117 | }; |
22 | 118 | ||
23 | +static const VMStateDescription vmstate_integratorcm = { | 119 | +static bool smmuv3_gbpa_needed(void *opaque) |
24 | + .name = "integratorcm", | 120 | +{ |
121 | + SMMUv3State *s = opaque; | ||
122 | + | ||
123 | + /* Only migrate GBPA if it has different reset value. */ | ||
124 | + return s->gbpa != SMMU_GBPA_RESET_VAL; | ||
125 | +} | ||
126 | + | ||
127 | +static const VMStateDescription vmstate_gbpa = { | ||
128 | + .name = "smmuv3/gbpa", | ||
25 | + .version_id = 1, | 129 | + .version_id = 1, |
26 | + .minimum_version_id = 1, | 130 | + .minimum_version_id = 1, |
27 | + .fields = (VMStateField[]) { | 131 | + .needed = smmuv3_gbpa_needed, |
28 | + VMSTATE_UINT32(cm_osc, IntegratorCMState), | 132 | + .fields = (VMStateField[]) { |
29 | + VMSTATE_UINT32(cm_ctrl, IntegratorCMState), | 133 | + VMSTATE_UINT32(gbpa, SMMUv3State), |
30 | + VMSTATE_UINT32(cm_lock, IntegratorCMState), | ||
31 | + VMSTATE_UINT32(cm_auxosc, IntegratorCMState), | ||
32 | + VMSTATE_UINT32(cm_sdram, IntegratorCMState), | ||
33 | + VMSTATE_UINT32(cm_init, IntegratorCMState), | ||
34 | + VMSTATE_UINT32(cm_flags, IntegratorCMState), | ||
35 | + VMSTATE_UINT32(cm_nvflags, IntegratorCMState), | ||
36 | + VMSTATE_UINT32(int_level, IntegratorCMState), | ||
37 | + VMSTATE_UINT32(irq_enabled, IntegratorCMState), | ||
38 | + VMSTATE_UINT32(fiq_enabled, IntegratorCMState), | ||
39 | + VMSTATE_END_OF_LIST() | 134 | + VMSTATE_END_OF_LIST() |
40 | + } | 135 | + } |
41 | +}; | 136 | +}; |
42 | + | 137 | + |
43 | static uint64_t integratorcm_read(void *opaque, hwaddr offset, | 138 | static const VMStateDescription vmstate_smmuv3 = { |
44 | unsigned size) | 139 | .name = "smmuv3", |
45 | { | 140 | .version_id = 1, |
46 | @@ -XXX,XX +XXX,XX @@ typedef struct icp_pic_state { | 141 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = { |
47 | qemu_irq parent_fiq; | 142 | |
48 | } icp_pic_state; | 143 | VMSTATE_END_OF_LIST(), |
49 | 144 | }, | |
50 | +static const VMStateDescription vmstate_icp_pic = { | 145 | + .subsections = (const VMStateDescription * []) { |
51 | + .name = "icp_pic", | 146 | + &vmstate_gbpa, |
52 | + .version_id = 1, | 147 | + NULL |
53 | + .minimum_version_id = 1, | ||
54 | + .fields = (VMStateField[]) { | ||
55 | + VMSTATE_UINT32(level, icp_pic_state), | ||
56 | + VMSTATE_UINT32(irq_enabled, icp_pic_state), | ||
57 | + VMSTATE_UINT32(fiq_enabled, icp_pic_state), | ||
58 | + VMSTATE_END_OF_LIST() | ||
59 | + } | 148 | + } |
60 | +}; | ||
61 | + | ||
62 | static void icp_pic_update(icp_pic_state *s) | ||
63 | { | ||
64 | uint32_t flags; | ||
65 | @@ -XXX,XX +XXX,XX @@ typedef struct ICPCtrlRegsState { | ||
66 | #define ICP_INTREG_WPROT (1 << 0) | ||
67 | #define ICP_INTREG_CARDIN (1 << 3) | ||
68 | |||
69 | +static const VMStateDescription vmstate_icp_control = { | ||
70 | + .name = "icp_control", | ||
71 | + .version_id = 1, | ||
72 | + .minimum_version_id = 1, | ||
73 | + .fields = (VMStateField[]) { | ||
74 | + VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), | ||
75 | + VMSTATE_END_OF_LIST() | ||
76 | + } | ||
77 | +}; | ||
78 | + | ||
79 | static uint64_t icp_control_read(void *opaque, hwaddr offset, | ||
80 | unsigned size) | ||
81 | { | ||
82 | @@ -XXX,XX +XXX,XX @@ static void core_class_init(ObjectClass *klass, void *data) | ||
83 | |||
84 | dc->props = core_properties; | ||
85 | dc->realize = integratorcm_realize; | ||
86 | + dc->vmsd = &vmstate_integratorcm; | ||
87 | +} | ||
88 | + | ||
89 | +static void icp_pic_class_init(ObjectClass *klass, void *data) | ||
90 | +{ | ||
91 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
92 | + | ||
93 | + dc->vmsd = &vmstate_icp_pic; | ||
94 | +} | ||
95 | + | ||
96 | +static void icp_control_class_init(ObjectClass *klass, void *data) | ||
97 | +{ | ||
98 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
99 | + | ||
100 | + dc->vmsd = &vmstate_icp_control; | ||
101 | } | ||
102 | |||
103 | static const TypeInfo core_info = { | ||
104 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_pic_info = { | ||
105 | .parent = TYPE_SYS_BUS_DEVICE, | ||
106 | .instance_size = sizeof(icp_pic_state), | ||
107 | .instance_init = icp_pic_init, | ||
108 | + .class_init = icp_pic_class_init, | ||
109 | }; | 149 | }; |
110 | 150 | ||
111 | static const TypeInfo icp_ctrl_regs_info = { | 151 | static void smmuv3_instance_init(Object *obj) |
112 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_ctrl_regs_info = { | ||
113 | .parent = TYPE_SYS_BUS_DEVICE, | ||
114 | .instance_size = sizeof(ICPCtrlRegsState), | ||
115 | .instance_init = icp_control_init, | ||
116 | + .class_init = icp_control_class_init, | ||
117 | }; | ||
118 | |||
119 | static void integratorcp_register_types(void) | ||
120 | -- | 152 | -- |
121 | 2.7.4 | 153 | 2.34.1 |
122 | |||
123 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Since commit acc0b8b05a when running the ZynqMP ZCU102 board with | ||
4 | a QEMU configured using --without-default-devices, we get: | ||
5 | |||
6 | $ qemu-system-aarch64 -M xlnx-zcu102 | ||
7 | qemu-system-aarch64: missing object type 'usb_dwc3' | ||
8 | Abort trap: 6 | ||
9 | |||
10 | Fix by adding the missing Kconfig dependency. | ||
11 | |||
12 | Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230216092327.2203-1-philmd@linaro.org | ||
15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | hw/arm/Kconfig | 1 + | ||
19 | 1 file changed, 1 insertion(+) | ||
20 | |||
21 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/arm/Kconfig | ||
24 | +++ b/hw/arm/Kconfig | ||
25 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM | ||
26 | select XLNX_CSU_DMA | ||
27 | select XLNX_ZYNQMP | ||
28 | select XLNX_ZDMA | ||
29 | + select USB_DWC3 | ||
30 | |||
31 | config XLNX_VERSAL | ||
32 | bool | ||
33 | -- | ||
34 | 2.34.1 | ||
35 | |||
36 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Cornelia Huck <cohuck@redhat.com> | ||
1 | 2 | ||
3 | Just use current_accel_name() directly. | ||
4 | |||
5 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> | ||
6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/virt.c | 6 +++--- | ||
11 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/virt.c | ||
16 | +++ b/hw/arm/virt.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
18 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { | ||
19 | error_report("mach-virt: %s does not support providing " | ||
20 | "Security extensions (TrustZone) to the guest CPU", | ||
21 | - kvm_enabled() ? "KVM" : "HVF"); | ||
22 | + current_accel_name()); | ||
23 | exit(1); | ||
24 | } | ||
25 | |||
26 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { | ||
27 | error_report("mach-virt: %s does not support providing " | ||
28 | "Virtualization extensions to the guest CPU", | ||
29 | - kvm_enabled() ? "KVM" : "HVF"); | ||
30 | + current_accel_name()); | ||
31 | exit(1); | ||
32 | } | ||
33 | |||
34 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { | ||
35 | error_report("mach-virt: %s does not support providing " | ||
36 | "MTE to the guest CPU", | ||
37 | - kvm_enabled() ? "KVM" : "HVF"); | ||
38 | + current_accel_name()); | ||
39 | exit(1); | ||
40 | } | ||
41 | |||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
1 | 2 | ||
3 | Havard is no longer working on the Nuvoton systems for a while | ||
4 | and won't be able to do any work on it in the future. So I'll | ||
5 | take over maintaining the Nuvoton system from him. | ||
6 | |||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Acked-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
10 | Message-id: 20230208235433.3989937-2-wuhaotsh@google.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/MAINTAINERS | ||
19 | +++ b/MAINTAINERS | ||
20 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h | ||
21 | F: docs/system/arm/musicpal.rst | ||
22 | |||
23 | Nuvoton NPCM7xx | ||
24 | -M: Havard Skinnemoen <hskinnemoen@google.com> | ||
25 | M: Tyrone Ting <kfting@nuvoton.com> | ||
26 | +M: Hao Wu <wuhaotsh@google.com> | ||
27 | L: qemu-arm@nongnu.org | ||
28 | S: Supported | ||
29 | F: hw/*/npcm7xx* | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The Aspeed SoC includes a set of watchdog timers using 32-bit | 3 | Nuvoton's PSPI is a general purpose SPI module which enables |
4 | decrement counters, which can be based either on the APB clock or | 4 | connections to SPI-based peripheral devices. |
5 | a 1 MHz clock. | ||
6 | 5 | ||
7 | The watchdog timer is designed to prevent system deadlock and, in | 6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
8 | general, it should be restarted before timeout. When a timeout occurs, | 7 | Reviewed-by: Chris Rauer <crauer@google.com> |
9 | different types of signals can be generated, ARM reset, SOC reset, | 8 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> |
10 | System reset, CPU Interrupt, external signal or boot from alternate | 9 | Message-id: 20230208235433.3989937-3-wuhaotsh@google.com |
11 | block. The current model only performs the system reset function as | ||
12 | this is used by U-Boot and Linux. | ||
13 | |||
14 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
15 | Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org | ||
16 | [clg: - fixed compile breakage | ||
17 | - fixed io region size | ||
18 | - added watchdog_perform_action() on timer expiry | ||
19 | - wrote a commit log | ||
20 | - merged fixes from Andrew Jeffery to scale the reload value ] | ||
21 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | ||
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | --- | 11 | --- |
25 | hw/watchdog/Makefile.objs | 1 + | 12 | MAINTAINERS | 6 +- |
26 | include/hw/watchdog/wdt_aspeed.h | 32 ++++++ | 13 | include/hw/ssi/npcm_pspi.h | 53 +++++++++ |
27 | hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++ | 14 | hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ |
28 | 3 files changed, 258 insertions(+) | 15 | hw/ssi/meson.build | 2 +- |
29 | create mode 100644 include/hw/watchdog/wdt_aspeed.h | 16 | hw/ssi/trace-events | 5 + |
30 | create mode 100644 hw/watchdog/wdt_aspeed.c | 17 | 5 files changed, 283 insertions(+), 4 deletions(-) |
18 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
19 | create mode 100644 hw/ssi/npcm_pspi.c | ||
31 | 20 | ||
32 | diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs | 21 | diff --git a/MAINTAINERS b/MAINTAINERS |
33 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/hw/watchdog/Makefile.objs | 23 | --- a/MAINTAINERS |
35 | +++ b/hw/watchdog/Makefile.objs | 24 | +++ b/MAINTAINERS |
36 | @@ -XXX,XX +XXX,XX @@ common-obj-y += watchdog.o | 25 | @@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com> |
37 | common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o | 26 | M: Hao Wu <wuhaotsh@google.com> |
38 | common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o | 27 | L: qemu-arm@nongnu.org |
39 | common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o | 28 | S: Supported |
40 | +common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o | 29 | -F: hw/*/npcm7xx* |
41 | diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h | 30 | -F: include/hw/*/npcm7xx* |
31 | -F: tests/qtest/npcm7xx* | ||
32 | +F: hw/*/npcm* | ||
33 | +F: include/hw/*/npcm* | ||
34 | +F: tests/qtest/npcm* | ||
35 | F: pc-bios/npcm7xx_bootrom.bin | ||
36 | F: roms/vbootrom | ||
37 | F: docs/system/arm/nuvoton.rst | ||
38 | diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h | ||
42 | new file mode 100644 | 39 | new file mode 100644 |
43 | index XXXXXXX..XXXXXXX | 40 | index XXXXXXX..XXXXXXX |
44 | --- /dev/null | 41 | --- /dev/null |
45 | +++ b/include/hw/watchdog/wdt_aspeed.h | 42 | +++ b/include/hw/ssi/npcm_pspi.h |
46 | @@ -XXX,XX +XXX,XX @@ | 43 | @@ -XXX,XX +XXX,XX @@ |
47 | +/* | 44 | +/* |
48 | + * ASPEED Watchdog Controller | 45 | + * Nuvoton Peripheral SPI Module |
49 | + * | 46 | + * |
50 | + * Copyright (C) 2016-2017 IBM Corp. | 47 | + * Copyright 2023 Google LLC |
51 | + * | 48 | + * |
52 | + * This code is licensed under the GPL version 2 or later. See the | 49 | + * This program is free software; you can redistribute it and/or modify it |
53 | + * COPYING file in the top-level directory. | 50 | + * under the terms of the GNU General Public License as published by the |
51 | + * Free Software Foundation; either version 2 of the License, or | ||
52 | + * (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
55 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
56 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
57 | + * for more details. | ||
54 | + */ | 58 | + */ |
55 | +#ifndef ASPEED_WDT_H | 59 | +#ifndef NPCM_PSPI_H |
56 | +#define ASPEED_WDT_H | 60 | +#define NPCM_PSPI_H |
57 | + | 61 | + |
62 | +#include "hw/ssi/ssi.h" | ||
58 | +#include "hw/sysbus.h" | 63 | +#include "hw/sysbus.h" |
59 | + | 64 | + |
60 | +#define TYPE_ASPEED_WDT "aspeed.wdt" | 65 | +/* |
61 | +#define ASPEED_WDT(obj) \ | 66 | + * Number of registers in our device state structure. Don't change this without |
62 | + OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) | 67 | + * incrementing the version_id in the vmstate. |
63 | + | 68 | + */ |
64 | +#define ASPEED_WDT_REGS_MAX (0x20 / 4) | 69 | +#define NPCM_PSPI_NR_REGS 3 |
65 | + | 70 | + |
66 | +typedef struct AspeedWDTState { | 71 | +/** |
67 | + /*< private >*/ | 72 | + * NPCMPSPIState - Device state for one Flash Interface Unit. |
68 | + SysBusDevice parent_obj; | 73 | + * @parent: System bus device. |
69 | + QEMUTimer *timer; | 74 | + * @mmio: Memory region for register access. |
70 | + | 75 | + * @spi: The SPI bus mastered by this controller. |
71 | + /*< public >*/ | 76 | + * @regs: Register contents. |
72 | + MemoryRegion iomem; | 77 | + * @irq: The interrupt request queue for this module. |
73 | + uint32_t regs[ASPEED_WDT_REGS_MAX]; | 78 | + * |
74 | + | 79 | + * Each PSPI has a shared bank of registers, and controls up to four chip |
75 | + uint32_t pclk_freq; | 80 | + * selects. Each chip select has a dedicated memory region which may be used to |
76 | +} AspeedWDTState; | 81 | + * read and write the flash connected to that chip select as if it were memory. |
77 | + | 82 | + */ |
78 | +#endif /* ASPEED_WDT_H */ | 83 | +typedef struct NPCMPSPIState { |
79 | diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c | 84 | + SysBusDevice parent; |
85 | + | ||
86 | + MemoryRegion mmio; | ||
87 | + | ||
88 | + SSIBus *spi; | ||
89 | + uint16_t regs[NPCM_PSPI_NR_REGS]; | ||
90 | + qemu_irq irq; | ||
91 | +} NPCMPSPIState; | ||
92 | + | ||
93 | +#define TYPE_NPCM_PSPI "npcm-pspi" | ||
94 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) | ||
95 | + | ||
96 | +#endif /* NPCM_PSPI_H */ | ||
97 | diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c | ||
80 | new file mode 100644 | 98 | new file mode 100644 |
81 | index XXXXXXX..XXXXXXX | 99 | index XXXXXXX..XXXXXXX |
82 | --- /dev/null | 100 | --- /dev/null |
83 | +++ b/hw/watchdog/wdt_aspeed.c | 101 | +++ b/hw/ssi/npcm_pspi.c |
84 | @@ -XXX,XX +XXX,XX @@ | 102 | @@ -XXX,XX +XXX,XX @@ |
85 | +/* | 103 | +/* |
86 | + * ASPEED Watchdog Controller | 104 | + * Nuvoton NPCM Peripheral SPI Module (PSPI) |
87 | + * | 105 | + * |
88 | + * Copyright (C) 2016-2017 IBM Corp. | 106 | + * Copyright 2023 Google LLC |
89 | + * | 107 | + * |
90 | + * This code is licensed under the GPL version 2 or later. See the | 108 | + * This program is free software; you can redistribute it and/or modify it |
91 | + * COPYING file in the top-level directory. | 109 | + * under the terms of the GNU General Public License as published by the |
110 | + * Free Software Foundation; either version 2 of the License, or | ||
111 | + * (at your option) any later version. | ||
112 | + * | ||
113 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
114 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
115 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
116 | + * for more details. | ||
92 | + */ | 117 | + */ |
93 | + | 118 | + |
94 | +#include "qemu/osdep.h" | 119 | +#include "qemu/osdep.h" |
120 | + | ||
121 | +#include "hw/irq.h" | ||
122 | +#include "hw/registerfields.h" | ||
123 | +#include "hw/ssi/npcm_pspi.h" | ||
124 | +#include "migration/vmstate.h" | ||
125 | +#include "qapi/error.h" | ||
126 | +#include "qemu/error-report.h" | ||
95 | +#include "qemu/log.h" | 127 | +#include "qemu/log.h" |
96 | +#include "sysemu/watchdog.h" | 128 | +#include "qemu/module.h" |
97 | +#include "hw/sysbus.h" | 129 | +#include "qemu/units.h" |
98 | +#include "qemu/timer.h" | 130 | + |
99 | +#include "hw/watchdog/wdt_aspeed.h" | 131 | +#include "trace.h" |
100 | + | 132 | + |
101 | +#define WDT_STATUS (0x00 / 4) | 133 | +REG16(PSPI_DATA, 0x0) |
102 | +#define WDT_RELOAD_VALUE (0x04 / 4) | 134 | +REG16(PSPI_CTL1, 0x2) |
103 | +#define WDT_RESTART (0x08 / 4) | 135 | + FIELD(PSPI_CTL1, SPIEN, 0, 1) |
104 | +#define WDT_CTRL (0x0C / 4) | 136 | + FIELD(PSPI_CTL1, MOD, 2, 1) |
105 | +#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) | 137 | + FIELD(PSPI_CTL1, EIR, 5, 1) |
106 | +#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) | 138 | + FIELD(PSPI_CTL1, EIW, 6, 1) |
107 | +#define WDT_CTRL_1MHZ_CLK BIT(4) | 139 | + FIELD(PSPI_CTL1, SCM, 7, 1) |
108 | +#define WDT_CTRL_WDT_EXT BIT(3) | 140 | + FIELD(PSPI_CTL1, SCIDL, 8, 1) |
109 | +#define WDT_CTRL_WDT_INTR BIT(2) | 141 | + FIELD(PSPI_CTL1, SCDV, 9, 7) |
110 | +#define WDT_CTRL_RESET_SYSTEM BIT(1) | 142 | +REG16(PSPI_STAT, 0x4) |
111 | +#define WDT_CTRL_ENABLE BIT(0) | 143 | + FIELD(PSPI_STAT, BSY, 0, 1) |
112 | + | 144 | + FIELD(PSPI_STAT, RBF, 1, 1) |
113 | +#define WDT_TIMEOUT_STATUS (0x10 / 4) | 145 | + |
114 | +#define WDT_TIMEOUT_CLEAR (0x14 / 4) | 146 | +static void npcm_pspi_update_irq(NPCMPSPIState *s) |
115 | +#define WDT_RESET_WDITH (0x18 / 4) | 147 | +{ |
116 | + | 148 | + int level = 0; |
117 | +#define WDT_RESTART_MAGIC 0x4755 | 149 | + |
118 | + | 150 | + /* Only fire IRQ when the module is enabled. */ |
119 | +static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) | 151 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { |
120 | +{ | 152 | + /* Update interrupt as BSY is cleared. */ |
121 | + return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; | 153 | + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && |
122 | +} | 154 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { |
123 | + | 155 | + level = 1; |
124 | +static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) | 156 | + } |
125 | +{ | 157 | + |
126 | + AspeedWDTState *s = ASPEED_WDT(opaque); | 158 | + /* Update interrupt as RBF is set. */ |
127 | + | 159 | + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && |
128 | + offset >>= 2; | 160 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { |
129 | + | 161 | + level = 1; |
130 | + switch (offset) { | 162 | + } |
131 | + case WDT_STATUS: | 163 | + } |
132 | + return s->regs[WDT_STATUS]; | 164 | + qemu_set_irq(s->irq, level); |
133 | + case WDT_RELOAD_VALUE: | 165 | +} |
134 | + return s->regs[WDT_RELOAD_VALUE]; | 166 | + |
135 | + case WDT_RESTART: | 167 | +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) |
136 | + qemu_log_mask(LOG_GUEST_ERROR, | 168 | +{ |
137 | + "%s: read from write-only reg at offset 0x%" | 169 | + uint16_t value = s->regs[R_PSPI_DATA]; |
138 | + HWADDR_PRIx "\n", __func__, offset); | 170 | + |
139 | + return 0; | 171 | + /* Clear stat bits as the value are read out. */ |
140 | + case WDT_CTRL: | 172 | + s->regs[R_PSPI_STAT] = 0; |
141 | + return s->regs[WDT_CTRL]; | 173 | + |
142 | + case WDT_TIMEOUT_STATUS: | 174 | + return value; |
143 | + case WDT_TIMEOUT_CLEAR: | 175 | +} |
144 | + case WDT_RESET_WDITH: | 176 | + |
145 | + qemu_log_mask(LOG_UNIMP, | 177 | +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) |
146 | + "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", | 178 | +{ |
147 | + __func__, offset); | 179 | + uint16_t value = 0; |
148 | + return 0; | 180 | + |
181 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { | ||
182 | + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; | ||
183 | + } | ||
184 | + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); | ||
185 | + s->regs[R_PSPI_DATA] = value; | ||
186 | + | ||
187 | + /* Mark data as available */ | ||
188 | + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; | ||
189 | +} | ||
190 | + | ||
191 | +/* Control register read handler. */ | ||
192 | +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, | ||
193 | + unsigned int size) | ||
194 | +{ | ||
195 | + NPCMPSPIState *s = opaque; | ||
196 | + uint16_t value; | ||
197 | + | ||
198 | + switch (addr) { | ||
199 | + case A_PSPI_DATA: | ||
200 | + value = npcm_pspi_read_data(s); | ||
201 | + break; | ||
202 | + | ||
203 | + case A_PSPI_CTL1: | ||
204 | + value = s->regs[R_PSPI_CTL1]; | ||
205 | + break; | ||
206 | + | ||
207 | + case A_PSPI_STAT: | ||
208 | + value = s->regs[R_PSPI_STAT]; | ||
209 | + break; | ||
210 | + | ||
149 | + default: | 211 | + default: |
150 | + qemu_log_mask(LOG_GUEST_ERROR, | 212 | + qemu_log_mask(LOG_GUEST_ERROR, |
151 | + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", | 213 | + "%s: write to invalid offset 0x%" PRIx64 "\n", |
152 | + __func__, offset); | 214 | + DEVICE(s)->canonical_path, addr); |
153 | + return 0; | 215 | + return 0; |
154 | + } | 216 | + } |
155 | + | 217 | + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); |
156 | +} | 218 | + npcm_pspi_update_irq(s); |
157 | + | 219 | + |
158 | +static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) | 220 | + return value; |
159 | +{ | 221 | +} |
160 | + uint32_t reload; | 222 | + |
161 | + | 223 | +/* Control register write handler. */ |
162 | + if (pclk) { | 224 | +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, |
163 | + reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, | 225 | + unsigned int size) |
164 | + s->pclk_freq); | 226 | +{ |
165 | + } else { | 227 | + NPCMPSPIState *s = opaque; |
166 | + reload = s->regs[WDT_RELOAD_VALUE] * 1000; | 228 | + uint16_t value = v; |
167 | + } | 229 | + |
168 | + | 230 | + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); |
169 | + if (aspeed_wdt_is_enabled(s)) { | 231 | + |
170 | + timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); | 232 | + switch (addr) { |
171 | + } | 233 | + case A_PSPI_DATA: |
172 | +} | 234 | + npcm_pspi_write_data(s, value); |
173 | + | 235 | + break; |
174 | +static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, | 236 | + |
175 | + unsigned size) | 237 | + case A_PSPI_CTL1: |
176 | +{ | 238 | + s->regs[R_PSPI_CTL1] = value; |
177 | + AspeedWDTState *s = ASPEED_WDT(opaque); | 239 | + break; |
178 | + bool enable = data & WDT_CTRL_ENABLE; | 240 | + |
179 | + | 241 | + case A_PSPI_STAT: |
180 | + offset >>= 2; | ||
181 | + | ||
182 | + switch (offset) { | ||
183 | + case WDT_STATUS: | ||
184 | + qemu_log_mask(LOG_GUEST_ERROR, | 242 | + qemu_log_mask(LOG_GUEST_ERROR, |
185 | + "%s: write to read-only reg at offset 0x%" | 243 | + "%s: write to read-only register PSPI_STAT: 0x%08" |
186 | + HWADDR_PRIx "\n", __func__, offset); | 244 | + PRIx64 "\n", DEVICE(s)->canonical_path, v); |
187 | + break; | 245 | + break; |
188 | + case WDT_RELOAD_VALUE: | 246 | + |
189 | + s->regs[WDT_RELOAD_VALUE] = data; | ||
190 | + break; | ||
191 | + case WDT_RESTART: | ||
192 | + if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { | ||
193 | + s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; | ||
194 | + aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | ||
195 | + } | ||
196 | + break; | ||
197 | + case WDT_CTRL: | ||
198 | + if (enable && !aspeed_wdt_is_enabled(s)) { | ||
199 | + s->regs[WDT_CTRL] = data; | ||
200 | + aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); | ||
201 | + } else if (!enable && aspeed_wdt_is_enabled(s)) { | ||
202 | + s->regs[WDT_CTRL] = data; | ||
203 | + timer_del(s->timer); | ||
204 | + } | ||
205 | + break; | ||
206 | + case WDT_TIMEOUT_STATUS: | ||
207 | + case WDT_TIMEOUT_CLEAR: | ||
208 | + case WDT_RESET_WDITH: | ||
209 | + qemu_log_mask(LOG_UNIMP, | ||
210 | + "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", | ||
211 | + __func__, offset); | ||
212 | + break; | ||
213 | + default: | 247 | + default: |
214 | + qemu_log_mask(LOG_GUEST_ERROR, | 248 | + qemu_log_mask(LOG_GUEST_ERROR, |
215 | + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", | 249 | + "%s: write to invalid offset 0x%" PRIx64 "\n", |
216 | + __func__, offset); | 250 | + DEVICE(s)->canonical_path, addr); |
251 | + return; | ||
217 | + } | 252 | + } |
218 | + return; | 253 | + npcm_pspi_update_irq(s); |
219 | +} | 254 | +} |
220 | + | 255 | + |
221 | +static WatchdogTimerModel model = { | 256 | +static const MemoryRegionOps npcm_pspi_ctrl_ops = { |
222 | + .wdt_name = TYPE_ASPEED_WDT, | 257 | + .read = npcm_pspi_ctrl_read, |
223 | + .wdt_description = "Aspeed watchdog device", | 258 | + .write = npcm_pspi_ctrl_write, |
259 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
260 | + .valid = { | ||
261 | + .min_access_size = 1, | ||
262 | + .max_access_size = 2, | ||
263 | + .unaligned = false, | ||
264 | + }, | ||
265 | + .impl = { | ||
266 | + .min_access_size = 2, | ||
267 | + .max_access_size = 2, | ||
268 | + .unaligned = false, | ||
269 | + }, | ||
224 | +}; | 270 | +}; |
225 | + | 271 | + |
226 | +static const VMStateDescription vmstate_aspeed_wdt = { | 272 | +static void npcm_pspi_enter_reset(Object *obj, ResetType type) |
227 | + .name = "vmstate_aspeed_wdt", | 273 | +{ |
274 | + NPCMPSPIState *s = NPCM_PSPI(obj); | ||
275 | + | ||
276 | + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); | ||
277 | + memset(s->regs, 0, sizeof(s->regs)); | ||
278 | +} | ||
279 | + | ||
280 | +static void npcm_pspi_realize(DeviceState *dev, Error **errp) | ||
281 | +{ | ||
282 | + NPCMPSPIState *s = NPCM_PSPI(dev); | ||
283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
284 | + Object *obj = OBJECT(dev); | ||
285 | + | ||
286 | + s->spi = ssi_create_bus(dev, "pspi"); | ||
287 | + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, | ||
288 | + "mmio", 4 * KiB); | ||
289 | + sysbus_init_mmio(sbd, &s->mmio); | ||
290 | + sysbus_init_irq(sbd, &s->irq); | ||
291 | +} | ||
292 | + | ||
293 | +static const VMStateDescription vmstate_npcm_pspi = { | ||
294 | + .name = "npcm-pspi", | ||
228 | + .version_id = 0, | 295 | + .version_id = 0, |
229 | + .minimum_version_id = 0, | 296 | + .minimum_version_id = 0, |
230 | + .fields = (VMStateField[]) { | 297 | + .fields = (VMStateField[]) { |
231 | + VMSTATE_TIMER_PTR(timer, AspeedWDTState), | 298 | + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), |
232 | + VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), | 299 | + VMSTATE_END_OF_LIST(), |
233 | + VMSTATE_END_OF_LIST() | 300 | + }, |
234 | + } | ||
235 | +}; | 301 | +}; |
236 | + | 302 | + |
237 | +static const MemoryRegionOps aspeed_wdt_ops = { | 303 | + |
238 | + .read = aspeed_wdt_read, | 304 | +static void npcm_pspi_class_init(ObjectClass *klass, void *data) |
239 | + .write = aspeed_wdt_write, | 305 | +{ |
240 | + .endianness = DEVICE_LITTLE_ENDIAN, | 306 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
241 | + .valid.min_access_size = 4, | 307 | + DeviceClass *dc = DEVICE_CLASS(klass); |
242 | + .valid.max_access_size = 4, | 308 | + |
243 | + .valid.unaligned = false, | 309 | + dc->desc = "NPCM Peripheral SPI Module"; |
310 | + dc->realize = npcm_pspi_realize; | ||
311 | + dc->vmsd = &vmstate_npcm_pspi; | ||
312 | + rc->phases.enter = npcm_pspi_enter_reset; | ||
313 | +} | ||
314 | + | ||
315 | +static const TypeInfo npcm_pspi_types[] = { | ||
316 | + { | ||
317 | + .name = TYPE_NPCM_PSPI, | ||
318 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
319 | + .instance_size = sizeof(NPCMPSPIState), | ||
320 | + .class_init = npcm_pspi_class_init, | ||
321 | + }, | ||
244 | +}; | 322 | +}; |
245 | + | 323 | +DEFINE_TYPES(npcm_pspi_types); |
246 | +static void aspeed_wdt_reset(DeviceState *dev) | 324 | diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build |
247 | +{ | 325 | index XXXXXXX..XXXXXXX 100644 |
248 | + AspeedWDTState *s = ASPEED_WDT(dev); | 326 | --- a/hw/ssi/meson.build |
249 | + | 327 | +++ b/hw/ssi/meson.build |
250 | + s->regs[WDT_STATUS] = 0x3EF1480; | 328 | @@ -XXX,XX +XXX,XX @@ |
251 | + s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; | 329 | softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) |
252 | + s->regs[WDT_RESTART] = 0; | 330 | softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) |
253 | + s->regs[WDT_CTRL] = 0; | 331 | -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) |
254 | + | 332 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) |
255 | + timer_del(s->timer); | 333 | softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) |
256 | +} | 334 | softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) |
257 | + | 335 | softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) |
258 | +static void aspeed_wdt_timer_expired(void *dev) | 336 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events |
259 | +{ | 337 | index XXXXXXX..XXXXXXX 100644 |
260 | + AspeedWDTState *s = ASPEED_WDT(dev); | 338 | --- a/hw/ssi/trace-events |
261 | + | 339 | +++ b/hw/ssi/trace-events |
262 | + qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); | 340 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: |
263 | + watchdog_perform_action(); | 341 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 |
264 | + timer_del(s->timer); | 342 | npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 |
265 | +} | 343 | |
266 | + | 344 | +# npcm_pspi.c |
267 | +#define PCLK_HZ 24000000 | 345 | +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" |
268 | + | 346 | +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 |
269 | +static void aspeed_wdt_realize(DeviceState *dev, Error **errp) | 347 | +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 |
270 | +{ | 348 | + |
271 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 349 | # ibex_spi_host.c |
272 | + AspeedWDTState *s = ASPEED_WDT(dev); | 350 | |
273 | + | 351 | ibex_spi_host_reset(const char *msg) "%s" |
274 | + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); | ||
275 | + | ||
276 | + /* FIXME: This setting should be derived from the SCU hw strapping | ||
277 | + * register SCU70 | ||
278 | + */ | ||
279 | + s->pclk_freq = PCLK_HZ; | ||
280 | + | ||
281 | + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, | ||
282 | + TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); | ||
283 | + sysbus_init_mmio(sbd, &s->iomem); | ||
284 | +} | ||
285 | + | ||
286 | +static void aspeed_wdt_class_init(ObjectClass *klass, void *data) | ||
287 | +{ | ||
288 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
289 | + | ||
290 | + dc->realize = aspeed_wdt_realize; | ||
291 | + dc->reset = aspeed_wdt_reset; | ||
292 | + set_bit(DEVICE_CATEGORY_MISC, dc->categories); | ||
293 | + dc->vmsd = &vmstate_aspeed_wdt; | ||
294 | +} | ||
295 | + | ||
296 | +static const TypeInfo aspeed_wdt_info = { | ||
297 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
298 | + .name = TYPE_ASPEED_WDT, | ||
299 | + .instance_size = sizeof(AspeedWDTState), | ||
300 | + .class_init = aspeed_wdt_class_init, | ||
301 | +}; | ||
302 | + | ||
303 | +static void wdt_aspeed_register_types(void) | ||
304 | +{ | ||
305 | + watchdog_add_model(&model); | ||
306 | + type_register_static(&aspeed_wdt_info); | ||
307 | +} | ||
308 | + | ||
309 | +type_init(wdt_aspeed_register_types) | ||
310 | -- | 352 | -- |
311 | 2.7.4 | 353 | 2.34.1 |
312 | |||
313 | diff view generated by jsdifflib |
1 | Create a new "unimplemented" sysbus device, which simply accepts | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | all read and write accesses, and implements them as read-as-zero, | ||
3 | write-ignored, with logging of the access as LOG_UNIMP. | ||
4 | 2 | ||
5 | This is useful for stubbing out bits of an SoC or board model | 3 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
6 | which haven't been written yet. | 4 | Reviewed-by: Titus Rwantare <titusr@google.com> |
5 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
6 | Message-id: 20230208235433.3989937-4-wuhaotsh@google.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | docs/system/arm/nuvoton.rst | 2 +- | ||
10 | include/hw/arm/npcm7xx.h | 2 ++ | ||
11 | hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- | ||
12 | 3 files changed, 26 insertions(+), 3 deletions(-) | ||
7 | 13 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
10 | Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/misc/Makefile.objs | 2 + | ||
13 | include/hw/misc/unimp.h | 39 ++++++++++++++++++ | ||
14 | hw/misc/unimp.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++ | ||
15 | 3 files changed, 148 insertions(+) | ||
16 | create mode 100644 include/hw/misc/unimp.h | ||
17 | create mode 100644 hw/misc/unimp.c | ||
18 | |||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/Makefile.objs | 16 | --- a/docs/system/arm/nuvoton.rst |
22 | +++ b/hw/misc/Makefile.objs | 17 | +++ b/docs/system/arm/nuvoton.rst |
23 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o | 18 | @@ -XXX,XX +XXX,XX @@ Supported devices |
24 | common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o | 19 | * SMBus controller (SMBF) |
25 | common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o | 20 | * Ethernet controller (EMC) |
26 | 21 | * Tachometer | |
27 | +common-obj-y += unimp.o | 22 | + * Peripheral SPI controller (PSPI) |
28 | + | 23 | |
29 | obj-$(CONFIG_VMPORT) += vmport.o | 24 | Missing devices |
30 | 25 | --------------- | |
31 | # ARM devices | 26 | @@ -XXX,XX +XXX,XX @@ Missing devices |
32 | diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h | 27 | |
33 | new file mode 100644 | 28 | * Ethernet controller (GMAC) |
34 | index XXXXXXX..XXXXXXX | 29 | * USB device (USBD) |
35 | --- /dev/null | 30 | - * Peripheral SPI controller (PSPI) |
36 | +++ b/include/hw/misc/unimp.h | 31 | * SD/MMC host |
32 | * PECI interface | ||
33 | * PCI and PCIe root complex and bridges | ||
34 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/npcm7xx.h | ||
37 | +++ b/include/hw/arm/npcm7xx.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | 38 | @@ -XXX,XX +XXX,XX @@ |
38 | +/* | 39 | #include "hw/nvram/npcm7xx_otp.h" |
39 | + * "Unimplemented" device | 40 | #include "hw/timer/npcm7xx_timer.h" |
40 | + * | 41 | #include "hw/ssi/npcm7xx_fiu.h" |
41 | + * Copyright Linaro Limited, 2017 | 42 | +#include "hw/ssi/npcm_pspi.h" |
42 | + * Written by Peter Maydell | 43 | #include "hw/usb/hcd-ehci.h" |
43 | + */ | 44 | #include "hw/usb/hcd-ohci.h" |
44 | + | 45 | #include "target/arm/cpu.h" |
45 | +#ifndef HW_MISC_UNIMP_H | 46 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxState { |
46 | +#define HW_MISC_UNIMP_H | 47 | NPCM7xxFIUState fiu[2]; |
47 | + | 48 | NPCM7xxEMCState emc[2]; |
48 | +#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device" | 49 | NPCM7xxSDHCIState mmc; |
49 | + | 50 | + NPCMPSPIState pspi[2]; |
50 | +/** | 51 | }; |
51 | + * create_unimplemented_device: create and map a dummy device | 52 | |
52 | + * @name: name of the device for debug logging | 53 | #define TYPE_NPCM7XX "npcm7xx" |
53 | + * @base: base address of the device's MMIO region | 54 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c |
54 | + * @size: size of the device's MMIO region | 55 | index XXXXXXX..XXXXXXX 100644 |
55 | + * | 56 | --- a/hw/arm/npcm7xx.c |
56 | + * This utility function creates and maps an instance of unimplemented-device, | 57 | +++ b/hw/arm/npcm7xx.c |
57 | + * which is a dummy device which simply logs all guest accesses to | 58 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { |
58 | + * it via the qemu_log LOG_UNIMP debug log. | 59 | NPCM7XX_EMC1RX_IRQ = 15, |
59 | + * The device is mapped at priority -1000, which means that you can | 60 | NPCM7XX_EMC1TX_IRQ, |
60 | + * use it to cover a large region and then map other devices on top of it | 61 | NPCM7XX_MMC_IRQ = 26, |
61 | + * if necessary. | 62 | + NPCM7XX_PSPI2_IRQ = 28, |
62 | + */ | 63 | + NPCM7XX_PSPI1_IRQ = 31, |
63 | +static inline void create_unimplemented_device(const char *name, | 64 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ |
64 | + hwaddr base, | 65 | NPCM7XX_TIMER1_IRQ, |
65 | + hwaddr size) | 66 | NPCM7XX_TIMER2_IRQ, |
66 | +{ | 67 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = { |
67 | + DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE); | 68 | 0xf0826000, |
68 | + | 69 | }; |
69 | + qdev_prop_set_string(dev, "name", name); | 70 | |
70 | + qdev_prop_set_uint64(dev, "size", size); | 71 | +/* Register base address for each PSPI Module */ |
71 | + qdev_init_nofail(dev); | 72 | +static const hwaddr npcm7xx_pspi_addr[] = { |
72 | + | 73 | + 0xf0200000, |
73 | + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000); | 74 | + 0xf0201000, |
74 | +} | ||
75 | + | ||
76 | +#endif | ||
77 | diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c | ||
78 | new file mode 100644 | ||
79 | index XXXXXXX..XXXXXXX | ||
80 | --- /dev/null | ||
81 | +++ b/hw/misc/unimp.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | ||
83 | +/* "Unimplemented" device | ||
84 | + * | ||
85 | + * This is a dummy device which accepts and logs all accesses. | ||
86 | + * It's useful for stubbing out regions of an SoC or board | ||
87 | + * map which correspond to devices that have not yet been | ||
88 | + * implemented. This is often sufficient to placate initial | ||
89 | + * guest device driver probing such that the system will | ||
90 | + * come up. | ||
91 | + * | ||
92 | + * Copyright Linaro Limited, 2017 | ||
93 | + * Written by Peter Maydell | ||
94 | + */ | ||
95 | + | ||
96 | +#include "qemu/osdep.h" | ||
97 | +#include "hw/hw.h" | ||
98 | +#include "hw/sysbus.h" | ||
99 | +#include "hw/misc/unimp.h" | ||
100 | +#include "qemu/log.h" | ||
101 | +#include "qapi/error.h" | ||
102 | + | ||
103 | +#define UNIMPLEMENTED_DEVICE(obj) \ | ||
104 | + OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE) | ||
105 | + | ||
106 | +typedef struct { | ||
107 | + SysBusDevice parent_obj; | ||
108 | + MemoryRegion iomem; | ||
109 | + char *name; | ||
110 | + uint64_t size; | ||
111 | +} UnimplementedDeviceState; | ||
112 | + | ||
113 | +static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size) | ||
114 | +{ | ||
115 | + UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
116 | + | ||
117 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
118 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
119 | + s->name, size, offset); | ||
120 | + return 0; | ||
121 | +} | ||
122 | + | ||
123 | +static void unimp_write(void *opaque, hwaddr offset, | ||
124 | + uint64_t value, unsigned size) | ||
125 | +{ | ||
126 | + UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque); | ||
127 | + | ||
128 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | ||
129 | + "(size %d, value 0x%" PRIx64 | ||
130 | + ", offset 0x%" HWADDR_PRIx ")\n", | ||
131 | + s->name, size, value, offset); | ||
132 | +} | ||
133 | + | ||
134 | +static const MemoryRegionOps unimp_ops = { | ||
135 | + .read = unimp_read, | ||
136 | + .write = unimp_write, | ||
137 | + .impl.min_access_size = 1, | ||
138 | + .impl.max_access_size = 8, | ||
139 | + .valid.min_access_size = 1, | ||
140 | + .valid.max_access_size = 8, | ||
141 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
142 | +}; | 75 | +}; |
143 | + | 76 | + |
144 | +static void unimp_realize(DeviceState *dev, Error **errp) | 77 | static const struct { |
145 | +{ | 78 | hwaddr regs_addr; |
146 | + UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev); | 79 | uint32_t unconnected_pins; |
147 | + | 80 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) |
148 | + if (s->size == 0) { | 81 | object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); |
149 | + error_setg(errp, "property 'size' not specified or zero"); | 82 | } |
150 | + return; | 83 | |
84 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
85 | + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); | ||
151 | + } | 86 | + } |
152 | + | 87 | + |
153 | + if (s->name == NULL) { | 88 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); |
154 | + error_setg(errp, "property 'name' not specified"); | 89 | } |
155 | + return; | 90 | |
91 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
92 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, | ||
93 | npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); | ||
94 | |||
95 | + /* PSPI */ | ||
96 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); | ||
97 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
98 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); | ||
99 | + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; | ||
100 | + | ||
101 | + sysbus_realize(sbd, &error_abort); | ||
102 | + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); | ||
103 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); | ||
156 | + } | 104 | + } |
157 | + | 105 | + |
158 | + memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s, | 106 | create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); |
159 | + s->name, s->size); | 107 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); |
160 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | 108 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); |
161 | +} | 109 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
162 | + | 110 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); |
163 | +static Property unimp_properties[] = { | 111 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); |
164 | + DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0), | 112 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); |
165 | + DEFINE_PROP_STRING("name", UnimplementedDeviceState, name), | 113 | - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); |
166 | + DEFINE_PROP_END_OF_LIST(), | 114 | - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); |
167 | +}; | 115 | create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); |
168 | + | 116 | create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); |
169 | +static void unimp_class_init(ObjectClass *klass, void *data) | 117 | create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); |
170 | +{ | ||
171 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
172 | + | ||
173 | + dc->realize = unimp_realize; | ||
174 | + dc->props = unimp_properties; | ||
175 | +} | ||
176 | + | ||
177 | +static const TypeInfo unimp_info = { | ||
178 | + .name = TYPE_UNIMPLEMENTED_DEVICE, | ||
179 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
180 | + .instance_size = sizeof(UnimplementedDeviceState), | ||
181 | + .class_init = unimp_class_init, | ||
182 | +}; | ||
183 | + | ||
184 | +static void unimp_register_types(void) | ||
185 | +{ | ||
186 | + type_register_static(&unimp_info); | ||
187 | +} | ||
188 | + | ||
189 | +type_init(unimp_register_types) | ||
190 | -- | 118 | -- |
191 | 2.7.4 | 119 | 2.34.1 |
192 | |||
193 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
1 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set. Ensure the IOMMU region covers all 64 bits. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/smmu-common.h | 2 -- | ||
13 | hw/arm/smmu-common.c | 2 +- | ||
14 | 2 files changed, 1 insertion(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/smmu-common.h | ||
19 | +++ b/include/hw/arm/smmu-common.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #define SMMU_PCI_DEVFN_MAX 256 | ||
22 | #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) | ||
23 | |||
24 | -#define SMMU_MAX_VA_BITS 48 | ||
25 | - | ||
26 | /* | ||
27 | * Page table walk error types | ||
28 | */ | ||
29 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/smmu-common.c | ||
32 | +++ b/hw/arm/smmu-common.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | ||
34 | |||
35 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), | ||
36 | s->mrtypename, | ||
37 | - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); | ||
38 | + OBJECT(s), name, UINT64_MAX); | ||
39 | address_space_init(&sdev->as, | ||
40 | MEMORY_REGION(&sdev->iommu), name); | ||
41 | trace_smmu_add_mr(name); | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
1 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set (except for the top byte when TBI is enabled). Fix | ||
5 | the TTB1 check. | ||
6 | |||
7 | Reported-by: Ola Hugosson <ola.hugosson@arm.com> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/smmu-common.c | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/smmu-common.c | ||
20 | +++ b/hw/arm/smmu-common.c | ||
21 | @@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) | ||
22 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | ||
23 | return &cfg->tt[0]; | ||
24 | } else if (cfg->tt[1].tsz && | ||
25 | - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { | ||
26 | + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { | ||
27 | /* there is a ttbr1 region and we are in it (high bits all one) */ | ||
28 | return &cfg->tt[1]; | ||
29 | } else if (!cfg->tt[0].tsz) { | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Claudio Fontana <cfontana@suse.de> | ||
1 | 2 | ||
3 | make it clearer from the name that this is a tcg-only function. | ||
4 | |||
5 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper.c | 4 ++-- | ||
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.c | ||
18 | +++ b/target/arm/helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
20 | * trapped to the hypervisor in KVM. | ||
21 | */ | ||
22 | #ifdef CONFIG_TCG | ||
23 | -static void handle_semihosting(CPUState *cs) | ||
24 | +static void tcg_handle_semihosting(CPUState *cs) | ||
25 | { | ||
26 | ARMCPU *cpu = ARM_CPU(cs); | ||
27 | CPUARMState *env = &cpu->env; | ||
28 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
29 | */ | ||
30 | #ifdef CONFIG_TCG | ||
31 | if (cs->exception_index == EXCP_SEMIHOST) { | ||
32 | - handle_semihosting(cs); | ||
33 | + tcg_handle_semihosting(cs); | ||
34 | return; | ||
35 | } | ||
36 | #endif | ||
37 | -- | ||
38 | 2.34.1 | ||
39 | |||
40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Claudio Fontana <cfontana@suse.de> | ||
1 | 2 | ||
3 | for "all" builds (tcg + kvm), we want to avoid doing | ||
4 | the psci check if tcg is built-in, but not enabled. | ||
5 | |||
6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper.c | 3 ++- | ||
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.c | ||
18 | +++ b/target/arm/helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "hw/irq.h" | ||
21 | #include "sysemu/cpu-timers.h" | ||
22 | #include "sysemu/kvm.h" | ||
23 | +#include "sysemu/tcg.h" | ||
24 | #include "qapi/qapi-commands-machine-target.h" | ||
25 | #include "qapi/error.h" | ||
26 | #include "qemu/guest-random.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
28 | env->exception.syndrome); | ||
29 | } | ||
30 | |||
31 | - if (arm_is_psci_call(cpu, cs->exception_index)) { | ||
32 | + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { | ||
33 | arm_handle_psci_call(cpu); | ||
34 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | ||
35 | return; | ||
36 | -- | ||
37 | 2.34.1 | ||
38 | |||
39 | diff view generated by jsdifflib |
1 | From: Julian Brown <julian@codesourcery.com> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Since the integratorcp board creates the CPU object directly | 3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
4 | rather than via cpu_arm_init(), we have to call the CPU | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | class parse_features() method ourselves if we want to | 5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
6 | support the user passing features via the -cpu command | 6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | line argument as well as just the cpu name. Do so. | ||
8 | |||
9 | Signed-off-by: Julian Brown <julian@codesourcery.com> | ||
10 | [PMM: split out into its own patch] | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 8 | --- |
14 | hw/arm/integratorcp.c | 19 +++++++++++++++++-- | 9 | target/arm/helper.c | 12 +++++++----- |
15 | 1 file changed, 17 insertions(+), 2 deletions(-) | 10 | 1 file changed, 7 insertions(+), 5 deletions(-) |
16 | 11 | ||
17 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
18 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/integratorcp.c | 14 | --- a/target/arm/helper.c |
20 | +++ b/hw/arm/integratorcp.c | 15 | +++ b/target/arm/helper.c |
21 | @@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine) | 16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
22 | const char *kernel_filename = machine->kernel_filename; | 17 | unsigned int cur_el = arm_current_el(env); |
23 | const char *kernel_cmdline = machine->kernel_cmdline; | 18 | int rt; |
24 | const char *initrd_filename = machine->initrd_filename; | 19 | |
25 | + char **cpustr; | 20 | - /* |
26 | ObjectClass *cpu_oc; | 21 | - * Note that new_el can never be 0. If cur_el is 0, then |
27 | + CPUClass *cc; | 22 | - * el0_a64 is is_a64(), else el0_a64 is ignored. |
28 | Object *cpuobj; | 23 | - */ |
29 | ARMCPU *cpu; | 24 | - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
30 | + const char *typename; | 25 | + if (tcg_enabled()) { |
31 | MemoryRegion *address_space_mem = get_system_memory(); | 26 | + /* |
32 | MemoryRegion *ram = g_new(MemoryRegion, 1); | 27 | + * Note that new_el can never be 0. If cur_el is 0, then |
33 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); | 28 | + * el0_a64 is is_a64(), else el0_a64 is ignored. |
34 | qemu_irq pic[32]; | 29 | + */ |
35 | DeviceState *dev, *sic, *icp; | 30 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
36 | int i; | ||
37 | + Error *err = NULL; | ||
38 | |||
39 | if (!cpu_model) { | ||
40 | cpu_model = "arm926"; | ||
41 | } | ||
42 | |||
43 | - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); | ||
44 | + cpustr = g_strsplit(cpu_model, ",", 2); | ||
45 | + | ||
46 | + cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); | ||
47 | if (!cpu_oc) { | ||
48 | fprintf(stderr, "Unable to find CPU definition\n"); | ||
49 | exit(1); | ||
50 | } | ||
51 | + typename = object_class_get_name(cpu_oc); | ||
52 | + | ||
53 | + cc = CPU_CLASS(cpu_oc); | ||
54 | + cc->parse_features(typename, cpustr[1], &err); | ||
55 | + g_strfreev(cpustr); | ||
56 | + if (err) { | ||
57 | + error_report_err(err); | ||
58 | + exit(1); | ||
59 | + } | 31 | + } |
60 | 32 | ||
61 | - cpuobj = object_new(object_class_get_name(cpu_oc)); | 33 | if (cur_el < new_el) { |
62 | + cpuobj = object_new(typename); | 34 | /* |
63 | |||
64 | /* By default ARM1176 CPUs have EL3 enabled. This board does not | ||
65 | * currently support EL3 so the CPU EL3 property is disabled before | ||
66 | -- | 35 | -- |
67 | 2.7.4 | 36 | 2.34.1 |
68 | 37 | ||
69 | 38 | diff view generated by jsdifflib |
1 | Use the 'unimplemented' dummy device to cover regions of the | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | SoC device memory map which we don't have proper device | ||
3 | implementations for yet. | ||
4 | 2 | ||
3 | Move this earlier to make the next patch diff cleaner. While here | ||
4 | update the comment slightly to not give the impression that the | ||
5 | misalignment affects only TCG. | ||
6 | |||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org | ||
8 | --- | 12 | --- |
9 | hw/arm/stellaris.c | 14 ++++++++++++++ | 13 | target/arm/machine.c | 18 +++++++++--------- |
10 | 1 file changed, 14 insertions(+) | 14 | 1 file changed, 9 insertions(+), 9 deletions(-) |
11 | 15 | ||
12 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 16 | diff --git a/target/arm/machine.c b/target/arm/machine.c |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/stellaris.c | 18 | --- a/target/arm/machine.c |
15 | +++ b/hw/arm/stellaris.c | 19 | +++ b/target/arm/machine.c |
16 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
17 | #include "exec/address-spaces.h" | ||
18 | #include "sysemu/sysemu.h" | ||
19 | #include "hw/char/pl011.h" | ||
20 | +#include "hw/misc/unimp.h" | ||
21 | |||
22 | #define GPIO_A 0 | ||
23 | #define GPIO_B 1 | ||
24 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, | ||
25 | } | ||
26 | } | 21 | } |
27 | } | 22 | } |
23 | |||
24 | + /* | ||
25 | + * Misaligned thumb pc is architecturally impossible. Fail the | ||
26 | + * incoming migration. For TCG it would trigger the assert in | ||
27 | + * thumb_tr_translate_insn(). | ||
28 | + */ | ||
29 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
30 | + return -1; | ||
31 | + } | ||
28 | + | 32 | + |
29 | + /* Add dummy regions for the devices we don't implement yet, | 33 | hw_breakpoint_update_all(cpu); |
30 | + * so guest accesses don't cause unlogged crashes. | 34 | hw_watchpoint_update_all(cpu); |
31 | + */ | 35 | |
32 | + create_unimplemented_device("wdtimer", 0x40000000, 0x1000); | 36 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
33 | + create_unimplemented_device("i2c-0", 0x40002000, 0x1000); | 37 | } |
34 | + create_unimplemented_device("i2c-2", 0x40021000, 0x1000); | 38 | } |
35 | + create_unimplemented_device("PWM", 0x40028000, 0x1000); | 39 | |
36 | + create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); | 40 | - /* |
37 | + create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); | 41 | - * Misaligned thumb pc is architecturally impossible. |
38 | + create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); | 42 | - * We have an assert in thumb_tr_translate_insn to verify this. |
39 | + create_unimplemented_device("hibernation", 0x400fc000, 0x1000); | 43 | - * Fail an incoming migrate to avoid this assert. |
40 | + create_unimplemented_device("flash-control", 0x400fd000, 0x1000); | 44 | - */ |
41 | } | 45 | - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { |
42 | 46 | - return -1; | |
43 | /* FIXME: Figure out how to generate these from stellaris_boards. */ | 47 | - } |
48 | - | ||
49 | if (!kvm_enabled()) { | ||
50 | pmu_op_finish(&cpu->env); | ||
51 | } | ||
44 | -- | 52 | -- |
45 | 2.7.4 | 53 | 2.34.1 |
46 | 54 | ||
47 | 55 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Fabiano Rosas <farosas@suse.de> | |
2 | |||
3 | Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have | ||
4 | a cpregs.h header which is more suitable for this code. | ||
5 | |||
6 | Code moved verbatim. | ||
7 | |||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ | ||
15 | target/arm/cpu.h | 91 ----------------------------------------- | ||
16 | 2 files changed, 98 insertions(+), 91 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpregs.h | ||
21 | +++ b/target/arm/cpregs.h | ||
22 | @@ -XXX,XX +XXX,XX @@ enum { | ||
23 | ARM_CP_SME = 1 << 19, | ||
24 | }; | ||
25 | |||
26 | +/* | ||
27 | + * Interface for defining coprocessor registers. | ||
28 | + * Registers are defined in tables of arm_cp_reginfo structs | ||
29 | + * which are passed to define_arm_cp_regs(). | ||
30 | + */ | ||
31 | + | ||
32 | +/* | ||
33 | + * When looking up a coprocessor register we look for it | ||
34 | + * via an integer which encodes all of: | ||
35 | + * coprocessor number | ||
36 | + * Crn, Crm, opc1, opc2 fields | ||
37 | + * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
38 | + * or via MRRC/MCRR?) | ||
39 | + * non-secure/secure bank (AArch32 only) | ||
40 | + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
41 | + * (In this case crn and opc2 should be zero.) | ||
42 | + * For AArch64, there is no 32/64 bit size distinction; | ||
43 | + * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
44 | + * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
45 | + * to be easy to convert to and from the KVM encodings, and also | ||
46 | + * so that the hashtable can contain both AArch32 and AArch64 | ||
47 | + * registers (to allow for interprocessing where we might run | ||
48 | + * 32 bit code on a 64 bit core). | ||
49 | + */ | ||
50 | +/* | ||
51 | + * This bit is private to our hashtable cpreg; in KVM register | ||
52 | + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
53 | + * in the upper bits of the 64 bit ID. | ||
54 | + */ | ||
55 | +#define CP_REG_AA64_SHIFT 28 | ||
56 | +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
57 | + | ||
58 | +/* | ||
59 | + * To enable banking of coprocessor registers depending on ns-bit we | ||
60 | + * add a bit to distinguish between secure and non-secure cpregs in the | ||
61 | + * hashtable. | ||
62 | + */ | ||
63 | +#define CP_REG_NS_SHIFT 29 | ||
64 | +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
65 | + | ||
66 | +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
67 | + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
68 | + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
69 | + | ||
70 | +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
71 | + (CP_REG_AA64_MASK | \ | ||
72 | + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
73 | + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
74 | + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
75 | + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
76 | + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
77 | + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
78 | + | ||
79 | +/* | ||
80 | + * Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
81 | + * version used as a key for the coprocessor register hashtable | ||
82 | + */ | ||
83 | +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
84 | +{ | ||
85 | + uint32_t cpregid = kvmid; | ||
86 | + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
87 | + cpregid |= CP_REG_AA64_MASK; | ||
88 | + } else { | ||
89 | + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
90 | + cpregid |= (1 << 15); | ||
91 | + } | ||
92 | + | ||
93 | + /* | ||
94 | + * KVM is always non-secure so add the NS flag on AArch32 register | ||
95 | + * entries. | ||
96 | + */ | ||
97 | + cpregid |= 1 << CP_REG_NS_SHIFT; | ||
98 | + } | ||
99 | + return cpregid; | ||
100 | +} | ||
101 | + | ||
102 | +/* | ||
103 | + * Convert a truncated 32 bit hashtable key into the full | ||
104 | + * 64 bit KVM register ID. | ||
105 | + */ | ||
106 | +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
107 | +{ | ||
108 | + uint64_t kvmid; | ||
109 | + | ||
110 | + if (cpregid & CP_REG_AA64_MASK) { | ||
111 | + kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
112 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
113 | + } else { | ||
114 | + kvmid = cpregid & ~(1 << 15); | ||
115 | + if (cpregid & (1 << 15)) { | ||
116 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
117 | + } else { | ||
118 | + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
119 | + } | ||
120 | + } | ||
121 | + return kvmid; | ||
122 | +} | ||
123 | + | ||
124 | /* | ||
125 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
126 | * the AArch32 and AArch64 execution states this register is visible in. | ||
127 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/cpu.h | ||
130 | +++ b/target/arm/cpu.h | ||
131 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
132 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
133 | uint32_t cur_el, bool secure); | ||
134 | |||
135 | -/* Interface for defining coprocessor registers. | ||
136 | - * Registers are defined in tables of arm_cp_reginfo structs | ||
137 | - * which are passed to define_arm_cp_regs(). | ||
138 | - */ | ||
139 | - | ||
140 | -/* When looking up a coprocessor register we look for it | ||
141 | - * via an integer which encodes all of: | ||
142 | - * coprocessor number | ||
143 | - * Crn, Crm, opc1, opc2 fields | ||
144 | - * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
145 | - * or via MRRC/MCRR?) | ||
146 | - * non-secure/secure bank (AArch32 only) | ||
147 | - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
148 | - * (In this case crn and opc2 should be zero.) | ||
149 | - * For AArch64, there is no 32/64 bit size distinction; | ||
150 | - * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
151 | - * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
152 | - * to be easy to convert to and from the KVM encodings, and also | ||
153 | - * so that the hashtable can contain both AArch32 and AArch64 | ||
154 | - * registers (to allow for interprocessing where we might run | ||
155 | - * 32 bit code on a 64 bit core). | ||
156 | - */ | ||
157 | -/* This bit is private to our hashtable cpreg; in KVM register | ||
158 | - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
159 | - * in the upper bits of the 64 bit ID. | ||
160 | - */ | ||
161 | -#define CP_REG_AA64_SHIFT 28 | ||
162 | -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
163 | - | ||
164 | -/* To enable banking of coprocessor registers depending on ns-bit we | ||
165 | - * add a bit to distinguish between secure and non-secure cpregs in the | ||
166 | - * hashtable. | ||
167 | - */ | ||
168 | -#define CP_REG_NS_SHIFT 29 | ||
169 | -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
170 | - | ||
171 | -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
172 | - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
173 | - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
174 | - | ||
175 | -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
176 | - (CP_REG_AA64_MASK | \ | ||
177 | - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
178 | - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
179 | - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
180 | - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
181 | - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
182 | - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
183 | - | ||
184 | -/* Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
185 | - * version used as a key for the coprocessor register hashtable | ||
186 | - */ | ||
187 | -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
188 | -{ | ||
189 | - uint32_t cpregid = kvmid; | ||
190 | - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
191 | - cpregid |= CP_REG_AA64_MASK; | ||
192 | - } else { | ||
193 | - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
194 | - cpregid |= (1 << 15); | ||
195 | - } | ||
196 | - | ||
197 | - /* KVM is always non-secure so add the NS flag on AArch32 register | ||
198 | - * entries. | ||
199 | - */ | ||
200 | - cpregid |= 1 << CP_REG_NS_SHIFT; | ||
201 | - } | ||
202 | - return cpregid; | ||
203 | -} | ||
204 | - | ||
205 | -/* Convert a truncated 32 bit hashtable key into the full | ||
206 | - * 64 bit KVM register ID. | ||
207 | - */ | ||
208 | -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
209 | -{ | ||
210 | - uint64_t kvmid; | ||
211 | - | ||
212 | - if (cpregid & CP_REG_AA64_MASK) { | ||
213 | - kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
214 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
215 | - } else { | ||
216 | - kvmid = cpregid & ~(1 << 15); | ||
217 | - if (cpregid & (1 << 15)) { | ||
218 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
219 | - } else { | ||
220 | - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
221 | - } | ||
222 | - } | ||
223 | - return kvmid; | ||
224 | -} | ||
225 | - | ||
226 | /* Return the highest implemented Exception Level */ | ||
227 | static inline int arm_highest_el(CPUARMState *env) | ||
228 | { | ||
229 | -- | ||
230 | 2.34.1 | ||
231 | |||
232 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | If a test was tagged with the "accel" tag and the specified | ||
4 | accelerator it not present in the qemu binary, cancel the test. | ||
5 | |||
6 | We can now write tests without explicit calls to require_accelerator, | ||
7 | just the tag is enough. | ||
8 | |||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | tests/avocado/avocado_qemu/__init__.py | 4 ++++ | ||
15 | 1 file changed, 4 insertions(+) | ||
16 | |||
17 | diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/tests/avocado/avocado_qemu/__init__.py | ||
20 | +++ b/tests/avocado/avocado_qemu/__init__.py | ||
21 | @@ -XXX,XX +XXX,XX @@ def setUp(self): | ||
22 | |||
23 | super().setUp('qemu-system-') | ||
24 | |||
25 | + accel_required = self._get_unique_tag_val('accel') | ||
26 | + if accel_required: | ||
27 | + self.require_accelerator(accel_required) | ||
28 | + | ||
29 | self.machine = self.params.get('machine', | ||
30 | default=self._get_unique_tag_val('machine')) | ||
31 | |||
32 | -- | ||
33 | 2.34.1 | ||
34 | |||
35 | diff view generated by jsdifflib |
1 | Add a comment documenting the memory map of the SoC devices and which | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | are not implemented. | ||
3 | 2 | ||
3 | This allows the test to be skipped when TCG is not present in the QEMU | ||
4 | binary. | ||
5 | |||
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org | ||
6 | --- | 10 | --- |
7 | hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++ | 11 | tests/avocado/boot_linux_console.py | 1 + |
8 | 1 file changed, 34 insertions(+) | 12 | tests/avocado/reverse_debugging.py | 8 ++++++++ |
13 | 2 files changed, 9 insertions(+) | ||
9 | 14 | ||
10 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py |
11 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/hw/arm/stellaris.c | 17 | --- a/tests/avocado/boot_linux_console.py |
13 | +++ b/hw/arm/stellaris.c | 18 | +++ b/tests/avocado/boot_linux_console.py |
14 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, | 19 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self): |
15 | 0x40024000, 0x40025000, 0x40026000}; | 20 | |
16 | static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; | 21 | def test_aarch64_raspi3_atf(self): |
17 | 22 | """ | |
18 | + /* Memory map of SoC devices, from | 23 | + :avocado: tags=accel:tcg |
19 | + * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) | 24 | :avocado: tags=arch:aarch64 |
20 | + * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf | 25 | :avocado: tags=machine:raspi3b |
21 | + * | 26 | :avocado: tags=cpu:cortex-a53 |
22 | + * 40000000 wdtimer (unimplemented) | 27 | diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py |
23 | + * 40002000 i2c (unimplemented) | 28 | index XXXXXXX..XXXXXXX 100644 |
24 | + * 40004000 GPIO | 29 | --- a/tests/avocado/reverse_debugging.py |
25 | + * 40005000 GPIO | 30 | +++ b/tests/avocado/reverse_debugging.py |
26 | + * 40006000 GPIO | 31 | @@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None): |
27 | + * 40007000 GPIO | 32 | vm.shutdown() |
28 | + * 40008000 SSI | 33 | |
29 | + * 4000c000 UART | 34 | class ReverseDebugging_X86_64(ReverseDebugging): |
30 | + * 4000d000 UART | 35 | + """ |
31 | + * 4000e000 UART | 36 | + :avocado: tags=accel:tcg |
32 | + * 40020000 i2c | 37 | + """ |
33 | + * 40021000 i2c (unimplemented) | ||
34 | + * 40024000 GPIO | ||
35 | + * 40025000 GPIO | ||
36 | + * 40026000 GPIO | ||
37 | + * 40028000 PWM (unimplemented) | ||
38 | + * 4002c000 QEI (unimplemented) | ||
39 | + * 4002d000 QEI (unimplemented) | ||
40 | + * 40030000 gptimer | ||
41 | + * 40031000 gptimer | ||
42 | + * 40032000 gptimer | ||
43 | + * 40033000 gptimer | ||
44 | + * 40038000 ADC | ||
45 | + * 4003c000 analogue comparator (unimplemented) | ||
46 | + * 40048000 ethernet | ||
47 | + * 400fc000 hibernation module (unimplemented) | ||
48 | + * 400fd000 flash memory control (unimplemented) | ||
49 | + * 400fe000 system control | ||
50 | + */ | ||
51 | + | 38 | + |
52 | DeviceState *gpio_dev[7], *nvic; | 39 | REG_PC = 0x10 |
53 | qemu_irq gpio_in[7][8]; | 40 | REG_CS = 0x12 |
54 | qemu_irq gpio_out[7][8]; | 41 | def get_pc(self, g): |
42 | @@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self): | ||
43 | self.reverse_debugging() | ||
44 | |||
45 | class ReverseDebugging_AArch64(ReverseDebugging): | ||
46 | + """ | ||
47 | + :avocado: tags=accel:tcg | ||
48 | + """ | ||
49 | + | ||
50 | REG_PC = 32 | ||
51 | |||
52 | # unidentified gitlab timeout problem | ||
55 | -- | 53 | -- |
56 | 2.7.4 | 54 | 2.34.1 |
57 | 55 | ||
58 | 56 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a | ||
4 | KVM-only build the 'max' cpu. | ||
5 | |||
6 | Note that we cannot use 'host' here because the qtests can run without | ||
7 | any other accelerator (than qtest) and 'host' depends on KVM being | ||
8 | enabled. | ||
9 | |||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/arm/virt.c | 4 ++++ | ||
16 | 1 file changed, 4 insertions(+) | ||
17 | |||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/arm/virt.c | ||
21 | +++ b/hw/arm/virt.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
23 | mc->minimum_page_bits = 12; | ||
24 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; | ||
25 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | ||
26 | +#ifdef CONFIG_TCG | ||
27 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | ||
28 | +#else | ||
29 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); | ||
30 | +#endif | ||
31 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; | ||
32 | mc->kvm_type = virt_kvm_type; | ||
33 | assert(!mc->get_hotplug_handler); | ||
34 | -- | ||
35 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- | ||
9 | 1 file changed, 18 insertions(+), 10 deletions(-) | ||
10 | |||
11 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tests/qtest/arm-cpu-features.c | ||
14 | +++ b/tests/qtest/arm-cpu-features.c | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #define SVE_MAX_VQ 16 | ||
17 | |||
18 | #define MACHINE "-machine virt,gic-version=max -accel tcg " | ||
19 | -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " | ||
20 | +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " | ||
21 | #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ | ||
22 | " 'arguments': { 'type': 'full', " | ||
23 | #define QUERY_TAIL "}}" | ||
24 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | ||
25 | { | ||
26 | g_test_init(&argc, &argv, NULL); | ||
27 | |||
28 | - qtest_add_data_func("/arm/query-cpu-model-expansion", | ||
29 | - NULL, test_query_cpu_model_expansion); | ||
30 | + if (qtest_has_accel("tcg")) { | ||
31 | + qtest_add_data_func("/arm/query-cpu-model-expansion", | ||
32 | + NULL, test_query_cpu_model_expansion); | ||
33 | + } | ||
34 | + | ||
35 | + if (!g_str_equal(qtest_get_arch(), "aarch64")) { | ||
36 | + goto out; | ||
37 | + } | ||
38 | |||
39 | /* | ||
40 | * For now we only run KVM specific tests with AArch64 QEMU in | ||
41 | * order avoid attempting to run an AArch32 QEMU with KVM on | ||
42 | * AArch64 hosts. That won't work and isn't easy to detect. | ||
43 | */ | ||
44 | - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { | ||
45 | + if (qtest_has_accel("kvm")) { | ||
46 | /* | ||
47 | * This tests target the 'host' CPU type, so register it only if | ||
48 | * KVM is available. | ||
49 | */ | ||
50 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", | ||
51 | NULL, test_query_cpu_model_expansion_kvm); | ||
52 | - } | ||
53 | |||
54 | - if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
55 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
56 | - NULL, sve_tests_sve_max_vq_8); | ||
57 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
58 | - NULL, sve_tests_sve_off); | ||
59 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", | ||
60 | NULL, sve_tests_sve_off_kvm); | ||
61 | } | ||
62 | |||
63 | + if (qtest_has_accel("tcg")) { | ||
64 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
65 | + NULL, sve_tests_sve_max_vq_8); | ||
66 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
67 | + NULL, sve_tests_sve_off); | ||
68 | + } | ||
69 | + | ||
70 | +out: | ||
71 | return g_test_run(); | ||
72 | } | ||
73 | -- | ||
74 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | These tests set -accel tcg, so restrict them to when TCG is present. | ||
4 | |||
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
6 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | tests/qtest/meson.build | 4 ++-- | ||
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/tests/qtest/meson.build | ||
16 | +++ b/tests/qtest/meson.build | ||
17 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ | ||
18 | # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional | ||
19 | qtests_aarch64 = \ | ||
20 | (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ | ||
21 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ | ||
22 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ | ||
23 | + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ | ||
24 | + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ | ||
25 | (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ | ||
26 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ | ||
27 | ['arm-cpu-features', | ||
28 | -- | ||
29 | 2.34.1 | diff view generated by jsdifflib |