A random mix of items here, nothing very major.

The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:

Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207

for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:

stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)

target-arm:

* new "unimplemented" device for stubbing out devices in a

system model so accesses can be logged

* stellaris: document the SoC memory map

* arm: create instruction syndromes for AArch32 data aborts

* arm: Correctly handle watchpoints for BE32 CPUs

* Fix Thumb-1 BE32 execution and disassembly

* arm: Add cfgend parameter for ARM CPU selection

* sd: sdhci: check data length during dma_memory_read

* aspeed: add a watchdog controller

* integratorcp: adding vmstate for save/restore

Cédric Le Goater (2):

wdt: Add Aspeed watchdog device model

aspeed: add a watchdog controller

Julian Brown (4):

hw/arm/integratorcp: Support specifying features via -cpu

target/arm: Add cfgend parameter for ARM CPU selection.

Fix Thumb-1 BE32 execution and disassembly.

arm: Correctly handle watchpoints for BE32 CPUs

Pavel Dovgalyuk (1):

integratorcp: adding vmstate for save/restore

Peter Maydell (5):

target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode

target/arm: A32, T32: Create Instruction Syndromes for Data Aborts

stellaris: Document memory map and which SoC devices are unimplemented

hw/misc: New "unimplemented" sysbus device

stellaris: Use the 'unimplemented' device for parts we don't implement

Prasad J Pandit (1):

sd: sdhci: check data length during dma_memory_read

hw/misc/Makefile.objs | 2 +

hw/watchdog/Makefile.objs | 1 +

include/disas/bfd.h | 7 ++

include/hw/arm/aspeed_soc.h | 2 +

include/hw/misc/unimp.h | 39 +++++++

include/hw/watchdog/wdt_aspeed.h | 32 ++++++

include/qom/cpu.h | 3 +

target/arm/arm_ldst.h | 10 +-

target/arm/cpu.h | 7 ++

target/arm/internals.h | 5 +

target/arm/translate.h | 14 +++

disas.c | 1 +

exec.c | 1 +

hw/arm/aspeed_soc.c | 13 +++

hw/arm/integratorcp.c | 78 +++++++++++++-

hw/arm/stellaris.c | 48 +++++++++

hw/misc/unimp.c | 107 +++++++++++++++++++

hw/sd/sdhci.c | 2 +-

hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++

qom/cpu.c | 6 ++

target/arm/cpu.c | 39 +++++++

target/arm/op_helper.c | 22 ++++

target/arm/translate-a64.c | 14 ---

target/arm/translate.c | 193 ++++++++++++++++++++++++---------

24 files changed, 801 insertions(+), 70 deletions(-)

create mode 100644 include/hw/misc/unimp.h

create mode 100644 include/hw/watchdog/wdt_aspeed.h

create mode 100644 hw/misc/unimp.c

create mode 100644 hw/watchdog/wdt_aspeed.c

Create a new "unimplemented" sysbus device, which simply accepts

all read and write accesses, and implements them as read-as-zero,

write-ignored, with logging of the access as LOG_UNIMP.

This is useful for stubbing out bits of an SoC or board model

which haven't been written yet.

hw/misc/Makefile.objs | 2 +

include/hw/misc/unimp.h | 39 ++++++++++++++++++

hw/misc/unimp.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++

3 files changed, 148 insertions(+)

create mode 100644 include/hw/misc/unimp.h

create mode 100644 hw/misc/unimp.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o

common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o

common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o

+common-obj-y += unimp.o

+

obj-$(CONFIG_VMPORT) += vmport.o

# ARM devices

diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h

+++ b/include/hw/misc/unimp.h

+ * "Unimplemented" device

+ *

+ * Copyright Linaro Limited, 2017

+ * Written by Peter Maydell

+#ifndef HW_MISC_UNIMP_H

+#define HW_MISC_UNIMP_H

+#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"

+

+/**

+ * create_unimplemented_device: create and map a dummy device

+ * @name: name of the device for debug logging

+ * @base: base address of the device's MMIO region

+ * @size: size of the device's MMIO region

+ *

+ * This utility function creates and maps an instance of unimplemented-device,

+ * which is a dummy device which simply logs all guest accesses to

+ * it via the qemu_log LOG_UNIMP debug log.

+ * The device is mapped at priority -1000, which means that you can

+ * use it to cover a large region and then map other devices on top of it

+ * if necessary.

+ */

+static inline void create_unimplemented_device(const char *name,

+ hwaddr base,

+ hwaddr size)

+ DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);

+

+ qdev_prop_set_string(dev, "name", name);

+ qdev_prop_set_uint64(dev, "size", size);

+ qdev_init_nofail(dev);

+

+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);

+#endif

diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/unimp.c

@@ -XXX,XX +XXX,XX @@

+/* "Unimplemented" device

+ *

+ * This is a dummy device which accepts and logs all accesses.

+ * It's useful for stubbing out regions of an SoC or board

+ * map which correspond to devices that have not yet been

+ * implemented. This is often sufficient to placate initial

+ * guest device driver probing such that the system will

+ * come up.

+ *

+ * Copyright Linaro Limited, 2017

+ * Written by Peter Maydell

+ */

+#include "qemu/osdep.h"

+#include "hw/hw.h"

+#include "hw/sysbus.h"

+#include "hw/misc/unimp.h"

+#include "qemu/log.h"

+#include "qapi/error.h"

+#define UNIMPLEMENTED_DEVICE(obj) \

+ OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)

+typedef struct {

+ SysBusDevice parent_obj;

+ MemoryRegion iomem;

+ char *name;

+ uint64_t size;

+} UnimplementedDeviceState;

+static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)

+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);

+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "

+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",

+ s->name, size, offset);

+ return 0;

+

+static void unimp_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);

+

+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "

+ "(size %d, value 0x%" PRIx64

+ ", offset 0x%" HWADDR_PRIx ")\n",

+ s->name, size, value, offset);

+}

+

+static const MemoryRegionOps unimp_ops = {

+ .read = unimp_read,

+ .write = unimp_write,

+ .impl.min_access_size = 1,

+ .impl.max_access_size = 8,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 8,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+};

+

+static void unimp_realize(DeviceState *dev, Error **errp)

+{

+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);

+

+ if (s->size == 0) {

+ error_setg(errp, "property 'size' not specified or zero");

+ return;

+ }

+

+ if (s->name == NULL) {

+ error_setg(errp, "property 'name' not specified");

+ return;

+ }

+

+ memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,

+ s->name, s->size);

+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);

+}

+

+static Property unimp_properties[] = {

+ DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),

+ DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void unimp_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->realize = unimp_realize;

+ dc->props = unimp_properties;

+}

+

+static const TypeInfo unimp_info = {

+ .name = TYPE_UNIMPLEMENTED_DEVICE,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(UnimplementedDeviceState),

+ .class_init = unimp_class_init,

+};

+

+static void unimp_register_types(void)

+{

+ type_register_static(&unimp_info);

+}

+

+type_init(unimp_register_types)

2.7.4

From: Julian Brown <julian@codesourcery.com>

In BE32 mode, sub-word size watchpoints can fail to trigger because the

address of the access is adjusted in the opcode helpers before being

compared with the watchpoint registers. This patch reverses the address

adjustment before performing the comparison with the help of a new CPUClass

hook.

This version of the patch augments and tidies up comments a little.

Signed-off-by: Julian Brown <julian@codesourcery.com>

Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com

include/qom/cpu.h | 3 +++

target/arm/internals.h | 5 +++++

exec.c | 1 +

qom/cpu.c | 6 ++++++

target/arm/cpu.c | 3 +++

target/arm/op_helper.c | 22 ++++++++++++++++++++++

6 files changed, 40 insertions(+)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/include/qom/cpu.h

+++ b/include/qom/cpu.h

@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;

* @cpu_exec_exit: Callback for cpu_exec cleanup.

* @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.

* @disas_set_info: Setup architecture specific components of disassembly info

+ * @adjust_watchpoint_address: Perform a target-specific adjustment to an

+ * address before attempting to match it against watchpoints.

*

* Represents a CPU family or model.

*/

@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {

bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);

void (*disas_set_info)(CPUState *cpu, disassemble_info *info);

+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);

} CPUClass;

#ifdef HOST_WORDS_BIGENDIAN

diff --git a/target/arm/internals.h b/target/arm/internals.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/internals.h

+++ b/target/arm/internals.h

@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu);

/* Callback function for checking if a watchpoint should trigger. */

bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);

+/* Adjust addresses (in BE32 mode) before testing against watchpoint

+ * addresses.

+ */

+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);

+

/* Callback function for when a watchpoint or breakpoint triggers. */

void arm_debug_excp_handler(CPUState *cs);

diff --git a/exec.c b/exec.c

index XXXXXXX..XXXXXXX 100644

--- a/exec.c

+++ b/exec.c

@@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)

return;

+static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)

+{

+ return addr;

+}

+

static void cpu_class_init(ObjectClass *klass, void *data)

{

DeviceClass *dc = DEVICE_CLASS(klass);

@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)

k->cpu_exec_enter = cpu_common_noop;

k->cpu_exec_exit = cpu_common_noop;

k->cpu_exec_interrupt = cpu_common_exec_interrupt;

+ k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;

set_bit(DEVICE_CATEGORY_CPU, dc->categories);

dc->realize = cpu_common_realizefn;

dc->unrealize = cpu_common_unrealizefn;

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)

cc->gdb_stop_before_watchpoint = true;

cc->debug_excp_handler = arm_debug_excp_handler;

cc->debug_check_watchpoint = arm_debug_check_watchpoint;

+#if !defined(CONFIG_USER_ONLY)

+ cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;

+#endif

cc->disas_set_info = arm_disas_set_info;

}

@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)

return check_watchpoints(cpu);

}

+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)

+{

+ ARMCPU *cpu = ARM_CPU(cs);