A random mix of items here, nothing very major.

The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:

Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207

for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:

stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)

target-arm:

* new "unimplemented" device for stubbing out devices in a

system model so accesses can be logged

* stellaris: document the SoC memory map

* arm: create instruction syndromes for AArch32 data aborts

* arm: Correctly handle watchpoints for BE32 CPUs

* Fix Thumb-1 BE32 execution and disassembly

* arm: Add cfgend parameter for ARM CPU selection

* sd: sdhci: check data length during dma_memory_read

* aspeed: add a watchdog controller

* integratorcp: adding vmstate for save/restore

Cédric Le Goater (2):

wdt: Add Aspeed watchdog device model

aspeed: add a watchdog controller

Julian Brown (4):

hw/arm/integratorcp: Support specifying features via -cpu

target/arm: Add cfgend parameter for ARM CPU selection.

Fix Thumb-1 BE32 execution and disassembly.

arm: Correctly handle watchpoints for BE32 CPUs

Pavel Dovgalyuk (1):

integratorcp: adding vmstate for save/restore

Peter Maydell (5):

target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode

target/arm: A32, T32: Create Instruction Syndromes for Data Aborts

stellaris: Document memory map and which SoC devices are unimplemented

hw/misc: New "unimplemented" sysbus device

stellaris: Use the 'unimplemented' device for parts we don't implement

Prasad J Pandit (1):

sd: sdhci: check data length during dma_memory_read

hw/misc/Makefile.objs | 2 +

hw/watchdog/Makefile.objs | 1 +

include/disas/bfd.h | 7 ++

include/hw/arm/aspeed_soc.h | 2 +

include/hw/misc/unimp.h | 39 +++++++

include/hw/watchdog/wdt_aspeed.h | 32 ++++++

include/qom/cpu.h | 3 +

target/arm/arm_ldst.h | 10 +-

target/arm/cpu.h | 7 ++

target/arm/internals.h | 5 +

target/arm/translate.h | 14 +++

disas.c | 1 +

exec.c | 1 +

hw/arm/aspeed_soc.c | 13 +++

hw/arm/integratorcp.c | 78 +++++++++++++-

hw/arm/stellaris.c | 48 +++++++++

hw/misc/unimp.c | 107 +++++++++++++++++++

hw/sd/sdhci.c | 2 +-

hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++

qom/cpu.c | 6 ++

target/arm/cpu.c | 39 +++++++

target/arm/op_helper.c | 22 ++++

target/arm/translate-a64.c | 14 ---

target/arm/translate.c | 193 ++++++++++++++++++++++++---------

24 files changed, 801 insertions(+), 70 deletions(-)

create mode 100644 include/hw/misc/unimp.h

create mode 100644 include/hw/watchdog/wdt_aspeed.h

create mode 100644 hw/misc/unimp.c

create mode 100644 hw/watchdog/wdt_aspeed.c

From: Julian Brown <julian@codesourcery.com>

Thumb-1 code has some issues in BE32 mode (as currently implemented). In

short, since bytes are swapped within words at load time for BE32

executables, this also swaps pairs of adjacent Thumb-1 instructions.

This patch un-swaps those pairs of instructions again, both for execution,

and for disassembly. (The previous version of the patch always read four

bytes in arm_read_memory_func and then extracted the proper two bytes,

in a probably misguided attempt to match the behaviour of actual hardware

as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for

instruction fetches". It's less complicated to just read the correct

two bytes though.)

Signed-off-by: Julian Brown <julian@codesourcery.com>

Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com

include/disas/bfd.h | 7 +++++++

target/arm/arm_ldst.h | 10 +++++++++-

disas.c | 1 +

target/arm/cpu.c | 23 +++++++++++++++++++++++

4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/include/disas/bfd.h b/include/disas/bfd.h

--- a/include/disas/bfd.h

+++ b/include/disas/bfd.h

@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {

The bottom 16 bits are for the internal use of the disassembler. */

unsigned long flags;

#define INSN_HAS_RELOC    0x80000000

+#define INSN_ARM_BE32    0x00010000

PTR private_data;

/* Function used to get bytes to disassemble. MEMADDR is the

@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {

(bfd_vma memaddr, bfd_byte *myaddr, int length,

     struct disassemble_info *info);

+ /* A place to stash the real read_memory_func if read_memory_func wants to

+ do some funky address arithmetic or similar (e.g. for ARM BE32 mode). */

+ int (*read_memory_inner_func)

+ (bfd_vma memaddr, bfd_byte *myaddr, int length,

+ struct disassemble_info *info);

+

/* Function which should be called if we get an error that we can't

recover from. STATUS is the errno value from read_memory_func and

MEMADDR is the address that we were trying to read. INFO is a

diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/arm_ldst.h

+++ b/target/arm/arm_ldst.h

@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,

static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,

bool sctlr_b)

{

- uint16_t insn = cpu_lduw_code(env, addr);

+ uint16_t insn;

+#ifndef CONFIG_USER_ONLY

+ /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped

+ within each word. Undo that now. */

+ if (sctlr_b) {

+ addr ^= 2;

+ }

+#endif

+ insn = cpu_lduw_code(env, addr);

if (bswap_code(sctlr_b)) {

return bswap16(insn);

}

diff --git a/disas.c b/disas.c

index XXXXXXX..XXXXXXX 100644

--- a/disas.c

+++ b/disas.c

@@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,

s.cpu = cpu;

s.info.read_memory_func = target_read_memory;

+ s.info.read_memory_inner_func = NULL;

s.info.buffer_vma = code;

s.info.buffer_length = size;

s.info.print_address_func = generic_print_address;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)

return print_insn_arm(pc | 1, info);

}

+static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,

+ int length, struct disassemble_info *info)

+{

+ assert(info->read_memory_inner_func);

+ assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);

+

+ if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {

+ assert(info->endian == BFD_ENDIAN_LITTLE);

+ return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,

+ info);

+ } else {

+ return info->read_memory_inner_func(memaddr, b, length, info);

+ }

+}

+

static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)

{

ARMCPU *ac = ARM_CPU(cpu);

@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)

info->endian = BFD_ENDIAN_BIG;

#endif

}

+ if (info->read_memory_inner_func == NULL) {

+ info->read_memory_inner_func = info->read_memory_func;

+ info->read_memory_func = arm_read_memory_func;

+ }

+ info->flags &= ~INSN_ARM_BE32;

+ if (arm_sctlr_b(env)) {

+ info->flags |= INSN_ARM_BE32;

+ }

}

static void arm_cpu_initfn(Object *obj)

2.7.4

In the ARM ldr/str decode path, rather than directly testing

"insn & (1 << 21)" and "insn & (1 << 24)", abstract these

bits out into wbit and pbit local flags. (We will want to

do more tests against them to determine whether we need to

provide syndrome information.)

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

target/arm/translate.c | 9 ++++++---

1 file changed, 6 insertions(+), 3 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

} else {

int address_offset;

bool load = insn & (1 << 20);

+ bool wbit = insn & (1 << 21);

+ bool pbit = insn & (1 << 24);

bool doubleword = false;

/* Misc load/store */

rn = (insn >> 16) & 0xf;

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

}

addr = load_reg(s, rn);

- if (insn & (1 << 24))

+ if (pbit) {

gen_add_datah_offset(s, insn, 0, addr);

+ }

address_offset = 0;

if (doubleword) {

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

ensure correct behavior with overlapping index registers.

ldrd with base writeback is undefined if the

destination and index registers overlap. */

- if (!(insn & (1 << 24))) {

+ if (!pbit) {

gen_add_datah_offset(s, insn, address_offset, addr);

store_reg(s, rn, addr);

- } else if (insn & (1 << 21)) {

+ } else if (wbit) {

if (address_offset)

tcg_gen_addi_i32(addr, addr, address_offset);

store_reg(s, rn, addr);

2.7.4

Use the 'unimplemented' dummy device to cover regions of the

SoC device memory map which we don't have proper device

implementations for yet.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org

hw/arm/stellaris.c | 14 ++++++++++++++

1 file changed, 14 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@

#include "exec/address-spaces.h"

#include "sysemu/sysemu.h"

#include "hw/char/pl011.h"

+#include "hw/misc/unimp.h"

#define GPIO_A 0

#define GPIO_B 1

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,

}

}

+

+ /* Add dummy regions for the devices we don't implement yet,

+ * so guest accesses don't cause unlogged crashes.

+ */

+ create_unimplemented_device("wdtimer", 0x40000000, 0x1000);

+ create_unimplemented_device("i2c-0", 0x40002000, 0x1000);

+ create_unimplemented_device("i2c-2", 0x40021000, 0x1000);

+ create_unimplemented_device("PWM", 0x40028000, 0x1000);

+ create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);

+ create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);

+ create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);

+ create_unimplemented_device("hibernation", 0x400fc000, 0x1000);

+ create_unimplemented_device("flash-control", 0x400fd000, 0x1000);

}

/* FIXME: Figure out how to generate these from stellaris_boards. */

2.7.4

Create a new "unimplemented" sysbus device, which simply accepts

all read and write accesses, and implements them as read-as-zero,

write-ignored, with logging of the access as LOG_UNIMP.

This is useful for stubbing out bits of an SoC or board model

which haven't been written yet.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org

hw/misc/Makefile.objs | 2 +

include/hw/misc/unimp.h | 39 ++++++++++++++++++

hw/misc/unimp.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++

3 files changed, 148 insertions(+)

create mode 100644 include/hw/misc/unimp.h

create mode 100644 hw/misc/unimp.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o

common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o

common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o

+common-obj-y += unimp.o

+

obj-$(CONFIG_VMPORT) += vmport.o

# ARM devices

diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/unimp.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * "Unimplemented" device

+ *

+ * Copyright Linaro Limited, 2017

+ * Written by Peter Maydell

+ */

+

+#ifndef HW_MISC_UNIMP_H

+#define HW_MISC_UNIMP_H

+

+#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"

+

+/**

+ * create_unimplemented_device: create and map a dummy device

+ * @name: name of the device for debug logging

+ * @base: base address of the device's MMIO region

+ * @size: size of the device's MMIO region

+ *

+ * This utility function creates and maps an instance of unimplemented-device,

+ * which is a dummy device which simply logs all guest accesses to

+ * it via the qemu_log LOG_UNIMP debug log.

+ * The device is mapped at priority -1000, which means that you can

+ * use it to cover a large region and then map other devices on top of it

+ * if necessary.

+ */

+static inline void create_unimplemented_device(const char *name,

+ hwaddr base,

+ hwaddr size)

+{

+ DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);

+

+ qdev_prop_set_string(dev, "name", name);

+ qdev_prop_set_uint64(dev, "size", size);

+ qdev_init_nofail(dev);

+

+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);

+}

+

+#endif

diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/unimp.c

@@ -XXX,XX +XXX,XX @@

+/* "Unimplemented" device

+ *

+ * This is a dummy device which accepts and logs all accesses.

+ * It's useful for stubbing out regions of an SoC or board

+ * map which correspond to devices that have not yet been

+ * implemented. This is often sufficient to placate initial

+ * guest device driver probing such that the system will

+ * come up.

+ *

+ * Copyright Linaro Limited, 2017

+ * Written by Peter Maydell

+ */

+

+#include "qemu/osdep.h"

+#include "hw/hw.h"

+#include "hw/sysbus.h"

+#include "hw/misc/unimp.h"

+#include "qemu/log.h"

+#include "qapi/error.h"

+

+#define UNIMPLEMENTED_DEVICE(obj) \

+ OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)

+

+typedef struct {

+ SysBusDevice parent_obj;

+ MemoryRegion iomem;

+ char *name;

+ uint64_t size;

+} UnimplementedDeviceState;

+

+static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)

+{

+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);

+

+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "

+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",

+ s->name, size, offset);

+ return 0;

+}

+

+static void unimp_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);

+

+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "

+ "(size %d, value 0x%" PRIx64

+ ", offset 0x%" HWADDR_PRIx ")\n",

+ s->name, size, value, offset);

+}

+

+static const MemoryRegionOps unimp_ops = {

+ .read = unimp_read,

+ .write = unimp_write,

+ .impl.min_access_size = 1,

+ .impl.max_access_size = 8,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 8,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+};

+

+static void unimp_realize(DeviceState *dev, Error **errp)

+{

+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);

+

+ if (s->size == 0) {

+ error_setg(errp, "property 'size' not specified or zero");

+ return;

+ }

+

+ if (s->name == NULL) {

+ error_setg(errp, "property 'name' not specified");

+ return;

+ }

+

+ memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,

+ s->name, s->size);

+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);

+}

+

+static Property unimp_properties[] = {

+ DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),

+ DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void unimp_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->realize = unimp_realize;

+ dc->props = unimp_properties;

+}

+

+static const TypeInfo unimp_info = {

+ .name = TYPE_UNIMPLEMENTED_DEVICE,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(UnimplementedDeviceState),

+ .class_init = unimp_class_init,

+};

+

+static void unimp_register_types(void)

+{

+ type_register_static(&unimp_info);

+}

+

+type_init(unimp_register_types)

2.7.4

Add a comment documenting the memory map of the SoC devices and which

are not implemented.

Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org

hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++

1 file changed, 34 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,

0x40024000, 0x40025000, 0x40026000};

static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};

+ /* Memory map of SoC devices, from

+ * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)

+ * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf

+ *

+ * 40000000 wdtimer (unimplemented)

+ * 40002000 i2c (unimplemented)

+ * 40004000 GPIO

+ * 40005000 GPIO

+ * 40006000 GPIO

+ * 40007000 GPIO

+ * 40008000 SSI

+ * 4000c000 UART

+ * 4000d000 UART

+ * 4000e000 UART

+ * 40020000 i2c

+ * 40021000 i2c (unimplemented)

+ * 40024000 GPIO

+ * 40025000 GPIO

+ * 40026000 GPIO

+ * 40028000 PWM (unimplemented)

+ * 4002c000 QEI (unimplemented)

+ * 4002d000 QEI (unimplemented)

+ * 40030000 gptimer

+ * 40031000 gptimer

+ * 40032000 gptimer

+ * 40033000 gptimer

+ * 40038000 ADC

+ * 4003c000 analogue comparator (unimplemented)

+ * 40048000 ethernet

+ * 400fc000 hibernation module (unimplemented)

+ * 400fd000 flash memory control (unimplemented)

+ * 400fe000 system control

+ */

+

DeviceState *gpio_dev[7], *nvic;

qemu_irq gpio_in[7][8];

qemu_irq gpio_out[7][8];

2.7.4

From: Prasad J Pandit <pjp@fedoraproject.org>

hw/sd/sdhci.c | 2 +-

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c

--- a/hw/sd/sdhci.c

+++ b/hw/sd/sdhci.c

@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)

boundary_count -= block_size - begin;

}

dma_memory_read(&address_space_memory, s->sdmasysad,

- &s->fifo_buffer[begin], s->data_count);

+ &s->fifo_buffer[begin], s->data_count - begin);

s->sdmasysad += s->data_count - begin;

if (s->data_count == block_size) {

for (n = 0; n < block_size; n++) {

2.7.4

Add support for generating the ISS (Instruction Specific Syndrome)

for Data Abort exceptions taken from AArch32. These syndromes are

used by hypervisors for example to trap and emulate memory accesses.

This is the equivalent for AArch32 guests of the work done for AArch64

guests in commit aaa1f954d4cab243.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

target/arm/translate.h | 14 ++++

target/arm/translate-a64.c | 14 ----

target/arm/translate.c | 184 +++++++++++++++++++++++++++++++++------------

3 files changed, 149 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s)

? 3 : MAX(1, s->current_el);

+static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)

+ /* We don't need to save all of the syndrome so we mask and shift

+ * out unneeded bits to help the sleb128 encoder do a better job.

+ */

+ syn &= ARM_INSN_START_WORD2_MASK;

+ syn >>= ARM_INSN_START_WORD2_SHIFT;

+

+ /* We check and clear insn_start_idx to catch multiple updates. */

+ assert(s->insn_start_idx != 0);

+ tcg_set_insn_param(s->insn_start_idx, 2, syn);

+ s->insn_start_idx = 0;

/* target-specific extra values for is_jmp */

/* These instructions trap after executing, so the A32/T32 decoder must

* defer them until after the conditional execution state has been updated.

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)

}

}

-static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)

-{

- /* We don't need to save all of the syndrome so we mask and shift

- * out uneeded bits to help the sleb128 encoder do a better job.

- */

- syn &= ARM_INSN_START_WORD2_MASK;

- syn >>= ARM_INSN_START_WORD2_SHIFT;

-

- /* We check and clear insn_start_idx to catch multiple updates. */

- assert(s->insn_start_idx != 0);

- tcg_set_insn_param(s->insn_start_idx, 2, syn);

- s->insn_start_idx = 0;

-}

-

static void unallocated_encoding(DisasContext *s)

/* Unallocated and reserved encodings are uncategorized */

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)

a64_translate_init();

}

+/* Flags for the disas_set_da_iss info argument:

+ * lower bits hold the Rt register number, higher bits are flags.

+ */

+typedef enum ISSInfo {

+ ISSNone = 0,

+ ISSRegMask = 0x1f,

+ ISSInvalid = (1 << 5),

+ ISSIsAcqRel = (1 << 6),

+ ISSIsWrite = (1 << 7),

+ ISSIs16Bit = (1 << 8),

+} ISSInfo;

+

+/* Save the syndrome information for a Data Abort */

+static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)

+{

+ uint32_t syn;

+ int sas = memop & MO_SIZE;

+ bool sse = memop & MO_SIGN;

+ bool is_acqrel = issinfo & ISSIsAcqRel;

+ bool is_write = issinfo & ISSIsWrite;

+ bool is_16bit = issinfo & ISSIs16Bit;

+ int srt = issinfo & ISSRegMask;

+

+ if (issinfo & ISSInvalid) {

+ /* Some callsites want to conditionally provide ISS info,

+ * eg "only if this was not a writeback"

+ */

+ return;

+ }

+

+ if (srt == 15) {

+ /* For AArch32, insns where the src/dest is R15 never generate

+ * ISS information. Catching that here saves checking at all

+ * the call sites.

+ */

+ return;

+ }

+

+ syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,

+ 0, 0, 0, is_write, 0, is_16bit);

+ disas_set_insn_syndrome(s, syn);

+}

+

static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)

{

/* Return the mmu_idx to use for A32/T32 "unprivileged load/store"

@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \

TCGv_i32 a32, int index) \

{ \

gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \

+} \

+static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \

+ TCGv_i32 val, \

+ TCGv_i32 a32, int index, \

+ ISSInfo issinfo) \

+{ \

+ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \

+ disas_set_da_iss(s, OPC, issinfo); \

}

#define DO_GEN_ST(SUFF, OPC) \

@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \

TCGv_i32 a32, int index) \

{ \

gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \

+} \

+static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \

+ TCGv_i32 val, \

+ TCGv_i32 a32, int index, \

+ ISSInfo issinfo) \

+{ \

+ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \

+ disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \

}

static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

tmp = tcg_temp_new_i32();

switch (op1) {

case 0: /* lda */

- gen_aa32_ld32u(s, tmp, addr,

- get_mem_index(s));

+ gen_aa32_ld32u_iss(s, tmp, addr,

+ get_mem_index(s),

+ rd | ISSIsAcqRel);

break;

case 2: /* ldab */

- gen_aa32_ld8u(s, tmp, addr,

- get_mem_index(s));

+ gen_aa32_ld8u_iss(s, tmp, addr,

+ get_mem_index(s),

+ rd | ISSIsAcqRel);

break;

case 3: /* ldah */

- gen_aa32_ld16u(s, tmp, addr,

- get_mem_index(s));

+ gen_aa32_ld16u_iss(s, tmp, addr,

+ get_mem_index(s),

+ rd | ISSIsAcqRel);

break;

default:

abort();

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

tmp = load_reg(s, rm);

switch (op1) {

case 0: /* stl */

- gen_aa32_st32(s, tmp, addr,

- get_mem_index(s));

+ gen_aa32_st32_iss(s, tmp, addr,

+ get_mem_index(s),

+ rm | ISSIsAcqRel);

break;

case 2: /* stlb */

- gen_aa32_st8(s, tmp, addr,

- get_mem_index(s));

+ gen_aa32_st8_iss(s, tmp, addr,

+ get_mem_index(s),

+ rm | ISSIsAcqRel);

break;

case 3: /* stlh */

- gen_aa32_st16(s, tmp, addr,

- get_mem_index(s));

+ gen_aa32_st16_iss(s, tmp, addr,

+ get_mem_index(s),

+ rm | ISSIsAcqRel);

break;

default:

abort();

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

bool wbit = insn & (1 << 21);

bool pbit = insn & (1 << 24);

bool doubleword = false;

+ ISSInfo issinfo;

+

/* Misc load/store */

rn = (insn >> 16) & 0xf;

rd = (insn >> 12) & 0xf;

+ /* ISS not valid if writeback */

+ issinfo = (pbit & !wbit) ? rd : ISSInvalid;

+

if (!load && (sh & 2)) {

/* doubleword */

ARCH(5TE);

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

tmp = tcg_temp_new_i32();

switch (sh) {

case 1:

- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),

+ issinfo);

break;

case 2:

- gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),

+ issinfo);

break;

default:

case 3:

- gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),

+ issinfo);

break;

}

} else {

/* store */

tmp = load_reg(s, rd);

- gen_aa32_st16(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);

tcg_temp_free_i32(tmp);

}

/* Perform base writeback before the loaded value to

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

/* load */

tmp = tcg_temp_new_i32();

if (insn & (1 << 22)) {

- gen_aa32_ld8u(s, tmp, tmp2, i);

+ gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);

} else {

- gen_aa32_ld32u(s, tmp, tmp2, i);

+ gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);

}

} else {

/* store */

tmp = load_reg(s, rd);

if (insn & (1 << 22)) {

- gen_aa32_st8(s, tmp, tmp2, i);

+ gen_aa32_st8_iss(s, tmp, tmp2, i, rd);

} else {

- gen_aa32_st32(s, tmp, tmp2, i);

+ gen_aa32_st32_iss(s, tmp, tmp2, i, rd);

}

tcg_temp_free_i32(tmp);

}

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

tmp = tcg_temp_new_i32();

switch (op) {

case 0: /* ldab */

- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),

+ rs | ISSIsAcqRel);

break;

case 1: /* ldah */

- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),

+ rs | ISSIsAcqRel);

break;

case 2: /* lda */

- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),

+ rs | ISSIsAcqRel);

break;

default:

abort();

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

tmp = load_reg(s, rs);

switch (op) {

case 0: /* stlb */

- gen_aa32_st8(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),

+ rs | ISSIsAcqRel);

break;

case 1: /* stlh */

- gen_aa32_st16(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),

+ rs | ISSIsAcqRel);

break;

case 2: /* stl */

- gen_aa32_st32(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),

+ rs | ISSIsAcqRel);

break;

default:

abort();

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

int postinc = 0;

int writeback = 0;

int memidx;

+ ISSInfo issinfo;

+

if ((insn & 0x01100000) == 0x01000000) {

if (disas_neon_ls_insn(s, insn)) {

goto illegal_op;

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

}

}

}

+

+ issinfo = writeback ? ISSInvalid : rs;

+

if (insn & (1 << 20)) {

/* Load. */

tmp = tcg_temp_new_i32();

switch (op) {

case 0:

- gen_aa32_ld8u(s, tmp, addr, memidx);

+ gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);

break;

case 4:

- gen_aa32_ld8s(s, tmp, addr, memidx);

+ gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);

break;

case 1:

- gen_aa32_ld16u(s, tmp, addr, memidx);

+ gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);

break;

case 5:

- gen_aa32_ld16s(s, tmp, addr, memidx);

+ gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);

break;

case 2:

- gen_aa32_ld32u(s, tmp, addr, memidx);

+ gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);

break;

default:

tcg_temp_free_i32(tmp);

@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw

tmp = load_reg(s, rs);

switch (op) {

case 0:

- gen_aa32_st8(s, tmp, addr, memidx);

+ gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);

break;

case 1:

- gen_aa32_st16(s, tmp, addr, memidx);

+ gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);

break;

case 2:

- gen_aa32_st32(s, tmp, addr, memidx);

+ gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);

break;

default:

tcg_temp_free_i32(tmp);

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

addr = tcg_temp_new_i32();

tcg_gen_movi_i32(addr, val);

tmp = tcg_temp_new_i32();

- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),

+ rd | ISSIs16Bit);

tcg_temp_free_i32(addr);

store_reg(s, rd, tmp);

break;

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

switch (op) {

case 0: /* str */

- gen_aa32_st32(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 1: /* strh */

- gen_aa32_st16(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 2: /* strb */

- gen_aa32_st8(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 3: /* ldrsb */

- gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 4: /* ldr */

- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 5: /* ldrh */

- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 6: /* ldrb */

- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

case 7: /* ldrsh */

- gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

break;

}

if (op >= 3) { /* load */

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

if (insn & (1 << 11)) {

/* load */

tmp = tcg_temp_new_i32();

- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

store_reg(s, rd, tmp);

} else {

/* store */

tmp = load_reg(s, rd);

- gen_aa32_st8(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

tcg_temp_free_i32(tmp);

}

tcg_temp_free_i32(addr);

@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)

if (insn & (1 << 11)) {

/* load */

tmp = tcg_temp_new_i32();

- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));

+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

store_reg(s, rd, tmp);

} else {

/* store */

tmp = load_reg(s, rd);

- gen_aa32_st16(s, tmp, addr, get_mem_index(s));

+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);

tcg_temp_free_i32(tmp);