Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[PULL 00/21] target-arm queue
-A random mix of items here, nothing very major.
+Arm queue; not huge but I figured I might as well send it out since
 I've been doing code review today and there's no queue of unprocessed
 pullreqs...
 thanks
 -- PMM
+The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
-The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:
+  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
-  Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)
+are available in the Git repository at:
-are available in the git repository at:
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207
+for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
-for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:
+  ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
   stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)
 ----------------------------------------------------------------
-target-arm:
+target-arm queue:
- * new "unimplemented" device for stubbing out devices in a
+ * arm: Support emulation of ARMv8.4-TTST extension
-   system model so accesses can be logged
+ * arm: Update cpu.h ID register field definitions
- * stellaris: document the SoC memory map
+ * arm: Fix breakage of XScale instruction emulation
- * arm: create instruction syndromes for AArch32 data aborts
+ * hw/net/lan9118: Fix RX Status FIFO PEEK value
- * arm: Correctly handle watchpoints for BE32 CPUs
+ * npcm7xx: Add ADC and PWM emulation
- * Fix Thumb-1 BE32 execution and disassembly
+ * ui/cocoa: Make "open docs" help menu entry work again when binary
- * arm: Add cfgend parameter for ARM CPU selection
+   is run from the build tree
- * sd: sdhci: check data length during dma_memory_read
+ * ui/cocoa: Fix openFile: deprecation on Big Sur
- * aspeed: add a watchdog controller
+ * docs: Add qemu-storage-daemon(1) manpage to meson.build
- * integratorcp: adding vmstate for save/restore
+ * docs: Build and install all the docs in a single manual
 ----------------------------------------------------------------
-Cédric Le Goater (2):
+Hao Wu (6):
-      wdt: Add Aspeed watchdog device model
+      hw/misc: Add clock converter in NPCM7XX CLK module
-      aspeed: add a watchdog controller
+      hw/timer: Refactor NPCM7XX Timer to use CLK clock
       hw/adc: Add an ADC module for NPCM7XX
       hw/misc: Add a PWM module for NPCM7XX
       hw/misc: Add QTest for NPCM7XX PWM Module
       hw/*: Use type casting for SysBusDevice in NPCM7XX
-Julian Brown (4):
+Leif Lindholm (6):
-      hw/arm/integratorcp: Support specifying features via -cpu
+      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
-      target/arm: Add cfgend parameter for ARM CPU selection.
+      target/arm: make ARMCPU.clidr 64-bit
-      Fix Thumb-1 BE32 execution and disassembly.
+      target/arm: make ARMCPU.ctr 64-bit
-      arm: Correctly handle watchpoints for BE32 CPUs
+      target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
+      target/arm: add aarch64 ID register fields to cpu.h
-Pavel Dovgalyuk (1):
+      target/arm: add aarch32 ID register fields to cpu.h
       integratorcp: adding vmstate for save/restore
 Peter Maydell (5):
-      target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
+      docs: Add qemu-storage-daemon(1) manpage to meson.build
-      target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
+      docs: Build and install all the docs in a single manual
-      stellaris: Document memory map and which SoC devices are unimplemented
+      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
-      hw/misc: New "unimplemented" sysbus device
+      hw/net/lan9118: Fix RX Status FIFO PEEK value
-      stellaris: Use the 'unimplemented' device for parts we don't implement
+      hw/net/lan9118: Add symbolic constants for register offsets
-Prasad J Pandit (1):
+Roman Bolshakov (2):
-      sd: sdhci: check data length during dma_memory_read
+      ui/cocoa: Update path to docs in build tree
       ui/cocoa: Fix openFile: deprecation on Big Sur
- hw/misc/Makefile.objs            |   2 +
+Rémi Denis-Courmont (2):
- hw/watchdog/Makefile.objs        |   1 +
+      target/arm: ARMv8.4-TTST extension
- include/disas/bfd.h              |   7 ++
+      target/arm: enable Small Translation tables in max CPU
  include/hw/arm/aspeed_soc.h      |   2 +
  include/hw/misc/unimp.h          |  39 +++++++
  include/hw/watchdog/wdt_aspeed.h |  32 ++++++
  include/qom/cpu.h                |   3 +
  target/arm/arm_ldst.h            |  10 +-
  target/arm/cpu.h                 |   7 ++
  target/arm/internals.h           |   5 +
  target/arm/translate.h           |  14 +++
  disas.c                          |   1 +
  exec.c                           |   1 +
  hw/arm/aspeed_soc.c              |  13 +++
  hw/arm/integratorcp.c            |  78 +++++++++++++-
  hw/arm/stellaris.c               |  48 +++++++++
  hw/misc/unimp.c                  | 107 +++++++++++++++++++
  hw/sd/sdhci.c                    |   2 +-
  hw/watchdog/wdt_aspeed.c         | 225 +++++++++++++++++++++++++++++++++++++++
  qom/cpu.c                        |   6 ++
  target/arm/cpu.c                 |  39 +++++++
  target/arm/op_helper.c           |  22 ++++
  target/arm/translate-a64.c       |  14 ---
  target/arm/translate.c           | 193 ++++++++++++++++++++++++---------
 files changed, 801 insertions(+), 70 deletions(-)
  create mode 100644 include/hw/misc/unimp.h
  create mode 100644 include/hw/watchdog/wdt_aspeed.h
  create mode 100644 hw/misc/unimp.c
  create mode 100644 hw/watchdog/wdt_aspeed.c
+ docs/conf.py                     |  46 ++-
+ docs/devel/conf.py               |  15 -
+ docs/index.html.in               |  17 -
+ docs/interop/conf.py             |  28 --
+ docs/meson.build                 |  65 ++--
+ docs/specs/conf.py               |  16 -
+ docs/system/arm/nuvoton.rst      |   4 +-
+ docs/system/conf.py              |  28 --
+ docs/tools/conf.py               |  37 --
+ docs/user/conf.py                |  15 -
+ meson.build                      |   1 +
+ hw/adc/trace.h                   |   1 +
+ include/hw/adc/npcm7xx_adc.h     |  69 ++++
+ include/hw/arm/npcm7xx.h         |   4 +
+ include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
+ include/hw/misc/npcm7xx_pwm.h    | 105 +++++
+ include/hw/timer/npcm7xx_timer.h |   1 +
+ target/arm/cpu.h                 |  85 ++++-
+ hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
+ hw/arm/npcm7xx.c                 |  55 ++-
+ hw/arm/npcm7xx_boards.c          |   2 +-
+ hw/mem/npcm7xx_mc.c              |   2 +-
+ hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
+ hw/misc/npcm7xx_gcr.c            |   2 +-
+ hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
+ hw/misc/npcm7xx_rng.c            |   2 +-
+ hw/net/lan9118.c                 |  26 +-
+ hw/nvram/npcm7xx_otp.c           |   2 +-
+ hw/ssi/npcm7xx_fiu.c             |   2 +-
+ hw/timer/npcm7xx_timer.c         |  39 +-
+ target/arm/cpu64.c               |   1 +
+ target/arm/helper.c              |  15 +-
+ target/arm/translate.c           |   7 +
+ tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
+ tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
+ hw/adc/meson.build               |   1 +
+ hw/adc/trace-events              |   5 +
+ hw/misc/meson.build              |   1 +
+ hw/misc/trace-events             |   6 +
+ tests/qtest/meson.build          |   4 +-
+ ui/cocoa.m                       |   7 +-
+files changed, 3124 insertions(+), 263 deletions(-)
+ delete mode 100644 docs/devel/conf.py
+ delete mode 100644 docs/index.html.in
+ delete mode 100644 docs/interop/conf.py
+ delete mode 100644 docs/specs/conf.py
+ delete mode 100644 docs/system/conf.py
+ delete mode 100644 docs/tools/conf.py
+ delete mode 100644 docs/user/conf.py
+ create mode 100644 hw/adc/trace.h
+ create mode 100644 include/hw/adc/npcm7xx_adc.h
+ create mode 100644 include/hw/misc/npcm7xx_pwm.h
+ create mode 100644 hw/adc/npcm7xx_adc.c
+ create mode 100644 hw/misc/npcm7xx_pwm.c
+ create mode 100644 tests/qtest/npcm7xx_adc-test.c
+ create mode 100644 tests/qtest/npcm7xx_pwm-test.c
+ create mode 100644 hw/adc/trace-events

-[Qemu-devel] [PULL 08/13] arm: Correctly handle watchpoints for BE32 CPUs
+[PULL 01/21] target/arm: ARMv8.4-TTST extension
-From: Julian Brown <julian@codesourcery.com>
+From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
-In BE32 mode, sub-word size watchpoints can fail to trigger because the
+This adds for the Small Translation tables extension in AArch64 state.
 address of the access is adjusted in the opcode helpers before being
 compared with the watchpoint registers.  This patch reverses the address
 adjustment before performing the comparison with the help of a new CPUClass
 hook.
-This version of the patch augments and tidies up comments a little.
+Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Julian Brown <julian@codesourcery.com>
 Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/qom/cpu.h      |  3 +++
+ target/arm/cpu.h    |  5 +++++
- target/arm/internals.h |  5 +++++
+ target/arm/helper.c | 15 +++++++++++++--
- exec.c                 |  1 +
+files changed, 18 insertions(+), 2 deletions(-)
  qom/cpu.c              |  6 ++++++
  target/arm/cpu.c       |  3 +++
  target/arm/op_helper.c | 22 ++++++++++++++++++++++
 files changed, 40 insertions(+)
-diff --git a/include/qom/cpu.h b/include/qom/cpu.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/qom/cpu.h
+--- a/target/arm/cpu.h
-+++ b/include/qom/cpu.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
-  * @cpu_exec_exit: Callback for cpu_exec cleanup.
+     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
   * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
   * @disas_set_info: Setup architecture specific components of disassembly info
 + * @adjust_watchpoint_address: Perform a target-specific adjustment to an
 + * address before attempting to match it against watchpoints.
   *
   * Represents a CPU family or model.
   */
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
      bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
      void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
 +    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
  } CPUClass;
  #ifdef HOST_WORDS_BIGENDIAN
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu);
  /* Callback function for checking if a watchpoint should trigger. */
  bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 +/* Adjust addresses (in BE32 mode) before testing against watchpoint
 + * addresses.
 + */
 +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
 +
  /* Callback function for when a watchpoint or breakpoint triggers. */
  void arm_debug_excp_handler(CPUState *cs);
 diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/exec.c
 +++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
          return;
      }
      vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
 +    vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
      QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
          if (cpu_watchpoint_address_matches(wp, vaddr, len)
              && (wp->flags & flags)) {
 diff --git a/qom/cpu.c b/qom/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/qom/cpu.c
 +++ b/qom/cpu.c
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
      return cpu->cpu_index;
  }
-+static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
++static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
 +{
-+    return addr;
++    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
 +}
 +
- static void cpu_class_init(ObjectClass *klass, void *data)
+ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
  {
-     DeviceClass *dc = DEVICE_CLASS(klass);
+     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
-@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
      k->cpu_exec_enter = cpu_common_noop;
      k->cpu_exec_exit = cpu_common_noop;
      k->cpu_exec_interrupt = cpu_common_exec_interrupt;
 +    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
      set_bit(DEVICE_CATEGORY_CPU, dc->categories);
      dc->realize = cpu_common_realizefn;
      dc->unrealize = cpu_common_unrealizefn;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/helper.c
-+++ b/target/arm/cpu.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
-     cc->gdb_stop_before_watchpoint = true;
+ {
-     cc->debug_excp_handler = arm_debug_excp_handler;
+     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
-     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
+     bool epd, hpd, using16k, using64k;
-+#if !defined(CONFIG_USER_ONLY)
+-    int select, tsz, tbi;
-+    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
++    int select, tsz, tbi, max_tsz;
-+#endif
+     if (!regime_has_2_ranges(mmu_idx)) {
-     cc->disas_set_info = arm_disas_set_info;
+         select = 0;
- }
+@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
-diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
+             hpd = extract64(tcr, 42, 1);
-index XXXXXXX..XXXXXXX 100644
+         }
---- a/target/arm/op_helper.c
+     }
-+++ b/target/arm/op_helper.c
+-    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
      return check_watchpoints(cpu);
  }
 +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +
-+    /* In BE32 system mode, target memory is stored byteswapped (on a
++    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
-+     * little-endian host system), and by the time we reach here (via an
++        max_tsz = 48 - using64k;
-+     * opcode helper) the addresses of subword accesses have been adjusted
++    } else {
-+     * to account for that, which means that watchpoints will not match.
++        max_tsz = 39;
 +     * Undo the adjustment here.
 +     */
 +    if (arm_sctlr_b(env)) {
 +        if (len == 1) {
 +            addr ^= 3;
 +        } else if (len == 2) {
 +            addr ^= 2;
 +        }
 +    }
 +
-+    return addr;
++    tsz = MIN(tsz, max_tsz);
-+}
+     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
      /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
          if (!aarch64 || stride == 9) {
              /* AArch32 or 4KB pages */
              startlevel = 2 - sl0;
 +
- void arm_debug_excp_handler(CPUState *cs)
++            if (cpu_isar_feature(aa64_st, cpu)) {
- {
++                startlevel &= 3;
-     /* Called by core code when a watchpoint or breakpoint fires;
++            }
          } else {
              /* 16KB or 64KB pages */
              startlevel = 3 - sl0;
 --
-.7.4
+.20.1

-New patch
+[PULL 02/21] target/arm: enable Small Translation tables in max CPU
+From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu64.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu64.c
++++ b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+         t = cpu->isar.id_aa64mmfr2;
+         t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
+         t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
++        t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
+         cpu->isar.id_aa64mmfr2 = t;
+         /* Replicate the same data to the 32-bit id registers.  */
+--
+.20.1

-New patch
+[PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name
+From: Leif Lindholm <leif@nuviainc.com>
+SBSS -> SSBS
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-2-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
+ FIELD(ID_AA64PFR0, SVE, 32, 4)
+ FIELD(ID_AA64PFR1, BT, 0, 4)
+-FIELD(ID_AA64PFR1, SBSS, 4, 4)
++FIELD(ID_AA64PFR1, SSBS, 4, 4)
+ FIELD(ID_AA64PFR1, MTE, 8, 4)
+ FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+--
+.20.1

-New patch
+[PULL 04/21] target/arm: make ARMCPU.clidr 64-bit
+From: Leif Lindholm <leif@nuviainc.com>
+The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
+, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
+Extend the clidr field to be able to hold this context.
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-3-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+     uint32_t id_afr0;
+     uint64_t id_aa64afr0;
+     uint64_t id_aa64afr1;
+-    uint32_t clidr;
++    uint64_t clidr;
+     uint64_t mp_affinity; /* MP ID without feature bits */
+     /* The elements of this array are the CCSIDR values for each cache,
+      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
+--
+.20.1

-[Qemu-devel] [PULL 06/13] target/arm: Add cfgend parameter for ARM CPU selection.
+[PULL 05/21] target/arm: make ARMCPU.ctr 64-bit
-From: Julian Brown <julian@codesourcery.com>
+From: Leif Lindholm <leif@nuviainc.com>
-Add a new "cfgend" property which selects whether the CPU resets into
+When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
-big-endian mode or not.  This setting affects whether we reset with
+TminLine field in bits [37:32].
-SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set.
+Extend the ctr field to be able to hold this context.
-Signed-off-by: Julian Brown <julian@codesourcery.com>
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
-Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com
+Reviewed-by: Hao Wu <wuhaotsh@google.com>
-[PMM: use error_report_err() rather than error_report();
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- move the integratorcp changes to their own patch;
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
- drop an unnecessary extra #include;
+Message-id: 20210108185154.8108-4-leif@nuviainc.com
  rephrase commit message accordingly;
  move setting of reset_sctlr above registration of cpregs
  so it actually has an effect]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h |  7 +++++++
+ target/arm/cpu.h | 2 +-
- target/arm/cpu.c | 13 +++++++++++++
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 20 insertions(+)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
 @@ -XXX,XX +XXX,XX @@ struct ARMCPU {
-     int gic_vpribits; /* number of virtual priority bits */
+     uint64_t midr;
-     int gic_vprebits; /* number of virtual preemption bits */
+     uint32_t revidr;
+     uint32_t reset_fpsid;
-+    /* Whether the cfgend input is high (i.e. this CPU should reset into
+-    uint32_t ctr;
-+     * big-endian mode).  This setting isn't used directly: instead it modifies
++    uint64_t ctr;
-+     * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
+     uint32_t reset_sctlr;
-+     * architecture version.
+     uint64_t pmceid0;
-+     */
+     uint64_t pmceid1;
 +    bool cfgend;
 +
      ARMELChangeHook *el_change_hook;
      void *el_change_hook_opaque;
  };
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el2_property =
  static Property arm_cpu_has_el3_property =
              DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 +static Property arm_cpu_cfgend_property =
 +            DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 +
  /* use property name "pmu" to match other archs and virt tools */
  static Property arm_cpu_has_pmu_property =
              DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
          }
      }
 +    qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
 +                             &error_abort);
  }
  static void arm_cpu_finalizefn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
              cpu->reset_sctlr |= (1 << 13);
      }
 +    if (cpu->cfgend) {
 +        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 +            cpu->reset_sctlr |= SCTLR_EE;
 +        } else {
 +            cpu->reset_sctlr |= SCTLR_B;
 +        }
 +    }
 +
      if (!cpu->has_el3) {
          /* If the has_el3 CPU property is disabled then we need to disable the
           * feature.
 --
-.7.4
+.20.1

-New patch
+[PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
+From: Leif Lindholm <leif@nuviainc.com>
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-5-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
+file changed, 31 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
+ /*
+  * System register ID fields.
+  */
++FIELD(CLIDR_EL1, CTYPE1, 0, 3)
++FIELD(CLIDR_EL1, CTYPE2, 3, 3)
++FIELD(CLIDR_EL1, CTYPE3, 6, 3)
++FIELD(CLIDR_EL1, CTYPE4, 9, 3)
++FIELD(CLIDR_EL1, CTYPE5, 12, 3)
++FIELD(CLIDR_EL1, CTYPE6, 15, 3)
++FIELD(CLIDR_EL1, CTYPE7, 18, 3)
++FIELD(CLIDR_EL1, LOUIS, 21, 3)
++FIELD(CLIDR_EL1, LOC, 24, 3)
++FIELD(CLIDR_EL1, LOUU, 27, 3)
++FIELD(CLIDR_EL1, ICB, 30, 3)
++
++/* When FEAT_CCIDX is implemented */
++FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
++FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
++FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
++
++/* When FEAT_CCIDX is not implemented */
++FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
++FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
++FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
++
++FIELD(CTR_EL0,  IMINLINE, 0, 4)
++FIELD(CTR_EL0,  L1IP, 14, 2)
++FIELD(CTR_EL0,  DMINLINE, 16, 4)
++FIELD(CTR_EL0,  ERG, 20, 4)
++FIELD(CTR_EL0,  CWG, 24, 4)
++FIELD(CTR_EL0,  IDC, 28, 1)
++FIELD(CTR_EL0,  DIC, 29, 1)
++FIELD(CTR_EL0,  TMINLINE, 32, 6)
++
+ FIELD(MIDR_EL1, REVISION, 0, 4)
+ FIELD(MIDR_EL1, PARTNUM, 4, 12)
+ FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
+--
+.20.1

-New patch
+[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h
+From: Leif Lindholm <leif@nuviainc.com>
+Add entries present in ARM DDI 0487F.c (August 2020).
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-6-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 15 +++++++++++++++
+file changed, 15 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
+ FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
+ FIELD(ID_AA64ISAR1, SB, 36, 4)
+ FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
++FIELD(ID_AA64ISAR1, BF16, 44, 4)
++FIELD(ID_AA64ISAR1, DGH, 48, 4)
++FIELD(ID_AA64ISAR1, I8MM, 52, 4)
+ FIELD(ID_AA64PFR0, EL0, 0, 4)
+ FIELD(ID_AA64PFR0, EL1, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
+ FIELD(ID_AA64PFR0, GIC, 24, 4)
+ FIELD(ID_AA64PFR0, RAS, 28, 4)
+ FIELD(ID_AA64PFR0, SVE, 32, 4)
++FIELD(ID_AA64PFR0, SEL2, 36, 4)
++FIELD(ID_AA64PFR0, MPAM, 40, 4)
++FIELD(ID_AA64PFR0, AMU, 44, 4)
++FIELD(ID_AA64PFR0, DIT, 48, 4)
++FIELD(ID_AA64PFR0, CSV2, 56, 4)
++FIELD(ID_AA64PFR0, CSV3, 60, 4)
+ FIELD(ID_AA64PFR1, BT, 0, 4)
+ FIELD(ID_AA64PFR1, SSBS, 4, 4)
+ FIELD(ID_AA64PFR1, MTE, 8, 4)
+ FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
++FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
+ FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
+ FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
+ FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
+ FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
+ FIELD(ID_AA64MMFR0, EXS, 44, 4)
++FIELD(ID_AA64MMFR0, FGT, 56, 4)
++FIELD(ID_AA64MMFR0, ECV, 60, 4)
+ FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
+ FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
+ FIELD(ID_AA64MMFR1, PAN, 20, 4)
+ FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
+ FIELD(ID_AA64MMFR1, XNX, 28, 4)
++FIELD(ID_AA64MMFR1, TWED, 32, 4)
++FIELD(ID_AA64MMFR1, ETS, 36, 4)
+ FIELD(ID_AA64MMFR2, CNP, 0, 4)
+ FIELD(ID_AA64MMFR2, UAO, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
+ FIELD(ID_AA64DFR0, PMSVER, 32, 4)
+ FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
+ FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
++FIELD(ID_AA64DFR0, MTPMU, 48, 4)
+ FIELD(ID_DFR0, COPDBG, 0, 4)
+ FIELD(ID_DFR0, COPSDBG, 4, 4)
+--
+.20.1

-New patch
+[PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h
+From: Leif Lindholm <leif@nuviainc.com>
+Add entries present in ARM DDI 0487F.c (August 2020).
+Signed-off-by: Leif Lindholm <leif@nuviainc.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Message-id: 20210108185154.8108-7-leif@nuviainc.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
+file changed, 28 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
+ FIELD(ID_ISAR6, FHM, 8, 4)
+ FIELD(ID_ISAR6, SB, 12, 4)
+ FIELD(ID_ISAR6, SPECRES, 16, 4)
++FIELD(ID_ISAR6, BF16, 20, 4)
++FIELD(ID_ISAR6, I8MM, 24, 4)
+ FIELD(ID_MMFR0, VMSA, 0, 4)
+ FIELD(ID_MMFR0, PMSA, 4, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
+ FIELD(ID_MMFR0, FCSE, 24, 4)
+ FIELD(ID_MMFR0, INNERSHR, 28, 4)
++FIELD(ID_MMFR1, L1HVDVA, 0, 4)
++FIELD(ID_MMFR1, L1UNIVA, 4, 4)
++FIELD(ID_MMFR1, L1HVDSW, 8, 4)
++FIELD(ID_MMFR1, L1UNISW, 12, 4)
++FIELD(ID_MMFR1, L1HVD, 16, 4)
++FIELD(ID_MMFR1, L1UNI, 20, 4)
++FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
++FIELD(ID_MMFR1, BPRED, 28, 4)
++
++FIELD(ID_MMFR2, L1HVDFG, 0, 4)
++FIELD(ID_MMFR2, L1HVDBG, 4, 4)
++FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
++FIELD(ID_MMFR2, HVDTLB, 12, 4)
++FIELD(ID_MMFR2, UNITLB, 16, 4)
++FIELD(ID_MMFR2, MEMBARR, 20, 4)
++FIELD(ID_MMFR2, WFISTALL, 24, 4)
++FIELD(ID_MMFR2, HWACCFLG, 28, 4)
++
+ FIELD(ID_MMFR3, CMAINTVA, 0, 4)
+ FIELD(ID_MMFR3, CMAINTSW, 4, 4)
+ FIELD(ID_MMFR3, BPMAINT, 8, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
+ FIELD(ID_MMFR4, CCIDX, 24, 4)
+ FIELD(ID_MMFR4, EVT, 28, 4)
++FIELD(ID_MMFR5, ETS, 0, 4)
++
+ FIELD(ID_PFR0, STATE0, 0, 4)
+ FIELD(ID_PFR0, STATE1, 4, 4)
+ FIELD(ID_PFR0, STATE2, 8, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
+ FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
+ FIELD(ID_PFR1, GIC, 28, 4)
++FIELD(ID_PFR2, CSV3, 0, 4)
++FIELD(ID_PFR2, SSBS, 4, 4)
++FIELD(ID_PFR2, RAS_FRAC, 8, 4)
++
+ FIELD(ID_AA64ISAR0, AES, 4, 4)
+ FIELD(ID_AA64ISAR0, SHA1, 8, 4)
+ FIELD(ID_AA64ISAR0, SHA2, 12, 4)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
+ FIELD(ID_DFR0, PERFMON, 24, 4)
+ FIELD(ID_DFR0, TRACEFILT, 28, 4)
++FIELD(ID_DFR1, MTPMU, 0, 4)
++
+ FIELD(DBGDIDR, SE_IMP, 12, 1)
+ FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
+ FIELD(DBGDIDR, VERSION, 16, 4)
+--
+.20.1

-[Qemu-devel] [PULL 07/13] Fix Thumb-1 BE32 execution and disassembly.
+[PULL 09/21] ui/cocoa: Update path to docs in build tree
-From: Julian Brown <julian@codesourcery.com>
+From: Roman Bolshakov <r.bolshakov@yadro.com>
-Thumb-1 code has some issues in BE32 mode (as currently implemented). In
+QEMU documentation can't be opened if QEMU is run from build tree
-short, since bytes are swapped within words at load time for BE32
+because executables are placed in the top of build tree after conversion
-executables, this also swaps pairs of adjacent Thumb-1 instructions.
+to meson.
-This patch un-swaps those pairs of instructions again, both for execution,
+Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
-and for disassembly. (The previous version of the patch always read four
+Reported-by: Peter Maydell <peter.maydell@linaro.org>
-bytes in arm_read_memory_func and then extracted the proper two bytes,
+Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
 in a probably misguided attempt to match the behaviour of actual hardware
 as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for
 instruction fetches". It's less complicated to just read the correct
 two bytes though.)
 Signed-off-by: Julian Brown <julian@codesourcery.com>
 Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/disas/bfd.h   |  7 +++++++
+ ui/cocoa.m | 2 +-
- target/arm/arm_ldst.h | 10 +++++++++-
+file changed, 1 insertion(+), 1 deletion(-)
  disas.c               |  1 +
  target/arm/cpu.c      | 23 +++++++++++++++++++++++
 files changed, 40 insertions(+), 1 deletion(-)
-diff --git a/include/disas/bfd.h b/include/disas/bfd.h
+diff --git a/ui/cocoa.m b/ui/cocoa.m
 index XXXXXXX..XXXXXXX 100644
---- a/include/disas/bfd.h
+--- a/ui/cocoa.m
-+++ b/include/disas/bfd.h
++++ b/ui/cocoa.m
-@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-      The bottom 16 bits are for the internal use of the disassembler.  */
+ - (void) openDocumentation: (NSString *) filename
    unsigned long flags;
  #define INSN_HAS_RELOC    0x80000000
 +#define INSN_ARM_BE32    0x00010000
    PTR private_data;
    /* Function used to get bytes to disassemble.  MEMADDR is the
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
      (bfd_vma memaddr, bfd_byte *myaddr, int length,
           struct disassemble_info *info);
 +  /* A place to stash the real read_memory_func if read_memory_func wants to
 +     do some funky address arithmetic or similar (e.g. for ARM BE32 mode).  */
 +  int (*read_memory_inner_func)
 +    (bfd_vma memaddr, bfd_byte *myaddr, int length,
 +             struct disassemble_info *info);
 +
    /* Function which should be called if we get an error that we can't
       recover from.  STATUS is the errno value from read_memory_func and
       MEMADDR is the address that we were trying to read.  INFO is a
 diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/arm_ldst.h
 +++ b/target/arm/arm_ldst.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
  static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
                                       bool sctlr_b)
  {
--    uint16_t insn = cpu_lduw_code(env, addr);
+     /* Where to look for local files */
-+    uint16_t insn;
+-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
-+#ifndef CONFIG_USER_ONLY
++    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
-+    /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
+     NSString *full_file_path;
-+       within each word.  Undo that now.  */
-+    if (sctlr_b) {
+     /* iterate thru the possible paths until the file is found */
 +        addr ^= 2;
 +    }
 +#endif
 +    insn = cpu_lduw_code(env, addr);
      if (bswap_code(sctlr_b)) {
          return bswap16(insn);
      }
 diff --git a/disas.c b/disas.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas.c
 +++ b/disas.c
@@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
      s.cpu = cpu;
      s.info.read_memory_func = target_read_memory;
 +    s.info.read_memory_inner_func = NULL;
      s.info.buffer_vma = code;
      s.info.buffer_length = size;
      s.info.print_address_func = generic_print_address;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
    return print_insn_arm(pc | 1, info);
  }
 +static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
 +                                int length, struct disassemble_info *info)
 +{
 +    assert(info->read_memory_inner_func);
 +    assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
 +
 +    if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
 +        assert(info->endian == BFD_ENDIAN_LITTLE);
 +        return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
 +                                            info);
 +    } else {
 +        return info->read_memory_inner_func(memaddr, b, length, info);
 +    }
 +}
 +
  static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
  {
      ARMCPU *ac = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
          info->endian = BFD_ENDIAN_BIG;
  #endif
      }
 +    if (info->read_memory_inner_func == NULL) {
 +        info->read_memory_inner_func = info->read_memory_func;
 +        info->read_memory_func = arm_read_memory_func;
 +    }
 +    info->flags &= ~INSN_ARM_BE32;
 +    if (arm_sctlr_b(env)) {
 +        info->flags |= INSN_ARM_BE32;
 +    }
  }
  static void arm_cpu_initfn(Object *obj)
 --
-.7.4
+.20.1

-New patch
+[PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build
+In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
+At the moment new manpages have to be listed both in the conf.py for
+Sphinx and also in docs/meson.build for Meson. We forgot the second
+of those -- correct the omission.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
+---
+ docs/meson.build | 1 +
+file changed, 1 insertion(+)
+diff --git a/docs/meson.build b/docs/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/meson.build
++++ b/docs/meson.build
+@@ -XXX,XX +XXX,XX @@ if build_docs
+         'qemu-img.1': (have_tools ? 'man1' : ''),
+         'qemu-nbd.8': (have_tools ? 'man8' : ''),
+         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
++        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
+         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
+         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
+         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
+--
+.20.1

-New patch
+[PULL 11/21] docs: Build and install all the docs in a single manual
+When we first converted our documentation to Sphinx, we split it into
 multiple manuals (system, interop, tools, etc), which are all built
 separately.  The primary driver for this was wanting to be able to
 avoid shipping the 'devel' manual to end-users.  However, this is
 working against the grain of the way Sphinx wants to be used and
 causes some annoyances:
  * Cross-references between documents become much harder or
    possibly impossible
  * There is no single index to the whole documentation
  * Within one manual there's no links or table-of-contents info
    that lets you easily navigate to the others
  * The devel manual doesn't get published on the QEMU website
    (it would be nice to able to refer to it there)
 Merely hiding our developer documentation from end users seems like
 it's not enough benefit for these costs.  Combine all the
 documentation into a single manual (the same way that the readthedocs
 site builds it) and install the whole thing.  The previous manual
 divisions remain as the new top level sections in the manual.
  * The per-manual conf.py files are no longer needed
  * The man_pages[] specifications previously in each per-manual
    conf.py move to the top level conf.py
  * docs/meson.build logic is simplified as we now only need to run
    Sphinx once for the HTML and then once for the manpages5B
  * The old index.html.in that produced the top-level page with
    links to each manual is no longer needed
 Unfortunately this means that we now have to build the HTML
 documentation into docs/manual in the build tree rather than directly
 into docs/; otherwise it is too awkward to ensure we install only the
 built manual and not also the dependency info, stamp file, etc.  The
 manual still ends up in the same place in the final installed
 directory, but anybody who was consulting documentation from within
 the build tree will have to adjust where they're looking.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
 Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
 ---
  docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
  docs/devel/conf.py   | 15 -----------
  docs/index.html.in   | 17 ------------
  docs/interop/conf.py | 28 -------------------
  docs/meson.build     | 64 +++++++++++++++++---------------------------
  docs/specs/conf.py   | 16 -----------
  docs/system/conf.py  | 28 -------------------
  docs/tools/conf.py   | 37 -------------------------
  docs/user/conf.py    | 15 -----------
 files changed, 70 insertions(+), 196 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
 diff --git a/docs/conf.py b/docs/conf.py
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/conf.py
 +++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ latex_documents = [
  # -- Options for manual page output ---------------------------------------
  # Individual manual/conf.py can override this to create man pages
 -man_pages = []
 +man_pages = [
 +    ('interop/qemu-ga', 'qemu-ga',
 +     'QEMU Guest Agent',
 +     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
 +    ('interop/qemu-ga-ref', 'qemu-ga-ref',
 +     'QEMU Guest Agent Protocol Reference',
 +     [], 7),
 +    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
 +     'QEMU QMP Reference Manual',
 +     [], 7),
 +    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 +     'QEMU Storage Daemon QMP Reference Manual',
 +     [], 7),
 +    ('system/qemu-manpage', 'qemu',
 +     'QEMU User Documentation',
 +     ['Fabrice Bellard'], 1),
 +    ('system/qemu-block-drivers', 'qemu-block-drivers',
 +     'QEMU block drivers reference',
 +     ['Fabrice Bellard and the QEMU Project developers'], 7),
 +    ('system/qemu-cpu-models', 'qemu-cpu-models',
 +     'QEMU CPU Models',
 +     ['The QEMU Project developers'], 7),
 +    ('tools/qemu-img', 'qemu-img',
 +     'QEMU disk image utility',
 +     ['Fabrice Bellard'], 1),
 +    ('tools/qemu-nbd', 'qemu-nbd',
 +     'QEMU Disk Network Block Device Server',
 +     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 +    ('tools/qemu-pr-helper', 'qemu-pr-helper',
 +     'QEMU persistent reservation helper',
 +     [], 8),
 +    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
 +     'QEMU storage daemon',
 +     [], 1),
 +    ('tools/qemu-trace-stap', 'qemu-trace-stap',
 +     'QEMU SystemTap trace tool',
 +     [], 1),
 +    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
 +     'QEMU 9p virtfs proxy filesystem helper',
 +     ['M. Mohan Kumar'], 1),
 +    ('tools/virtiofsd', 'virtiofsd',
 +     'QEMU virtio-fs shared file system daemon',
 +     ['Stefan Hajnoczi <stefanha@redhat.com>',
 +      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 +]
  # -- Options for Texinfo output -------------------------------------------
 diff --git a/docs/devel/conf.py b/docs/devel/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/devel/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'devel' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'Developer''s Guide'
 diff --git a/docs/index.html.in b/docs/index.html.in
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/index.html.in
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -<!DOCTYPE html>
 -<html lang="en">
 -    <head>
 -        <meta charset="UTF-8">
 -        <title>QEMU @VERSION@ Documentation</title>
 -    </head>
 -    <body>
 -        <h1>QEMU @VERSION@ Documentation</h1>
 -        <ul>
 -            <li><a href="system/index.html">System Emulation User's Guide</a></li>
 -            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
 -            <li><a href="tools/index.html">Tools Guide</a></li>
 -            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
 -            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
 -        </ul>
 -    </body>
 -</html>
 diff --git a/docs/interop/conf.py b/docs/interop/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/interop/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'interop' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
 -     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
 -    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
 -     [], 7),
 -    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
 -     [], 7),
 -    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
 -     'QEMU Storage Daemon QMP Reference Manual', [], 7),
 -]
 diff --git a/docs/meson.build b/docs/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/meson.build
 +++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                            meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                            qapi_gen_depends ]
 -  configure_file(output: 'index.html',
 -                 input: files('index.html.in'),
 -                 configuration: {'VERSION': meson.project_version()},
 -                 install_dir: qemu_docdir)
 -  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
    man_pages = {
 -    'interop' : {
          'qemu-ga.8': (have_tools ? 'man8' : ''),
          'qemu-ga-ref.7': 'man7',
          'qemu-qmp-ref.7': 'man7',
          'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
 -    },
 -    'tools': {
          'qemu-img.1': (have_tools ? 'man1' : ''),
          'qemu-nbd.8': (have_tools ? 'man8' : ''),
          'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
          'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
          'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
          'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
 -    },
 -    'system': {
          'qemu.1': 'man1',
          'qemu-block-drivers.7': 'man7',
          'qemu-cpu-models.7': 'man7'
 -    },
    }
    sphinxdocs = []
    sphinxmans = []
 -  foreach manual : manuals
 -    private_dir = meson.current_build_dir() / (manual + '.p')
 -    output_dir = meson.current_build_dir() / manual
 -    input_dir = meson.current_source_dir() / manual
 -    this_manual = custom_target(manual + ' manual',
 +  private_dir = meson.current_build_dir() / 'manual.p'
 +  output_dir = meson.current_build_dir() / 'manual'
 +  input_dir = meson.current_source_dir()
 +
 +  this_manual = custom_target('QEMU manual',
                  build_by_default: build_docs,
 -                output: [manual + '.stamp'],
 -                input: [files('conf.py'), files(manual / 'conf.py')],
 -                depfile: manual + '.d',
 +                output: 'docs.stamp',
 +                input: files('conf.py'),
 +                depfile: 'docs.d',
                  depend_files: sphinx_extn_depends,
                  command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
                            '-Ddepfile_stamp=@OUTPUT0@',
                            '-b', 'html', '-d', private_dir,
                            input_dir, output_dir])
 -    sphinxdocs += this_manual
 -    if build_docs and manual != 'devel'
 -      install_subdir(output_dir, install_dir: qemu_docdir)
 -    endif
 +  sphinxdocs += this_manual
 +  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 -    these_man_pages = []
 -    install_dirs = []
 -    foreach page, section : man_pages.get(manual, {})
 -      these_man_pages += page
 -      install_dirs += section == '' ? false : get_option('mandir') / section
 -    endforeach
 -    if these_man_pages.length() > 0
 -      sphinxmans += custom_target(manual + ' man pages',
 -                         build_by_default: build_docs,
 -                         output: these_man_pages,
 -                         input: this_manual,
 -                         install: build_docs,
 -                         install_dir: install_dirs,
 -                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 -                                   input_dir, meson.current_build_dir()])
 -    endif
 +  these_man_pages = []
 +  install_dirs = []
 +  foreach page, section : man_pages
 +    these_man_pages += page
 +    install_dirs += section == '' ? false : get_option('mandir') / section
    endforeach
 +
 +  sphinxmans += custom_target('QEMU man pages',
 +                              build_by_default: build_docs,
 +                              output: these_man_pages,
 +                              input: this_manual,
 +                              install: build_docs,
 +                              install_dir: install_dirs,
 +                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
 +                                        input_dir, meson.current_build_dir()])
 +
    alias_target('sphinxdocs', sphinxdocs)
    alias_target('html', sphinxdocs)
    alias_target('man', sphinxmans)
 diff --git a/docs/specs/conf.py b/docs/specs/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/specs/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'specs' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'System Emulation Guest Hardware Specifications'
 diff --git a/docs/system/conf.py b/docs/system/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/system/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'system' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'System Emulation User''s Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-block-drivers', 'qemu-block-drivers',
 -     u'QEMU block drivers reference',
 -     ['Fabrice Bellard and the QEMU Project developers'], 7),
 -    ('qemu-cpu-models', 'qemu-cpu-models',
 -     u'QEMU CPU Models',
 -     ['The QEMU Project developers'], 7)
 -]
 diff --git a/docs/tools/conf.py b/docs/tools/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/tools/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'tools' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = \
 -    u'Tools Guide'
 -
 -# One entry per manual page. List of tuples
 -# (source start file, name, description, authors, manual section).
 -man_pages = [
 -    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
 -     ['Fabrice Bellard'], 1),
 -    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
 -     [], 1),
 -    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
 -     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
 -    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
 -     [], 8),
 -    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
 -     [], 1),
 -    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
 -     u'QEMU 9p virtfs proxy filesystem helper',
 -     ['M. Mohan Kumar'], 1),
 -    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
 -     ['Stefan Hajnoczi <stefanha@redhat.com>',
 -      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
 -]
 diff --git a/docs/user/conf.py b/docs/user/conf.py
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/docs/user/conf.py
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# -*- coding: utf-8 -*-
 -#
 -# QEMU documentation build configuration file for the 'user' manual.
 -#
 -# This includes the top level conf file and then makes any necessary tweaks.
 -import sys
 -import os
 -
 -qemu_docdir = os.path.abspath("..")
 -parent_config = os.path.join(qemu_docdir, "conf.py")
 -exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
 -
 -# This slightly misuses the 'description', but is the best way to get
 -# the manual title to appear in the sidebar.
 -html_theme_options['description'] = u'User Mode Emulation User''s Guide'
 --
 .20.1

-[Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
+[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
-In the ARM ldr/str decode path, rather than directly testing
+In commit cd8be50e58f63413c0 we converted the A32 coprocessor
-"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
+insns to decodetree. This accidentally broke XScale/iWMMXt insns,
-bits out into wbit and pbit local flags. (We will want to
+because it moved the handling of "cp insns which are handled
-do more tests against them to determine whether we need to
+by looking up the cp register in the hashtable" from after the
-provide syndrome information.)
+call to the legacy disas_xscale_insn() decode to before it,
 with the result that all XScale/iWMMXt insns now UNDEF.
+Update valid_cp() so that it knows that on XScale cp 0 and 1
+are not standard coprocessor instructions; this will cause
+the decodetree trans_ functions to ignore them, so that
+execution will correctly get through to the legacy decode again.
+Cc: qemu-stable@nongnu.org
+Reported-by: Guenter Roeck <linux@roeck-us.net>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 9 ++++++---
+ target/arm/translate.c | 7 +++++++
-file changed, 6 insertions(+), 3 deletions(-)
+file changed, 7 insertions(+)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
-             } else {
+      * only cp14 and cp15 are valid, and other values aren't considered
-                 int address_offset;
+      * to be in the coprocessor-instruction space at all. v8M still
-                 bool load = insn & (1 << 20);
+      * permits coprocessors 0..7.
-+                bool wbit = insn & (1 << 21);
++     * For XScale, we must not decode the XScale cp0, cp1 space as
-+                bool pbit = insn & (1 << 24);
++     * a standard coprocessor insn, because we want to fall through to
-                 bool doubleword = false;
++     * the legacy disas_xscale_insn() decoder after decodetree is done.
-                 /* Misc load/store */
+      */
-                 rn = (insn >> 16) & 0xf;
++    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
++        return false;
-                 }
++    }
++
-                 addr = load_reg(s, rn);
+     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
--                if (insn & (1 << 24))
+         !arm_dc_feature(s, ARM_FEATURE_M)) {
-+                if (pbit) {
+         return cp >= 14;
                      gen_add_datah_offset(s, insn, 0, addr);
 +                }
                  address_offset = 0;
                  if (doubleword) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     ensure correct behavior with overlapping index registers.
                     ldrd with base writeback is undefined if the
                     destination and index registers overlap.  */
 -                if (!(insn & (1 << 24))) {
 +                if (!pbit) {
                      gen_add_datah_offset(s, insn, address_offset, addr);
                      store_reg(s, rn, addr);
 -                } else if (insn & (1 << 21)) {
 +                } else if (wbit) {
                      if (address_offset)
                          tcg_gen_addi_i32(addr, addr, address_offset);
                      store_reg(s, rn, addr);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 04/13] sd: sdhci: check data length during dma_memory_read
+[PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value
-From: Prasad J Pandit <pjp@fedoraproject.org>
+A copy-and-paste error meant that the return value for register offset 0x44
+(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
-While doing multi block SDMA transfer in routine
+the rx status FIFO. Fix the typo.
 'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting
 index 'begin' and data length 's->data_count' could end up to be same.
 This could lead to an OOB access issue. Correct transfer data length
 to avoid it.
 Cc: qemu-stable@nongnu.org
-Reported-by: Jiang Xin <jiangxin1@huawei.com>
+Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
 Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20170130064736.9236-1-ppandit@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
 ---
- hw/sd/sdhci.c | 2 +-
+ hw/net/lan9118.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
+diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/sdhci.c
+--- a/hw/net/lan9118.c
-+++ b/hw/sd/sdhci.c
++++ b/hw/net/lan9118.c
-@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
+@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
-                 boundary_count -= block_size - begin;
+     case 0x40:
-             }
+         return rx_status_fifo_pop(s);
-             dma_memory_read(&address_space_memory, s->sdmasysad,
+     case 0x44:
--                            &s->fifo_buffer[begin], s->data_count);
+-        return s->rx_status_fifo[s->tx_status_fifo_head];
-+                            &s->fifo_buffer[begin], s->data_count - begin);
++        return s->rx_status_fifo[s->rx_status_fifo_head];
-             s->sdmasysad += s->data_count - begin;
+     case 0x48:
-             if (s->data_count == block_size) {
+         return tx_status_fifo_pop(s);
-                 for (n = 0; n < block_size; n++) {
+     case 0x4c:
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 11/13] stellaris: Document memory map and which SoC devices are unimplemented
+[PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets
-Add a comment documenting the memory map of the SoC devices and which
+The lan9118 code mostly uses symbolic constants for register offsets;
-are not implemented.
+the exceptions are those which the datasheet doesn't give an official
 symbolic name to.
 Add some names for the registers which don't already have them, based
 on the longer names they are given in the memory map.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
 ---
- hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++
+ hw/net/lan9118.c | 24 ++++++++++++++++++------
-file changed, 34 insertions(+)
+file changed, 18 insertions(+), 6 deletions(-)
-diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/stellaris.c
+--- a/hw/net/lan9118.c
-+++ b/hw/arm/stellaris.c
++++ b/hw/net/lan9118.c
-@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
+@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
-x40024000, 0x40025000, 0x40026000};
+ do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
-     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
+ #endif
-+    /* Memory map of SoC devices, from
++/* The tx and rx fifo ports are a range of aliased 32-bit registers */
-+     * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
++#define RX_DATA_FIFO_PORT_FIRST 0x00
-+     * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
++#define RX_DATA_FIFO_PORT_LAST 0x1f
-+     *
++#define TX_DATA_FIFO_PORT_FIRST 0x20
-+     * 40000000 wdtimer (unimplemented)
++#define TX_DATA_FIFO_PORT_LAST 0x3f
 +     * 40002000 i2c (unimplemented)
 +     * 40004000 GPIO
 +     * 40005000 GPIO
 +     * 40006000 GPIO
 +     * 40007000 GPIO
 +     * 40008000 SSI
 +     * 4000c000 UART
 +     * 4000d000 UART
 +     * 4000e000 UART
 +     * 40020000 i2c
 +     * 40021000 i2c (unimplemented)
 +     * 40024000 GPIO
 +     * 40025000 GPIO
 +     * 40026000 GPIO
 +     * 40028000 PWM (unimplemented)
 +     * 4002c000 QEI (unimplemented)
 +     * 4002d000 QEI (unimplemented)
 +     * 40030000 gptimer
 +     * 40031000 gptimer
 +     * 40032000 gptimer
 +     * 40033000 gptimer
 +     * 40038000 ADC
 +     * 4003c000 analogue comparator (unimplemented)
 +     * 40048000 ethernet
 +     * 400fc000 hibernation module (unimplemented)
 +     * 400fd000 flash memory control (unimplemented)
 +     * 400fe000 system control
 +     */
 +
-     DeviceState *gpio_dev[7], *nvic;
++#define RX_STATUS_FIFO_PORT 0x40
-     qemu_irq gpio_in[7][8];
++#define RX_STATUS_FIFO_PEEK 0x44
-     qemu_irq gpio_out[7][8];
++#define TX_STATUS_FIFO_PORT 0x48
 +#define TX_STATUS_FIFO_PEEK 0x4c
 +
  #define CSR_ID_REV      0x50
  #define CSR_IRQ_CFG     0x54
  #define CSR_INT_STS     0x58
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
      offset &= 0xff;
      //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
 -    if (offset >= 0x20 && offset < 0x40) {
 +    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
 +        offset <= TX_DATA_FIFO_PORT_LAST) {
          /* TX FIFO */
          tx_fifo_push(s, val);
          return;
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
      lan9118_state *s = (lan9118_state *)opaque;
      //DPRINTF("Read reg 0x%02x\n", (int)offset);
 -    if (offset < 0x20) {
 +    if (offset <= RX_DATA_FIFO_PORT_LAST) {
          /* RX FIFO */
          return rx_fifo_pop(s);
      }
      switch (offset) {
 -    case 0x40:
 +    case RX_STATUS_FIFO_PORT:
          return rx_status_fifo_pop(s);
 -    case 0x44:
 +    case RX_STATUS_FIFO_PEEK:
          return s->rx_status_fifo[s->rx_status_fifo_head];
 -    case 0x48:
 +    case TX_STATUS_FIFO_PORT:
          return tx_status_fifo_pop(s);
 -    case 0x4c:
 +    case TX_STATUS_FIFO_PEEK:
          return s->tx_status_fifo[s->tx_status_fifo_head];
      case CSR_ID_REV:
          return 0x01180001;
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 01/13] integratorcp: adding vmstate for save/restore
+[PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module
-From: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
+From: Hao Wu <wuhaotsh@google.com>
-VMState added by this patch preserves correct
+This patch allows NPCM7XX CLK module to compute clocks that are used by
-loading of the integratorcp device state.
+other NPCM7XX modules.
-Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
+Add a new struct NPCM7xxClockConverterState which represents a
-Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP
+single converter.  Each clock converter in CLK module represents one
-[PMM: removed unnecessary minimum_version_id_old lines]
+converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
 takes one or more input clocks and converts them into one output clock.
 They form a clock hierarchy in the CLK module and are responsible for
 outputing clocks for various other modules in an NPCM7XX SoC.
 Each converter has a function pointer called "convert" which represents
 the unique logic for that converter.
 The clock contains two initialization information: ConverterInitInfo and
 ConverterConnectionInfo. They represent the vertices and edges in the
 clock diagram respectively.
 Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210108190945.949196-2-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/integratorcp.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ include/hw/misc/npcm7xx_clk.h | 140 +++++-
-file changed, 59 insertions(+)
+ hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
 files changed, 932 insertions(+), 13 deletions(-)
-diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/integratorcp.c
+--- a/include/hw/misc/npcm7xx_clk.h
-+++ b/hw/arm/integratorcp.c
++++ b/include/hw/misc/npcm7xx_clk.h
-@@ -XXX,XX +XXX,XX @@ static uint8_t integrator_spd[128] = {
+@@ -XXX,XX +XXX,XX @@
-xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
+ #define NPCM7XX_CLK_H
  #include "exec/memory.h"
 +#include "hw/clock.h"
  #include "hw/sysbus.h"
  /*
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
 -typedef struct NPCM7xxCLKState {
 +/* Maximum amount of clock inputs in a SEL module. */
 +#define NPCM7XX_CLK_SEL_MAX_INPUT 5
 +
 +/* PLLs in CLK module. */
 +typedef enum NPCM7xxClockPLL {
 +    NPCM7XX_CLOCK_PLL0,
 +    NPCM7XX_CLOCK_PLL1,
 +    NPCM7XX_CLOCK_PLL2,
 +    NPCM7XX_CLOCK_PLLG,
 +    NPCM7XX_CLOCK_NR_PLLS,
 +} NPCM7xxClockPLL;
 +
 +/* SEL/MUX in CLK module. */
 +typedef enum NPCM7xxClockSEL {
 +    NPCM7XX_CLOCK_PIXCKSEL,
 +    NPCM7XX_CLOCK_MCCKSEL,
 +    NPCM7XX_CLOCK_CPUCKSEL,
 +    NPCM7XX_CLOCK_CLKOUTSEL,
 +    NPCM7XX_CLOCK_UARTCKSEL,
 +    NPCM7XX_CLOCK_TIMCKSEL,
 +    NPCM7XX_CLOCK_SDCKSEL,
 +    NPCM7XX_CLOCK_GFXMSEL,
 +    NPCM7XX_CLOCK_SUCKSEL,
 +    NPCM7XX_CLOCK_NR_SELS,
 +} NPCM7xxClockSEL;
 +
 +/* Dividers in CLK module. */
 +typedef enum NPCM7xxClockDivider {
 +    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
 +    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
 +    NPCM7XX_CLOCK_MC_DIVIDER,
 +    NPCM7XX_CLOCK_AXI_DIVIDER,
 +    NPCM7XX_CLOCK_AHB_DIVIDER,
 +    NPCM7XX_CLOCK_AHB3_DIVIDER,
 +    NPCM7XX_CLOCK_SPI0_DIVIDER,
 +    NPCM7XX_CLOCK_SPIX_DIVIDER,
 +    NPCM7XX_CLOCK_APB1_DIVIDER,
 +    NPCM7XX_CLOCK_APB2_DIVIDER,
 +    NPCM7XX_CLOCK_APB3_DIVIDER,
 +    NPCM7XX_CLOCK_APB4_DIVIDER,
 +    NPCM7XX_CLOCK_APB5_DIVIDER,
 +    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
 +    NPCM7XX_CLOCK_UART_DIVIDER,
 +    NPCM7XX_CLOCK_TIMER_DIVIDER,
 +    NPCM7XX_CLOCK_ADC_DIVIDER,
 +    NPCM7XX_CLOCK_MMC_DIVIDER,
 +    NPCM7XX_CLOCK_SDHC_DIVIDER,
 +    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
 +    NPCM7XX_CLOCK_UTMI_DIVIDER,
 +    NPCM7XX_CLOCK_NR_DIVIDERS,
 +} NPCM7xxClockConverter;
 +
 +typedef struct NPCM7xxCLKState NPCM7xxCLKState;
 +
 +/**
 + * struct NPCM7xxClockPLLState - A PLL module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @clock_in: The input clock of this module.
 + * @clock_out: The output clock of this module.
 + * @reg: The control registers for this PLL module.
 + */
 +typedef struct NPCM7xxClockPLLState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    Clock *clock_in;
 +    Clock *clock_out;
 +
 +    int reg;
 +} NPCM7xxClockPLLState;
 +
 +/**
 + * struct NPCM7xxClockSELState - A SEL module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @input_size: The size of inputs of this module.
 + * @clock_in: The input clocks of this module.
 + * @clock_out: The output clocks of this module.
 + * @offset: The offset of this module in the control register.
 + * @len: The length of this module in the control register.
 + */
 +typedef struct NPCM7xxClockSELState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    uint8_t input_size;
 +    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    Clock *clock_out;
 +
 +    int offset;
 +    int len;
 +} NPCM7xxClockSELState;
 +
 +/**
 + * struct NPCM7xxClockDividerState - A Divider module in CLK module.
 + * @name: The name of the module.
 + * @clk: The CLK module that owns this module.
 + * @clock_in: The input clock of this module.
 + * @clock_out: The output clock of this module.
 + * @divide: The function the divider uses to divide the input.
 + * @reg: The index of the control register that contains the divisor.
 + * @offset: The offset of the divisor in the control register.
 + * @len: The length of the divisor in the control register.
 + * @divisor: The divisor for a constant divisor
 + */
 +typedef struct NPCM7xxClockDividerState {
 +    DeviceState parent;
 +
 +    const char *name;
 +    NPCM7xxCLKState *clk;
 +    Clock *clock_in;
 +    Clock *clock_out;
 +
 +    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
 +    union {
 +        struct {
 +            int reg;
 +            int offset;
 +            int len;
 +        };
 +        int divisor;
 +    };
 +} NPCM7xxClockDividerState;
 +
 +struct NPCM7xxCLKState {
      SysBusDevice parent;
      MemoryRegion iomem;
 +    /* Clock converters */
 +    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
 +    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
 +    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
 +
      uint32_t regs[NPCM7XX_CLK_NR_REGS];
      /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
      int64_t ref_ns;
 -} NPCM7xxCLKState;
 +
 +    /* The incoming reference clock. */
 +    Clock *clkref;
 +};
  #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
  #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_clk.c
 +++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/timer/npcm7xx_timer.h"
 +#include "hw/qdev-clock.h"
  #include "migration/vmstate.h"
  #include "qemu/error-report.h"
  #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
  #include "trace.h"
  #include "sysemu/watchdog.h"
 +/*
 + * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
 + * is always 25 MHz.
 + */
 +#define NPCM7XX_CLOCK_REF_HZ            (25000000)
 +
 +/* Register Field Definitions */
 +#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 +
  #define PLLCON_LOKI     BIT(31)
  #define PLLCON_LOKS     BIT(30)
  #define PLLCON_PWDEN    BIT(12)
 +#define PLLCON_FBDV(con) extract32((con), 16, 12)
 +#define PLLCON_OTDV2(con) extract32((con), 13, 3)
 +#define PLLCON_OTDV1(con) extract32((con), 8, 3)
 +#define PLLCON_INDV(con) extract32((con), 0, 6)
  enum NPCM7xxCLKRegisters {
      NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
      [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
  };
-+static const VMStateDescription vmstate_integratorcm = {
+-/* Register Field Definitions */
-+    .name = "integratorcm",
+-#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
 -
  /* The number of watchdogs that can trigger a reset. */
  #define NPCM7XX_NR_WATCHDOGS    (3)
 +/* Clock converter functions */
 +
 +#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
 +#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_PLL)
 +#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
 +#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_SEL)
 +#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
 +#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
 +        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
 +
 +static void npcm7xx_clk_update_pll(void *opaque)
 +{
 +    NPCM7xxClockPLLState *s = opaque;
 +    uint32_t con = s->clk->regs[s->reg];
 +    uint64_t freq;
 +
 +    /* The PLL is grounded if it is not locked yet. */
 +    if (con & PLLCON_LOKI) {
 +        freq = clock_get_hz(s->clock_in);
 +        freq *= PLLCON_FBDV(con);
 +        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
 +    } else {
 +        freq = 0;
 +    }
 +
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static void npcm7xx_clk_update_sel(void *opaque)
 +{
 +    NPCM7xxClockSELState *s = opaque;
 +    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
 +            s->len);
 +
 +    if (index >= s->input_size) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: SEL index: %u out of range\n",
 +                      __func__, index);
 +        index = 0;
 +    }
 +    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
 +}
 +
 +static void npcm7xx_clk_update_divider(void *opaque)
 +{
 +    NPCM7xxClockDividerState *s = opaque;
 +    uint32_t freq;
 +
 +    freq = s->divide(s);
 +    clock_update_hz(s->clock_out, freq);
 +}
 +
 +static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) / s->divisor;
 +}
 +
 +static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) /
 +            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
 +}
 +
 +static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
 +{
 +    return divide_by_reg_divisor(s) / 2;
 +}
 +
 +static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
 +{
 +    return clock_get_hz(s->clock_in) >>
 +        extract32(s->clk->regs[s->reg], s->offset, s->len);
 +}
 +
 +static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
 +{
 +    switch (reg) {
 +    case NPCM7XX_CLK_PLLCON0:
 +        return NPCM7XX_CLOCK_PLL0;
 +    case NPCM7XX_CLK_PLLCON1:
 +        return NPCM7XX_CLOCK_PLL1;
 +    case NPCM7XX_CLK_PLLCON2:
 +        return NPCM7XX_CLOCK_PLL2;
 +    case NPCM7XX_CLK_PLLCONG:
 +        return NPCM7XX_CLOCK_PLLG;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        npcm7xx_clk_update_pll(&clk->plls[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        npcm7xx_clk_update_sel(&clk->sels[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
 +{
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        npcm7xx_clk_update_divider(&clk->dividers[i]);
 +    }
 +}
 +
 +static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
 +{
 +    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
 +    npcm7xx_clk_update_all_plls(clk);
 +    npcm7xx_clk_update_all_sels(clk);
 +    npcm7xx_clk_update_all_dividers(clk);
 +}
 +
 +/* Types of clock sources. */
 +typedef enum ClockSrcType {
 +    CLKSRC_REF,
 +    CLKSRC_PLL,
 +    CLKSRC_SEL,
 +    CLKSRC_DIV,
 +} ClockSrcType;
 +
 +typedef struct PLLInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    int reg;
 +    const char *public_name;
 +} PLLInitInfo;
 +
 +typedef struct SELInitInfo {
 +    const char *name;
 +    uint8_t input_size;
 +    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
 +    int offset;
 +    int len;
 +    const char *public_name;
 +} SELInitInfo;
 +
 +typedef struct DividerInitInfo {
 +    const char *name;
 +    ClockSrcType src_type;
 +    int src_index;
 +    uint32_t (*divide)(NPCM7xxClockDividerState *s);
 +    int reg; /* not used when type == CONSTANT */
 +    int offset; /* not used when type == CONSTANT */
 +    int len; /* not used when type == CONSTANT */
 +    int divisor; /* used only when type == CONSTANT */
 +    const char *public_name;
 +} DividerInitInfo;
 +
 +static const PLLInitInfo pll_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL0] = {
 +        .name = "pll0",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON0,
 +    },
 +    [NPCM7XX_CLOCK_PLL1] = {
 +        .name = "pll1",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON1,
 +    },
 +    [NPCM7XX_CLOCK_PLL2] = {
 +        .name = "pll2",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCON2,
 +    },
 +    [NPCM7XX_CLOCK_PLLG] = {
 +        .name = "pllg",
 +        .src_type = CLKSRC_REF,
 +        .reg = NPCM7XX_CLK_PLLCONG,
 +    },
 +};
 +
 +static const SELInitInfo sel_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PIXCKSEL] = {
 +        .name = "pixcksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_PLL, CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
 +        .offset = 5,
 +        .len = 1,
 +        .public_name = "pixel-clock",
 +    },
 +    [NPCM7XX_CLOCK_MCCKSEL] = {
 +        .name = "mccksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
 +            /*MCBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
 +        .offset = 12,
 +        .len = 2,
 +        .public_name = "mc-phy-clock",
 +    },
 +    [NPCM7XX_CLOCK_CPUCKSEL] = {
 +        .name = "cpucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            /*SYSBPCK, shouldn't be used in normal operation*/
 +            CLKSRC_REF},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
 +        .offset = 0,
 +        .len = 2,
 +        .public_name = "system-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUTSEL] = {
 +        .name = "clkoutsel",
 +        .input_size = 5,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
 +            CLKSRC_PLL, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 18,
 +        .len = 3,
 +        .public_name = "tock",
 +    },
 +    [NPCM7XX_CLOCK_UARTCKSEL] = {
 +        .name = "uartcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 8,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_TIMCKSEL] = {
 +        .name = "timcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 14,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_SDCKSEL] = {
 +        .name = "sdcksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 6,
 +        .len = 2,
 +    },
 +    [NPCM7XX_CLOCK_GFXMSEL] = {
 +        .name = "gfxmksel",
 +        .input_size = 2,
 +        .src_type = {CLKSRC_REF, CLKSRC_PLL},
 +        .src_index = {0, NPCM7XX_CLOCK_PLL2},
 +        .offset = 21,
 +        .len = 1,
 +    },
 +    [NPCM7XX_CLOCK_SUCKSEL] = {
 +        .name = "sucksel",
 +        .input_size = 4,
 +        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
 +        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
 +            NPCM7XX_CLOCK_PLL2D2},
 +        .offset = 10,
 +        .len = 2,
 +    },
 +};
 +
 +static const DividerInitInfo divider_init_info_list[] = {
 +    [NPCM7XX_CLOCK_PLL1D2] = {
 +        .name = "pll1d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL1,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_PLL2D2] = {
 +        .name = "pll2d2",
 +        .src_type = CLKSRC_PLL,
 +        .src_index = NPCM7XX_CLOCK_PLL2,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +    },
 +    [NPCM7XX_CLOCK_MC_DIVIDER] = {
 +        .name = "mc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_MCCKSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 2,
 +        .public_name = "mc-clock"
 +    },
 +    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
 +        .name = "axi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 0,
 +        .len = 1,
 +        .public_name = "clk2"
 +    },
 +    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
 +        .name = "ahb-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "clk4"
 +    },
 +    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
 +        .name = "ahb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "ahb3-spi3-clock"
 +    },
 +    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
 +        .name = "spi0-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 6,
 +        .len = 5,
 +        .public_name = "spi0-clock",
 +    },
 +    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
 +        .name = "spix-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV3,
 +        .offset = 1,
 +        .len = 5,
 +        .public_name = "spix-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
 +        .name = "apb1-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 24,
 +        .len = 2,
 +        .public_name = "apb1-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
 +        .name = "apb2-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 26,
 +        .len = 2,
 +        .public_name = "apb2-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
 +        .name = "apb3-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 28,
 +        .len = 2,
 +        .public_name = "apb3-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
 +        .name = "apb4-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 30,
 +        .len = 2,
 +        .public_name = "apb4-clock",
 +    },
 +    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
 +        .name = "apb5-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 22,
 +        .len = 2,
 +        .public_name = "apb5-clock",
 +    },
 +    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
 +        .name = "clkout-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "clkout",
 +    },
 +    [NPCM7XX_CLOCK_UART_DIVIDER] = {
 +        .name = "uart-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 16,
 +        .len = 5,
 +        .public_name = "uart-clock",
 +    },
 +    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
 +        .name = "timer-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 21,
 +        .len = 5,
 +        .public_name = "timer-clock",
 +    },
 +    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
 +        .name = "adc-divider",
 +        .src_type = CLKSRC_DIV,
 +        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
 +        .divide = shift_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 28,
 +        .len = 3,
 +        .public_name = "adc-clock",
 +    },
 +    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
 +        .name = "mmc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV1,
 +        .offset = 11,
 +        .len = 5,
 +        .public_name = "mmc-clock",
 +    },
 +    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
 +        .name = "sdhc-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SDCKSEL,
 +        .divide = divide_by_reg_divisor_times_2,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 0,
 +        .len = 4,
 +        .public_name = "sdhc-clock",
 +    },
 +    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
 +        .name = "gfxm-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_GFXMSEL,
 +        .divide = divide_by_constant,
 +        .divisor = 3,
 +        .public_name = "gfxm-clock",
 +    },
 +    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
 +        .name = "utmi-divider",
 +        .src_type = CLKSRC_SEL,
 +        .src_index = NPCM7XX_CLOCK_SUCKSEL,
 +        .divide = divide_by_reg_divisor,
 +        .reg = NPCM7XX_CLK_CLKDIV2,
 +        .offset = 8,
 +        .len = 5,
 +        .public_name = "utmi-clock",
 +    },
 +};
 +
 +static void npcm7xx_clk_pll_init(Object *obj)
 +{
 +    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
 +
 +    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
 +            npcm7xx_clk_update_pll, pll);
 +    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
 +}
 +
 +static void npcm7xx_clk_sel_init(Object *obj)
 +{
 +    int i;
 +    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
 +
 +    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
 +        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
 +                g_strdup_printf("clock-in[%d]", i),
 +                npcm7xx_clk_update_sel, sel);
 +    }
 +    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
 +}
 +static void npcm7xx_clk_divider_init(Object *obj)
 +{
 +    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
 +
 +    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
 +            npcm7xx_clk_update_divider, div);
 +    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
 +}
 +
 +static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
 +        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
 +{
 +    pll->name = init_info->name;
 +    pll->clk = clk;
 +    pll->reg = init_info->reg;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
 +        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
 +{
 +    int input_size = init_info->input_size;
 +
 +    sel->name = init_info->name;
 +    sel->clk = clk;
 +    sel->input_size = init_info->input_size;
 +    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
 +    sel->offset = init_info->offset;
 +    sel->len = init_info->len;
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
 +        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
 +{
 +    div->name = init_info->name;
 +    div->clk = clk;
 +
 +    div->divide = init_info->divide;
 +    if (div->divide == divide_by_constant) {
 +        div->divisor = init_info->divisor;
 +    } else {
 +        div->reg = init_info->reg;
 +        div->offset = init_info->offset;
 +        div->len = init_info->len;
 +    }
 +    if (init_info->public_name != NULL) {
 +        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
 +                init_info->public_name);
 +    }
 +}
 +
 +static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
 +        int index)
 +{
 +    switch (type) {
 +    case CLKSRC_REF:
 +        return clk->clkref;
 +    case CLKSRC_PLL:
 +        return clk->plls[index].clock_out;
 +    case CLKSRC_SEL:
 +        return clk->sels[index].clock_out;
 +    case CLKSRC_DIV:
 +        return clk->dividers[index].clock_out;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
 +{
 +    int i, j;
 +    Clock *src;
 +
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
 +                pll_init_info_list[i].src_index);
 +        clock_set_source(clk->plls[i].clock_in, src);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
 +            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
 +                    sel_init_info_list[i].src_index[j]);
 +            clock_set_source(clk->sels[i].clock_in[j], src);
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
 +                divider_init_info_list[i].src_index);
 +        clock_set_source(clk->dividers[i].clock_in, src);
 +    }
 +}
 +
  static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
  {
      uint32_t reg = offset / sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
           *
           * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
           */
 -        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
 +        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
          break;
      default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                  value |= (value & PLLCON_LOKS);
              }
          }
 +        /* Only update PLL when it is locked. */
 +        if (value & PLLCON_LOKI) {
 +            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
 +        }
 +        break;
 +
 +    case NPCM7XX_CLK_CLKSEL:
 +        npcm7xx_clk_update_all_sels(s);
 +        break;
 +
 +    case NPCM7XX_CLK_CLKDIV1:
 +    case NPCM7XX_CLK_CLKDIV2:
 +    case NPCM7XX_CLK_CLKDIV3:
 +        npcm7xx_clk_update_all_dividers(s);
          break;
      case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
      case RESET_TYPE_COLD:
          memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
          s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +        npcm7xx_clk_update_all_clocks(s);
          return;
      }
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
                    __func__, type);
  }
 +static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
 +{
 +    int i;
 +
 +    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
 +
 +    /* First pass: init all converter modules */
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
 +            != NPCM7XX_CLOCK_NR_DIVIDERS);
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
 +                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
 +        npcm7xx_init_clock_pll(&s->plls[i], s,
 +                &pll_init_info_list[i]);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
 +                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
 +        npcm7xx_init_clock_sel(&s->sels[i], s,
 +                &sel_init_info_list[i]);
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
 +                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
 +        npcm7xx_init_clock_divider(&s->dividers[i], s,
 +                &divider_init_info_list[i]);
 +    }
 +
 +    /* Second pass: connect converter modules */
 +    npcm7xx_connect_clocks(s);
 +
 +    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
 +}
 +
  static void npcm7xx_clk_init(Object *obj)
  {
      NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                            TYPE_NPCM7XX_CLK, 4 * KiB);
      sysbus_init_mmio(&s->parent, &s->iomem);
 -    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
 -            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
  }
 -static const VMStateDescription vmstate_npcm7xx_clk = {
 -    .name = "npcm7xx-clk",
 +static int npcm7xx_clk_post_load(void *opaque, int version_id)
 +{
 +    if (version_id >= 1) {
 +        NPCM7xxCLKState *clk = opaque;
 +
 +        npcm7xx_clk_update_all_clocks(clk);
 +    }
 +
 +    return 0;
 +}
 +
 +static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
 +{
 +    int i;
 +    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
 +
 +    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
 +            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 +    npcm7xx_clk_init_clock_hierarchy(s);
 +
 +    /* Realize child devices */
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
 +        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_pll = {
 +    .name = "npcm7xx-clock-pll",
      .version_id = 0,
      .minimum_version_id = 0,
 -    .fields = (VMStateField[]) {
 -        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 -        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
          VMSTATE_END_OF_LIST(),
      },
  };
 +static const VMStateDescription vmstate_npcm7xx_clk_sel = {
 +    .name = "npcm7xx-clock-sel",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
 +                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk_divider = {
 +    .name = "npcm7xx-clock-divider",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields =  (VMStateField[]) {
 +        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_clk = {
 +    .name = "npcm7xx-clk",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
-+    .fields      = (VMStateField[]) {
++    .post_load = npcm7xx_clk_post_load,
-+        VMSTATE_UINT32(cm_osc, IntegratorCMState),
++    .fields = (VMStateField[]) {
-+        VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
++        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
-+        VMSTATE_UINT32(cm_lock, IntegratorCMState),
++        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
-+        VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
++        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
-+        VMSTATE_UINT32(cm_sdram, IntegratorCMState),
++        VMSTATE_END_OF_LIST(),
-+        VMSTATE_UINT32(cm_init, IntegratorCMState),
++    },
 +        VMSTATE_UINT32(cm_flags, IntegratorCMState),
 +        VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
 +        VMSTATE_UINT32(int_level, IntegratorCMState),
 +        VMSTATE_UINT32(irq_enabled, IntegratorCMState),
 +        VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
- static uint64_t integratorcm_read(void *opaque, hwaddr offset,
++static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
-                                   unsigned size)
++{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock PLL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_pll;
 +}
 +
 +static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock SEL Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_sel;
 +}
 +
 +static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "NPCM7xx Clock Divider Module";
 +    dc->vmsd = &vmstate_npcm7xx_clk_divider;
 +}
 +
  static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
  {
-@@ -XXX,XX +XXX,XX @@ typedef struct icp_pic_state {
+     ResettableClass *rc = RESETTABLE_CLASS(klass);
-     qemu_irq parent_fiq;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
- } icp_pic_state;
+     dc->desc = "NPCM7xx Clock Control Registers";
-+static const VMStateDescription vmstate_icp_pic = {
+     dc->vmsd = &vmstate_npcm7xx_clk;
-+    .name = "icp_pic",
++    dc->realize = npcm7xx_clk_realize;
-+    .version_id = 1,
+     rc->phases.enter = npcm7xx_clk_enter_reset;
-+    .minimum_version_id = 1,
+ }
-+    .fields      = (VMStateField[]) {
-+        VMSTATE_UINT32(level, icp_pic_state),
++static const TypeInfo npcm7xx_clk_pll_info = {
-+        VMSTATE_UINT32(irq_enabled, icp_pic_state),
++    .name               = TYPE_NPCM7XX_CLOCK_PLL,
-+        VMSTATE_UINT32(fiq_enabled, icp_pic_state),
++    .parent             = TYPE_DEVICE,
-+        VMSTATE_END_OF_LIST()
++    .instance_size      = sizeof(NPCM7xxClockPLLState),
-+    }
++    .instance_init      = npcm7xx_clk_pll_init,
 +    .class_init         = npcm7xx_clk_pll_class_init,
 +};
 +
- static void icp_pic_update(icp_pic_state *s)
++static const TypeInfo npcm7xx_clk_sel_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_SEL,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockSELState),
 +    .instance_init      = npcm7xx_clk_sel_init,
 +    .class_init         = npcm7xx_clk_sel_class_init,
 +};
 +
 +static const TypeInfo npcm7xx_clk_divider_info = {
 +    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
 +    .parent             = TYPE_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxClockDividerState),
 +    .instance_init      = npcm7xx_clk_divider_init,
 +    .class_init         = npcm7xx_clk_divider_class_init,
 +};
 +
  static const TypeInfo npcm7xx_clk_info = {
      .name               = TYPE_NPCM7XX_CLK,
      .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
  static void npcm7xx_clk_register_type(void)
  {
-     uint32_t flags;
++    type_register_static(&npcm7xx_clk_pll_info);
-@@ -XXX,XX +XXX,XX @@ typedef struct ICPCtrlRegsState {
++    type_register_static(&npcm7xx_clk_sel_info);
- #define ICP_INTREG_WPROT        (1 << 0)
++    type_register_static(&npcm7xx_clk_divider_info);
- #define ICP_INTREG_CARDIN       (1 << 3)
+     type_register_static(&npcm7xx_clk_info);
 +static const VMStateDescription vmstate_icp_control = {
 +    .name = "icp_control",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields      = (VMStateField[]) {
 +        VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static uint64_t icp_control_read(void *opaque, hwaddr offset,
                                   unsigned size)
  {
@@ -XXX,XX +XXX,XX @@ static void core_class_init(ObjectClass *klass, void *data)
      dc->props = core_properties;
      dc->realize = integratorcm_realize;
 +    dc->vmsd = &vmstate_integratorcm;
 +}
 +
 +static void icp_pic_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->vmsd = &vmstate_icp_pic;
 +}
 +
 +static void icp_control_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->vmsd = &vmstate_icp_control;
  }
+ type_init(npcm7xx_clk_register_type);
  static const TypeInfo core_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_pic_info = {
      .parent        = TYPE_SYS_BUS_DEVICE,
      .instance_size = sizeof(icp_pic_state),
      .instance_init = icp_pic_init,
 +    .class_init    = icp_pic_class_init,
  };
  static const TypeInfo icp_ctrl_regs_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_ctrl_regs_info = {
      .parent        = TYPE_SYS_BUS_DEVICE,
      .instance_size = sizeof(ICPCtrlRegsState),
      .instance_init = icp_control_init,
 +    .class_init    = icp_control_class_init,
  };
  static void integratorcp_register_types(void)
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 10/13] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
+[PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock
-Add support for generating the ISS (Instruction Specific Syndrome)
+From: Hao Wu <wuhaotsh@google.com>
 for Data Abort exceptions taken from AArch32. These syndromes are
 used by hypervisors for example to trap and emulate memory accesses.
-This is the equivalent for AArch32 guests of the work done for AArch64
+This patch makes NPCM7XX Timer to use a the timer clock generated by the
-guests in commit aaa1f954d4cab243.
+CLK module instead of the magic number TIMER_REF_HZ.
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Message-id: 20210108190945.949196-3-wuhaotsh@google.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 ---
- target/arm/translate.h     |  14 ++++
+ include/hw/misc/npcm7xx_clk.h    |  6 -----
- target/arm/translate-a64.c |  14 ----
+ include/hw/timer/npcm7xx_timer.h |  1 +
- target/arm/translate.c     | 184 +++++++++++++++++++++++++++++++++------------
+ hw/arm/npcm7xx.c                 |  5 ++++
-files changed, 149 insertions(+), 63 deletions(-)
+ hw/timer/npcm7xx_timer.c         | 39 +++++++++++++++-----------------
 files changed, 24 insertions(+), 27 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/include/hw/misc/npcm7xx_clk.h
-+++ b/target/arm/translate.h
++++ b/include/hw/misc/npcm7xx_clk.h
-@@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@
-             ? 3 : MAX(1, s->current_el);
+ #include "hw/clock.h"
  #include "hw/sysbus.h"
 -/*
 - * The reference clock frequency for the timer modules, and the SECCNT and
 - * CNTR25M registers in this module, is always 25 MHz.
 - */
 -#define NPCM7XX_TIMER_REF_HZ            (25000000)
 -
  /*
   * Number of registers in our device state structure. Don't change this without
   * incrementing the version_id in the vmstate.
 diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/timer/npcm7xx_timer.h
 +++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
      uint32_t    tisr;
 +    Clock       *clock;
      NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
      NPCM7xxWatchdogTimer watchdog_timer;
  };
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/char/serial.h"
  #include "hw/loader.h"
  #include "hw/misc/unimp.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
  #include "qapi/error.h"
  #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
          int first_irq;
          int j;
 +        /* Connect the timer clock. */
 +        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
 +                    DEVICE(&s->clk), "timer-clock"));
 +
          sysbus_realize(sbd, &error_abort);
          sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/npcm7xx_timer.c
 +++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/irq.h"
 +#include "hw/qdev-clock.h"
  #include "hw/qdev-properties.h"
 -#include "hw/misc/npcm7xx_clk.h"
  #include "hw/timer/npcm7xx_timer.h"
  #include "migration/vmstate.h"
  #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
  /* Convert a timer cycle count to a time interval in nanoseconds. */
  static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
  {
 -    int64_t ns = count;
 +    int64_t ticks = count;
 -    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
 -    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
 +    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 -    return ns;
 +    return clock_ticks_to_ns(t->ctrl->clock, ticks);
  }
-+static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+ /* Convert a time interval in nanoseconds to a timer cycle count. */
-+{
+ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
-+    /* We don't need to save all of the syndrome so we mask and shift
+ {
-+     * out unneeded bits to help the sleb128 encoder do a better job.
+-    int64_t count;
-+     */
+-
-+    syn &= ARM_INSN_START_WORD2_MASK;
+-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
-+    syn >>= ARM_INSN_START_WORD2_SHIFT;
+-    count /= npcm7xx_tcsr_prescaler(t->tcsr);
-+
+-
-+    /* We check and clear insn_start_idx to catch multiple updates.  */
+-    return count;
-+    assert(s->insn_start_idx != 0);
++    return ns / clock_ticks_to_ns(t->ctrl->clock,
-+    tcg_set_insn_param(s->insn_start_idx, 2, syn);
++                                  npcm7xx_tcsr_prescaler(t->tcsr));
 +    s->insn_start_idx = 0;
 +}
 +
  /* target-specific extra values for is_jmp */
  /* These instructions trap after executing, so the A32/T32 decoder must
   * defer them until after the conditional execution state has been updated.
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
      }
  }
--static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
--{
+@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
--    /* We don't need to save all of the syndrome so we mask and shift
+ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
--     * out uneeded bits to help the sleb128 encoder do a better job.
+         int64_t cycles)
 -     */
 -    syn &= ARM_INSN_START_WORD2_MASK;
 -    syn >>= ARM_INSN_START_WORD2_SHIFT;
 -
 -    /* We check and clear insn_start_idx to catch multiple updates.  */
 -    assert(s->insn_start_idx != 0);
 -    tcg_set_insn_param(s->insn_start_idx, 2, syn);
 -    s->insn_start_idx = 0;
 -}
 -
  static void unallocated_encoding(DisasContext *s)
  {
-     /* Unallocated and reserved encodings are uncategorized */
+-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
-index XXXXXXX..XXXXXXX 100644
++    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
---- a/target/arm/translate.c
++    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
+     /*
-     a64_translate_init();
+      * The reset function always clears the current timer. The caller of the
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
       */
      npcm7xx_timer_clear(&t->base_timer);
 -    ns *= prescaler;
      t->base_timer.remaining_ns = ns;
  }
-+/* Flags for the disas_set_da_iss info argument:
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
-+ * lower bits hold the Rt register number, higher bits are flags.
+     qemu_irq_lower(s->watchdog_timer.irq);
-+ */
+ }
-+typedef enum ISSInfo {
-+    ISSNone = 0,
+-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-+    ISSRegMask = 0x1f,
++static void npcm7xx_timer_init(Object *obj)
 +    ISSInvalid = (1 << 5),
 +    ISSIsAcqRel = (1 << 6),
 +    ISSIsWrite = (1 << 7),
 +    ISSIs16Bit = (1 << 8),
 +} ISSInfo;
 +
 +/* Save the syndrome information for a Data Abort */
 +static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
 +{
 +    uint32_t syn;
 +    int sas = memop & MO_SIZE;
 +    bool sse = memop & MO_SIGN;
 +    bool is_acqrel = issinfo & ISSIsAcqRel;
 +    bool is_write = issinfo & ISSIsWrite;
 +    bool is_16bit = issinfo & ISSIs16Bit;
 +    int srt = issinfo & ISSRegMask;
 +
 +    if (issinfo & ISSInvalid) {
 +        /* Some callsites want to conditionally provide ISS info,
 +         * eg "only if this was not a writeback"
 +         */
 +        return;
 +    }
 +
 +    if (srt == 15) {
 +        /* For AArch32, insns where the src/dest is R15 never generate
 +         * ISS information. Catching that here saves checking at all
 +         * the call sites.
 +         */
 +        return;
 +    }
 +
 +    syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,
 +                                  0, 0, 0, is_write, 0, is_16bit);
 +    disas_set_insn_syndrome(s, syn);
 +}
 +
  static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
  {
-     /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
+-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val,      \
+-    SysBusDevice *sbd = &s->parent;
-                                      TCGv_i32 a32, int index)            \
++    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
- {                                                                        \
++    DeviceState *dev = DEVICE(obj);
-     gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
++    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-+}                                                                        \
+     int i;
-+static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s,              \
+     NPCM7xxWatchdogTimer *w;
-+                                           TCGv_i32 val,                 \
-+                                           TCGv_i32 a32, int index,      \
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
-+                                           ISSInfo issinfo)              \
+             npcm7xx_watchdog_timer_expired, w);
-+{                                                                        \
+     sysbus_init_irq(sbd, &w->irq);
-+    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
-+    disas_set_da_iss(s, OPC, issinfo);                                   \
+-    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
                            TYPE_NPCM7XX_TIMER, 4 * KiB);
      sysbus_init_mmio(sbd, &s->iomem);
      qdev_init_gpio_out_named(dev, &w->reset_signal,
              NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
 +    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
  }
- #define DO_GEN_ST(SUFF, OPC)                                             \
+ static const VMStateDescription vmstate_npcm7xx_base_timer = {
-@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val,      \
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
-                                      TCGv_i32 a32, int index)            \
- {                                                                        \
+ static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
-     gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
+     .name = "npcm7xx-timer-ctrl",
-+}                                                                        \
+-    .version_id = 1,
-+static inline void gen_aa32_st##SUFF##_iss(DisasContext *s,              \
+-    .minimum_version_id = 1,
-+                                           TCGv_i32 val,                 \
++    .version_id = 2,
-+                                           TCGv_i32 a32, int index,      \
++    .minimum_version_id = 2,
-+                                           ISSInfo issinfo)              \
+     .fields = (VMStateField[]) {
-+{                                                                        \
+         VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
-+    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
++        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
-+    disas_set_da_iss(s, OPC, issinfo | ISSIsWrite);                      \
+         VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
- }
+                              NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
+                              NPCM7xxTimer),
- static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+     QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
-                                 tmp = tcg_temp_new_i32();
-                                 switch (op1) {
+     dc->desc = "NPCM7xx Timer Controller";
-                                 case 0: /* lda */
+-    dc->realize = npcm7xx_timer_realize;
--                                    gen_aa32_ld32u(s, tmp, addr,
+     dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
--                                                   get_mem_index(s));
+     rc->phases.enter = npcm7xx_timer_enter_reset;
-+                                    gen_aa32_ld32u_iss(s, tmp, addr,
+     rc->phases.hold = npcm7xx_timer_hold_reset;
-+                                                       get_mem_index(s),
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
-+                                                       rd | ISSIsAcqRel);
+     .parent             = TYPE_SYS_BUS_DEVICE,
-                                     break;
+     .instance_size      = sizeof(NPCM7xxTimerCtrlState),
-                                 case 2: /* ldab */
+     .class_init         = npcm7xx_timer_class_init,
--                                    gen_aa32_ld8u(s, tmp, addr,
++    .instance_init      = npcm7xx_timer_init,
--                                                  get_mem_index(s));
+ };
-+                                    gen_aa32_ld8u_iss(s, tmp, addr,
-+                                                      get_mem_index(s),
+ static void npcm7xx_timer_register_type(void)
 +                                                      rd | ISSIsAcqRel);
                                      break;
                                  case 3: /* ldah */
 -                                    gen_aa32_ld16u(s, tmp, addr,
 -                                                   get_mem_index(s));
 +                                    gen_aa32_ld16u_iss(s, tmp, addr,
 +                                                       get_mem_index(s),
 +                                                       rd | ISSIsAcqRel);
                                      break;
                                  default:
                                      abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                  tmp = load_reg(s, rm);
                                  switch (op1) {
                                  case 0: /* stl */
 -                                    gen_aa32_st32(s, tmp, addr,
 -                                                  get_mem_index(s));
 +                                    gen_aa32_st32_iss(s, tmp, addr,
 +                                                      get_mem_index(s),
 +                                                      rm | ISSIsAcqRel);
                                      break;
                                  case 2: /* stlb */
 -                                    gen_aa32_st8(s, tmp, addr,
 -                                                 get_mem_index(s));
 +                                    gen_aa32_st8_iss(s, tmp, addr,
 +                                                     get_mem_index(s),
 +                                                     rm | ISSIsAcqRel);
                                      break;
                                  case 3: /* stlh */
 -                                    gen_aa32_st16(s, tmp, addr,
 -                                                  get_mem_index(s));
 +                                    gen_aa32_st16_iss(s, tmp, addr,
 +                                                      get_mem_index(s),
 +                                                      rm | ISSIsAcqRel);
                                      break;
                                  default:
                                      abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                  bool wbit = insn & (1 << 21);
                  bool pbit = insn & (1 << 24);
                  bool doubleword = false;
 +                ISSInfo issinfo;
 +
                  /* Misc load/store */
                  rn = (insn >> 16) & 0xf;
                  rd = (insn >> 12) & 0xf;
 +                /* ISS not valid if writeback */
 +                issinfo = (pbit & !wbit) ? rd : ISSInvalid;
 +
                  if (!load && (sh & 2)) {
                      /* doubleword */
                      ARCH(5TE);
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                      tmp = tcg_temp_new_i32();
                      switch (sh) {
                      case 1:
 -                        gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +                        gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
 +                                           issinfo);
                          break;
                      case 2:
 -                        gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
 +                        gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
 +                                          issinfo);
                          break;
                      default:
                      case 3:
 -                        gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
 +                        gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
 +                                           issinfo);
                          break;
                      }
                  } else {
                      /* store */
                      tmp = load_reg(s, rd);
 -                    gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +                    gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
                      tcg_temp_free_i32(tmp);
                  }
                  /* Perform base writeback before the loaded value to
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                  /* load */
                  tmp = tcg_temp_new_i32();
                  if (insn & (1 << 22)) {
 -                    gen_aa32_ld8u(s, tmp, tmp2, i);
 +                    gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
                  } else {
 -                    gen_aa32_ld32u(s, tmp, tmp2, i);
 +                    gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
                  }
              } else {
                  /* store */
                  tmp = load_reg(s, rd);
                  if (insn & (1 << 22)) {
 -                    gen_aa32_st8(s, tmp, tmp2, i);
 +                    gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
                  } else {
 -                    gen_aa32_st32(s, tmp, tmp2, i);
 +                    gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
                  }
                  tcg_temp_free_i32(tmp);
              }
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                          tmp = tcg_temp_new_i32();
                          switch (op) {
                          case 0: /* ldab */
 -                            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
 +                                              rs | ISSIsAcqRel);
                              break;
                          case 1: /* ldah */
 -                            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
 +                                               rs | ISSIsAcqRel);
                              break;
                          case 2: /* lda */
 -                            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
 +                                               rs | ISSIsAcqRel);
                              break;
                          default:
                              abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                          tmp = load_reg(s, rs);
                          switch (op) {
                          case 0: /* stlb */
 -                            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
 +                                             rs | ISSIsAcqRel);
                              break;
                          case 1: /* stlh */
 -                            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
 +                                              rs | ISSIsAcqRel);
                              break;
                          case 2: /* stl */
 -                            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
 +                                              rs | ISSIsAcqRel);
                              break;
                          default:
                              abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
          int postinc = 0;
          int writeback = 0;
          int memidx;
 +        ISSInfo issinfo;
 +
          if ((insn & 0x01100000) == 0x01000000) {
              if (disas_neon_ls_insn(s, insn)) {
                  goto illegal_op;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                  }
              }
          }
 +
 +        issinfo = writeback ? ISSInvalid : rs;
 +
          if (insn & (1 << 20)) {
              /* Load.  */
              tmp = tcg_temp_new_i32();
              switch (op) {
              case 0:
 -                gen_aa32_ld8u(s, tmp, addr, memidx);
 +                gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 4:
 -                gen_aa32_ld8s(s, tmp, addr, memidx);
 +                gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 1:
 -                gen_aa32_ld16u(s, tmp, addr, memidx);
 +                gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 5:
 -                gen_aa32_ld16s(s, tmp, addr, memidx);
 +                gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 2:
 -                gen_aa32_ld32u(s, tmp, addr, memidx);
 +                gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
                  break;
              default:
                  tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
              tmp = load_reg(s, rs);
              switch (op) {
              case 0:
 -                gen_aa32_st8(s, tmp, addr, memidx);
 +                gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 1:
 -                gen_aa32_st16(s, tmp, addr, memidx);
 +                gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 2:
 -                gen_aa32_st32(s, tmp, addr, memidx);
 +                gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
                  break;
              default:
                  tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
              addr = tcg_temp_new_i32();
              tcg_gen_movi_i32(addr, val);
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
 +                               rd | ISSIs16Bit);
              tcg_temp_free_i32(addr);
              store_reg(s, rd, tmp);
              break;
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          switch (op) {
          case 0: /* str */
 -            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 1: /* strh */
 -            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 2: /* strb */
 -            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 3: /* ldrsb */
 -            gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 4: /* ldr */
 -            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 5: /* ldrh */
 -            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 6: /* ldrb */
 -            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 7: /* ldrsh */
 -            gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          }
          if (op >= 3) { /* load */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          if (insn & (1 << 11)) {
              /* load */
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              store_reg(s, rd, tmp);
          } else {
              /* store */
              tmp = load_reg(s, rd);
 -            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              tcg_temp_free_i32(tmp);
          }
          tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          if (insn & (1 << 11)) {
              /* load */
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              store_reg(s, rd, tmp);
          } else {
              /* store */
              tmp = load_reg(s, rd);
 -            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              tcg_temp_free_i32(tmp);
          }
          tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          if (insn & (1 << 11)) {
              /* load */
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              store_reg(s, rd, tmp);
          } else {
              /* store */
              tmp = load_reg(s, rd);
 -            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              tcg_temp_free_i32(tmp);
          }
          tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
          store_cpu_field(tmp, condexec_bits);
        }
      do {
 +        dc->insn_start_idx = tcg_op_buf_count();
          tcg_gen_insn_start(dc->pc,
                             (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
 );
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 12/13] hw/misc: New "unimplemented" sysbus device
+[PULL 17/21] hw/adc: Add an ADC module for NPCM7XX
-Create a new "unimplemented" sysbus device, which simply accepts
+From: Hao Wu <wuhaotsh@google.com>
 all read and write accesses, and implements them as read-as-zero,
 write-ignored, with logging of the access as LOG_UNIMP.
-This is useful for stubbing out bits of an SoC or board model
+The ADC is part of NPCM7XX Module. Its behavior is controled by the
-which haven't been written yet.
+ADC_CON register. It converts one of the eight analog inputs into a
 digital input and stores it in the ADC_DATA register when enabled.
+Users can alter input value by using qom-set QMP command.
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Message-id: 20210108190945.949196-4-wuhaotsh@google.com
+[PMM: Added missing hw/adc/trace.h file]
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org
 ---
- hw/misc/Makefile.objs   |   2 +
+ docs/system/arm/nuvoton.rst    |   2 +-
- include/hw/misc/unimp.h |  39 ++++++++++++++++++
+ meson.build                    |   1 +
- hw/misc/unimp.c         | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
+ hw/adc/trace.h                 |   1 +
-files changed, 148 insertions(+)
+ include/hw/adc/npcm7xx_adc.h   |  69 ++++++
- create mode 100644 include/hw/misc/unimp.h
+ include/hw/arm/npcm7xx.h       |   2 +
- create mode 100644 hw/misc/unimp.c
+ hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
  hw/arm/npcm7xx.c               |  24 ++-
  tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
  hw/adc/meson.build             |   1 +
  hw/adc/trace-events            |   5 +
  tests/qtest/meson.build        |   3 +-
 files changed, 783 insertions(+), 3 deletions(-)
  create mode 100644 hw/adc/trace.h
  create mode 100644 include/hw/adc/npcm7xx_adc.h
  create mode 100644 hw/adc/npcm7xx_adc.c
  create mode 100644 tests/qtest/npcm7xx_adc-test.c
  create mode 100644 hw/adc/trace-events
-diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/docs/system/arm/nuvoton.rst
-+++ b/hw/misc/Makefile.objs
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
+@@ -XXX,XX +XXX,XX @@ Supported devices
- common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
+  * Random Number Generator (RNG)
- common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
+  * USB host (USBH)
+  * GPIO controller
-+common-obj-y += unimp.o
++ * Analog to Digital Converter (ADC)
-+
- obj-$(CONFIG_VMPORT) += vmport.o
+ Missing devices
+ ---------------
- # ARM devices
+@@ -XXX,XX +XXX,XX @@ Missing devices
-diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
+  * USB device (USBD)
   * SMBus controller (SMBF)
   * Peripheral SPI controller (PSPI)
 - * Analog to Digital Converter (ADC)
   * SD/MMC host
   * PECI interface
   * Pulse Width Modulation (PWM)
 diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/meson.build
 +++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
      'chardev',
      'hw/9pfs',
      'hw/acpi',
 +    'hw/adc',
      'hw/alpha',
      'hw/arm',
      'hw/audio',
 diff --git a/hw/adc/trace.h b/hw/adc/trace.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/misc/unimp.h
++++ b/hw/adc/trace.h
-@@ -XXX,XX +XXX,XX @@
+@@ -0,0 +1 @@
-+/*
++#include "trace/trace-hw_adc.h"
-+ * "Unimplemented" device
+diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
 + *
 + * Copyright Linaro Limited, 2017
 + * Written by Peter Maydell
 + */
 +
 +#ifndef HW_MISC_UNIMP_H
 +#define HW_MISC_UNIMP_H
 +
 +#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
 +
 +/**
 + * create_unimplemented_device: create and map a dummy device
 + * @name: name of the device for debug logging
 + * @base: base address of the device's MMIO region
 + * @size: size of the device's MMIO region
 + *
 + * This utility function creates and maps an instance of unimplemented-device,
 + * which is a dummy device which simply logs all guest accesses to
 + * it via the qemu_log LOG_UNIMP debug log.
 + * The device is mapped at priority -1000, which means that you can
 + * use it to cover a large region and then map other devices on top of it
 + * if necessary.
 + */
 +static inline void create_unimplemented_device(const char *name,
 +                                               hwaddr base,
 +                                               hwaddr size)
 +{
 +    DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
 +
 +    qdev_prop_set_string(dev, "name", name);
 +    qdev_prop_set_uint64(dev, "size", size);
 +    qdev_init_nofail(dev);
 +
 +    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
 +}
 +
 +#endif
 diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/misc/unimp.c
++++ b/include/hw/adc/npcm7xx_adc.h
 @@ -XXX,XX +XXX,XX @@
-+/* "Unimplemented" device
++/*
 + * Nuvoton NPCM7xx ADC Module
 + *
-+ * This is a dummy device which accepts and logs all accesses.
++ * Copyright 2020 Google LLC
 + * It's useful for stubbing out regions of an SoC or board
 + * map which correspond to devices that have not yet been
 + * implemented. This is often sufficient to placate initial
 + * guest device driver probing such that the system will
 + * come up.
 + *
-+ * Copyright Linaro Limited, 2017
++ * This program is free software; you can redistribute it and/or modify it
-+ * Written by Peter Maydell
++ * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
++#ifndef NPCM7XX_ADC_H
++#define NPCM7XX_ADC_H
++
++#include "hw/clock.h"
++#include "hw/irq.h"
++#include "hw/sysbus.h"
++#include "qemu/timer.h"
++
++#define NPCM7XX_ADC_NUM_INPUTS      8
++/**
++ * This value should not be changed unless write_adc_calibration function in
++ * hw/arm/npcm7xx.c is also changed.
++ */
++#define NPCM7XX_ADC_NUM_CALIB       2
++
++/**
++ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
++ * @parent: System bus device.
++ * @iomem: Memory region through which registers are accessed.
++ * @conv_timer: The timer counts down remaining cycles for the conversion.
++ * @irq: GIC interrupt line to fire on expiration (if enabled).
++ * @con: The Control Register.
++ * @data: The Data Buffer.
++ * @clock: The ADC Clock.
++ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
++ * @vref: The external reference voltage.
++ * @iref: The internal reference voltage, initialized at launch time.
++ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
++ */
++typedef struct {
++    SysBusDevice parent;
++
++    MemoryRegion iomem;
++
++    QEMUTimer    conv_timer;
++
++    qemu_irq     irq;
++    uint32_t     con;
++    uint32_t     data;
++    Clock       *clock;
++
++    /* Voltages are in unit of uV. 1V = 1000000uV. */
++    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
++    uint32_t     vref;
++    uint32_t     iref;
++
++    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
++} NPCM7xxADCState;
++
++#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
++#define NPCM7XX_ADC(obj) \
++    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
++
++#endif /* NPCM7XX_ADC_H */
+diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/npcm7xx.h
++++ b/include/hw/arm/npcm7xx.h
+@@ -XXX,XX +XXX,XX @@
+ #define NPCM7XX_H
+ #include "hw/boards.h"
++#include "hw/adc/npcm7xx_adc.h"
+ #include "hw/cpu/a9mpcore.h"
+ #include "hw/gpio/npcm7xx_gpio.h"
+ #include "hw/mem/npcm7xx_mc.h"
+@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
+     NPCM7xxGCRState     gcr;
+     NPCM7xxCLKState     clk;
+     NPCM7xxTimerCtrlState tim[3];
++    NPCM7xxADCState     adc;
+     NPCM7xxOTPState     key_storage;
+     NPCM7xxOTPState     fuse_array;
+     NPCM7xxMCState      mc;
+diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/adc/npcm7xx_adc.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton NPCM7xx ADC Module
++ *
++ * Copyright 2020 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
 +
 +#include "qemu/osdep.h"
-+#include "hw/hw.h"
++#include "hw/adc/npcm7xx_adc.h"
-+#include "hw/sysbus.h"
++#include "hw/qdev-clock.h"
-+#include "hw/misc/unimp.h"
++#include "hw/qdev-properties.h"
 +#include "hw/registerfields.h"
 +#include "migration/vmstate.h"
 +#include "qemu/log.h"
-+#include "qapi/error.h"
++#include "qemu/module.h"
-+
++#include "qemu/timer.h"
-+#define UNIMPLEMENTED_DEVICE(obj) \
++#include "qemu/units.h"
-+    OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)
++#include "trace.h"
 +
-+typedef struct {
++REG32(NPCM7XX_ADC_CON, 0x0)
-+    SysBusDevice parent_obj;
++REG32(NPCM7XX_ADC_DATA, 0x4)
-+    MemoryRegion iomem;
++
-+    char *name;
++/* Register field definitions. */
-+    uint64_t size;
++#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
-+} UnimplementedDeviceState;
++#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
-+
++#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
-+static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
++#define NPCM7XX_ADC_CON_INT     BIT(18)
-+{
++#define NPCM7XX_ADC_CON_EN      BIT(17)
-+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
++#define NPCM7XX_ADC_CON_RST     BIT(16)
-+
++#define NPCM7XX_ADC_CON_CONV    BIT(14)
-+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
++#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
-+                  "(size %d, offset 0x%" HWADDR_PRIx ")\n",
++
-+                  s->name, size, offset);
++#define NPCM7XX_ADC_MAX_RESULT      1023
-+    return 0;
++#define NPCM7XX_ADC_DEFAULT_IREF    2000000
-+}
++#define NPCM7XX_ADC_CONV_CYCLES     20
-+
++#define NPCM7XX_ADC_RESET_CYCLES    10
-+static void unimp_write(void *opaque, hwaddr offset,
++#define NPCM7XX_ADC_R0_INPUT        500000
-+                        uint64_t value, unsigned size)
++#define NPCM7XX_ADC_R1_INPUT        1500000
-+{
++
-+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
++static void npcm7xx_adc_reset(NPCM7xxADCState *s)
-+
++{
-+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
++    timer_del(&s->conv_timer);
-+                  "(size %d, value 0x%" PRIx64
++    s->con = 0x000c0001;
-+                  ", offset 0x%" HWADDR_PRIx ")\n",
++    s->data = 0x00000000;
-+                  s->name, size, value, offset);
++}
-+}
++
-+
++static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
-+static const MemoryRegionOps unimp_ops = {
++{
-+    .read = unimp_read,
++    uint32_t result;
-+    .write = unimp_write,
++
-+    .impl.min_access_size = 1,
++    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
-+    .impl.max_access_size = 8,
++    if (result > NPCM7XX_ADC_MAX_RESULT) {
-+    .valid.min_access_size = 1,
++        result = NPCM7XX_ADC_MAX_RESULT;
-+    .valid.max_access_size = 8,
++    }
-+    .endianness = DEVICE_NATIVE_ENDIAN,
++
 +    return result;
 +}
 +
 +static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
 +{
 +    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
 +}
 +
 +static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
 +        uint32_t cycles, uint32_t prescaler)
 +{
 +    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    int64_t ticks = cycles;
 +    int64_t ns;
 +
 +    ticks *= prescaler;
 +    ns = clock_ticks_to_ns(clk, ticks);
 +    ns += now;
 +    timer_mod(timer, ns);
 +}
 +
 +static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
 +{
 +    uint32_t prescaler = npcm7xx_adc_prescaler(s);
 +
 +    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
 +            prescaler);
 +}
 +
 +static void npcm7xx_adc_convert_done(void *opaque)
 +{
 +    NPCM7xxADCState *s = opaque;
 +    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
 +    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
 +        ? s->iref : s->vref;
 +
 +    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
 +                      __func__, input);
 +        return;
 +    }
 +    s->data = npcm7xx_adc_convert(s->adci[input], ref);
 +    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
 +        s->con |= NPCM7XX_ADC_CON_INT;
 +        qemu_irq_raise(s->irq);
 +    }
 +    s->con &= ~NPCM7XX_ADC_CON_CONV;
 +}
 +
 +static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
 +{
 +    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
 +            adc->iref);
 +    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
 +            adc->iref);
 +}
 +
 +static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
 +{
 +    uint32_t old_con = s->con;
 +
 +    /* Write ADC_INT to 1 to clear it */
 +    if (new_con & NPCM7XX_ADC_CON_INT) {
 +        new_con &= ~NPCM7XX_ADC_CON_INT;
 +        qemu_irq_lower(s->irq);
 +    } else if (old_con & NPCM7XX_ADC_CON_INT) {
 +        new_con |= NPCM7XX_ADC_CON_INT;
 +    }
 +
 +    s->con = new_con;
 +
 +    if (s->con & NPCM7XX_ADC_CON_RST) {
 +        npcm7xx_adc_reset(s);
 +        return;
 +    }
 +
 +    if ((s->con & NPCM7XX_ADC_CON_EN)) {
 +        if (s->con & NPCM7XX_ADC_CON_CONV) {
 +            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
 +                npcm7xx_adc_start_convert(s);
 +            }
 +        } else {
 +            timer_del(&s->conv_timer);
 +        }
 +    }
 +}
 +
 +static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint64_t value = 0;
 +    NPCM7xxADCState *s = opaque;
 +
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        value = s->con;
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        value = s->data;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
 +    return value;
 +}
 +
 +static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
 +        unsigned size)
 +{
 +    NPCM7xxADCState *s = opaque;
 +
 +    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
 +    switch (offset) {
 +    case A_NPCM7XX_ADC_CON:
 +        npcm7xx_adc_write_con(s, v);
 +        break;
 +
 +    case A_NPCM7XX_ADC_DATA:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_adc_ops = {
 +    .read       = npcm7xx_adc_read,
 +    .write      = npcm7xx_adc_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
-+static void unimp_realize(DeviceState *dev, Error **errp)
++static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
 +{
-+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);
++    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
 +
-+    if (s->size == 0) {
++    npcm7xx_adc_reset(s);
-+        error_setg(errp, "property 'size' not specified or zero");
++}
-+        return;
++
-+    }
++static void npcm7xx_adc_hold_reset(Object *obj)
-+
++{
-+    if (s->name == NULL) {
++    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
-+        error_setg(errp, "property 'name' not specified");
++
-+        return;
++    qemu_irq_lower(s->irq);
-+    }
++}
 +
-+    memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
++static void npcm7xx_adc_init(Object *obj)
-+                          s->name, s->size);
++{
-+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
++    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
-+}
++    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-+
++    int i;
-+static Property unimp_properties[] = {
++
-+    DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),
++    sysbus_init_irq(sbd, &s->irq);
-+    DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),
++
 +    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
 +            npcm7xx_adc_convert_done, s);
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
 +                          TYPE_NPCM7XX_ADC, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
 +        object_property_add_uint32_ptr(obj, "adci[*]",
 +                &s->adci[i], OBJ_PROP_FLAG_WRITE);
 +    }
 +    object_property_add_uint32_ptr(obj, "vref",
 +            &s->vref, OBJ_PROP_FLAG_WRITE);
 +    npcm7xx_adc_calibrate(s);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_adc = {
 +    .name = "npcm7xx-adc",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
 +        VMSTATE_UINT32(con, NPCM7xxADCState),
 +        VMSTATE_UINT32(data, NPCM7xxADCState),
 +        VMSTATE_CLOCK(clock, NPCM7xxADCState),
 +        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
 +        VMSTATE_UINT32(vref, NPCM7xxADCState),
 +        VMSTATE_UINT32(iref, NPCM7xxADCState),
 +        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
 +                NPCM7XX_ADC_NUM_CALIB),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static Property npcm7xx_timer_properties[] = {
 +    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
-+static void unimp_class_init(ObjectClass *klass, void *data)
++static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
-+    dc->realize = unimp_realize;
++    dc->desc = "NPCM7xx ADC Module";
-+    dc->props = unimp_properties;
++    dc->vmsd = &vmstate_npcm7xx_adc;
-+}
++    rc->phases.enter = npcm7xx_adc_enter_reset;
-+
++    rc->phases.hold = npcm7xx_adc_hold_reset;
-+static const TypeInfo unimp_info = {
++
-+    .name = TYPE_UNIMPLEMENTED_DEVICE,
++    device_class_set_props(dc, npcm7xx_timer_properties);
-+    .parent = TYPE_SYS_BUS_DEVICE,
++}
-+    .instance_size = sizeof(UnimplementedDeviceState),
++
-+    .class_init = unimp_class_init,
++static const TypeInfo npcm7xx_adc_info = {
 +    .name               = TYPE_NPCM7XX_ADC,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxADCState),
 +    .class_init         = npcm7xx_adc_class_init,
 +    .instance_init      = npcm7xx_adc_init,
 +};
 +
-+static void unimp_register_types(void)
++static void npcm7xx_adc_register_types(void)
 +{
-+    type_register_static(&unimp_info);
++    type_register_static(&npcm7xx_adc_info);
 +}
 +
-+type_init(unimp_register_types)
++type_init(npcm7xx_adc_register_types);
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_EHCI_BA         (0xf0806000)
  #define NPCM7XX_OHCI_BA         (0xf0807000)
 +/* ADC Module */
 +#define NPCM7XX_ADC_BA          (0xf000c000)
 +
  /* Internal AHB SRAM */
  #define NPCM7XX_RAM3_BA         (0xc0008000)
  #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_ROM_BA          (0xffff0000)
  #define NPCM7XX_ROM_SZ          (64 * KiB)
 +
  /* Clock configuration values to be fixed up when bypassing bootloader */
  /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
   * interrupts.
   */
  enum NPCM7xxInterrupt {
 +    NPCM7XX_ADC_IRQ             = 0,
      NPCM7XX_UART0_IRQ           = 2,
      NPCM7XX_UART1_IRQ,
      NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                              sizeof(value));
  }
 +static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
 +{
 +    /* Both ADC and the fuse array must have realized. */
 +    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
 +    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
 +            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
 +}
 +
  static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
  {
      return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                              TYPE_NPCM7XX_FUSE_ARRAY);
      object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
      object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
 +    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
          object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 +    /* ADC Modules. Cannot fail. */
 +    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
 +                          DEVICE(&s->clk), "adc-clock"));
 +    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
 +            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
 +    npcm7xx_write_adc_calibration(s);
 +
      /* Timer Modules (TIM). Cannot fail. */
      QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
      create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
      create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
      create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
 diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTests for Nuvoton NPCM7xx ADCModules.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/timer.h"
 +#include "libqos/libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +
 +#define REF_HZ          (25000000)
 +
 +#define CON_OFFSET      0x0
 +#define DATA_OFFSET     0x4
 +
 +#define NUM_INPUTS      8
 +#define DEFAULT_IREF    2000000
 +#define CONV_CYCLES     20
 +#define RESET_CYCLES    10
 +#define R0_INPUT        500000
 +#define R1_INPUT        1500000
 +#define MAX_RESULT      1023
 +
 +#define DEFAULT_CLKDIV  5
 +
 +#define FUSE_ARRAY_BA   0xf018a000
 +#define FCTL_OFFSET     0x14
 +#define FST_OFFSET      0x0
 +#define FADDR_OFFSET    0x4
 +#define FDATA_OFFSET    0x8
 +#define ADC_CALIB_ADDR  24
 +#define FUSE_READ       0x2
 +
 +/* Register field definitions. */
 +#define CON_MUX(rv) ((rv) << 24)
 +#define CON_INT_EN  BIT(21)
 +#define CON_REFSEL  BIT(19)
 +#define CON_INT     BIT(18)
 +#define CON_EN      BIT(17)
 +#define CON_RST     BIT(16)
 +#define CON_CONV    BIT(14)
 +#define CON_DIV(rv) extract32(rv, 1, 8)
 +
 +#define FST_RDST    BIT(1)
 +#define FDATA_MASK  0xff
 +
 +#define MAX_ERROR   10000
 +#define MIN_CALIB_INPUT 100000
 +#define MAX_CALIB_INPUT 1800000
 +
 +static const uint32_t input_list[] = {
 +    100000,
 +    500000,
 +    1000000,
 +    1500000,
 +    1800000,
 +    2000000,
 +};
 +
 +static const uint32_t vref_list[] = {
 +    2000000,
 +    2200000,
 +    2500000,
 +};
 +
 +static const uint32_t iref_list[] = {
 +    1800000,
 +    1900000,
 +    2000000,
 +    2100000,
 +    2200000,
 +};
 +
 +static const uint32_t div_list[] = {0, 1, 3, 7, 15};
 +
 +typedef struct ADC {
 +    int irq;
 +    uint64_t base_addr;
 +} ADC;
 +
 +ADC adc = {
 +    .irq        = 0,
 +    .base_addr  = 0xf000c000
 +};
 +
 +static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
 +}
 +
 +static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
 +}
 +
 +static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
 +{
 +    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
 +}
 +
 +static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
 +{
 +    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
 +        / (int32_t)(rv[1] - rv[0]);
 +}
 +
 +static void adc_qom_set(QTestState *qts, const ADC *adc,
 +        const char *name, uint32_t value)
 +{
 +    QDict *response;
 +    const char *path = "/machine/soc/adc";
 +
 +    g_test_message("Setting properties %s of %s with value %u",
 +            name, path, value);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
 +            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
 +            path, name, value);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +}
 +
 +static void adc_write_input(QTestState *qts, const ADC *adc,
 +        uint32_t index, uint32_t value)
 +{
 +    char name[100];
 +
 +    sprintf(name, "adci[%u]", index);
 +    adc_qom_set(qts, adc, name, value);
 +}
 +
 +static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
 +{
 +    adc_qom_set(qts, adc, "vref", value);
 +}
 +
 +static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
 +{
 +    uint32_t output;
 +
 +    g_assert_cmpuint(input, <=, ref);
 +    output = (input * (MAX_RESULT + 1)) / ref;
 +    if (output > MAX_RESULT) {
 +        output = MAX_RESULT;
 +    }
 +
 +    return output;
 +}
 +
 +static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
 +{
 +    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
 +
 +    return 2 * (div + 1);
 +}
 +
 +static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
 +        uint32_t clkdiv)
 +{
 +    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
 +}
 +
 +static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
 +        uint32_t clkdiv)
 +{
 +    uint32_t prescaler = adc_prescaler(qts, adc);
 +
 +    /*
 +     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
 +     * should take 10~30 cycles here.
 +     */
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
 +                clkdiv));
 +    /* ADC is still converting. */
 +    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
 +    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
 +    /* ADC has finished conversion. */
 +    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
 +}
 +
 +/* Check ADC can be reset to default value. */
 +static void test_init(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an internal reference. */
 +static void test_convert_internal(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            input = input_list[i];
 +            expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
 +                    CON_REFSEL | CON_EN);
 +            g_assert_false(qtest_get_irq(qts, adc->irq));
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC can convert from an external reference. */
 +static void test_convert_external(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, vref, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +
 +    for (index = 0; index < NUM_INPUTS; ++index) {
 +        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
 +                input = input_list[i];
 +                vref = vref_list[j];
 +                expected_output = adc_calculate_output(input, vref);
 +
 +                adc_write_input(qts, adc, index, input);
 +                adc_write_vref(qts, adc, vref);
 +                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
 +                        CON_CONV);
 +                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +                g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                        CON_MUX(index) | CON_EN);
 +                g_assert_false(qtest_get_irq(qts, adc->irq));
 +                output = adc_read_data(qts, adc);
 +                g_assert_cmpuint(output, ==, expected_output);
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC interrupt files if and only if CON_INT_EN is set. */
 +static void test_interrupt(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    uint32_t index, input, output, expected_output;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    index = 1;
 +    input = input_list[1];
 +    expected_output = adc_calculate_output(input, DEFAULT_IREF);
 +
 +    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
 +    adc_write_input(qts, adc, index, input);
 +    g_assert_false(qtest_get_irq(qts, adc->irq));
 +    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
 +            | CON_EN | CON_CONV);
 +    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
 +            | CON_REFSEL | CON_INT | CON_EN);
 +    g_assert_true(qtest_get_irq(qts, adc->irq));
 +    output = adc_read_data(qts, adc);
 +    g_assert_cmpuint(output, ==, expected_output);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
 +static void test_reset(gconstpointer adc_p)
 +{
 +    const ADC *adc = adc_p;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +
 +    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
 +        uint32_t div = div_list[i];
 +
 +        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
 +        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
 +                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
 +        g_assert_false(adc_read_con(qts, adc) & CON_EN);
 +    }
 +    qtest_quit(qts);
 +}
 +
 +/* Check ADC Calibration works as desired. */
 +static void test_calibrate(gconstpointer adc_p)
 +{
 +    int i, j;
 +    const ADC *adc = adc_p;
 +
 +    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
 +        uint32_t iref = iref_list[j];
 +        uint32_t expected_rv[] = {
 +            adc_calculate_output(R0_INPUT, iref),
 +            adc_calculate_output(R1_INPUT, iref),
 +        };
 +        char buf[100];
 +        QTestState *qts;
 +
 +        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
 +        qts = qtest_init(buf);
 +
 +        /* Check the converted value is correct using the calibration value. */
 +        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
 +            uint32_t input;
 +            uint32_t output;
 +            uint32_t expected_output;
 +            uint32_t calibrated_voltage;
 +            uint32_t index = 0;
 +
 +            input = input_list[i];
 +            /* Calibration only works for input range 0.1V ~ 1.8V. */
 +            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
 +                continue;
 +            }
 +            expected_output = adc_calculate_output(input, iref);
 +
 +            adc_write_input(qts, adc, index, input);
 +            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
 +                    CON_EN | CON_CONV);
 +            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
 +            g_assert_cmphex(adc_read_con(qts, adc), ==,
 +                    CON_REFSEL | CON_MUX(index) | CON_EN);
 +            output = adc_read_data(qts, adc);
 +            g_assert_cmpuint(output, ==, expected_output);
 +
 +            calibrated_voltage = adc_calibrate(output, expected_rv);
 +            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
 +            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
 +        }
 +
 +        qtest_quit(qts);
 +    }
 +}
 +
 +static void adc_add_test(const char *name, const ADC* wd,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
 +    qtest_add_data_func(full_name, wd, fn);
 +}
 +#define add_test(name, td) adc_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +
 +    add_test(init, &adc);
 +    add_test(convert_internal, &adc);
 +    add_test(convert_external, &adc);
 +    add_test(interrupt, &adc);
 +    add_test(reset, &adc);
 +    add_test(calibrate, &adc);
 +
 +    return g_test_run();
 +}
 diff --git a/hw/adc/meson.build b/hw/adc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/adc/meson.build
 +++ b/hw/adc/meson.build
@@ -1 +1,2 @@
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
 diff --git a/hw/adc/trace-events b/hw/adc/trace-events
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
 +# See docs/devel/tracing.txt for syntax documentation.
 +
 +# npcm7xx_adc.c
 +npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 +npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
    ['prom-env-test', 'boot-serial-test']
  qtests_npcm7xx = \
 -  ['npcm7xx_gpio-test',
 +  ['npcm7xx_adc-test',
 +   'npcm7xx_gpio-test',
     'npcm7xx_rng-test',
     'npcm7xx_timer-test',
     'npcm7xx_watchdog_timer-test']
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 02/13] wdt: Add Aspeed watchdog device model
+[PULL 18/21] hw/misc: Add a PWM module for NPCM7XX
-From: Cédric Le Goater <clg@kaod.org>
+From: Hao Wu <wuhaotsh@google.com>
-The Aspeed SoC includes a set of watchdog timers using 32-bit
+The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
-decrement counters, which can be based either on the APB clock or
+identical PWM modules. Each module contains 4 PWM entries. Each PWM has
-a 1 MHz clock.
+two outputs: frequency and duty_cycle. Both are computed using inputs
 from software side.
-The watchdog timer is designed to prevent system deadlock and, in
+This module does not model detail pulse signals since it is expensive.
-general, it should be restarted before timeout. When a timeout occurs,
+It also does not model interrupts and watchdogs that are dependant on
-different types of signals can be generated, ARM reset, SOC reset,
+the detail models. The interfaces for these are left in the module so
-System reset, CPU Interrupt, external signal or boot from alternate
+that anyone in need for these functionalities can implement on their
-block. The current model only performs the system reset function as
+own.
 this is used by U-Boot and Linux.
-Signed-off-by: Joel Stanley <joel@jms.id.au>
+The user can read the duty cycle and frequency using qom-get command.
-Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org
-[clg: - fixed compile breakage
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
-      - fixed io region size
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
-      - added watchdog_perform_action() on timer expiry
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-      - wrote a commit log
+Message-id: 20210108190945.949196-5-wuhaotsh@google.com
       - merged fixes from Andrew Jeffery to scale the reload value ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/watchdog/Makefile.objs        |   1 +
+ docs/system/arm/nuvoton.rst   |   2 +-
- include/hw/watchdog/wdt_aspeed.h |  32 ++++++
+ include/hw/arm/npcm7xx.h      |   2 +
- hw/watchdog/wdt_aspeed.c         | 225 +++++++++++++++++++++++++++++++++++++++
+ include/hw/misc/npcm7xx_pwm.h | 105 +++++++
-files changed, 258 insertions(+)
+ hw/arm/npcm7xx.c              |  26 +-
- create mode 100644 include/hw/watchdog/wdt_aspeed.h
+ hw/misc/npcm7xx_pwm.c         | 550 ++++++++++++++++++++++++++++++++++
- create mode 100644 hw/watchdog/wdt_aspeed.c
+ hw/misc/meson.build           |   1 +
  hw/misc/trace-events          |   6 +
 files changed, 689 insertions(+), 3 deletions(-)
  create mode 100644 include/hw/misc/npcm7xx_pwm.h
  create mode 100644 hw/misc/npcm7xx_pwm.c
-diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/Makefile.objs
+--- a/docs/system/arm/nuvoton.rst
-+++ b/hw/watchdog/Makefile.objs
++++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@ common-obj-y += watchdog.o
+@@ -XXX,XX +XXX,XX @@ Supported devices
- common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
+  * USB host (USBH)
- common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
+  * GPIO controller
- common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
+  * Analog to Digital Converter (ADC)
-+common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
++ * Pulse Width Modulation (PWM)
-diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
  Missing devices
  ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
   * Peripheral SPI controller (PSPI)
   * SD/MMC host
   * PECI interface
 - * Pulse Width Modulation (PWM)
   * Tachometer
   * PCI and PCIe root complex and bridges
   * VDM and MCTP support
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/npcm7xx.h
 +++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/mem/npcm7xx_mc.h"
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/misc/npcm7xx_gcr.h"
 +#include "hw/misc/npcm7xx_pwm.h"
  #include "hw/misc/npcm7xx_rng.h"
  #include "hw/nvram/npcm7xx_otp.h"
  #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxCLKState     clk;
      NPCM7xxTimerCtrlState tim[3];
      NPCM7xxADCState     adc;
 +    NPCM7xxPWMState     pwm[2];
      NPCM7xxOTPState     key_storage;
      NPCM7xxOTPState     fuse_array;
      NPCM7xxMCState      mc;
 diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/watchdog/wdt_aspeed.h
++++ b/include/hw/misc/npcm7xx_pwm.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * ASPEED Watchdog Controller
++ * Nuvoton NPCM7xx PWM Module
 + *
-+ * Copyright (C) 2016-2017 IBM Corp.
++ * Copyright 2020 Google LLC
 + *
-+ * This code is licensed under the GPL version 2 or later. See the
++ * This program is free software; you can redistribute it and/or modify it
-+ * COPYING file in the top-level directory.
++ * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
-+#ifndef ASPEED_WDT_H
++#ifndef NPCM7XX_PWM_H
-+#define ASPEED_WDT_H
++#define NPCM7XX_PWM_H
 +
 +#include "hw/clock.h"
 +#include "hw/sysbus.h"
-+
++#include "hw/irq.h"
-+#define TYPE_ASPEED_WDT "aspeed.wdt"
++
-+#define ASPEED_WDT(obj) \
++/* Each PWM module holds 4 PWM channels. */
-+    OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
++#define NPCM7XX_PWM_PER_MODULE 4
 +
-+#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
++/*
-+
++ * Number of registers in one pwm module. Don't change this without increasing
-+typedef struct AspeedWDTState {
++ * the version_id in vmstate.
-+    /*< private >*/
++ */
-+    SysBusDevice parent_obj;
++#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
-+    QEMUTimer *timer;
++
-+
++/*
-+    /*< public >*/
++ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
 + * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
 + * value of 100,000 the duty cycle for that PWM is 10%.
 + */
 +#define NPCM7XX_PWM_MAX_DUTY 1000000
 +
 +typedef struct NPCM7xxPWMState NPCM7xxPWMState;
 +
 +/**
 + * struct NPCM7xxPWM - The state of a single PWM channel.
 + * @module: The PWM module that contains this channel.
 + * @irq: GIC interrupt line to fire on expiration if enabled.
 + * @running: Whether this PWM channel is generating output.
 + * @inverted: Whether this PWM channel is inverted.
 + * @index: The index of this PWM channel.
 + * @cnr: The counter register.
 + * @cmr: The comparator register.
 + * @pdr: The data register.
 + * @pwdr: The watchdog register.
 + * @freq: The frequency of this PWM channel.
 + * @duty: The duty cycle of this PWM channel. One unit represents
 + *   1/NPCM7XX_MAX_DUTY cycles.
 + */
 +typedef struct NPCM7xxPWM {
 +    NPCM7xxPWMState         *module;
 +
 +    qemu_irq                irq;
 +
 +    bool                    running;
 +    bool                    inverted;
 +
 +    uint8_t                 index;
 +    uint32_t                cnr;
 +    uint32_t                cmr;
 +    uint32_t                pdr;
 +    uint32_t                pwdr;
 +
 +    uint32_t                freq;
 +    uint32_t                duty;
 +} NPCM7xxPWM;
 +
 +/**
 + * struct NPCM7xxPWMState - Pulse Width Modulation device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @clock: The PWM clock.
 + * @pwm: The PWM channels owned by this module.
 + * @ppr: The prescaler register.
 + * @csr: The clock selector register.
 + * @pcr: The control register.
 + * @pier: The interrupt enable register.
 + * @piir: The interrupt indication register.
 + */
 +struct NPCM7xxPWMState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
-+    uint32_t regs[ASPEED_WDT_REGS_MAX];
++
-+
++    Clock       *clock;
-+    uint32_t pclk_freq;
++    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
-+} AspeedWDTState;
++
-+
++    uint32_t    ppr;
-+#endif  /* ASPEED_WDT_H */
++    uint32_t    csr;
-diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
++    uint32_t    pcr;
 +    uint32_t    pier;
 +    uint32_t    piir;
 +};
 +
 +#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
 +#define NPCM7XX_PWM(obj) \
 +    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
 +
 +#endif /* NPCM7XX_PWM_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
      NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
      NPCM7XX_EHCI_IRQ            = 61,
      NPCM7XX_OHCI_IRQ            = 62,
 +    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
 +    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
      NPCM7XX_GPIO0_IRQ           = 116,
      NPCM7XX_GPIO1_IRQ,
      NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 xb8000000, /* CS3 */
  };
 +/* Register base address for each PWM Module */
 +static const hwaddr npcm7xx_pwm_addr[] = {
 +    0xf0103000,
 +    0xf0104000,
 +};
 +
  static const struct {
      hwaddr regs_addr;
      uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
          object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                  TYPE_NPCM7XX_FIU);
      }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 +        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
 +    }
  }
  static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                         npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 +    /* PWM Modules. Cannot fail. */
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
 +    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
 +
 +        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
 +                    DEVICE(&s->clk), "apb3-clock"));
 +        sysbus_realize(sbd, &error_abort);
 +        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
 +        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
 +    }
 +
      /*
       * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
       * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
      create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
      create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
 -    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
      create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
 diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/watchdog/wdt_aspeed.c
++++ b/hw/misc/npcm7xx_pwm.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * ASPEED Watchdog Controller
++ * Nuvoton NPCM7xx PWM Module
 + *
-+ * Copyright (C) 2016-2017 IBM Corp.
++ * Copyright 2020 Google LLC
 + *
-+ * This code is licensed under the GPL version 2 or later. See the
++ * This program is free software; you can redistribute it and/or modify it
-+ * COPYING file in the top-level directory.
++ * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
++#include "hw/irq.h"
++#include "hw/qdev-clock.h"
++#include "hw/qdev-properties.h"
++#include "hw/misc/npcm7xx_pwm.h"
++#include "hw/registerfields.h"
++#include "migration/vmstate.h"
++#include "qemu/bitops.h"
++#include "qemu/error-report.h"
 +#include "qemu/log.h"
-+#include "sysemu/watchdog.h"
++#include "qemu/module.h"
-+#include "hw/sysbus.h"
++#include "qemu/units.h"
-+#include "qemu/timer.h"
++#include "trace.h"
-+#include "hw/watchdog/wdt_aspeed.h"
++
-+
++REG32(NPCM7XX_PWM_PPR, 0x00);
-+#define WDT_STATUS              (0x00 / 4)
++REG32(NPCM7XX_PWM_CSR, 0x04);
-+#define WDT_RELOAD_VALUE        (0x04 / 4)
++REG32(NPCM7XX_PWM_PCR, 0x08);
-+#define WDT_RESTART             (0x08 / 4)
++REG32(NPCM7XX_PWM_CNR0, 0x0c);
-+#define WDT_CTRL                (0x0C / 4)
++REG32(NPCM7XX_PWM_CMR0, 0x10);
-+#define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
++REG32(NPCM7XX_PWM_PDR0, 0x14);
-+#define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
++REG32(NPCM7XX_PWM_CNR1, 0x18);
-+#define   WDT_CTRL_1MHZ_CLK             BIT(4)
++REG32(NPCM7XX_PWM_CMR1, 0x1c);
-+#define   WDT_CTRL_WDT_EXT              BIT(3)
++REG32(NPCM7XX_PWM_PDR1, 0x20);
-+#define   WDT_CTRL_WDT_INTR             BIT(2)
++REG32(NPCM7XX_PWM_CNR2, 0x24);
-+#define   WDT_CTRL_RESET_SYSTEM         BIT(1)
++REG32(NPCM7XX_PWM_CMR2, 0x28);
-+#define   WDT_CTRL_ENABLE               BIT(0)
++REG32(NPCM7XX_PWM_PDR2, 0x2c);
-+
++REG32(NPCM7XX_PWM_CNR3, 0x30);
-+#define WDT_TIMEOUT_STATUS      (0x10 / 4)
++REG32(NPCM7XX_PWM_CMR3, 0x34);
-+#define WDT_TIMEOUT_CLEAR       (0x14 / 4)
++REG32(NPCM7XX_PWM_PDR3, 0x38);
-+#define WDT_RESET_WDITH         (0x18 / 4)
++REG32(NPCM7XX_PWM_PIER, 0x3c);
-+
++REG32(NPCM7XX_PWM_PIIR, 0x40);
-+#define WDT_RESTART_MAGIC       0x4755
++REG32(NPCM7XX_PWM_PWDR0, 0x44);
-+
++REG32(NPCM7XX_PWM_PWDR1, 0x48);
-+static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
++REG32(NPCM7XX_PWM_PWDR2, 0x4c);
-+{
++REG32(NPCM7XX_PWM_PWDR3, 0x50);
-+    return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
++
-+}
++/* Register field definitions. */
-+
++#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
-+static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
++#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
-+{
++#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
-+    AspeedWDTState *s = ASPEED_WDT(opaque);
++#define NPCM7XX_CH_EN               BIT(0)
-+
++#define NPCM7XX_CH_INV              BIT(2)
-+    offset >>= 2;
++#define NPCM7XX_CH_MOD              BIT(3)
 +
 +/* Offset of each PWM channel's prescaler in the PPR register. */
 +static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
 +/* Offset of each PWM channel's clock selector in the CSR register. */
 +static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
 +/* Offset of each PWM channel's control variable in the PCR register. */
 +static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
 +
 +static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t ppr;
 +    uint32_t csr;
 +    uint32_t freq;
 +
 +    if (!p->running) {
 +        return 0;
 +    }
 +
 +    csr = NPCM7XX_CSR(p->module->csr, p->index);
 +    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
 +    freq = clock_get_hz(p->module->clock);
 +    freq /= ppr + 1;
 +    /* csr can only be 0~4 */
 +    if (csr > 4) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid csr value %u\n",
 +                      __func__, csr);
 +        csr = 4;
 +    }
 +    /* freq won't be changed if csr == 4. */
 +    if (csr < 4) {
 +        freq >>= csr + 1;
 +    }
 +
 +    return freq / (p->cnr + 1);
 +}
 +
 +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
 +{
 +    uint64_t duty;
 +
 +    if (p->running) {
 +        if (p->cnr == 0) {
 +            duty = 0;
 +        } else if (p->cmr >= p->cnr) {
 +            duty = NPCM7XX_PWM_MAX_DUTY;
 +        } else {
 +            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
 +        }
 +    } else {
 +        duty = 0;
 +    }
 +
 +    if (p->inverted) {
 +        duty = NPCM7XX_PWM_MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
 +{
 +    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
 +
 +    if (freq != p->freq) {
 +        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->freq, freq);
 +        p->freq = freq;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
 +{
 +    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
 +
 +    if (duty != p->duty) {
 +        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
 +                                      p->index, p->duty, duty);
 +        p->duty = duty;
 +    }
 +}
 +
 +static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
 +{
 +    npcm7xx_pwm_update_freq(p);
 +    npcm7xx_pwm_update_duty(p);
 +}
 +
 +static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
 +{
 +    int i;
 +    uint32_t old_ppr = s->ppr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->ppr = new_ppr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
 +{
 +    int i;
 +    uint32_t old_csr = s->csr;
 +
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
 +    s->csr = new_csr;
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
 +            npcm7xx_pwm_update_freq(&s->pwm[i]);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
 +{
 +    int i;
 +    bool inverted;
 +    uint32_t pcr;
 +    NPCM7xxPWM *p;
 +
 +    s->pcr = new_pcr;
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        p = &s->pwm[i];
 +        pcr = NPCM7XX_CH(new_pcr, i);
 +        inverted = pcr & NPCM7XX_CH_INV;
 +
 +        /*
 +         * We only run a PWM channel with toggle mode. Single-shot mode does not
 +         * generate frequency and duty-cycle values.
 +         */
 +        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
 +            if (p->running) {
 +                /* Re-run this PWM channel if inverted changed. */
 +                if (p->inverted ^ inverted) {
 +                    p->inverted = inverted;
 +                    npcm7xx_pwm_update_duty(p);
 +                }
 +            } else {
 +                /* Run this PWM channel. */
 +                p->running = true;
 +                p->inverted = inverted;
 +                npcm7xx_pwm_update_output(p);
 +            }
 +        } else {
 +            /* Clear this PWM channel. */
 +            p->running = false;
 +            p->inverted = inverted;
 +            npcm7xx_pwm_update_output(p);
 +        }
 +    }
 +
 +}
 +
 +static hwaddr npcm7xx_cnr_index(hwaddr offset)
 +{
 +    switch (offset) {
-+    case WDT_STATUS:
++    case A_NPCM7XX_PWM_CNR0:
 +        return s->regs[WDT_STATUS];
 +    case WDT_RELOAD_VALUE:
 +        return s->regs[WDT_RELOAD_VALUE];
 +    case WDT_RESTART:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: read from write-only reg at offset 0x%"
 +                      HWADDR_PRIx "\n", __func__, offset);
 +        return 0;
-+    case WDT_CTRL:
++    case A_NPCM7XX_PWM_CNR1:
-+        return s->regs[WDT_CTRL];
++        return 1;
-+    case WDT_TIMEOUT_STATUS:
++    case A_NPCM7XX_PWM_CNR2:
-+    case WDT_TIMEOUT_CLEAR:
++        return 2;
-+    case WDT_RESET_WDITH:
++    case A_NPCM7XX_PWM_CNR3:
-+        qemu_log_mask(LOG_UNIMP,
++        return 3;
-+                      "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
++    default:
-+                      __func__, offset);
++        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_cmr_index(hwaddr offset)
 +{
 +    switch (offset) {
 +    case A_NPCM7XX_PWM_CMR0:
 +        return 0;
++    case A_NPCM7XX_PWM_CMR1:
++        return 1;
++    case A_NPCM7XX_PWM_CMR2:
++        return 2;
++    case A_NPCM7XX_PWM_CMR3:
++        return 3;
++    default:
++        g_assert_not_reached();
++    }
++}
++
++static hwaddr npcm7xx_pdr_index(hwaddr offset)
++{
++    switch (offset) {
++    case A_NPCM7XX_PWM_PDR0:
++        return 0;
++    case A_NPCM7XX_PWM_PDR1:
++        return 1;
++    case A_NPCM7XX_PWM_PDR2:
++        return 2;
++    case A_NPCM7XX_PWM_PDR3:
++        return 3;
++    default:
++        g_assert_not_reached();
++    }
++}
++
++static hwaddr npcm7xx_pwdr_index(hwaddr offset)
++{
++    switch (offset) {
++    case A_NPCM7XX_PWM_PWDR0:
++        return 0;
++    case A_NPCM7XX_PWM_PWDR1:
++        return 1;
++    case A_NPCM7XX_PWM_PWDR2:
++        return 2;
++    case A_NPCM7XX_PWM_PWDR3:
++        return 3;
++    default:
++        g_assert_not_reached();
++    }
++}
++
++static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
++{
++    NPCM7xxPWMState *s = opaque;
++    uint64_t value = 0;
++
++    switch (offset) {
++    case A_NPCM7XX_PWM_CNR0:
++    case A_NPCM7XX_PWM_CNR1:
++    case A_NPCM7XX_PWM_CNR2:
++    case A_NPCM7XX_PWM_CNR3:
++        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
++        break;
++
++    case A_NPCM7XX_PWM_CMR0:
++    case A_NPCM7XX_PWM_CMR1:
++    case A_NPCM7XX_PWM_CMR2:
++    case A_NPCM7XX_PWM_CMR3:
++        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
++        break;
++
++    case A_NPCM7XX_PWM_PDR0:
++    case A_NPCM7XX_PWM_PDR1:
++    case A_NPCM7XX_PWM_PDR2:
++    case A_NPCM7XX_PWM_PDR3:
++        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
++        break;
++
++    case A_NPCM7XX_PWM_PWDR0:
++    case A_NPCM7XX_PWM_PWDR1:
++    case A_NPCM7XX_PWM_PWDR2:
++    case A_NPCM7XX_PWM_PWDR3:
++        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
++        break;
++
++    case A_NPCM7XX_PWM_PPR:
++        value = s->ppr;
++        break;
++
++    case A_NPCM7XX_PWM_CSR:
++        value = s->csr;
++        break;
++
++    case A_NPCM7XX_PWM_PCR:
++        value = s->pcr;
++        break;
++
++    case A_NPCM7XX_PWM_PIER:
++        value = s->pier;
++        break;
++
++    case A_NPCM7XX_PWM_PIIR:
++        value = s->piir;
++        break;
++
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
++                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
-+        return 0;
++        break;
 +    }
 +
-+}
++    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
-+
++    return value;
-+static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
++}
-+{
++
-+    uint32_t reload;
++static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
-+
++                                uint64_t v, unsigned size)
-+    if (pclk) {
++{
-+        reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
++    NPCM7xxPWMState *s = opaque;
-+                          s->pclk_freq);
++    NPCM7xxPWM *p;
-+    } else {
++    uint32_t value = v;
-+        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
++
-+    }
++    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
 +
 +    if (aspeed_wdt_is_enabled(s)) {
 +        timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
 +    }
 +}
 +
 +static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
 +                             unsigned size)
 +{
 +    AspeedWDTState *s = ASPEED_WDT(opaque);
 +    bool enable = data & WDT_CTRL_ENABLE;
 +
 +    offset >>= 2;
 +
 +    switch (offset) {
-+    case WDT_STATUS:
++    case A_NPCM7XX_PWM_CNR0:
 +    case A_NPCM7XX_PWM_CNR1:
 +    case A_NPCM7XX_PWM_CNR2:
 +    case A_NPCM7XX_PWM_CNR3:
 +        p = &s->pwm[npcm7xx_cnr_index(offset)];
 +        p->cnr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CMR0:
 +    case A_NPCM7XX_PWM_CMR1:
 +    case A_NPCM7XX_PWM_CMR2:
 +    case A_NPCM7XX_PWM_CMR3:
 +        p = &s->pwm[npcm7xx_cmr_index(offset)];
 +        p->cmr = value;
 +        npcm7xx_pwm_update_output(p);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PDR0:
 +    case A_NPCM7XX_PWM_PDR1:
 +    case A_NPCM7XX_PWM_PDR2:
 +    case A_NPCM7XX_PWM_PDR3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: write to read-only reg at offset 0x%"
++                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
-+                      HWADDR_PRIx "\n", __func__, offset);
++                      __func__, offset);
 +        break;
-+    case WDT_RELOAD_VALUE:
++
-+        s->regs[WDT_RELOAD_VALUE] = data;
++    case A_NPCM7XX_PWM_PWDR0:
-+        break;
++    case A_NPCM7XX_PWM_PWDR1:
-+    case WDT_RESTART:
++    case A_NPCM7XX_PWM_PWDR2:
-+        if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
++    case A_NPCM7XX_PWM_PWDR3:
 +            s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
 +            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
 +        }
 +        break;
 +    case WDT_CTRL:
 +        if (enable && !aspeed_wdt_is_enabled(s)) {
 +            s->regs[WDT_CTRL] = data;
 +            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
 +        } else if (!enable && aspeed_wdt_is_enabled(s)) {
 +            s->regs[WDT_CTRL] = data;
 +            timer_del(s->timer);
 +        }
 +        break;
 +    case WDT_TIMEOUT_STATUS:
 +    case WDT_TIMEOUT_CLEAR:
 +    case WDT_RESET_WDITH:
 +        qemu_log_mask(LOG_UNIMP,
-+                      "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
++                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
-+                      __func__, offset);
++                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PPR:
 +        npcm7xx_pwm_write_ppr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_CSR:
 +        npcm7xx_pwm_write_csr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PCR:
 +        npcm7xx_pwm_write_pcr(s, value);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIER:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    case A_NPCM7XX_PWM_PIIR:
 +        qemu_log_mask(LOG_UNIMP,
 +                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
 +                     __func__, offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
++                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
-+    }
++        break;
-+    return;
++    }
 +}
 +
-+static WatchdogTimerModel model = {
++static const struct MemoryRegionOps npcm7xx_pwm_ops = {
-+    .wdt_name = TYPE_ASPEED_WDT,
++    .read       = npcm7xx_pwm_read,
-+    .wdt_description = "Aspeed watchdog device",
++    .write      = npcm7xx_pwm_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
-+static const VMStateDescription vmstate_aspeed_wdt = {
++static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
-+    .name = "vmstate_aspeed_wdt",
++{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +
 +        p->cnr = 0x00000000;
 +        p->cmr = 0x00000000;
 +        p->pdr = 0x00000000;
 +        p->pwdr = 0x00000000;
 +    }
 +
 +    s->ppr = 0x00000000;
 +    s->csr = 0x00000000;
 +    s->pcr = 0x00000000;
 +    s->pier = 0x00000000;
 +    s->piir = 0x00000000;
 +}
 +
 +static void npcm7xx_pwm_hold_reset(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        qemu_irq_lower(s->pwm[i].irq);
 +    }
 +}
 +
 +static void npcm7xx_pwm_init(Object *obj)
 +{
 +    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
 +        NPCM7xxPWM *p = &s->pwm[i];
 +        p->module = s;
 +        p->index = i;
 +        sysbus_init_irq(sbd, &p->irq);
 +    }
 +
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
 +                          TYPE_NPCM7XX_PWM, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
 +
 +    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
 +        object_property_add_uint32_ptr(obj, "freq[*]",
 +                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
 +        object_property_add_uint32_ptr(obj, "duty[*]",
 +                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_pwm = {
 +    .name = "npcm7xx-pwm",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
-+        VMSTATE_TIMER_PTR(timer, AspeedWDTState),
++        VMSTATE_BOOL(running, NPCM7xxPWM),
-+        VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
++        VMSTATE_BOOL(inverted, NPCM7xxPWM),
-+        VMSTATE_END_OF_LIST()
++        VMSTATE_UINT8(index, NPCM7xxPWM),
-+    }
++        VMSTATE_UINT32(cnr, NPCM7xxPWM),
 +        VMSTATE_UINT32(cmr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
 +        VMSTATE_UINT32(freq, NPCM7xxPWM),
 +        VMSTATE_UINT32(duty, NPCM7xxPWM),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
-+static const MemoryRegionOps aspeed_wdt_ops = {
++static const VMStateDescription vmstate_npcm7xx_pwm_module = {
-+    .read = aspeed_wdt_read,
++    .name = "npcm7xx-pwm-module",
-+    .write = aspeed_wdt_write,
++    .version_id = 0,
-+    .endianness = DEVICE_LITTLE_ENDIAN,
++    .minimum_version_id = 0,
-+    .valid.min_access_size = 4,
++    .fields = (VMStateField[]) {
-+    .valid.max_access_size = 4,
++        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
-+    .valid.unaligned = false,
++        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
 +                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
 +                             NPCM7xxPWM),
 +        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(csr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
 +        VMSTATE_UINT32(pier, NPCM7xxPWMState),
 +        VMSTATE_UINT32(piir, NPCM7xxPWMState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
-+static void aspeed_wdt_reset(DeviceState *dev)
++static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
 +{
-+    AspeedWDTState *s = ASPEED_WDT(dev);
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    s->regs[WDT_STATUS] = 0x3EF1480;
 +    s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
 +    s->regs[WDT_RESTART] = 0;
 +    s->regs[WDT_CTRL] = 0;
 +
 +    timer_del(s->timer);
 +}
 +
 +static void aspeed_wdt_timer_expired(void *dev)
 +{
 +    AspeedWDTState *s = ASPEED_WDT(dev);
 +
 +    qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
 +    watchdog_perform_action();
 +    timer_del(s->timer);
 +}
 +
 +#define PCLK_HZ 24000000
 +
 +static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    AspeedWDTState *s = ASPEED_WDT(dev);
 +
 +    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
 +
 +    /* FIXME: This setting should be derived from the SCU hw strapping
 +     * register SCU70
 +     */
 +    s->pclk_freq = PCLK_HZ;
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
 +                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
-+    dc->realize = aspeed_wdt_realize;
++    dc->desc = "NPCM7xx PWM Controller";
-+    dc->reset = aspeed_wdt_reset;
++    dc->vmsd = &vmstate_npcm7xx_pwm_module;
-+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
++    rc->phases.enter = npcm7xx_pwm_enter_reset;
-+    dc->vmsd = &vmstate_aspeed_wdt;
++    rc->phases.hold = npcm7xx_pwm_hold_reset;
 +}
 +
-+static const TypeInfo aspeed_wdt_info = {
++static const TypeInfo npcm7xx_pwm_info = {
-+    .parent = TYPE_SYS_BUS_DEVICE,
++    .name               = TYPE_NPCM7XX_PWM,
-+    .name  = TYPE_ASPEED_WDT,
++    .parent             = TYPE_SYS_BUS_DEVICE,
-+    .instance_size  = sizeof(AspeedWDTState),
++    .instance_size      = sizeof(NPCM7xxPWMState),
-+    .class_init = aspeed_wdt_class_init,
++    .class_init         = npcm7xx_pwm_class_init,
 +    .instance_init      = npcm7xx_pwm_init,
 +};
 +
-+static void wdt_aspeed_register_types(void)
++static void npcm7xx_pwm_register_type(void)
 +{
-+    watchdog_add_model(&model);
++    type_register_static(&npcm7xx_pwm_info);
-+    type_register_static(&aspeed_wdt_info);
++}
-+}
++type_init(npcm7xx_pwm_register_type);
-+
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
-+type_init(wdt_aspeed_register_types)
+index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
  softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
    'npcm7xx_clk.c',
    'npcm7xx_gcr.c',
 +  'npcm7xx_pwm.c',
    'npcm7xx_rng.c',
  ))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
  npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
  npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 +# npcm7xx_pwm.c
 +npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
 +npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
 +
  # stm32f4xx_syscfg.c
  stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
  stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 05/13] hw/arm/integratorcp: Support specifying features via -cpu
+[PULL 19/21] hw/misc: Add QTest for NPCM7XX PWM Module
-From: Julian Brown <julian@codesourcery.com>
+From: Hao Wu <wuhaotsh@google.com>
-Since the integratorcp board creates the CPU object directly
+We add a qtest for the PWM in the previous patch. It proves it works as
-rather than via cpu_arm_init(), we have to call the CPU
+expected.
 class parse_features() method ourselves if we want to
 support the user passing features via the -cpu command
 line argument as well as just the cpu name. Do so.
-Signed-off-by: Julian Brown <julian@codesourcery.com>
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
-[PMM: split out into its own patch]
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210108190945.949196-6-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/integratorcp.c | 19 +++++++++++++++++--
+ tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
-file changed, 17 insertions(+), 2 deletions(-)
+ tests/qtest/meson.build        |   1 +
 files changed, 491 insertions(+)
  create mode 100644 tests/qtest/npcm7xx_pwm-test.c
-diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTests for Nuvoton NPCM7xx PWM Modules.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "libqos/libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +#include "qapi/qmp/qnum.h"
 +
 +#define REF_HZ          25000000
 +
 +/* Register field definitions. */
 +#define CH_EN           BIT(0)
 +#define CH_INV          BIT(2)
 +#define CH_MOD          BIT(3)
 +
 +/* Registers shared between all PWMs in a module */
 +#define PPR             0x00
 +#define CSR             0x04
 +#define PCR             0x08
 +#define PIER            0x3c
 +#define PIIR            0x40
 +
 +/* CLK module related */
 +#define CLK_BA          0xf0801000
 +#define CLKSEL          0x04
 +#define CLKDIV1         0x08
 +#define CLKDIV2         0x2c
 +#define PLLCON0         0x0c
 +#define PLLCON1         0x10
 +#define PLL_INDV(rv)    extract32((rv), 0, 6)
 +#define PLL_FBDV(rv)    extract32((rv), 16, 12)
 +#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
 +#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
 +#define APB3CKDIV(rv)   extract32((rv), 28, 2)
 +#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
 +#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
 +#define CPUCKSEL(rv)    extract32((rv), 0, 2)
 +
 +#define MAX_DUTY        1000000
 +
 +typedef struct PWMModule {
 +    int irq;
 +    uint64_t base_addr;
 +} PWMModule;
 +
 +typedef struct PWM {
 +    uint32_t cnr_offset;
 +    uint32_t cmr_offset;
 +    uint32_t pdr_offset;
 +    uint32_t pwdr_offset;
 +} PWM;
 +
 +typedef struct TestData {
 +    const PWMModule *module;
 +    const PWM *pwm;
 +} TestData;
 +
 +static const PWMModule pwm_module_list[] = {
 +    {
 +        .irq        = 93,
 +        .base_addr  = 0xf0103000
 +    },
 +    {
 +        .irq        = 94,
 +        .base_addr  = 0xf0104000
 +    }
 +};
 +
 +static const PWM pwm_list[] = {
 +    {
 +        .cnr_offset     = 0x0c,
 +        .cmr_offset     = 0x10,
 +        .pdr_offset     = 0x14,
 +        .pwdr_offset    = 0x44,
 +    },
 +    {
 +        .cnr_offset     = 0x18,
 +        .cmr_offset     = 0x1c,
 +        .pdr_offset     = 0x20,
 +        .pwdr_offset    = 0x48,
 +    },
 +    {
 +        .cnr_offset     = 0x24,
 +        .cmr_offset     = 0x28,
 +        .pdr_offset     = 0x2c,
 +        .pwdr_offset    = 0x4c,
 +    },
 +    {
 +        .cnr_offset     = 0x30,
 +        .cmr_offset     = 0x34,
 +        .pdr_offset     = 0x38,
 +        .pwdr_offset    = 0x50,
 +    },
 +};
 +
 +static const int ppr_base[] = { 0, 0, 8, 8 };
 +static const int csr_base[] = { 0, 4, 8, 12 };
 +static const int pcr_base[] = { 0, 8, 12, 16 };
 +
 +static const uint32_t ppr_list[] = {
 +    0,
 +    1,
 +    10,
 +    100,
 +    255, /* Max possible value. */
 +};
 +
 +static const uint32_t csr_list[] = {
 +    0,
 +    1,
 +    2,
 +    3,
 +    4, /* Max possible value. */
 +};
 +
 +static const uint32_t cnr_list[] = {
 +    0,
 +    1,
 +    50,
 +    100,
 +    150,
 +    200,
 +    1000,
 +    10000,
 +    65535, /* Max possible value. */
 +};
 +
 +static const uint32_t cmr_list[] = {
 +    0,
 +    1,
 +    10,
 +    50,
 +    100,
 +    150,
 +    200,
 +    1000,
 +    10000,
 +    65535, /* Max possible value. */
 +};
 +
 +/* Returns the index of the PWM module. */
 +static int pwm_module_index(const PWMModule *module)
 +{
 +    ptrdiff_t diff = module - pwm_module_list;
 +
 +    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
 +
 +    return diff;
 +}
 +
 +/* Returns the index of the PWM entry. */
 +static int pwm_index(const PWM *pwm)
 +{
 +    ptrdiff_t diff = pwm - pwm_list;
 +
 +    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
 +
 +    return diff;
 +}
 +
 +static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
 +{
 +    QDict *response;
 +
 +    g_test_message("Getting properties %s from %s", name, path);
 +    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
 +            " 'arguments': { 'path': %s, 'property': %s}}",
 +            path, name);
 +    /* The qom set message returns successfully. */
 +    g_assert_true(qdict_haskey(response, "return"));
 +    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
 +}
 +
 +static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "freq[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
 +{
 +    char path[100];
 +    char name[100];
 +
 +    sprintf(path, "/machine/soc/pwm[%d]", module_index);
 +    sprintf(name, "duty[%d]", pwm_index);
 +
 +    return pwm_qom_get(qts, path, name);
 +}
 +
 +static uint32_t get_pll(uint32_t con)
 +{
 +    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
 +            * PLL_OTDV2(con));
 +}
 +
 +static uint64_t read_pclk(QTestState *qts)
 +{
 +    uint64_t freq = REF_HZ;
 +    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
 +    uint32_t pllcon;
 +    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
 +    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
 +
 +    switch (CPUCKSEL(clksel)) {
 +    case 0:
 +        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 1:
 +        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
 +        freq = get_pll(pllcon);
 +        break;
 +    case 2:
 +        break;
 +    case 3:
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
 +
 +    return freq;
 +}
 +
 +static uint32_t pwm_selector(uint32_t csr)
 +{
 +    switch (csr) {
 +    case 0:
 +        return 2;
 +    case 1:
 +        return 4;
 +    case 2:
 +        return 8;
 +    case 3:
 +        return 16;
 +    case 4:
 +        return 1;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
 +        uint32_t cnr)
 +{
 +    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
 +}
 +
 +static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
 +{
 +    uint64_t duty;
 +
 +    if (cnr == 0) {
 +        /* PWM is stopped. */
 +        duty = 0;
 +    } else if (cmr >= cnr) {
 +        duty = MAX_DUTY;
 +    } else {
 +        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
 +    }
 +
 +    if (inverted) {
 +        duty = MAX_DUTY - duty;
 +    }
 +
 +    return duty;
 +}
 +
 +static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
 +{
 +    return qtest_readl(qts, td->module->base_addr + offset);
 +}
 +
 +static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
 +        uint32_t value)
 +{
 +    qtest_writel(qts, td->module->base_addr + offset, value);
 +}
 +
 +static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
 +}
 +
 +static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
 +}
 +
 +static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
 +{
 +    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
 +}
 +
 +static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
 +}
 +
 +static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cnr_offset);
 +}
 +
 +static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cnr_offset, value);
 +}
 +
 +static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
 +{
 +    return pwm_read(qts, td, td->pwm->cmr_offset);
 +}
 +
 +static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
 +{
 +    pwm_write(qts, td, td->pwm->cmr_offset, value);
 +}
 +
 +/* Check pwm registers can be reset to default value */
 +static void test_init(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +
 +    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +
 +    qtest_quit(qts);
 +}
 +
 +/* One-shot mode should not change frequency and duty cycle. */
 +static void test_oneshot(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr;
 +    int i, j;
 +
 +    pcr = CH_EN;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +            pwm_write_pcr(qts, td, pcr);
 +
 +            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
 +            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +/* In toggle mode, the PWM generates correct outputs. */
 +static void test_toggle(gconstpointer test_data)
 +{
 +    const TestData *td = test_data;
 +    QTestState *qts = qtest_init("-machine quanta-gsj");
 +    int module = pwm_module_index(td->module);
 +    int pwm = pwm_index(td->pwm);
 +    uint32_t ppr, csr, pcr, cnr, cmr;
 +    int i, j, k, l;
 +    uint64_t expected_freq, expected_duty;
 +
 +    pcr = CH_EN | CH_MOD;
 +    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
 +        ppr = ppr_list[i];
 +        pwm_write_ppr(qts, td, ppr);
 +
 +        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
 +            csr = csr_list[j];
 +            pwm_write_csr(qts, td, csr);
 +
 +            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
 +                cnr = cnr_list[k];
 +                pwm_write_cnr(qts, td, cnr);
 +
 +                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
 +                    cmr = cmr_list[l];
 +                    pwm_write_cmr(qts, td, cmr);
 +                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
 +                    expected_duty = pwm_compute_duty(cnr, cmr, false);
 +
 +                    pwm_write_pcr(qts, td, pcr);
 +                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
 +                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
 +                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
 +                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                    /* Test inverted mode */
 +                    expected_duty = pwm_compute_duty(cnr, cmr, true);
 +                    pwm_write_pcr(qts, td, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
 +                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
 +                            ==, expected_duty);
 +                    if (expected_duty != 0 && expected_duty != 100) {
 +                        /* Duty cycle with 0 or 100 doesn't need frequency. */
 +                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
 +                                ==, expected_freq);
 +                    }
 +
 +                }
 +            }
 +        }
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +static void pwm_add_test(const char *name, const TestData* td,
 +        GTestDataFunc fn)
 +{
 +    g_autofree char *full_name = g_strdup_printf(
 +            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
 +            pwm_index(td->pwm), name);
 +    qtest_add_data_func(full_name, td, fn);
 +}
 +#define add_test(name, td) pwm_add_test(#name, td, test_##name)
 +
 +int main(int argc, char **argv)
 +{
 +    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
 +
 +    g_test_init(&argc, &argv, NULL);
 +
 +    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
 +        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
 +            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
 +
 +            td->module = &pwm_module_list[i];
 +            td->pwm = &pwm_list[j];
 +
 +            add_test(init, td);
 +            add_test(oneshot, td);
 +            add_test(toggle, td);
 +        }
 +    }
 +
 +    return g_test_run();
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/integratorcp.c
+--- a/tests/qtest/meson.build
-+++ b/hw/arm/integratorcp.c
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
-     const char *kernel_filename = machine->kernel_filename;
+ qtests_npcm7xx = \
-     const char *kernel_cmdline = machine->kernel_cmdline;
+   ['npcm7xx_adc-test',
-     const char *initrd_filename = machine->initrd_filename;
+    'npcm7xx_gpio-test',
-+    char **cpustr;
++   'npcm7xx_pwm-test',
-     ObjectClass *cpu_oc;
+    'npcm7xx_rng-test',
-+    CPUClass *cc;
+    'npcm7xx_timer-test',
-     Object *cpuobj;
+    'npcm7xx_watchdog_timer-test']
      ARMCPU *cpu;
 +    const char *typename;
      MemoryRegion *address_space_mem = get_system_memory();
      MemoryRegion *ram = g_new(MemoryRegion, 1);
      MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
      qemu_irq pic[32];
      DeviceState *dev, *sic, *icp;
      int i;
 +    Error *err = NULL;
      if (!cpu_model) {
          cpu_model = "arm926";
      }
 -    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 +    cpustr = g_strsplit(cpu_model, ",", 2);
 +
 +    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
      if (!cpu_oc) {
          fprintf(stderr, "Unable to find CPU definition\n");
          exit(1);
      }
 +    typename = object_class_get_name(cpu_oc);
 +
 +    cc = CPU_CLASS(cpu_oc);
 +    cc->parse_features(typename, cpustr[1], &err);
 +    g_strfreev(cpustr);
 +    if (err) {
 +        error_report_err(err);
 +        exit(1);
 +    }
 -    cpuobj = object_new(object_class_get_name(cpu_oc));
 +    cpuobj = object_new(typename);
      /* By default ARM1176 CPUs have EL3 enabled.  This board does not
       * currently support EL3 so the CPU EL3 property is disabled before
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 03/13] aspeed: add a watchdog controller
+[PULL 20/21] hw/*: Use type casting for SysBusDevice in NPCM7XX
-From: Cédric Le Goater <clg@kaod.org>
+From: Hao Wu <wuhaotsh@google.com>
-This enables reboot of a guest from U-Boot and Linux.
+A device shouldn't access its parent object which is QOM internal.
 Instead it should use type cast for this purporse. This patch fixes this
 issue for all NPCM7XX Devices.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org
+Message-id: 20210108190945.949196-7-wuhaotsh@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/aspeed_soc.h |  2 ++
+ hw/arm/npcm7xx_boards.c | 2 +-
- hw/arm/aspeed_soc.c         | 13 +++++++++++++
+ hw/mem/npcm7xx_mc.c     | 2 +-
-files changed, 15 insertions(+)
+ hw/misc/npcm7xx_clk.c   | 2 +-
  hw/misc/npcm7xx_gcr.c   | 2 +-
  hw/misc/npcm7xx_rng.c   | 2 +-
  hw/nvram/npcm7xx_otp.c  | 2 +-
  hw/ssi/npcm7xx_fiu.c    | 2 +-
 files changed, 7 insertions(+), 7 deletions(-)
-diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
+--- a/hw/arm/npcm7xx_boards.c
-+++ b/include/hw/arm/aspeed_soc.h
++++ b/hw/arm/npcm7xx_boards.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
- #include "hw/timer/aspeed_timer.h"
+                                         uint32_t hw_straps)
- #include "hw/i2c/aspeed_i2c.h"
+ {
- #include "hw/ssi/aspeed_smc.h"
+     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
-+#include "hw/watchdog/wdt_aspeed.h"
+-    MachineClass *mc = &nmc->parent;
++    MachineClass *mc = MACHINE_CLASS(nmc);
- #define ASPEED_SPIS_NUM  2
+     Object *obj;
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
+     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
-     AspeedSMCState fmc;
+diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
      AspeedSMCState spi[ASPEED_SPIS_NUM];
      AspeedSDMCState sdmc;
 +    AspeedWDTState wdt;
  } AspeedSoCState;
  #define TYPE_ASPEED_SOC "aspeed-soc"
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
+--- a/hw/mem/npcm7xx_mc.c
-+++ b/hw/arm/aspeed_soc.c
++++ b/hw/mem/npcm7xx_mc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
- #define ASPEED_SOC_SCU_BASE         0x1E6E2000
- #define ASPEED_SOC_SRAM_BASE        0x1E720000
+     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
- #define ASPEED_SOC_TIMER_BASE       0x1E782000
+                           NPCM7XX_MC_REGS_SIZE);
-+#define ASPEED_SOC_WDT_BASE         0x1E785000
+-    sysbus_init_mmio(&s->parent, &s->mmio);
- #define ASPEED_SOC_I2C_BASE         0x1E78A000
++    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
  static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
                           sc->info->silicon_rev);
      object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                                "ram-size", &error_abort);
 +
 +    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
 +    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
 +    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
  }
- static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+ static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
-         return;
+index XXXXXXX..XXXXXXX 100644
-     }
+--- a/hw/misc/npcm7xx_clk.c
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
++++ b/hw/misc/npcm7xx_clk.c
-+
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
-+    /* Watch dog */
-+    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
+     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
-+    if (err) {
+                           TYPE_NPCM7XX_CLK, 4 * KiB);
-+        error_propagate(errp, err);
+-    sysbus_init_mmio(&s->parent, &s->iomem);
-+        return;
++    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 +    }
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
  }
- static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+ static int npcm7xx_clk_post_load(void *opaque, int version_id)
 diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_gcr.c
 +++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                            TYPE_NPCM7XX_GCR, 4 * KiB);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static const VMStateDescription vmstate_npcm7xx_gcr = {
 diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/npcm7xx_rng.c
 +++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                            NPCM7XX_RNG_REGS_SIZE);
 -    sysbus_init_mmio(&s->parent, &s->iomem);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
  }
  static const VMStateDescription vmstate_npcm7xx_rng = {
 diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/npcm7xx_otp.c
 +++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
  {
      NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
      NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
 -    SysBusDevice *sbd = &s->parent;
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      memset(s->array, 0, sizeof(s->array));
 diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/npcm7xx_fiu.c
 +++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
  static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
  {
      NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
 -    SysBusDevice *sbd = &s->parent;
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      int i;
      if (s->cs_count <= 0) {
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 13/13] stellaris: Use the 'unimplemented' device for parts we don't implement
+[PULL 21/21] ui/cocoa: Fix openFile: deprecation on Big Sur
-Use the 'unimplemented' dummy device to cover regions of the
+From: Roman Bolshakov <r.bolshakov@yadro.com>
 SoC device memory map which we don't have proper device
 implementations for yet.
+ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
+      [-Wdeprecated-declarations]
+        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+                                           ^
+/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
+      'openFile:' has been explicitly marked deprecated here
+- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
+^
+Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org
 ---
- hw/arm/stellaris.c | 14 ++++++++++++++
+ ui/cocoa.m | 5 ++++-
-file changed, 14 insertions(+)
+file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+diff --git a/ui/cocoa.m b/ui/cocoa.m
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/stellaris.c
+--- a/ui/cocoa.m
-+++ b/hw/arm/stellaris.c
++++ b/ui/cocoa.m
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
- #include "exec/address-spaces.h"
+     /* Where to look for local files */
- #include "sysemu/sysemu.h"
+     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
- #include "hw/char/pl011.h"
+     NSString *full_file_path;
-+#include "hw/misc/unimp.h"
++    NSURL *full_file_url;
- #define GPIO_A 0
+     /* iterate thru the possible paths until the file is found */
- #define GPIO_B 1
+     int index;
-@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
+@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
-             }
+         full_file_path = [full_file_path stringByDeletingLastPathComponent];
          full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
                            path_array[index], filename];
 -        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
 +        full_file_url = [NSURL fileURLWithPath: full_file_path
 +                                   isDirectory: false];
 +        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
              return;
          }
      }
-+
-+    /* Add dummy regions for the devices we don't implement yet,
-+     * so guest accesses don't cause unlogged crashes.
-+     */
-+    create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
-+    create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
-+    create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
-+    create_unimplemented_device("PWM", 0x40028000, 0x1000);
-+    create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
-+    create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
-+    create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
-+    create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
-+    create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
- }
- /* FIXME: Figure out how to generate these from stellaris_boards.  */
 --
-.7.4
+.20.1

A random mix of items here, nothing very major.

thanks
-- PMM

The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:

Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207

for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:

stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)

----------------------------------------------------------------
target-arm:
 * new "unimplemented" device for stubbing out devices in a
   system model so accesses can be logged
 * stellaris: document the SoC memory map
 * arm: create instruction syndromes for AArch32 data aborts
 * arm: Correctly handle watchpoints for BE32 CPUs
 * Fix Thumb-1 BE32 execution and disassembly
 * arm: Add cfgend parameter for ARM CPU selection
 * sd: sdhci: check data length during dma_memory_read
 * aspeed: add a watchdog controller
 * integratorcp: adding vmstate for save/restore

----------------------------------------------------------------
Cédric Le Goater (2):
      wdt: Add Aspeed watchdog device model
      aspeed: add a watchdog controller

Julian Brown (4):
      hw/arm/integratorcp: Support specifying features via -cpu
      target/arm: Add cfgend parameter for ARM CPU selection.
      Fix Thumb-1 BE32 execution and disassembly.
      arm: Correctly handle watchpoints for BE32 CPUs

Pavel Dovgalyuk (1):
      integratorcp: adding vmstate for save/restore

Peter Maydell (5):
      target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
      target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
      stellaris: Document memory map and which SoC devices are unimplemented
      hw/misc: New "unimplemented" sysbus device
      stellaris: Use the 'unimplemented' device for parts we don't implement

Prasad J Pandit (1):
      sd: sdhci: check data length during dma_memory_read

From: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>

VMState added by this patch preserves correct
loading of the integratorcp device state.

Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP
[PMM: removed unnecessary minimum_version_id_old lines]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/integratorcp.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@ static uint8_t integrator_spd[128] = {
    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
 };
 
+static const VMStateDescription vmstate_integratorcm = {
+    .name = "integratorcm",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(cm_osc, IntegratorCMState),
+        VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
+        VMSTATE_UINT32(cm_lock, IntegratorCMState),
+        VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
+        VMSTATE_UINT32(cm_sdram, IntegratorCMState),
+        VMSTATE_UINT32(cm_init, IntegratorCMState),
+        VMSTATE_UINT32(cm_flags, IntegratorCMState),
+        VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
+        VMSTATE_UINT32(int_level, IntegratorCMState),
+        VMSTATE_UINT32(irq_enabled, IntegratorCMState),
+        VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
                                   unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ typedef struct icp_pic_state {
     qemu_irq parent_fiq;
 } icp_pic_state;
 
+static const VMStateDescription vmstate_icp_pic = {
+    .name = "icp_pic",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(level, icp_pic_state),
+        VMSTATE_UINT32(irq_enabled, icp_pic_state),
+        VMSTATE_UINT32(fiq_enabled, icp_pic_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static void icp_pic_update(icp_pic_state *s)
 {
     uint32_t flags;
@@ -XXX,XX +XXX,XX @@ typedef struct ICPCtrlRegsState {
 #define ICP_INTREG_WPROT        (1 << 0)
 #define ICP_INTREG_CARDIN       (1 << 3)
 
+static const VMStateDescription vmstate_icp_control = {
+    .name = "icp_control",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static uint64_t icp_control_read(void *opaque, hwaddr offset,
                                  unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void core_class_init(ObjectClass *klass, void *data)
 
     dc->props = core_properties;
     dc->realize = integratorcm_realize;
+    dc->vmsd = &vmstate_integratorcm;
+}
+
+static void icp_pic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_icp_pic;
+}
+
+static void icp_control_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_icp_control;
 }
 
 static const TypeInfo core_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_pic_info = {
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(icp_pic_state),
     .instance_init = icp_pic_init,
+    .class_init    = icp_pic_class_init,
 };
 
 static const TypeInfo icp_ctrl_regs_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_ctrl_regs_info = {
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(ICPCtrlRegsState),
     .instance_init = icp_control_init,
+    .class_init    = icp_control_class_init,
 };
 
 static void integratorcp_register_types(void)
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

The Aspeed SoC includes a set of watchdog timers using 32-bit
decrement counters, which can be based either on the APB clock or
a 1 MHz clock.

The watchdog timer is designed to prevent system deadlock and, in
general, it should be restarted before timeout. When a timeout occurs,
different types of signals can be generated, ARM reset, SOC reset,
System reset, CPU Interrupt, external signal or boot from alternate
block. The current model only performs the system reset function as
this is used by U-Boot and Linux.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org
[clg: - fixed compile breakage
      - fixed io region size
      - added watchdog_perform_action() on timer expiry
      - wrote a commit log
      - merged fixes from Andrew Jeffery to scale the reload value ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/watchdog/Makefile.objs        |   1 +
 include/hw/watchdog/wdt_aspeed.h |  32 ++++++
 hw/watchdog/wdt_aspeed.c         | 225 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 258 insertions(+)
 create mode 100644 include/hw/watchdog/wdt_aspeed.h
 create mode 100644 hw/watchdog/wdt_aspeed.c

diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/Makefile.objs
+++ b/hw/watchdog/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-y += watchdog.o
 common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
 common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
 common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
+common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED Watchdog Controller
+ *
+ * Copyright (C) 2016-2017 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+#ifndef ASPEED_WDT_H
+#define ASPEED_WDT_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_WDT "aspeed.wdt"
+#define ASPEED_WDT(obj) \
+    OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
+
+#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
+
+typedef struct AspeedWDTState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    QEMUTimer *timer;
+
+    /*< public >*/
+    MemoryRegion iomem;
+    uint32_t regs[ASPEED_WDT_REGS_MAX];
+
+    uint32_t pclk_freq;
+} AspeedWDTState;
+
+#endif  /* ASPEED_WDT_H */
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED Watchdog Controller
+ *
+ * Copyright (C) 2016-2017 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "sysemu/watchdog.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/watchdog/wdt_aspeed.h"
+
+#define WDT_STATUS              (0x00 / 4)
+#define WDT_RELOAD_VALUE        (0x04 / 4)
+#define WDT_RESTART             (0x08 / 4)
+#define WDT_CTRL                (0x0C / 4)
+#define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
+#define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
+#define   WDT_CTRL_1MHZ_CLK             BIT(4)
+#define   WDT_CTRL_WDT_EXT              BIT(3)
+#define   WDT_CTRL_WDT_INTR             BIT(2)
+#define   WDT_CTRL_RESET_SYSTEM         BIT(1)
+#define   WDT_CTRL_ENABLE               BIT(0)
+
+#define WDT_TIMEOUT_STATUS      (0x10 / 4)
+#define WDT_TIMEOUT_CLEAR       (0x14 / 4)
+#define WDT_RESET_WDITH         (0x18 / 4)
+
+#define WDT_RESTART_MAGIC       0x4755
+
+static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
+{
+    return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
+}
+
+static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
+{
+    AspeedWDTState *s = ASPEED_WDT(opaque);
+
+    offset >>= 2;
+
+    switch (offset) {
+    case WDT_STATUS:
+        return s->regs[WDT_STATUS];
+    case WDT_RELOAD_VALUE:
+        return s->regs[WDT_RELOAD_VALUE];
+    case WDT_RESTART:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: read from write-only reg at offset 0x%"
+                      HWADDR_PRIx "\n", __func__, offset);
+        return 0;
+    case WDT_CTRL:
+        return s->regs[WDT_CTRL];
+    case WDT_TIMEOUT_STATUS:
+    case WDT_TIMEOUT_CLEAR:
+    case WDT_RESET_WDITH:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+        return 0;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+        return 0;
+    }
+
+}
+
+static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
+{
+    uint32_t reload;
+
+    if (pclk) {
+        reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
+                          s->pclk_freq);
+    } else {
+        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
+    }
+
+    if (aspeed_wdt_is_enabled(s)) {
+        timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
+    }
+}
+
+static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
+                             unsigned size)
+{
+    AspeedWDTState *s = ASPEED_WDT(opaque);
+    bool enable = data & WDT_CTRL_ENABLE;
+
+    offset >>= 2;
+
+    switch (offset) {
+    case WDT_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only reg at offset 0x%"
+                      HWADDR_PRIx "\n", __func__, offset);
+        break;
+    case WDT_RELOAD_VALUE:
+        s->regs[WDT_RELOAD_VALUE] = data;
+        break;
+    case WDT_RESTART:
+        if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
+            s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
+            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
+        }
+        break;
+    case WDT_CTRL:
+        if (enable && !aspeed_wdt_is_enabled(s)) {
+            s->regs[WDT_CTRL] = data;
+            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
+        } else if (!enable && aspeed_wdt_is_enabled(s)) {
+            s->regs[WDT_CTRL] = data;
+            timer_del(s->timer);
+        }
+        break;
+    case WDT_TIMEOUT_STATUS:
+    case WDT_TIMEOUT_CLEAR:
+    case WDT_RESET_WDITH:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+    }
+    return;
+}
+
+static WatchdogTimerModel model = {
+    .wdt_name = TYPE_ASPEED_WDT,
+    .wdt_description = "Aspeed watchdog device",
+};
+
+static const VMStateDescription vmstate_aspeed_wdt = {
+    .name = "vmstate_aspeed_wdt",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER_PTR(timer, AspeedWDTState),
+        VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const MemoryRegionOps aspeed_wdt_ops = {
+    .read = aspeed_wdt_read,
+    .write = aspeed_wdt_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 4,
+    .valid.unaligned = false,
+};
+
+static void aspeed_wdt_reset(DeviceState *dev)
+{
+    AspeedWDTState *s = ASPEED_WDT(dev);
+
+    s->regs[WDT_STATUS] = 0x3EF1480;
+    s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
+    s->regs[WDT_RESTART] = 0;
+    s->regs[WDT_CTRL] = 0;
+
+    timer_del(s->timer);
+}
+
+static void aspeed_wdt_timer_expired(void *dev)
+{
+    AspeedWDTState *s = ASPEED_WDT(dev);
+
+    qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
+    watchdog_perform_action();
+    timer_del(s->timer);
+}
+
+#define PCLK_HZ 24000000
+
+static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    AspeedWDTState *s = ASPEED_WDT(dev);
+
+    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
+
+    /* FIXME: This setting should be derived from the SCU hw strapping
+     * register SCU70
+     */
+    s->pclk_freq = PCLK_HZ;
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
+                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = aspeed_wdt_realize;
+    dc->reset = aspeed_wdt_reset;
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+    dc->vmsd = &vmstate_aspeed_wdt;
+}
+
+static const TypeInfo aspeed_wdt_info = {
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .name  = TYPE_ASPEED_WDT,
+    .instance_size  = sizeof(AspeedWDTState),
+    .class_init = aspeed_wdt_class_init,
+};
+
+static void wdt_aspeed_register_types(void)
+{
+    watchdog_add_model(&model);
+    type_register_static(&aspeed_wdt_info);
+}
+
+type_init(wdt_aspeed_register_types)
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

This enables reboot of a guest from U-Boot and Linux.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/aspeed_soc.h |  2 ++
 hw/arm/aspeed_soc.c         | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/timer/aspeed_timer.h"
 #include "hw/i2c/aspeed_i2c.h"
 #include "hw/ssi/aspeed_smc.h"
+#include "hw/watchdog/wdt_aspeed.h"
 
 #define ASPEED_SPIS_NUM  2
 
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
     AspeedSMCState fmc;
     AspeedSMCState spi[ASPEED_SPIS_NUM];
     AspeedSDMCState sdmc;
+    AspeedWDTState wdt;
 } AspeedSoCState;
 
 #define TYPE_ASPEED_SOC "aspeed-soc"
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
 #define ASPEED_SOC_SRAM_BASE        0x1E720000
 #define ASPEED_SOC_TIMER_BASE       0x1E782000
+#define ASPEED_SOC_WDT_BASE         0x1E785000
 #define ASPEED_SOC_I2C_BASE         0x1E78A000
 
 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
                          sc->info->silicon_rev);
     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                               "ram-size", &error_abort);
+
+    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
+    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
+    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
 }
 
 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
+
+    /* Watch dog */
+    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
 }
 
 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-- 
2.7.4

From: Prasad J Pandit <pjp@fedoraproject.org>

While doing multi block SDMA transfer in routine
'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting
index 'begin' and data length 's->data_count' could end up to be same.
This could lead to an OOB access issue. Correct transfer data length
to avoid it.

Cc: qemu-stable@nongnu.org
Reported-by: Jiang Xin <jiangxin1@huawei.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20170130064736.9236-1-ppandit@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/sd/sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
                 boundary_count -= block_size - begin;
             }
             dma_memory_read(&address_space_memory, s->sdmasysad,
-                            &s->fifo_buffer[begin], s->data_count);
+                            &s->fifo_buffer[begin], s->data_count - begin);
             s->sdmasysad += s->data_count - begin;
             if (s->data_count == block_size) {
                 for (n = 0; n < block_size; n++) {
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

Since the integratorcp board creates the CPU object directly
rather than via cpu_arm_init(), we have to call the CPU
class parse_features() method ourselves if we want to
support the user passing features via the -cpu command
line argument as well as just the cpu name. Do so.

Signed-off-by: Julian Brown <julian@codesourcery.com>
[PMM: split out into its own patch]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/integratorcp.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
+    char **cpustr;
     ObjectClass *cpu_oc;
+    CPUClass *cc;
     Object *cpuobj;
     ARMCPU *cpu;
+    const char *typename;
     MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *ram = g_new(MemoryRegion, 1);
     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
     qemu_irq pic[32];
     DeviceState *dev, *sic, *icp;
     int i;
+    Error *err = NULL;
 
     if (!cpu_model) {
         cpu_model = "arm926";
     }
 
-    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
+    cpustr = g_strsplit(cpu_model, ",", 2);
+
+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
     if (!cpu_oc) {
         fprintf(stderr, "Unable to find CPU definition\n");
         exit(1);
     }
+    typename = object_class_get_name(cpu_oc);
+
+    cc = CPU_CLASS(cpu_oc);
+    cc->parse_features(typename, cpustr[1], &err);
+    g_strfreev(cpustr);
+    if (err) {
+        error_report_err(err);
+        exit(1);
+    }
 
-    cpuobj = object_new(object_class_get_name(cpu_oc));
+    cpuobj = object_new(typename);
 
     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
      * currently support EL3 so the CPU EL3 property is disabled before
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

Add a new "cfgend" property which selects whether the CPU resets into
big-endian mode or not.  This setting affects whether we reset with
SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set.

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com
[PMM: use error_report_err() rather than error_report();
 move the integratorcp changes to their own patch;
 drop an unnecessary extra #include;
 rephrase commit message accordingly;
 move setting of reset_sctlr above registration of cpregs
 so it actually has an effect]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h |  7 +++++++
 target/arm/cpu.c | 13 +++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     int gic_vpribits; /* number of virtual priority bits */
     int gic_vprebits; /* number of virtual preemption bits */
 
+    /* Whether the cfgend input is high (i.e. this CPU should reset into
+     * big-endian mode).  This setting isn't used directly: instead it modifies
+     * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
+     * architecture version.
+     */
+    bool cfgend;
+
     ARMELChangeHook *el_change_hook;
     void *el_change_hook_opaque;
 };
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el2_property =
 static Property arm_cpu_has_el3_property =
             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 
+static Property arm_cpu_cfgend_property =
+            DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
+
 /* use property name "pmu" to match other archs and virt tools */
 static Property arm_cpu_has_pmu_property =
             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
         }
     }
 
+    qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
+                             &error_abort);
 }
 
 static void arm_cpu_finalizefn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
             cpu->reset_sctlr |= (1 << 13);
     }
 
+    if (cpu->cfgend) {
+        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+            cpu->reset_sctlr |= SCTLR_EE;
+        } else {
+            cpu->reset_sctlr |= SCTLR_B;
+        }
+    }
+
     if (!cpu->has_el3) {
         /* If the has_el3 CPU property is disabled then we need to disable the
          * feature.
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

Thumb-1 code has some issues in BE32 mode (as currently implemented). In
short, since bytes are swapped within words at load time for BE32
executables, this also swaps pairs of adjacent Thumb-1 instructions.

This patch un-swaps those pairs of instructions again, both for execution,
and for disassembly. (The previous version of the patch always read four
bytes in arm_read_memory_func and then extracted the proper two bytes,
in a probably misguided attempt to match the behaviour of actual hardware
as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for
instruction fetches". It's less complicated to just read the correct
two bytes though.)

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/disas/bfd.h   |  7 +++++++
 target/arm/arm_ldst.h | 10 +++++++++-
 disas.c               |  1 +
 target/arm/cpu.c      | 23 +++++++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index XXXXXXX..XXXXXXX 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
      The bottom 16 bits are for the internal use of the disassembler.  */
   unsigned long flags;
 #define INSN_HAS_RELOC	0x80000000
+#define INSN_ARM_BE32	0x00010000
   PTR private_data;
 
   /* Function used to get bytes to disassemble.  MEMADDR is the
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
     (bfd_vma memaddr, bfd_byte *myaddr, int length,
 	     struct disassemble_info *info);
 
+  /* A place to stash the real read_memory_func if read_memory_func wants to
+     do some funky address arithmetic or similar (e.g. for ARM BE32 mode).  */
+  int (*read_memory_inner_func)
+    (bfd_vma memaddr, bfd_byte *myaddr, int length,
+             struct disassemble_info *info);
+
   /* Function which should be called if we get an error that we can't
      recover from.  STATUS is the errno value from read_memory_func and
      MEMADDR is the address that we were trying to read.  INFO is a
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm_ldst.h
+++ b/target/arm/arm_ldst.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
                                      bool sctlr_b)
 {
-    uint16_t insn = cpu_lduw_code(env, addr);
+    uint16_t insn;
+#ifndef CONFIG_USER_ONLY
+    /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
+       within each word.  Undo that now.  */
+    if (sctlr_b) {
+        addr ^= 2;
+    }
+#endif
+    insn = cpu_lduw_code(env, addr);
     if (bswap_code(sctlr_b)) {
         return bswap16(insn);
     }
diff --git a/disas.c b/disas.c
index XXXXXXX..XXXXXXX 100644
--- a/disas.c
+++ b/disas.c
@@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 
     s.cpu = cpu;
     s.info.read_memory_func = target_read_memory;
+    s.info.read_memory_inner_func = NULL;
     s.info.buffer_vma = code;
     s.info.buffer_length = size;
     s.info.print_address_func = generic_print_address;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
   return print_insn_arm(pc | 1, info);
 }
 
+static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
+                                int length, struct disassemble_info *info)
+{
+    assert(info->read_memory_inner_func);
+    assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
+
+    if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
+        assert(info->endian == BFD_ENDIAN_LITTLE);
+        return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
+                                            info);
+    } else {
+        return info->read_memory_inner_func(memaddr, b, length, info);
+    }
+}
+
 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 {
     ARMCPU *ac = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
         info->endian = BFD_ENDIAN_BIG;
 #endif
     }
+    if (info->read_memory_inner_func == NULL) {
+        info->read_memory_inner_func = info->read_memory_func;
+        info->read_memory_func = arm_read_memory_func;
+    }
+    info->flags &= ~INSN_ARM_BE32;
+    if (arm_sctlr_b(env)) {
+        info->flags |= INSN_ARM_BE32;
+    }
 }
 
 static void arm_cpu_initfn(Object *obj)
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers.  This patch reverses the address
adjustment before performing the comparison with the help of a new CPUClass
hook.

This version of the patch augments and tidies up comments a little.

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/qom/cpu.h      |  3 +++
 target/arm/internals.h |  5 +++++
 exec.c                 |  1 +
 qom/cpu.c              |  6 ++++++
 target/arm/cpu.c       |  3 +++
 target/arm/op_helper.c | 22 ++++++++++++++++++++++
 6 files changed, 40 insertions(+)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
  * @cpu_exec_exit: Callback for cpu_exec cleanup.
  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
  * @disas_set_info: Setup architecture specific components of disassembly info
+ * @adjust_watchpoint_address: Perform a target-specific adjustment to an
+ * address before attempting to match it against watchpoints.
  *
  * Represents a CPU family or model.
  */
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 
     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
+    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
 } CPUClass;
 
 #ifdef HOST_WORDS_BIGENDIAN
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu);
 /* Callback function for checking if a watchpoint should trigger. */
 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 
+/* Adjust addresses (in BE32 mode) before testing against watchpoint
+ * addresses.
+ */
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+
 /* Callback function for when a watchpoint or breakpoint triggers. */
 void arm_debug_excp_handler(CPUState *cs);
 
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
         return;
     }
     vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
+    vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
     QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
         if (cpu_watchpoint_address_matches(wp, vaddr, len)
             && (wp->flags & flags)) {
diff --git a/qom/cpu.c b/qom/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
     return cpu->cpu_index;
 }
 
+static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
+{
+    return addr;
+}
+
 static void cpu_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
     k->cpu_exec_enter = cpu_common_noop;
     k->cpu_exec_exit = cpu_common_noop;
     k->cpu_exec_interrupt = cpu_common_exec_interrupt;
+    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
     dc->realize = cpu_common_realizefn;
     dc->unrealize = cpu_common_unrealizefn;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_stop_before_watchpoint = true;
     cc->debug_excp_handler = arm_debug_excp_handler;
     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
+#if !defined(CONFIG_USER_ONLY)
+    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+#endif
 
     cc->disas_set_info = arm_disas_set_info;
 }
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
     return check_watchpoints(cpu);
 }
 
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+
+    /* In BE32 system mode, target memory is stored byteswapped (on a
+     * little-endian host system), and by the time we reach here (via an
+     * opcode helper) the addresses of subword accesses have been adjusted
+     * to account for that, which means that watchpoints will not match.
+     * Undo the adjustment here.
+     */
+    if (arm_sctlr_b(env)) {
+        if (len == 1) {
+            addr ^= 3;
+        } else if (len == 2) {
+            addr ^= 2;
+        }
+    }
+
+    return addr;
+}
+
 void arm_debug_excp_handler(CPUState *cs)
 {
     /* Called by core code when a watchpoint or breakpoint fires;
-- 
2.7.4

In the ARM ldr/str decode path, rather than directly testing
"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
bits out into wbit and pbit local flags. (We will want to
do more tests against them to determine whether we need to
provide syndrome information.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/arm/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             } else {
                 int address_offset;
                 bool load = insn & (1 << 20);
+                bool wbit = insn & (1 << 21);
+                bool pbit = insn & (1 << 24);
                 bool doubleword = false;
                 /* Misc load/store */
                 rn = (insn >> 16) & 0xf;
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 }
 
                 addr = load_reg(s, rn);
-                if (insn & (1 << 24))
+                if (pbit) {
                     gen_add_datah_offset(s, insn, 0, addr);
+                }
                 address_offset = 0;
 
                 if (doubleword) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                    ensure correct behavior with overlapping index registers.
                    ldrd with base writeback is undefined if the
                    destination and index registers overlap.  */
-                if (!(insn & (1 << 24))) {
+                if (!pbit) {
                     gen_add_datah_offset(s, insn, address_offset, addr);
                     store_reg(s, rn, addr);
-                } else if (insn & (1 << 21)) {
+                } else if (wbit) {
                     if (address_offset)
                         tcg_gen_addi_i32(addr, addr, address_offset);
                     store_reg(s, rn, addr);
-- 
2.7.4

Add support for generating the ISS (Instruction Specific Syndrome)
for Data Abort exceptions taken from AArch32. These syndromes are
used by hypervisors for example to trap and emulate memory accesses.

This is the equivalent for AArch32 guests of the work done for AArch64
guests in commit aaa1f954d4cab243.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/arm/translate.h     |  14 ++++
 target/arm/translate-a64.c |  14 ----
 target/arm/translate.c     | 184 +++++++++++++++++++++++++++++++++------------
 3 files changed, 149 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s)
             ? 3 : MAX(1, s->current_el);
 }
 
+static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+{
+    /* We don't need to save all of the syndrome so we mask and shift
+     * out unneeded bits to help the sleb128 encoder do a better job.
+     */
+    syn &= ARM_INSN_START_WORD2_MASK;
+    syn >>= ARM_INSN_START_WORD2_SHIFT;
+
+    /* We check and clear insn_start_idx to catch multiple updates.  */
+    assert(s->insn_start_idx != 0);
+    tcg_set_insn_param(s->insn_start_idx, 2, syn);
+    s->insn_start_idx = 0;
+}
+
 /* target-specific extra values for is_jmp */
 /* These instructions trap after executing, so the A32/T32 decoder must
  * defer them until after the conditional execution state has been updated.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
     }
 }
 
-static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
-{
-    /* We don't need to save all of the syndrome so we mask and shift
-     * out uneeded bits to help the sleb128 encoder do a better job.
-     */
-    syn &= ARM_INSN_START_WORD2_MASK;
-    syn >>= ARM_INSN_START_WORD2_SHIFT;
-
-    /* We check and clear insn_start_idx to catch multiple updates.  */
-    assert(s->insn_start_idx != 0);
-    tcg_set_insn_param(s->insn_start_idx, 2, syn);
-    s->insn_start_idx = 0;
-}
-
 static void unallocated_encoding(DisasContext *s)
 {
     /* Unallocated and reserved encodings are uncategorized */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+/* Flags for the disas_set_da_iss info argument:
+ * lower bits hold the Rt register number, higher bits are flags.
+ */
+typedef enum ISSInfo {
+    ISSNone = 0,
+    ISSRegMask = 0x1f,
+    ISSInvalid = (1 << 5),
+    ISSIsAcqRel = (1 << 6),
+    ISSIsWrite = (1 << 7),
+    ISSIs16Bit = (1 << 8),
+} ISSInfo;
+
+/* Save the syndrome information for a Data Abort */
+static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
+{
+    uint32_t syn;
+    int sas = memop & MO_SIZE;
+    bool sse = memop & MO_SIGN;
+    bool is_acqrel = issinfo & ISSIsAcqRel;
+    bool is_write = issinfo & ISSIsWrite;
+    bool is_16bit = issinfo & ISSIs16Bit;
+    int srt = issinfo & ISSRegMask;
+
+    if (issinfo & ISSInvalid) {
+        /* Some callsites want to conditionally provide ISS info,
+         * eg "only if this was not a writeback"
+         */
+        return;
+    }
+
+    if (srt == 15) {
+        /* For AArch32, insns where the src/dest is R15 never generate
+         * ISS information. Catching that here saves checking at all
+         * the call sites.
+         */
+        return;
+    }
+
+    syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,
+                                  0, 0, 0, is_write, 0, is_16bit);
+    disas_set_insn_syndrome(s, syn);
+}
+
 static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
 {
     /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val,      \
                                      TCGv_i32 a32, int index)            \
 {                                                                        \
     gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
+}                                                                        \
+static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s,              \
+                                           TCGv_i32 val,                 \
+                                           TCGv_i32 a32, int index,      \
+                                           ISSInfo issinfo)              \
+{                                                                        \
+    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
+    disas_set_da_iss(s, OPC, issinfo);                                   \
 }
 
 #define DO_GEN_ST(SUFF, OPC)                                             \
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val,      \
                                      TCGv_i32 a32, int index)            \
 {                                                                        \
     gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
+}                                                                        \
+static inline void gen_aa32_st##SUFF##_iss(DisasContext *s,              \
+                                           TCGv_i32 val,                 \
+                                           TCGv_i32 a32, int index,      \
+                                           ISSInfo issinfo)              \
+{                                                                        \
+    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
+    disas_set_da_iss(s, OPC, issinfo | ISSIsWrite);                      \
 }
 
 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                 tmp = tcg_temp_new_i32();
                                 switch (op1) {
                                 case 0: /* lda */
-                                    gen_aa32_ld32u(s, tmp, addr,
-                                                   get_mem_index(s));
+                                    gen_aa32_ld32u_iss(s, tmp, addr,
+                                                       get_mem_index(s),
+                                                       rd | ISSIsAcqRel);
                                     break;
                                 case 2: /* ldab */
-                                    gen_aa32_ld8u(s, tmp, addr,
-                                                  get_mem_index(s));
+                                    gen_aa32_ld8u_iss(s, tmp, addr,
+                                                      get_mem_index(s),
+                                                      rd | ISSIsAcqRel);
                                     break;
                                 case 3: /* ldah */
-                                    gen_aa32_ld16u(s, tmp, addr,
-                                                   get_mem_index(s));
+                                    gen_aa32_ld16u_iss(s, tmp, addr,
+                                                       get_mem_index(s),
+                                                       rd | ISSIsAcqRel);
                                     break;
                                 default:
                                     abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                 tmp = load_reg(s, rm);
                                 switch (op1) {
                                 case 0: /* stl */
-                                    gen_aa32_st32(s, tmp, addr,
-                                                  get_mem_index(s));
+                                    gen_aa32_st32_iss(s, tmp, addr,
+                                                      get_mem_index(s),
+                                                      rm | ISSIsAcqRel);
                                     break;
                                 case 2: /* stlb */
-                                    gen_aa32_st8(s, tmp, addr,
-                                                 get_mem_index(s));
+                                    gen_aa32_st8_iss(s, tmp, addr,
+                                                     get_mem_index(s),
+                                                     rm | ISSIsAcqRel);
                                     break;
                                 case 3: /* stlh */
-                                    gen_aa32_st16(s, tmp, addr,
-                                                  get_mem_index(s));
+                                    gen_aa32_st16_iss(s, tmp, addr,
+                                                      get_mem_index(s),
+                                                      rm | ISSIsAcqRel);
                                     break;
                                 default:
                                     abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 bool wbit = insn & (1 << 21);
                 bool pbit = insn & (1 << 24);
                 bool doubleword = false;
+                ISSInfo issinfo;
+
                 /* Misc load/store */
                 rn = (insn >> 16) & 0xf;
                 rd = (insn >> 12) & 0xf;
 
+                /* ISS not valid if writeback */
+                issinfo = (pbit & !wbit) ? rd : ISSInvalid;
+
                 if (!load && (sh & 2)) {
                     /* doubleword */
                     ARCH(5TE);
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     tmp = tcg_temp_new_i32();
                     switch (sh) {
                     case 1:
-                        gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+                        gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
+                                           issinfo);
                         break;
                     case 2:
-                        gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
+                        gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
+                                          issinfo);
                         break;
                     default:
                     case 3:
-                        gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
+                        gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
+                                           issinfo);
                         break;
                     }
                 } else {
                     /* store */
                     tmp = load_reg(s, rd);
-                    gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+                    gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
                     tcg_temp_free_i32(tmp);
                 }
                 /* Perform base writeback before the loaded value to
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 /* load */
                 tmp = tcg_temp_new_i32();
                 if (insn & (1 << 22)) {
-                    gen_aa32_ld8u(s, tmp, tmp2, i);
+                    gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
                 } else {
-                    gen_aa32_ld32u(s, tmp, tmp2, i);
+                    gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
                 }
             } else {
                 /* store */
                 tmp = load_reg(s, rd);
                 if (insn & (1 << 22)) {
-                    gen_aa32_st8(s, tmp, tmp2, i);
+                    gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
                 } else {
-                    gen_aa32_st32(s, tmp, tmp2, i);
+                    gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
                 }
                 tcg_temp_free_i32(tmp);
             }
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         tmp = tcg_temp_new_i32();
                         switch (op) {
                         case 0: /* ldab */
-                            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
+                                              rs | ISSIsAcqRel);
                             break;
                         case 1: /* ldah */
-                            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
+                                               rs | ISSIsAcqRel);
                             break;
                         case 2: /* lda */
-                            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
+                                               rs | ISSIsAcqRel);
                             break;
                         default:
                             abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         tmp = load_reg(s, rs);
                         switch (op) {
                         case 0: /* stlb */
-                            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
+                                             rs | ISSIsAcqRel);
                             break;
                         case 1: /* stlh */
-                            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
+                                              rs | ISSIsAcqRel);
                             break;
                         case 2: /* stl */
-                            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
+                                              rs | ISSIsAcqRel);
                             break;
                         default:
                             abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
         int postinc = 0;
         int writeback = 0;
         int memidx;
+        ISSInfo issinfo;
+
         if ((insn & 0x01100000) == 0x01000000) {
             if (disas_neon_ls_insn(s, insn)) {
                 goto illegal_op;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                 }
             }
         }
+
+        issinfo = writeback ? ISSInvalid : rs;
+
         if (insn & (1 << 20)) {
             /* Load.  */
             tmp = tcg_temp_new_i32();
             switch (op) {
             case 0:
-                gen_aa32_ld8u(s, tmp, addr, memidx);
+                gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 4:
-                gen_aa32_ld8s(s, tmp, addr, memidx);
+                gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 1:
-                gen_aa32_ld16u(s, tmp, addr, memidx);
+                gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 5:
-                gen_aa32_ld16s(s, tmp, addr, memidx);
+                gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 2:
-                gen_aa32_ld32u(s, tmp, addr, memidx);
+                gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
                 break;
             default:
                 tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
             tmp = load_reg(s, rs);
             switch (op) {
             case 0:
-                gen_aa32_st8(s, tmp, addr, memidx);
+                gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 1:
-                gen_aa32_st16(s, tmp, addr, memidx);
+                gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 2:
-                gen_aa32_st32(s, tmp, addr, memidx);
+                gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
                 break;
             default:
                 tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
             addr = tcg_temp_new_i32();
             tcg_gen_movi_i32(addr, val);
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
+                               rd | ISSIs16Bit);
             tcg_temp_free_i32(addr);
             store_reg(s, rd, tmp);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 
         switch (op) {
         case 0: /* str */
-            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 1: /* strh */
-            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 2: /* strb */
-            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 3: /* ldrsb */
-            gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 4: /* ldr */
-            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 5: /* ldrh */
-            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 6: /* ldrb */
-            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 7: /* ldrsh */
-            gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         }
         if (op >= 3) { /* load */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         if (insn & (1 << 11)) {
             /* load */
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             store_reg(s, rd, tmp);
         } else {
             /* store */
             tmp = load_reg(s, rd);
-            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             tcg_temp_free_i32(tmp);
         }
         tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         if (insn & (1 << 11)) {
             /* load */
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             store_reg(s, rd, tmp);
         } else {
             /* store */
             tmp = load_reg(s, rd);
-            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             tcg_temp_free_i32(tmp);
         }
         tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         if (insn & (1 << 11)) {
             /* load */
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             store_reg(s, rd, tmp);
         } else {
             /* store */
             tmp = load_reg(s, rd);
-            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             tcg_temp_free_i32(tmp);
         }
         tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
         store_cpu_field(tmp, condexec_bits);
       }
     do {
+        dc->insn_start_idx = tcg_op_buf_count();
         tcg_gen_insn_start(dc->pc,
                            (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
                            0);
-- 
2.7.4

Add a comment documenting the memory map of the SoC devices and which
are not implemented.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org
---
 hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
         0x40024000, 0x40025000, 0x40026000};
     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
 
+    /* Memory map of SoC devices, from
+     * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
+     * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
+     *
+     * 40000000 wdtimer (unimplemented)
+     * 40002000 i2c (unimplemented)
+     * 40004000 GPIO
+     * 40005000 GPIO
+     * 40006000 GPIO
+     * 40007000 GPIO
+     * 40008000 SSI
+     * 4000c000 UART
+     * 4000d000 UART
+     * 4000e000 UART
+     * 40020000 i2c
+     * 40021000 i2c (unimplemented)
+     * 40024000 GPIO
+     * 40025000 GPIO
+     * 40026000 GPIO
+     * 40028000 PWM (unimplemented)
+     * 4002c000 QEI (unimplemented)
+     * 4002d000 QEI (unimplemented)
+     * 40030000 gptimer
+     * 40031000 gptimer
+     * 40032000 gptimer
+     * 40033000 gptimer
+     * 40038000 ADC
+     * 4003c000 analogue comparator (unimplemented)
+     * 40048000 ethernet
+     * 400fc000 hibernation module (unimplemented)
+     * 400fd000 flash memory control (unimplemented)
+     * 400fe000 system control
+     */
+
     DeviceState *gpio_dev[7], *nvic;
     qemu_irq gpio_in[7][8];
     qemu_irq gpio_out[7][8];
-- 
2.7.4

Create a new "unimplemented" sysbus device, which simply accepts
all read and write accesses, and implements them as read-as-zero,
write-ignored, with logging of the access as LOG_UNIMP.

This is useful for stubbing out bits of an SoC or board model
which haven't been written yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org
---
 hw/misc/Makefile.objs   |   2 +
 include/hw/misc/unimp.h |  39 ++++++++++++++++++
 hw/misc/unimp.c         | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 148 insertions(+)
 create mode 100644 include/hw/misc/unimp.h
 create mode 100644 hw/misc/unimp.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
 common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
 common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
 
+common-obj-y += unimp.o
+
 obj-$(CONFIG_VMPORT) += vmport.o
 
 # ARM devices
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/unimp.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * "Unimplemented" device
+ *
+ * Copyright Linaro Limited, 2017
+ * Written by Peter Maydell
+ */
+
+#ifndef HW_MISC_UNIMP_H
+#define HW_MISC_UNIMP_H
+
+#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
+
+/**
+ * create_unimplemented_device: create and map a dummy device
+ * @name: name of the device for debug logging
+ * @base: base address of the device's MMIO region
+ * @size: size of the device's MMIO region
+ *
+ * This utility function creates and maps an instance of unimplemented-device,
+ * which is a dummy device which simply logs all guest accesses to
+ * it via the qemu_log LOG_UNIMP debug log.
+ * The device is mapped at priority -1000, which means that you can
+ * use it to cover a large region and then map other devices on top of it
+ * if necessary.
+ */
+static inline void create_unimplemented_device(const char *name,
+                                               hwaddr base,
+                                               hwaddr size)
+{
+    DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
+
+    qdev_prop_set_string(dev, "name", name);
+    qdev_prop_set_uint64(dev, "size", size);
+    qdev_init_nofail(dev);
+
+    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
+}
+
+#endif
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/unimp.c
@@ -XXX,XX +XXX,XX @@
+/* "Unimplemented" device
+ *
+ * This is a dummy device which accepts and logs all accesses.
+ * It's useful for stubbing out regions of an SoC or board
+ * map which correspond to devices that have not yet been
+ * implemented. This is often sufficient to placate initial
+ * guest device driver probing such that the system will
+ * come up.
+ *
+ * Copyright Linaro Limited, 2017
+ * Written by Peter Maydell
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/unimp.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+
+#define UNIMPLEMENTED_DEVICE(obj) \
+    OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)
+
+typedef struct {
+    SysBusDevice parent_obj;
+    MemoryRegion iomem;
+    char *name;
+    uint64_t size;
+} UnimplementedDeviceState;
+
+static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
+{
+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
+
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                  "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                  s->name, size, offset);
+    return 0;
+}
+
+static void unimp_write(void *opaque, hwaddr offset,
+                        uint64_t value, unsigned size)
+{
+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
+
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                  "(size %d, value 0x%" PRIx64
+                  ", offset 0x%" HWADDR_PRIx ")\n",
+                  s->name, size, value, offset);
+}
+
+static const MemoryRegionOps unimp_ops = {
+    .read = unimp_read,
+    .write = unimp_write,
+    .impl.min_access_size = 1,
+    .impl.max_access_size = 8,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 8,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void unimp_realize(DeviceState *dev, Error **errp)
+{
+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);
+
+    if (s->size == 0) {
+        error_setg(errp, "property 'size' not specified or zero");
+        return;
+    }
+
+    if (s->name == NULL) {
+        error_setg(errp, "property 'name' not specified");
+        return;
+    }
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
+                          s->name, s->size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static Property unimp_properties[] = {
+    DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),
+    DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void unimp_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = unimp_realize;
+    dc->props = unimp_properties;
+}
+
+static const TypeInfo unimp_info = {
+    .name = TYPE_UNIMPLEMENTED_DEVICE,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(UnimplementedDeviceState),
+    .class_init = unimp_class_init,
+};
+
+static void unimp_register_types(void)
+{
+    type_register_static(&unimp_info);
+}
+
+type_init(unimp_register_types)
-- 
2.7.4

Use the 'unimplemented' dummy device to cover regions of the
SoC device memory map which we don't have proper device
implementations for yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org
---
 hw/arm/stellaris.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
 #include "hw/char/pl011.h"
+#include "hw/misc/unimp.h"
 
 #define GPIO_A 0
 #define GPIO_B 1
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
             }
         }
     }
+
+    /* Add dummy regions for the devices we don't implement yet,
+     * so guest accesses don't cause unlogged crashes.
+     */
+    create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
+    create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
+    create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
+    create_unimplemented_device("PWM", 0x40028000, 0x1000);
+    create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
+    create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
+    create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
+    create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
+    create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
 }
 
 /* FIXME: Figure out how to generate these from stellaris_boards.  */
-- 
2.7.4

Arm queue; not huge but I figured I might as well send it out since
I've been doing code review today and there's no queue of unprocessed
pullreqs...

thanks
-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

----------------------------------------------------------------
target-arm queue:
 * arm: Support emulation of ARMv8.4-TTST extension
 * arm: Update cpu.h ID register field definitions
 * arm: Fix breakage of XScale instruction emulation
 * hw/net/lan9118: Fix RX Status FIFO PEEK value
 * npcm7xx: Add ADC and PWM emulation
 * ui/cocoa: Make "open docs" help menu entry work again when binary
   is run from the build tree
 * ui/cocoa: Fix openFile: deprecation on Big Sur
 * docs: Add qemu-storage-daemon(1) manpage to meson.build
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Hao Wu (6):
      hw/misc: Add clock converter in NPCM7XX CLK module
      hw/timer: Refactor NPCM7XX Timer to use CLK clock
      hw/adc: Add an ADC module for NPCM7XX
      hw/misc: Add a PWM module for NPCM7XX
      hw/misc: Add QTest for NPCM7XX PWM Module
      hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):
      target/arm: fix typo in cpu.h ID_AA64PFR1 field name
      target/arm: make ARMCPU.clidr 64-bit
      target/arm: make ARMCPU.ctr 64-bit
      target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
      target/arm: add aarch64 ID register fields to cpu.h
      target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):
      docs: Add qemu-storage-daemon(1) manpage to meson.build
      docs: Build and install all the docs in a single manual
      target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
      hw/net/lan9118: Fix RX Status FIFO PEEK value
      hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):
      ui/cocoa: Update path to docs in build tree
      ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):
      target/arm: ARMv8.4-TTST extension
      target/arm: enable Small Translation tables in max CPU

docs/conf.py                     |  46 ++-
 docs/devel/conf.py               |  15 -
 docs/index.html.in               |  17 -
 docs/interop/conf.py             |  28 --
 docs/meson.build                 |  65 ++--
 docs/specs/conf.py               |  16 -
 docs/system/arm/nuvoton.rst      |   4 +-
 docs/system/conf.py              |  28 --
 docs/tools/conf.py               |  37 --
 docs/user/conf.py                |  15 -
 meson.build                      |   1 +
 hw/adc/trace.h                   |   1 +
 include/hw/adc/npcm7xx_adc.h     |  69 ++++
 include/hw/arm/npcm7xx.h         |   4 +
 include/hw/misc/npcm7xx_clk.h    | 146 ++++++-
 include/hw/misc/npcm7xx_pwm.h    | 105 +++++
 include/hw/timer/npcm7xx_timer.h |   1 +
 target/arm/cpu.h                 |  85 ++++-
 hw/adc/npcm7xx_adc.c             | 301 +++++++++++++++
 hw/arm/npcm7xx.c                 |  55 ++-
 hw/arm/npcm7xx_boards.c          |   2 +-
 hw/mem/npcm7xx_mc.c              |   2 +-
 hw/misc/npcm7xx_clk.c            | 807 ++++++++++++++++++++++++++++++++++++++-
 hw/misc/npcm7xx_gcr.c            |   2 +-
 hw/misc/npcm7xx_pwm.c            | 550 ++++++++++++++++++++++++++
 hw/misc/npcm7xx_rng.c            |   2 +-
 hw/net/lan9118.c                 |  26 +-
 hw/nvram/npcm7xx_otp.c           |   2 +-
 hw/ssi/npcm7xx_fiu.c             |   2 +-
 hw/timer/npcm7xx_timer.c         |  39 +-
 target/arm/cpu64.c               |   1 +
 target/arm/helper.c              |  15 +-
 target/arm/translate.c           |   7 +
 tests/qtest/npcm7xx_adc-test.c   | 377 ++++++++++++++++++
 tests/qtest/npcm7xx_pwm-test.c   | 490 ++++++++++++++++++++++++
 hw/adc/meson.build               |   1 +
 hw/adc/trace-events              |   5 +
 hw/misc/meson.build              |   1 +
 hw/misc/trace-events             |   6 +
 tests/qtest/meson.build          |   4 +-
 ui/cocoa.m                       |   7 +-
 41 files changed, 3124 insertions(+), 263 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 include/hw/misc/npcm7xx_pwm.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 hw/misc/npcm7xx_pwm.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c
 create mode 100644 hw/adc/trace-events

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds for the Small Translation tables extension in AArch64 state.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  5 +++++
 target/arm/helper.c | 15 +++++++++++++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
 }
 
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+}
+
 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
 {
     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
     bool epd, hpd, using16k, using64k;
-    int select, tsz, tbi;
+    int select, tsz, tbi, max_tsz;
 
     if (!regime_has_2_ranges(mmu_idx)) {
         select = 0;
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
             hpd = extract64(tcr, 42, 1);
         }
     }
-    tsz = MIN(tsz, 39);  /* TODO: ARMv8.4-TTST */
+
+    if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
+        max_tsz = 48 - using64k;
+    } else {
+        max_tsz = 39;
+    }
+
+    tsz = MIN(tsz, max_tsz);
     tsz = MAX(tsz, 16);  /* TODO: ARMv8.2-LVA  */
 
     /* Present TBI as a composite with TBID.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
         if (!aarch64 || stride == 9) {
             /* AArch32 or 4KB pages */
             startlevel = 2 - sl0;
+
+            if (cpu_isar_feature(aa64_st, cpu)) {
+                startlevel &= 3;
+            }
         } else {
             /* 16KB or 64KB pages */
             startlevel = 3 - sl0;
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-3-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     uint32_t id_afr0;
     uint64_t id_aa64afr0;
     uint64_t id_aa64afr1;
-    uint32_t clidr;
+    uint64_t clidr;
     uint64_t mp_affinity; /* MP ID without feature bits */
     /* The elements of this array are the CCSIDR values for each cache,
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-5-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+/* When FEAT_CCIDX is implemented */
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
+
+/* When FEAT_CCIDX is not implemented */
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+FIELD(CTR_EL0,  TMINLINE, 32, 6)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-6-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
 FIELD(ID_AA64ISAR1, SB, 36, 4)
 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
 
 FIELD(ID_AA64PFR0, EL0, 0, 4)
 FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SSBS, 4, 4)
 FIELD(ID_AA64PFR1, MTE, 8, 4)
 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
 
 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
 FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
 
 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
 FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
 
 FIELD(ID_AA64MMFR2, CNP, 0, 4)
 FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
 
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
-- 
2.20.1

From: Leif Lindholm <leif@nuviainc.com>

Add entries present in ARM DDI 0487F.c (August 2020).

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-7-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
 FIELD(ID_ISAR6, FHM, 8, 4)
 FIELD(ID_ISAR6, SB, 12, 4)
 FIELD(ID_ISAR6, SPECRES, 16, 4)
+FIELD(ID_ISAR6, BF16, 20, 4)
+FIELD(ID_ISAR6, I8MM, 24, 4)
 
 FIELD(ID_MMFR0, VMSA, 0, 4)
 FIELD(ID_MMFR0, PMSA, 4, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
 FIELD(ID_MMFR0, FCSE, 24, 4)
 FIELD(ID_MMFR0, INNERSHR, 28, 4)
 
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
+FIELD(ID_MMFR1, L1HVD, 16, 4)
+FIELD(ID_MMFR1, L1UNI, 20, 4)
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
+FIELD(ID_MMFR1, BPRED, 28, 4)
+
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
+FIELD(ID_MMFR2, UNITLB, 16, 4)
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
+
 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
 FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_MMFR5, ETS, 0, 4)
+
 FIELD(ID_PFR0, STATE0, 0, 4)
 FIELD(ID_PFR0, STATE1, 4, 4)
 FIELD(ID_PFR0, STATE2, 8, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
 FIELD(ID_PFR1, GIC, 28, 4)
 
+FIELD(ID_PFR2, CSV3, 0, 4)
+FIELD(ID_PFR2, SSBS, 4, 4)
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
+
 FIELD(ID_AA64ISAR0, AES, 4, 4)
 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(ID_DFR1, MTPMU, 0, 4)
+
 FIELD(DBGDIDR, SE_IMP, 12, 1)
 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
 FIELD(DBGDIDR, VERSION, 16, 4)
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

QEMU documentation can't be opened if QEMU is run from build tree
because executables are placed in the top of build tree after conversion
to meson.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
 - (void) openDocumentation: (NSString *) filename
 {
     /* Where to look for local files */
-    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
+    NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
 
     /* iterate thru the possible paths until the file is found */
-- 
2.20.1

In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
At the moment new manpages have to be listed both in the conf.py for
Sphinx and also in docs/meson.build for Meson. We forgot the second
of those -- correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
---
 docs/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
+        'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-- 
2.20.1

When we first converted our documentation to Sphinx, we split it into
multiple manuals (system, interop, tools, etc), which are all built
separately.  The primary driver for this was wanting to be able to
avoid shipping the 'devel' manual to end-users.  However, this is
working against the grain of the way Sphinx wants to be used and
causes some annoyances:
 * Cross-references between documents become much harder or
   possibly impossible
 * There is no single index to the whole documentation
 * Within one manual there's no links or table-of-contents info
   that lets you easily navigate to the others
 * The devel manual doesn't get published on the QEMU website
   (it would be nice to able to refer to it there)

Merely hiding our developer documentation from end users seems like
it's not enough benefit for these costs.  Combine all the
documentation into a single manual (the same way that the readthedocs
site builds it) and install the whole thing.  The previous manual
divisions remain as the new top level sections in the manual.

* The per-manual conf.py files are no longer needed
 * The man_pages[] specifications previously in each per-manual
   conf.py move to the top level conf.py
 * docs/meson.build logic is simplified as we now only need to run
   Sphinx once for the HTML and then once for the manpages5B
 * The old index.html.in that produced the top-level page with
   links to each manual is no longer needed

Unfortunately this means that we now have to build the HTML
documentation into docs/manual in the build tree rather than directly
into docs/; otherwise it is too awkward to ensure we install only the
built manual and not also the dependency info, stamp file, etc.  The
manual still ends up in the same place in the final installed
directory, but anybody who was consulting documentation from within
the build tree will have to adjust where they're looking.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
---
 docs/conf.py         | 46 ++++++++++++++++++++++++++++++-
 docs/devel/conf.py   | 15 -----------
 docs/index.html.in   | 17 ------------
 docs/interop/conf.py | 28 -------------------
 docs/meson.build     | 64 +++++++++++++++++---------------------------
 docs/specs/conf.py   | 16 -----------
 docs/system/conf.py  | 28 -------------------
 docs/tools/conf.py   | 37 -------------------------
 docs/user/conf.py    | 15 -----------
 9 files changed, 70 insertions(+), 196 deletions(-)
 delete mode 100644 docs/devel/conf.py
 delete mode 100644 docs/index.html.in
 delete mode 100644 docs/interop/conf.py
 delete mode 100644 docs/specs/conf.py
 delete mode 100644 docs/system/conf.py
 delete mode 100644 docs/tools/conf.py
 delete mode 100644 docs/user/conf.py

diff --git a/docs/conf.py b/docs/conf.py
index XXXXXXX..XXXXXXX 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -XXX,XX +XXX,XX @@ latex_documents = [
 
 # -- Options for manual page output ---------------------------------------
 # Individual manual/conf.py can override this to create man pages
-man_pages = []
+man_pages = [
+    ('interop/qemu-ga', 'qemu-ga',
+     'QEMU Guest Agent',
+     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
+    ('interop/qemu-ga-ref', 'qemu-ga-ref',
+     'QEMU Guest Agent Protocol Reference',
+     [], 7),
+    ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
+     'QEMU QMP Reference Manual',
+     [], 7),
+    ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
+     'QEMU Storage Daemon QMP Reference Manual',
+     [], 7),
+    ('system/qemu-manpage', 'qemu',
+     'QEMU User Documentation',
+     ['Fabrice Bellard'], 1),
+    ('system/qemu-block-drivers', 'qemu-block-drivers',
+     'QEMU block drivers reference',
+     ['Fabrice Bellard and the QEMU Project developers'], 7),
+    ('system/qemu-cpu-models', 'qemu-cpu-models',
+     'QEMU CPU Models',
+     ['The QEMU Project developers'], 7),
+    ('tools/qemu-img', 'qemu-img',
+     'QEMU disk image utility',
+     ['Fabrice Bellard'], 1),
+    ('tools/qemu-nbd', 'qemu-nbd',
+     'QEMU Disk Network Block Device Server',
+     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
+    ('tools/qemu-pr-helper', 'qemu-pr-helper',
+     'QEMU persistent reservation helper',
+     [], 8),
+    ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
+     'QEMU storage daemon',
+     [], 1),
+    ('tools/qemu-trace-stap', 'qemu-trace-stap',
+     'QEMU SystemTap trace tool',
+     [], 1),
+    ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
+     'QEMU 9p virtfs proxy filesystem helper',
+     ['M. Mohan Kumar'], 1),
+    ('tools/virtiofsd', 'virtiofsd',
+     'QEMU virtio-fs shared file system daemon',
+     ['Stefan Hajnoczi <stefanha@redhat.com>',
+      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
+]
 
 # -- Options for Texinfo output -------------------------------------------
 
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/devel/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'devel' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'Developer''s Guide'
diff --git a/docs/index.html.in b/docs/index.html.in
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/index.html.in
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-<!DOCTYPE html>
-<html lang="en">
-    <head>
-        <meta charset="UTF-8">
-        <title>QEMU @VERSION@ Documentation</title>
-    </head>
-    <body>
-        <h1>QEMU @VERSION@ Documentation</h1>
-        <ul>
-            <li><a href="system/index.html">System Emulation User's Guide</a></li>
-            <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
-            <li><a href="tools/index.html">Tools Guide</a></li>
-            <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
-            <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
-        </ul>
-    </body>
-</html>
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/interop/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'interop' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
-     ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
-    ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
-     [], 7),
-    ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
-     [], 7),
-    ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
-     'QEMU Storage Daemon QMP Reference Manual', [], 7),
-]
diff --git a/docs/meson.build b/docs/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/docs/meson.build
+++ b/docs/meson.build
@@ -XXX,XX +XXX,XX @@ if build_docs
                           meson.source_root() / 'docs/sphinx/qmp_lexer.py',
                           qapi_gen_depends ]
 
-  configure_file(output: 'index.html',
-                 input: files('index.html.in'),
-                 configuration: {'VERSION': meson.project_version()},
-                 install_dir: qemu_docdir)
-  manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
   man_pages = {
-    'interop' : {
         'qemu-ga.8': (have_tools ? 'man8' : ''),
         'qemu-ga-ref.7': 'man7',
         'qemu-qmp-ref.7': 'man7',
         'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
-    },
-    'tools': {
         'qemu-img.1': (have_tools ? 'man1' : ''),
         'qemu-nbd.8': (have_tools ? 'man8' : ''),
         'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
@@ -XXX,XX +XXX,XX @@ if build_docs
         'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
         'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
         'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
-    },
-    'system': {
         'qemu.1': 'man1',
         'qemu-block-drivers.7': 'man7',
         'qemu-cpu-models.7': 'man7'
-    },
   }
 
   sphinxdocs = []
   sphinxmans = []
-  foreach manual : manuals
-    private_dir = meson.current_build_dir() / (manual + '.p')
-    output_dir = meson.current_build_dir() / manual
-    input_dir = meson.current_source_dir() / manual
 
-    this_manual = custom_target(manual + ' manual',
+  private_dir = meson.current_build_dir() / 'manual.p'
+  output_dir = meson.current_build_dir() / 'manual'
+  input_dir = meson.current_source_dir()
+
+  this_manual = custom_target('QEMU manual',
                 build_by_default: build_docs,
-                output: [manual + '.stamp'],
-                input: [files('conf.py'), files(manual / 'conf.py')],
-                depfile: manual + '.d',
+                output: 'docs.stamp',
+                input: files('conf.py'),
+                depfile: 'docs.d',
                 depend_files: sphinx_extn_depends,
                 command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
                           '-Ddepfile_stamp=@OUTPUT0@',
                           '-b', 'html', '-d', private_dir,
                           input_dir, output_dir])
-    sphinxdocs += this_manual
-    if build_docs and manual != 'devel'
-      install_subdir(output_dir, install_dir: qemu_docdir)
-    endif
+  sphinxdocs += this_manual
+  install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
 
-    these_man_pages = []
-    install_dirs = []
-    foreach page, section : man_pages.get(manual, {})
-      these_man_pages += page
-      install_dirs += section == '' ? false : get_option('mandir') / section
-    endforeach
-    if these_man_pages.length() > 0
-      sphinxmans += custom_target(manual + ' man pages',
-                         build_by_default: build_docs,
-                         output: these_man_pages,
-                         input: this_manual,
-                         install: build_docs,
-                         install_dir: install_dirs,
-                         command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
-                                   input_dir, meson.current_build_dir()])
-    endif
+  these_man_pages = []
+  install_dirs = []
+  foreach page, section : man_pages
+    these_man_pages += page
+    install_dirs += section == '' ? false : get_option('mandir') / section
   endforeach
+
+  sphinxmans += custom_target('QEMU man pages',
+                              build_by_default: build_docs,
+                              output: these_man_pages,
+                              input: this_manual,
+                              install: build_docs,
+                              install_dir: install_dirs,
+                              command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
+                                        input_dir, meson.current_build_dir()])
+
   alias_target('sphinxdocs', sphinxdocs)
   alias_target('html', sphinxdocs)
   alias_target('man', sphinxmans)
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/specs/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'specs' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'System Emulation Guest Hardware Specifications'
diff --git a/docs/system/conf.py b/docs/system/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/system/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'system' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'System Emulation User''s Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-manpage', 'qemu', u'QEMU User Documentation',
-     ['Fabrice Bellard'], 1),
-    ('qemu-block-drivers', 'qemu-block-drivers',
-     u'QEMU block drivers reference',
-     ['Fabrice Bellard and the QEMU Project developers'], 7),
-    ('qemu-cpu-models', 'qemu-cpu-models',
-     u'QEMU CPU Models',
-     ['The QEMU Project developers'], 7)
-]
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/tools/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'tools' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = \
-    u'Tools Guide'
-
-# One entry per manual page. List of tuples
-# (source start file, name, description, authors, manual section).
-man_pages = [
-    ('qemu-img', 'qemu-img', u'QEMU disk image utility',
-     ['Fabrice Bellard'], 1),
-    ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
-     [], 1),
-    ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
-     ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
-    ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
-     [], 8),
-    ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
-     [], 1),
-    ('virtfs-proxy-helper', 'virtfs-proxy-helper',
-     u'QEMU 9p virtfs proxy filesystem helper',
-     ['M. Mohan Kumar'], 1),
-    ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
-     ['Stefan Hajnoczi <stefanha@redhat.com>',
-      'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
-]
diff --git a/docs/user/conf.py b/docs/user/conf.py
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/docs/user/conf.py
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# -*- coding: utf-8 -*-
-#
-# QEMU documentation build configuration file for the 'user' manual.
-#
-# This includes the top level conf file and then makes any necessary tweaks.
-import sys
-import os
-
-qemu_docdir = os.path.abspath("..")
-parent_config = os.path.join(qemu_docdir, "conf.py")
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
-
-# This slightly misuses the 'description', but is the best way to get
-# the manual title to appear in the sidebar.
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
-- 
2.20.1

In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
---
 target/arm/translate.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
      * only cp14 and cp15 are valid, and other values aren't considered
      * to be in the coprocessor-instruction space at all. v8M still
      * permits coprocessors 0..7.
+     * For XScale, we must not decode the XScale cp0, cp1 space as
+     * a standard coprocessor insn, because we want to fall through to
+     * the legacy disas_xscale_insn() decoder after decodetree is done.
      */
+    if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
+        return false;
+    }
+
     if (arm_dc_feature(s, ARM_FEATURE_V8) &&
         !arm_dc_feature(s, ARM_FEATURE_M)) {
         return cp >= 14;
-- 
2.20.1

The lan9118 code mostly uses symbolic constants for register offsets;
the exceptions are those which the datasheet doesn't give an official
symbolic name to.

Add some names for the registers which don't already have them, based
on the longer names they are given in the memory map.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
---
 hw/net/lan9118.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/lan9118.c
+++ b/hw/net/lan9118.c
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
 #endif
 
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
+#define RX_DATA_FIFO_PORT_FIRST 0x00
+#define RX_DATA_FIFO_PORT_LAST 0x1f
+#define TX_DATA_FIFO_PORT_FIRST 0x20
+#define TX_DATA_FIFO_PORT_LAST 0x3f
+
+#define RX_STATUS_FIFO_PORT 0x40
+#define RX_STATUS_FIFO_PEEK 0x44
+#define TX_STATUS_FIFO_PORT 0x48
+#define TX_STATUS_FIFO_PEEK 0x4c
+
 #define CSR_ID_REV      0x50
 #define CSR_IRQ_CFG     0x54
 #define CSR_INT_STS     0x58
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
     offset &= 0xff;
 
     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
-    if (offset >= 0x20 && offset < 0x40) {
+    if (offset >= TX_DATA_FIFO_PORT_FIRST &&
+        offset <= TX_DATA_FIFO_PORT_LAST) {
         /* TX FIFO */
         tx_fifo_push(s, val);
         return;
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
     lan9118_state *s = (lan9118_state *)opaque;
 
     //DPRINTF("Read reg 0x%02x\n", (int)offset);
-    if (offset < 0x20) {
+    if (offset <= RX_DATA_FIFO_PORT_LAST) {
         /* RX FIFO */
         return rx_fifo_pop(s);
     }
     switch (offset) {
-    case 0x40:
+    case RX_STATUS_FIFO_PORT:
         return rx_status_fifo_pop(s);
-    case 0x44:
+    case RX_STATUS_FIFO_PEEK:
         return s->rx_status_fifo[s->rx_status_fifo_head];
-    case 0x48:
+    case TX_STATUS_FIFO_PORT:
         return tx_status_fifo_pop(s);
-    case 0x4c:
+    case TX_STATUS_FIFO_PEEK:
         return s->tx_status_fifo[s->tx_status_fifo_head];
     case CSR_ID_REV:
         return 0x01180001;
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch allows NPCM7XX CLK module to compute clocks that are used by
other NPCM7XX modules.

Add a new struct NPCM7xxClockConverterState which represents a
single converter.  Each clock converter in CLK module represents one
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
takes one or more input clocks and converts them into one output clock.
They form a clock hierarchy in the CLK module and are responsible for
outputing clocks for various other modules in an NPCM7XX SoC.

Each converter has a function pointer called "convert" which represents
the unique logic for that converter.

The clock contains two initialization information: ConverterInitInfo and
ConverterConnectionInfo. They represent the vertices and edges in the
clock diagram respectively.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_clk.h | 140 +++++-
 hw/misc/npcm7xx_clk.c         | 805 +++++++++++++++++++++++++++++++++-
 2 files changed, 932 insertions(+), 13 deletions(-)

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_CLK_H
 
 #include "exec/memory.h"
+#include "hw/clock.h"
 #include "hw/sysbus.h"
 
 /*
@@ -XXX,XX +XXX,XX @@
 
 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
 
-typedef struct NPCM7xxCLKState {
+/* Maximum amount of clock inputs in a SEL module. */
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
+
+/* PLLs in CLK module. */
+typedef enum NPCM7xxClockPLL {
+    NPCM7XX_CLOCK_PLL0,
+    NPCM7XX_CLOCK_PLL1,
+    NPCM7XX_CLOCK_PLL2,
+    NPCM7XX_CLOCK_PLLG,
+    NPCM7XX_CLOCK_NR_PLLS,
+} NPCM7xxClockPLL;
+
+/* SEL/MUX in CLK module. */
+typedef enum NPCM7xxClockSEL {
+    NPCM7XX_CLOCK_PIXCKSEL,
+    NPCM7XX_CLOCK_MCCKSEL,
+    NPCM7XX_CLOCK_CPUCKSEL,
+    NPCM7XX_CLOCK_CLKOUTSEL,
+    NPCM7XX_CLOCK_UARTCKSEL,
+    NPCM7XX_CLOCK_TIMCKSEL,
+    NPCM7XX_CLOCK_SDCKSEL,
+    NPCM7XX_CLOCK_GFXMSEL,
+    NPCM7XX_CLOCK_SUCKSEL,
+    NPCM7XX_CLOCK_NR_SELS,
+} NPCM7xxClockSEL;
+
+/* Dividers in CLK module. */
+typedef enum NPCM7xxClockDivider {
+    NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
+    NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
+    NPCM7XX_CLOCK_MC_DIVIDER,
+    NPCM7XX_CLOCK_AXI_DIVIDER,
+    NPCM7XX_CLOCK_AHB_DIVIDER,
+    NPCM7XX_CLOCK_AHB3_DIVIDER,
+    NPCM7XX_CLOCK_SPI0_DIVIDER,
+    NPCM7XX_CLOCK_SPIX_DIVIDER,
+    NPCM7XX_CLOCK_APB1_DIVIDER,
+    NPCM7XX_CLOCK_APB2_DIVIDER,
+    NPCM7XX_CLOCK_APB3_DIVIDER,
+    NPCM7XX_CLOCK_APB4_DIVIDER,
+    NPCM7XX_CLOCK_APB5_DIVIDER,
+    NPCM7XX_CLOCK_CLKOUT_DIVIDER,
+    NPCM7XX_CLOCK_UART_DIVIDER,
+    NPCM7XX_CLOCK_TIMER_DIVIDER,
+    NPCM7XX_CLOCK_ADC_DIVIDER,
+    NPCM7XX_CLOCK_MMC_DIVIDER,
+    NPCM7XX_CLOCK_SDHC_DIVIDER,
+    NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
+    NPCM7XX_CLOCK_UTMI_DIVIDER,
+    NPCM7XX_CLOCK_NR_DIVIDERS,
+} NPCM7xxClockConverter;
+
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
+
+/**
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @reg: The control registers for this PLL module.
+ */
+typedef struct NPCM7xxClockPLLState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    int reg;
+} NPCM7xxClockPLLState;
+
+/**
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @input_size: The size of inputs of this module.
+ * @clock_in: The input clocks of this module.
+ * @clock_out: The output clocks of this module.
+ * @offset: The offset of this module in the control register.
+ * @len: The length of this module in the control register.
+ */
+typedef struct NPCM7xxClockSELState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    uint8_t input_size;
+    Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
+    Clock *clock_out;
+
+    int offset;
+    int len;
+} NPCM7xxClockSELState;
+
+/**
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
+ * @name: The name of the module.
+ * @clk: The CLK module that owns this module.
+ * @clock_in: The input clock of this module.
+ * @clock_out: The output clock of this module.
+ * @divide: The function the divider uses to divide the input.
+ * @reg: The index of the control register that contains the divisor.
+ * @offset: The offset of the divisor in the control register.
+ * @len: The length of the divisor in the control register.
+ * @divisor: The divisor for a constant divisor
+ */
+typedef struct NPCM7xxClockDividerState {
+    DeviceState parent;
+
+    const char *name;
+    NPCM7xxCLKState *clk;
+    Clock *clock_in;
+    Clock *clock_out;
+
+    uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
+    union {
+        struct {
+            int reg;
+            int offset;
+            int len;
+        };
+        int divisor;
+    };
+} NPCM7xxClockDividerState;
+
+struct NPCM7xxCLKState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
 
+    /* Clock converters */
+    NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
+    NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
+    NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
+
     uint32_t regs[NPCM7XX_CLK_NR_REGS];
 
     /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
     int64_t ref_ns;
-} NPCM7xxCLKState;
+
+    /* The incoming reference clock. */
+    Clock *clkref;
+};
 
 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
 #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
+#include "hw/qdev-clock.h"
 #include "migration/vmstate.h"
 #include "qemu/error-report.h"
 #include "qemu/log.h"
@@ -XXX,XX +XXX,XX @@
 #include "trace.h"
 #include "sysemu/watchdog.h"
 
+/*
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
+ * is always 25 MHz.
+ */
+#define NPCM7XX_CLOCK_REF_HZ            (25000000)
+
+/* Register Field Definitions */
+#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
+
 #define PLLCON_LOKI     BIT(31)
 #define PLLCON_LOKS     BIT(30)
 #define PLLCON_PWDEN    BIT(12)
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
+#define PLLCON_INDV(con) extract32((con), 0, 6)
 
 enum NPCM7xxCLKRegisters {
     NPCM7XX_CLK_CLKEN1,
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
     [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
 };
 
-/* Register Field Definitions */
-#define NPCM7XX_CLK_WDRCR_CA9C  BIT(0) /* Cortex A9 Cores */
-
 /* The number of watchdogs that can trigger a reset. */
 #define NPCM7XX_NR_WATCHDOGS    (3)
 
+/* Clock converter functions */
+
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
+        (obj), TYPE_NPCM7XX_CLOCK_PLL)
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
+        (obj), TYPE_NPCM7XX_CLOCK_SEL)
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
+        (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
+
+static void npcm7xx_clk_update_pll(void *opaque)
+{
+    NPCM7xxClockPLLState *s = opaque;
+    uint32_t con = s->clk->regs[s->reg];
+    uint64_t freq;
+
+    /* The PLL is grounded if it is not locked yet. */
+    if (con & PLLCON_LOKI) {
+        freq = clock_get_hz(s->clock_in);
+        freq *= PLLCON_FBDV(con);
+        freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
+    } else {
+        freq = 0;
+    }
+
+    clock_update_hz(s->clock_out, freq);
+}
+
+static void npcm7xx_clk_update_sel(void *opaque)
+{
+    NPCM7xxClockSELState *s = opaque;
+    uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
+            s->len);
+
+    if (index >= s->input_size) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: SEL index: %u out of range\n",
+                      __func__, index);
+        index = 0;
+    }
+    clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
+}
+
+static void npcm7xx_clk_update_divider(void *opaque)
+{
+    NPCM7xxClockDividerState *s = opaque;
+    uint32_t freq;
+
+    freq = s->divide(s);
+    clock_update_hz(s->clock_out, freq);
+}
+
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) / s->divisor;
+}
+
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) /
+            (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
+}
+
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
+{
+    return divide_by_reg_divisor(s) / 2;
+}
+
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
+{
+    return clock_get_hz(s->clock_in) >>
+        extract32(s->clk->regs[s->reg], s->offset, s->len);
+}
+
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
+{
+    switch (reg) {
+    case NPCM7XX_CLK_PLLCON0:
+        return NPCM7XX_CLOCK_PLL0;
+    case NPCM7XX_CLK_PLLCON1:
+        return NPCM7XX_CLOCK_PLL1;
+    case NPCM7XX_CLK_PLLCON2:
+        return NPCM7XX_CLOCK_PLL2;
+    case NPCM7XX_CLK_PLLCONG:
+        return NPCM7XX_CLOCK_PLLG;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        npcm7xx_clk_update_pll(&clk->plls[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        npcm7xx_clk_update_sel(&clk->sels[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
+{
+    int i;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        npcm7xx_clk_update_divider(&clk->dividers[i]);
+    }
+}
+
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
+{
+    clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
+    npcm7xx_clk_update_all_plls(clk);
+    npcm7xx_clk_update_all_sels(clk);
+    npcm7xx_clk_update_all_dividers(clk);
+}
+
+/* Types of clock sources. */
+typedef enum ClockSrcType {
+    CLKSRC_REF,
+    CLKSRC_PLL,
+    CLKSRC_SEL,
+    CLKSRC_DIV,
+} ClockSrcType;
+
+typedef struct PLLInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    int reg;
+    const char *public_name;
+} PLLInitInfo;
+
+typedef struct SELInitInfo {
+    const char *name;
+    uint8_t input_size;
+    ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
+    int offset;
+    int len;
+    const char *public_name;
+} SELInitInfo;
+
+typedef struct DividerInitInfo {
+    const char *name;
+    ClockSrcType src_type;
+    int src_index;
+    uint32_t (*divide)(NPCM7xxClockDividerState *s);
+    int reg; /* not used when type == CONSTANT */
+    int offset; /* not used when type == CONSTANT */
+    int len; /* not used when type == CONSTANT */
+    int divisor; /* used only when type == CONSTANT */
+    const char *public_name;
+} DividerInitInfo;
+
+static const PLLInitInfo pll_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL0] = {
+        .name = "pll0",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON0,
+    },
+    [NPCM7XX_CLOCK_PLL1] = {
+        .name = "pll1",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON1,
+    },
+    [NPCM7XX_CLOCK_PLL2] = {
+        .name = "pll2",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCON2,
+    },
+    [NPCM7XX_CLOCK_PLLG] = {
+        .name = "pllg",
+        .src_type = CLKSRC_REF,
+        .reg = NPCM7XX_CLK_PLLCONG,
+    },
+};
+
+static const SELInitInfo sel_init_info_list[] = {
+    [NPCM7XX_CLOCK_PIXCKSEL] = {
+        .name = "pixcksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_PLL, CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLLG, 0},
+        .offset = 5,
+        .len = 1,
+        .public_name = "pixel-clock",
+    },
+    [NPCM7XX_CLOCK_MCCKSEL] = {
+        .name = "mccksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
+            /*MCBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
+        .offset = 12,
+        .len = 2,
+        .public_name = "mc-phy-clock",
+    },
+    [NPCM7XX_CLOCK_CPUCKSEL] = {
+        .name = "cpucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            /*SYSBPCK, shouldn't be used in normal operation*/
+            CLKSRC_REF},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
+        .offset = 0,
+        .len = 2,
+        .public_name = "system-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUTSEL] = {
+        .name = "clkoutsel",
+        .input_size = 5,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
+            CLKSRC_PLL, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
+        .offset = 18,
+        .len = 3,
+        .public_name = "tock",
+    },
+    [NPCM7XX_CLOCK_UARTCKSEL] = {
+        .name = "uartcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 8,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_TIMCKSEL] = {
+        .name = "timcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 14,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_SDCKSEL] = {
+        .name = "sdcksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 6,
+        .len = 2,
+    },
+    [NPCM7XX_CLOCK_GFXMSEL] = {
+        .name = "gfxmksel",
+        .input_size = 2,
+        .src_type = {CLKSRC_REF, CLKSRC_PLL},
+        .src_index = {0, NPCM7XX_CLOCK_PLL2},
+        .offset = 21,
+        .len = 1,
+    },
+    [NPCM7XX_CLOCK_SUCKSEL] = {
+        .name = "sucksel",
+        .input_size = 4,
+        .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
+        .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
+            NPCM7XX_CLOCK_PLL2D2},
+        .offset = 10,
+        .len = 2,
+    },
+};
+
+static const DividerInitInfo divider_init_info_list[] = {
+    [NPCM7XX_CLOCK_PLL1D2] = {
+        .name = "pll1d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL1,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_PLL2D2] = {
+        .name = "pll2d2",
+        .src_type = CLKSRC_PLL,
+        .src_index = NPCM7XX_CLOCK_PLL2,
+        .divide = divide_by_constant,
+        .divisor = 2,
+    },
+    [NPCM7XX_CLOCK_MC_DIVIDER] = {
+        .name = "mc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_MCCKSEL,
+        .divide = divide_by_constant,
+        .divisor = 2,
+        .public_name = "mc-clock"
+    },
+    [NPCM7XX_CLOCK_AXI_DIVIDER] = {
+        .name = "axi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CPUCKSEL,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 0,
+        .len = 1,
+        .public_name = "clk2"
+    },
+    [NPCM7XX_CLOCK_AHB_DIVIDER] = {
+        .name = "ahb-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 26,
+        .len = 2,
+        .public_name = "clk4"
+    },
+    [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
+        .name = "ahb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 6,
+        .len = 5,
+        .public_name = "ahb3-spi3-clock"
+    },
+    [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
+        .name = "spi0-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 6,
+        .len = 5,
+        .public_name = "spi0-clock",
+    },
+    [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
+        .name = "spix-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV3,
+        .offset = 1,
+        .len = 5,
+        .public_name = "spix-clock",
+    },
+    [NPCM7XX_CLOCK_APB1_DIVIDER] = {
+        .name = "apb1-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 24,
+        .len = 2,
+        .public_name = "apb1-clock",
+    },
+    [NPCM7XX_CLOCK_APB2_DIVIDER] = {
+        .name = "apb2-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 26,
+        .len = 2,
+        .public_name = "apb2-clock",
+    },
+    [NPCM7XX_CLOCK_APB3_DIVIDER] = {
+        .name = "apb3-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 28,
+        .len = 2,
+        .public_name = "apb3-clock",
+    },
+    [NPCM7XX_CLOCK_APB4_DIVIDER] = {
+        .name = "apb4-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 30,
+        .len = 2,
+        .public_name = "apb4-clock",
+    },
+    [NPCM7XX_CLOCK_APB5_DIVIDER] = {
+        .name = "apb5-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 22,
+        .len = 2,
+        .public_name = "apb5-clock",
+    },
+    [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
+        .name = "clkout-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 16,
+        .len = 5,
+        .public_name = "clkout",
+    },
+    [NPCM7XX_CLOCK_UART_DIVIDER] = {
+        .name = "uart-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_UARTCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 16,
+        .len = 5,
+        .public_name = "uart-clock",
+    },
+    [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
+        .name = "timer-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_TIMCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 21,
+        .len = 5,
+        .public_name = "timer-clock",
+    },
+    [NPCM7XX_CLOCK_ADC_DIVIDER] = {
+        .name = "adc-divider",
+        .src_type = CLKSRC_DIV,
+        .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
+        .divide = shift_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 28,
+        .len = 3,
+        .public_name = "adc-clock",
+    },
+    [NPCM7XX_CLOCK_MMC_DIVIDER] = {
+        .name = "mmc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV1,
+        .offset = 11,
+        .len = 5,
+        .public_name = "mmc-clock",
+    },
+    [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
+        .name = "sdhc-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SDCKSEL,
+        .divide = divide_by_reg_divisor_times_2,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 0,
+        .len = 4,
+        .public_name = "sdhc-clock",
+    },
+    [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
+        .name = "gfxm-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_GFXMSEL,
+        .divide = divide_by_constant,
+        .divisor = 3,
+        .public_name = "gfxm-clock",
+    },
+    [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
+        .name = "utmi-divider",
+        .src_type = CLKSRC_SEL,
+        .src_index = NPCM7XX_CLOCK_SUCKSEL,
+        .divide = divide_by_reg_divisor,
+        .reg = NPCM7XX_CLK_CLKDIV2,
+        .offset = 8,
+        .len = 5,
+        .public_name = "utmi-clock",
+    },
+};
+
+static void npcm7xx_clk_pll_init(Object *obj)
+{
+    NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
+
+    pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
+            npcm7xx_clk_update_pll, pll);
+    pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
+}
+
+static void npcm7xx_clk_sel_init(Object *obj)
+{
+    int i;
+    NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
+
+    for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
+        sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
+                g_strdup_printf("clock-in[%d]", i),
+                npcm7xx_clk_update_sel, sel);
+    }
+    sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
+}
+static void npcm7xx_clk_divider_init(Object *obj)
+{
+    NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
+
+    div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
+            npcm7xx_clk_update_divider, div);
+    div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
+}
+
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
+        NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
+{
+    pll->name = init_info->name;
+    pll->clk = clk;
+    pll->reg = init_info->reg;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
+        NPCM7xxCLKState *clk, const SELInitInfo *init_info)
+{
+    int input_size = init_info->input_size;
+
+    sel->name = init_info->name;
+    sel->clk = clk;
+    sel->input_size = init_info->input_size;
+    g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
+    sel->offset = init_info->offset;
+    sel->len = init_info->len;
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
+        NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
+{
+    div->name = init_info->name;
+    div->clk = clk;
+
+    div->divide = init_info->divide;
+    if (div->divide == divide_by_constant) {
+        div->divisor = init_info->divisor;
+    } else {
+        div->reg = init_info->reg;
+        div->offset = init_info->offset;
+        div->len = init_info->len;
+    }
+    if (init_info->public_name != NULL) {
+        qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
+                init_info->public_name);
+    }
+}
+
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
+        int index)
+{
+    switch (type) {
+    case CLKSRC_REF:
+        return clk->clkref;
+    case CLKSRC_PLL:
+        return clk->plls[index].clock_out;
+    case CLKSRC_SEL:
+        return clk->sels[index].clock_out;
+    case CLKSRC_DIV:
+        return clk->dividers[index].clock_out;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
+{
+    int i, j;
+    Clock *src;
+
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
+                pll_init_info_list[i].src_index);
+        clock_set_source(clk->plls[i].clock_in, src);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
+            src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
+                    sel_init_info_list[i].src_index[j]);
+            clock_set_source(clk->sels[i].clock_in[j], src);
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
+                divider_init_info_list[i].src_index);
+        clock_set_source(clk->dividers[i].clock_in, src);
+    }
+}
+
 static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
 {
     uint32_t reg = offset / sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
          *
          * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
          */
-        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
+        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
         break;
 
     default:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
                 value |= (value & PLLCON_LOKS);
             }
         }
+        /* Only update PLL when it is locked. */
+        if (value & PLLCON_LOKI) {
+            npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
+        }
+        break;
+
+    case NPCM7XX_CLK_CLKSEL:
+        npcm7xx_clk_update_all_sels(s);
+        break;
+
+    case NPCM7XX_CLK_CLKDIV1:
+    case NPCM7XX_CLK_CLKDIV2:
+    case NPCM7XX_CLK_CLKDIV3:
+        npcm7xx_clk_update_all_dividers(s);
         break;
 
     case NPCM7XX_CLK_CNTR25M:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
     case RESET_TYPE_COLD:
         memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
         s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        npcm7xx_clk_update_all_clocks(s);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
                   __func__, type);
 }
 
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
+{
+    int i;
+
+    s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
+
+    /* First pass: init all converter modules */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
+            != NPCM7XX_CLOCK_NR_DIVIDERS);
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
+                &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
+        npcm7xx_init_clock_pll(&s->plls[i], s,
+                &pll_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
+                &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
+        npcm7xx_init_clock_sel(&s->sels[i], s,
+                &sel_init_info_list[i]);
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
+                &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
+        npcm7xx_init_clock_divider(&s->dividers[i], s,
+                &divider_init_info_list[i]);
+    }
+
+    /* Second pass: connect converter modules */
+    npcm7xx_connect_clocks(s);
+
+    clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
+}
+
 static void npcm7xx_clk_init(Object *obj)
 {
     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
     sysbus_init_mmio(&s->parent, &s->iomem);
-    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
-            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
 }
 
-static const VMStateDescription vmstate_npcm7xx_clk = {
-    .name = "npcm7xx-clk",
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
+{
+    if (version_id >= 1) {
+        NPCM7xxCLKState *clk = opaque;
+
+        npcm7xx_clk_update_all_clocks(clk);
+    }
+
+    return 0;
+}
+
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
+{
+    int i;
+    NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
+
+    qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
+            NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
+    npcm7xx_clk_init_clock_hierarchy(s);
+
+    /* Realize child devices */
+    for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
+        if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
+        if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
+            return;
+        }
+    }
+    for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
+        if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
+            return;
+        }
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
+    .name = "npcm7xx-clock-pll",
     .version_id = 0,
     .minimum_version_id = 0,
-    .fields = (VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
-        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
         VMSTATE_END_OF_LIST(),
     },
 };
 
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
+    .name = "npcm7xx-clock-sel",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
+                NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
+    .name = "npcm7xx-clock-divider",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields =  (VMStateField[]) {
+        VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_clk = {
+    .name = "npcm7xx-clk",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .post_load = npcm7xx_clk_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
+        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+        VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock PLL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_pll;
+}
+
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock SEL Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_sel;
+}
+
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx Clock Divider Module";
+    dc->vmsd = &vmstate_npcm7xx_clk_divider;
+}
+
 static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 {
     ResettableClass *rc = RESETTABLE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 
     dc->desc = "NPCM7xx Clock Control Registers";
     dc->vmsd = &vmstate_npcm7xx_clk;
+    dc->realize = npcm7xx_clk_realize;
     rc->phases.enter = npcm7xx_clk_enter_reset;
 }
 
+static const TypeInfo npcm7xx_clk_pll_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_PLL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockPLLState),
+    .instance_init      = npcm7xx_clk_pll_init,
+    .class_init         = npcm7xx_clk_pll_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_sel_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_SEL,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockSELState),
+    .instance_init      = npcm7xx_clk_sel_init,
+    .class_init         = npcm7xx_clk_sel_class_init,
+};
+
+static const TypeInfo npcm7xx_clk_divider_info = {
+    .name               = TYPE_NPCM7XX_CLOCK_DIVIDER,
+    .parent             = TYPE_DEVICE,
+    .instance_size      = sizeof(NPCM7xxClockDividerState),
+    .instance_init      = npcm7xx_clk_divider_init,
+    .class_init         = npcm7xx_clk_divider_class_init,
+};
+
 static const TypeInfo npcm7xx_clk_info = {
     .name               = TYPE_NPCM7XX_CLK,
     .parent             = TYPE_SYS_BUS_DEVICE,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
 
 static void npcm7xx_clk_register_type(void)
 {
+    type_register_static(&npcm7xx_clk_pll_info);
+    type_register_static(&npcm7xx_clk_sel_info);
+    type_register_static(&npcm7xx_clk_divider_info);
     type_register_static(&npcm7xx_clk_info);
 }
 type_init(npcm7xx_clk_register_type);
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

This patch makes NPCM7XX Timer to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/clock.h"
 #include "hw/sysbus.h"
 
-/*
- * The reference clock frequency for the timer modules, and the SECCNT and
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ            (25000000)
-
 /*
  * Number of registers in our device state structure. Don't change this without
  * incrementing the version_id in the vmstate.
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/npcm7xx_timer.h
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
 
     uint32_t    tisr;
 
+    Clock       *clock;
     NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
     NPCM7xxWatchdogTimer watchdog_timer;
 };
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "hw/loader.h"
 #include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
         int first_irq;
         int j;
 
+        /* Connect the timer clock. */
+        qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "timer-clock"));
+
         sysbus_realize(sbd, &error_abort);
         sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 
 #include "hw/irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
-#include "hw/misc/npcm7xx_clk.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "migration/vmstate.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
 /* Convert a timer cycle count to a time interval in nanoseconds. */
 static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 {
-    int64_t ns = count;
+    int64_t ticks = count;
 
-    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
-    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
+    ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
 
-    return ns;
+    return clock_ticks_to_ns(t->ctrl->clock, ticks);
 }
 
 /* Convert a time interval in nanoseconds to a timer cycle count. */
 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 {
-    int64_t count;
-
-    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
-    count /= npcm7xx_tcsr_prescaler(t->tcsr);
-
-    return count;
+    return ns / clock_ticks_to_ns(t->ctrl->clock,
+                                  npcm7xx_tcsr_prescaler(t->tcsr));
 }
 
 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
 static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
         int64_t cycles)
 {
-    uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
-    int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
+    int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
+    int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
 
     /*
      * The reset function always clears the current timer. The caller of the
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
      */
     npcm7xx_timer_clear(&t->base_timer);
 
-    ns *= prescaler;
     t->base_timer.remaining_ns = ns;
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
     qemu_irq_lower(s->watchdog_timer.irq);
 }
 
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+static void npcm7xx_timer_init(Object *obj)
 {
-    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
-    SysBusDevice *sbd = &s->parent;
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+    DeviceState *dev = DEVICE(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     int i;
     NPCM7xxWatchdogTimer *w;
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
             npcm7xx_watchdog_timer_expired, w);
     sysbus_init_irq(sbd, &w->irq);
 
-    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
                           TYPE_NPCM7XX_TIMER, 4 * KiB);
     sysbus_init_mmio(sbd, &s->iomem);
     qdev_init_gpio_out_named(dev, &w->reset_signal,
             NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
+    s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
 }
 
 static const VMStateDescription vmstate_npcm7xx_base_timer = {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
 
 static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
     .name = "npcm7xx-timer-ctrl",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
+        VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
         VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
                              NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
                              NPCM7xxTimer),
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
     QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
 
     dc->desc = "NPCM7xx Timer Controller";
-    dc->realize = npcm7xx_timer_realize;
     dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
     rc->phases.enter = npcm7xx_timer_enter_reset;
     rc->phases.hold = npcm7xx_timer_hold_reset;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
     .parent             = TYPE_SYS_BUS_DEVICE,
     .instance_size      = sizeof(NPCM7xxTimerCtrlState),
     .class_init         = npcm7xx_timer_class_init,
+    .instance_init      = npcm7xx_timer_init,
 };
 
 static void npcm7xx_timer_register_type(void)
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The ADC is part of NPCM7XX Module. Its behavior is controled by the
ADC_CON register. It converts one of the eight analog inputs into a
digital input and stores it in the ADC_DATA register when enabled.

Users can alter input value by using qom-set QMP command.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
[PMM: Added missing hw/adc/trace.h file]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst    |   2 +-
 meson.build                    |   1 +
 hw/adc/trace.h                 |   1 +
 include/hw/adc/npcm7xx_adc.h   |  69 ++++++
 include/hw/arm/npcm7xx.h       |   2 +
 hw/adc/npcm7xx_adc.c           | 301 ++++++++++++++++++++++++++
 hw/arm/npcm7xx.c               |  24 ++-
 tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
 hw/adc/meson.build             |   1 +
 hw/adc/trace-events            |   5 +
 tests/qtest/meson.build        |   3 +-
 11 files changed, 783 insertions(+), 3 deletions(-)
 create mode 100644 hw/adc/trace.h
 create mode 100644 include/hw/adc/npcm7xx_adc.h
 create mode 100644 hw/adc/npcm7xx_adc.c
 create mode 100644 tests/qtest/npcm7xx_adc-test.c
 create mode 100644 hw/adc/trace-events

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * Random Number Generator (RNG)
  * USB host (USBH)
  * GPIO controller
+ * Analog to Digital Converter (ADC)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * USB device (USBD)
  * SMBus controller (SMBF)
  * Peripheral SPI controller (PSPI)
- * Analog to Digital Converter (ADC)
  * SD/MMC host
  * PECI interface
  * Pulse Width Modulation (PWM)
diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'chardev',
     'hw/9pfs',
     'hw/acpi',
+    'hw/adc',
     'hw/alpha',
     'hw/arm',
     'hw/audio',
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_adc.h"
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_ADC_H
+#define NPCM7XX_ADC_H
+
+#include "hw/clock.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+#define NPCM7XX_ADC_NUM_INPUTS      8
+/**
+ * This value should not be changed unless write_adc_calibration function in
+ * hw/arm/npcm7xx.c is also changed.
+ */
+#define NPCM7XX_ADC_NUM_CALIB       2
+
+/**
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @con: The Control Register.
+ * @data: The Data Buffer.
+ * @clock: The ADC Clock.
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
+ * @vref: The external reference voltage.
+ * @iref: The internal reference voltage, initialized at launch time.
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
+ */
+typedef struct {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    QEMUTimer    conv_timer;
+
+    qemu_irq     irq;
+    uint32_t     con;
+    uint32_t     data;
+    Clock       *clock;
+
+    /* Voltages are in unit of uV. 1V = 1000000uV. */
+    uint32_t     adci[NPCM7XX_ADC_NUM_INPUTS];
+    uint32_t     vref;
+    uint32_t     iref;
+
+    uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
+} NPCM7xxADCState;
+
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
+#define NPCM7XX_ADC(obj) \
+    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
+
+#endif /* NPCM7XX_ADC_H */
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_H
 
 #include "hw/boards.h"
+#include "hw/adc/npcm7xx_adc.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/gpio/npcm7xx_gpio.h"
 #include "hw/mem/npcm7xx_mc.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxGCRState     gcr;
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
+    NPCM7xxADCState     adc;
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/npcm7xx_adc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx ADC Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/adc/npcm7xx_adc.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_ADC_CON, 0x0)
+REG32(NPCM7XX_ADC_DATA, 0x4)
+
+/* Register field definitions. */
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
+#define NPCM7XX_ADC_CON_INT_EN  BIT(21)
+#define NPCM7XX_ADC_CON_REFSEL  BIT(19)
+#define NPCM7XX_ADC_CON_INT     BIT(18)
+#define NPCM7XX_ADC_CON_EN      BIT(17)
+#define NPCM7XX_ADC_CON_RST     BIT(16)
+#define NPCM7XX_ADC_CON_CONV    BIT(14)
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
+
+#define NPCM7XX_ADC_MAX_RESULT      1023
+#define NPCM7XX_ADC_DEFAULT_IREF    2000000
+#define NPCM7XX_ADC_CONV_CYCLES     20
+#define NPCM7XX_ADC_RESET_CYCLES    10
+#define NPCM7XX_ADC_R0_INPUT        500000
+#define NPCM7XX_ADC_R1_INPUT        1500000
+
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
+{
+    timer_del(&s->conv_timer);
+    s->con = 0x000c0001;
+    s->data = 0x00000000;
+}
+
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
+{
+    uint32_t result;
+
+    result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
+    if (result > NPCM7XX_ADC_MAX_RESULT) {
+        result = NPCM7XX_ADC_MAX_RESULT;
+    }
+
+    return result;
+}
+
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
+{
+    return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
+}
+
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
+        uint32_t cycles, uint32_t prescaler)
+{
+    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    int64_t ticks = cycles;
+    int64_t ns;
+
+    ticks *= prescaler;
+    ns = clock_ticks_to_ns(clk, ticks);
+    ns += now;
+    timer_mod(timer, ns);
+}
+
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
+{
+    uint32_t prescaler = npcm7xx_adc_prescaler(s);
+
+    npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
+            prescaler);
+}
+
+static void npcm7xx_adc_convert_done(void *opaque)
+{
+    NPCM7xxADCState *s = opaque;
+    uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
+    uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
+        ? s->iref : s->vref;
+
+    if (input >= NPCM7XX_ADC_NUM_INPUTS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
+                      __func__, input);
+        return;
+    }
+    s->data = npcm7xx_adc_convert(s->adci[input], ref);
+    if (s->con & NPCM7XX_ADC_CON_INT_EN) {
+        s->con |= NPCM7XX_ADC_CON_INT;
+        qemu_irq_raise(s->irq);
+    }
+    s->con &= ~NPCM7XX_ADC_CON_CONV;
+}
+
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
+{
+    adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
+            adc->iref);
+    adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
+            adc->iref);
+}
+
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
+{
+    uint32_t old_con = s->con;
+
+    /* Write ADC_INT to 1 to clear it */
+    if (new_con & NPCM7XX_ADC_CON_INT) {
+        new_con &= ~NPCM7XX_ADC_CON_INT;
+        qemu_irq_lower(s->irq);
+    } else if (old_con & NPCM7XX_ADC_CON_INT) {
+        new_con |= NPCM7XX_ADC_CON_INT;
+    }
+
+    s->con = new_con;
+
+    if (s->con & NPCM7XX_ADC_CON_RST) {
+        npcm7xx_adc_reset(s);
+        return;
+    }
+
+    if ((s->con & NPCM7XX_ADC_CON_EN)) {
+        if (s->con & NPCM7XX_ADC_CON_CONV) {
+            if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
+                npcm7xx_adc_start_convert(s);
+            }
+        } else {
+            timer_del(&s->conv_timer);
+        }
+    }
+}
+
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
+{
+    uint64_t value = 0;
+    NPCM7xxADCState *s = opaque;
+
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        value = s->con;
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        value = s->data;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
+        unsigned size)
+{
+    NPCM7xxADCState *s = opaque;
+
+    trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
+    switch (offset) {
+    case A_NPCM7XX_ADC_CON:
+        npcm7xx_adc_write_con(s, v);
+        break;
+
+    case A_NPCM7XX_ADC_DATA:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+}
+
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
+    .read       = npcm7xx_adc_read,
+    .write      = npcm7xx_adc_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    npcm7xx_adc_reset(s);
+}
+
+static void npcm7xx_adc_hold_reset(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+
+    qemu_irq_lower(s->irq);
+}
+
+static void npcm7xx_adc_init(Object *obj)
+{
+    NPCM7xxADCState *s = NPCM7XX_ADC(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    sysbus_init_irq(sbd, &s->irq);
+
+    timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
+            npcm7xx_adc_convert_done, s);
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
+                          TYPE_NPCM7XX_ADC, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
+        object_property_add_uint32_ptr(obj, "adci[*]",
+                &s->adci[i], OBJ_PROP_FLAG_WRITE);
+    }
+    object_property_add_uint32_ptr(obj, "vref",
+            &s->vref, OBJ_PROP_FLAG_WRITE);
+    npcm7xx_adc_calibrate(s);
+}
+
+static const VMStateDescription vmstate_npcm7xx_adc = {
+    .name = "npcm7xx-adc",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
+        VMSTATE_UINT32(con, NPCM7xxADCState),
+        VMSTATE_UINT32(data, NPCM7xxADCState),
+        VMSTATE_CLOCK(clock, NPCM7xxADCState),
+        VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
+        VMSTATE_UINT32(vref, NPCM7xxADCState),
+        VMSTATE_UINT32(iref, NPCM7xxADCState),
+        VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
+                NPCM7XX_ADC_NUM_CALIB),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static Property npcm7xx_timer_properties[] = {
+    DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx ADC Module";
+    dc->vmsd = &vmstate_npcm7xx_adc;
+    rc->phases.enter = npcm7xx_adc_enter_reset;
+    rc->phases.hold = npcm7xx_adc_hold_reset;
+
+    device_class_set_props(dc, npcm7xx_timer_properties);
+}
+
+static const TypeInfo npcm7xx_adc_info = {
+    .name               = TYPE_NPCM7XX_ADC,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxADCState),
+    .class_init         = npcm7xx_adc_class_init,
+    .instance_init      = npcm7xx_adc_init,
+};
+
+static void npcm7xx_adc_register_types(void)
+{
+    type_register_static(&npcm7xx_adc_info);
+}
+
+type_init(npcm7xx_adc_register_types);
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_EHCI_BA         (0xf0806000)
 #define NPCM7XX_OHCI_BA         (0xf0807000)
 
+/* ADC Module */
+#define NPCM7XX_ADC_BA          (0xf000c000)
+
 /* Internal AHB SRAM */
 #define NPCM7XX_RAM3_BA         (0xc0008000)
 #define NPCM7XX_RAM3_SZ         (4 * KiB)
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_ROM_BA          (0xffff0000)
 #define NPCM7XX_ROM_SZ          (64 * KiB)
 
+
 /* Clock configuration values to be fixed up when bypassing bootloader */
 
 /* Run PLL1 at 1600 MHz */
@@ -XXX,XX +XXX,XX @@
  * interrupts.
  */
 enum NPCM7xxInterrupt {
+    NPCM7XX_ADC_IRQ             = 0,
     NPCM7XX_UART0_IRQ           = 2,
     NPCM7XX_UART1_IRQ,
     NPCM7XX_UART2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
                             sizeof(value));
 }
 
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
+{
+    /* Both ADC and the fuse array must have realized. */
+    QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
+    npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
+            NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
+}
+
 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 {
     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                             TYPE_NPCM7XX_FUSE_ARRAY);
     object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
     object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
+    object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
 
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 
+    /* ADC Modules. Cannot fail. */
+    qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
+                          DEVICE(&s->clk), "adc-clock"));
+    sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
+            npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
+    npcm7xx_write_adc_calibration(s);
+
     /* Timer Modules (TIM). Cannot fail. */
     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
     create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
     create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx ADCModules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/timer.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+
+#define REF_HZ          (25000000)
+
+#define CON_OFFSET      0x0
+#define DATA_OFFSET     0x4
+
+#define NUM_INPUTS      8
+#define DEFAULT_IREF    2000000
+#define CONV_CYCLES     20
+#define RESET_CYCLES    10
+#define R0_INPUT        500000
+#define R1_INPUT        1500000
+#define MAX_RESULT      1023
+
+#define DEFAULT_CLKDIV  5
+
+#define FUSE_ARRAY_BA   0xf018a000
+#define FCTL_OFFSET     0x14
+#define FST_OFFSET      0x0
+#define FADDR_OFFSET    0x4
+#define FDATA_OFFSET    0x8
+#define ADC_CALIB_ADDR  24
+#define FUSE_READ       0x2
+
+/* Register field definitions. */
+#define CON_MUX(rv) ((rv) << 24)
+#define CON_INT_EN  BIT(21)
+#define CON_REFSEL  BIT(19)
+#define CON_INT     BIT(18)
+#define CON_EN      BIT(17)
+#define CON_RST     BIT(16)
+#define CON_CONV    BIT(14)
+#define CON_DIV(rv) extract32(rv, 1, 8)
+
+#define FST_RDST    BIT(1)
+#define FDATA_MASK  0xff
+
+#define MAX_ERROR   10000
+#define MIN_CALIB_INPUT 100000
+#define MAX_CALIB_INPUT 1800000
+
+static const uint32_t input_list[] = {
+    100000,
+    500000,
+    1000000,
+    1500000,
+    1800000,
+    2000000,
+};
+
+static const uint32_t vref_list[] = {
+    2000000,
+    2200000,
+    2500000,
+};
+
+static const uint32_t iref_list[] = {
+    1800000,
+    1900000,
+    2000000,
+    2100000,
+    2200000,
+};
+
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
+
+typedef struct ADC {
+    int irq;
+    uint64_t base_addr;
+} ADC;
+
+ADC adc = {
+    .irq        = 0,
+    .base_addr  = 0xf000c000
+};
+
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + CON_OFFSET);
+}
+
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
+}
+
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
+{
+    return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
+}
+
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
+{
+    return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
+        / (int32_t)(rv[1] - rv[0]);
+}
+
+static void adc_qom_set(QTestState *qts, const ADC *adc,
+        const char *name, uint32_t value)
+{
+    QDict *response;
+    const char *path = "/machine/soc/adc";
+
+    g_test_message("Setting properties %s of %s with value %u",
+            name, path, value);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
+            " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
+            path, name, value);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+}
+
+static void adc_write_input(QTestState *qts, const ADC *adc,
+        uint32_t index, uint32_t value)
+{
+    char name[100];
+
+    sprintf(name, "adci[%u]", index);
+    adc_qom_set(qts, adc, name, value);
+}
+
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
+{
+    adc_qom_set(qts, adc, "vref", value);
+}
+
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
+{
+    uint32_t output;
+
+    g_assert_cmpuint(input, <=, ref);
+    output = (input * (MAX_RESULT + 1)) / ref;
+    if (output > MAX_RESULT) {
+        output = MAX_RESULT;
+    }
+
+    return output;
+}
+
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
+{
+    uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
+
+    return 2 * (div + 1);
+}
+
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
+        uint32_t clkdiv)
+{
+    return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
+}
+
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
+        uint32_t clkdiv)
+{
+    uint32_t prescaler = adc_prescaler(qts, adc);
+
+    /*
+     * ADC should takes roughly 20 cycles to convert one sample. So we assert it
+     * should take 10~30 cycles here.
+     */
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
+                clkdiv));
+    /* ADC is still converting. */
+    g_assert_true(adc_read_con(qts, adc) & CON_CONV);
+    qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
+    /* ADC has finished conversion. */
+    g_assert_false(adc_read_con(qts, adc) & CON_CONV);
+}
+
+/* Check ADC can be reset to default value. */
+static void test_init(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    adc_write_con(qts, adc, CON_REFSEL | CON_INT);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an internal reference. */
+static void test_convert_internal(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            input = input_list[i];
+            expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
+                    CON_REFSEL | CON_EN);
+            g_assert_false(qtest_get_irq(qts, adc->irq));
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC can convert from an external reference. */
+static void test_convert_external(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, vref, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+
+    for (index = 0; index < NUM_INPUTS; ++index) {
+        for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
+                input = input_list[i];
+                vref = vref_list[j];
+                expected_output = adc_calculate_output(input, vref);
+
+                adc_write_input(qts, adc, index, input);
+                adc_write_vref(qts, adc, vref);
+                adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
+                        CON_CONV);
+                adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+                g_assert_cmphex(adc_read_con(qts, adc), ==,
+                        CON_MUX(index) | CON_EN);
+                g_assert_false(qtest_get_irq(qts, adc->irq));
+                output = adc_read_data(qts, adc);
+                g_assert_cmpuint(output, ==, expected_output);
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
+static void test_interrupt(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    uint32_t index, input, output, expected_output;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    index = 1;
+    input = input_list[1];
+    expected_output = adc_calculate_output(input, DEFAULT_IREF);
+
+    qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
+    adc_write_input(qts, adc, index, input);
+    g_assert_false(qtest_get_irq(qts, adc->irq));
+    adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
+            | CON_EN | CON_CONV);
+    adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+    g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
+            | CON_REFSEL | CON_INT | CON_EN);
+    g_assert_true(qtest_get_irq(qts, adc->irq));
+    output = adc_read_data(qts, adc);
+    g_assert_cmpuint(output, ==, expected_output);
+
+    qtest_quit(qts);
+}
+
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
+static void test_reset(gconstpointer adc_p)
+{
+    const ADC *adc = adc_p;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+
+    for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
+        uint32_t div = div_list[i];
+
+        adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
+        qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
+                    adc_prescaler(qts, adc), DEFAULT_CLKDIV));
+        g_assert_false(adc_read_con(qts, adc) & CON_EN);
+    }
+    qtest_quit(qts);
+}
+
+/* Check ADC Calibration works as desired. */
+static void test_calibrate(gconstpointer adc_p)
+{
+    int i, j;
+    const ADC *adc = adc_p;
+
+    for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
+        uint32_t iref = iref_list[j];
+        uint32_t expected_rv[] = {
+            adc_calculate_output(R0_INPUT, iref),
+            adc_calculate_output(R1_INPUT, iref),
+        };
+        char buf[100];
+        QTestState *qts;
+
+        sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
+        qts = qtest_init(buf);
+
+        /* Check the converted value is correct using the calibration value. */
+        for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
+            uint32_t input;
+            uint32_t output;
+            uint32_t expected_output;
+            uint32_t calibrated_voltage;
+            uint32_t index = 0;
+
+            input = input_list[i];
+            /* Calibration only works for input range 0.1V ~ 1.8V. */
+            if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
+                continue;
+            }
+            expected_output = adc_calculate_output(input, iref);
+
+            adc_write_input(qts, adc, index, input);
+            adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
+                    CON_EN | CON_CONV);
+            adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
+            g_assert_cmphex(adc_read_con(qts, adc), ==,
+                    CON_REFSEL | CON_MUX(index) | CON_EN);
+            output = adc_read_data(qts, adc);
+            g_assert_cmpuint(output, ==, expected_output);
+
+            calibrated_voltage = adc_calibrate(output, expected_rv);
+            g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
+            g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
+        }
+
+        qtest_quit(qts);
+    }
+}
+
+static void adc_add_test(const char *name, const ADC* wd,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s",  name);
+    qtest_add_data_func(full_name, wd, fn);
+}
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    add_test(init, &adc);
+    add_test(convert_internal, &adc);
+    add_test(convert_external, &adc);
+    add_test(interrupt, &adc);
+    add_test(reset, &adc);
+    add_test(calibrate, &adc);
+
+    return g_test_run();
+}
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/adc/meson.build
+++ b/hw/adc/meson.build
@@ -1 +1,2 @@
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/adc/trace-events
@@ -XXX,XX +XXX,XX @@
+# See docs/devel/tracing.txt for syntax documentation.
+
+# npcm7xx_adc.c
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
   ['prom-env-test', 'boot-serial-test']
 
 qtests_npcm7xx = \
-  ['npcm7xx_gpio-test',
+  ['npcm7xx_adc-test',
+   'npcm7xx_gpio-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
two outputs: frequency and duty_cycle. Both are computed using inputs
from software side.

This module does not model detail pulse signals since it is expensive.
It also does not model interrupts and watchdogs that are dependant on
the detail models. The interfaces for these are left in the module so
that anyone in need for these functionalities can implement on their
own.

The user can read the duty cycle and frequency using qom-get command.

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * USB host (USBH)
  * GPIO controller
  * Analog to Digital Converter (ADC)
+ * Pulse Width Modulation (PWM)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
  * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
- * Pulse Width Modulation (PWM)
  * Tachometer
  * PCI and PCIe root complex and bridges
  * VDM and MCTP support
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/mem/npcm7xx_mc.h"
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/misc/npcm7xx_gcr.h"
+#include "hw/misc/npcm7xx_pwm.h"
 #include "hw/misc/npcm7xx_rng.h"
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
     NPCM7xxADCState     adc;
+    NPCM7xxPWMState     pwm[2];
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_PWM_H
+#define NPCM7XX_PWM_H
+
+#include "hw/clock.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+
+/* Each PWM module holds 4 PWM channels. */
+#define NPCM7XX_PWM_PER_MODULE 4
+
+/*
+ * Number of registers in one pwm module. Don't change this without increasing
+ * the version_id in vmstate.
+ */
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
+
+/*
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
+ * value of 100,000 the duty cycle for that PWM is 10%.
+ */
+#define NPCM7XX_PWM_MAX_DUTY 1000000
+
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
+
+/**
+ * struct NPCM7xxPWM - The state of a single PWM channel.
+ * @module: The PWM module that contains this channel.
+ * @irq: GIC interrupt line to fire on expiration if enabled.
+ * @running: Whether this PWM channel is generating output.
+ * @inverted: Whether this PWM channel is inverted.
+ * @index: The index of this PWM channel.
+ * @cnr: The counter register.
+ * @cmr: The comparator register.
+ * @pdr: The data register.
+ * @pwdr: The watchdog register.
+ * @freq: The frequency of this PWM channel.
+ * @duty: The duty cycle of this PWM channel. One unit represents
+ *   1/NPCM7XX_MAX_DUTY cycles.
+ */
+typedef struct NPCM7xxPWM {
+    NPCM7xxPWMState         *module;
+
+    qemu_irq                irq;
+
+    bool                    running;
+    bool                    inverted;
+
+    uint8_t                 index;
+    uint32_t                cnr;
+    uint32_t                cmr;
+    uint32_t                pdr;
+    uint32_t                pwdr;
+
+    uint32_t                freq;
+    uint32_t                duty;
+} NPCM7xxPWM;
+
+/**
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @clock: The PWM clock.
+ * @pwm: The PWM channels owned by this module.
+ * @ppr: The prescaler register.
+ * @csr: The clock selector register.
+ * @pcr: The control register.
+ * @pier: The interrupt enable register.
+ * @piir: The interrupt indication register.
+ */
+struct NPCM7xxPWMState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    Clock       *clock;
+    NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
+
+    uint32_t    ppr;
+    uint32_t    csr;
+    uint32_t    pcr;
+    uint32_t    pier;
+    uint32_t    piir;
+};
+
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
+#define NPCM7XX_PWM(obj) \
+    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
+
+#endif /* NPCM7XX_PWM_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
     NPCM7XX_EHCI_IRQ            = 61,
     NPCM7XX_OHCI_IRQ            = 62,
+    NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
+    NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
     NPCM7XX_GPIO0_IRQ           = 116,
     NPCM7XX_GPIO1_IRQ,
     NPCM7XX_GPIO2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
     0xb8000000, /* CS3 */
 };
 
+/* Register base address for each PWM Module */
+static const hwaddr npcm7xx_pwm_addr[] = {
+    0xf0103000,
+    0xf0104000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
                                 TYPE_NPCM7XX_FIU);
     }
+
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
+    }
 }
 
 static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
                        npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 
+    /* PWM Modules. Cannot fail. */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
+    for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
+
+        qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
+                    DEVICE(&s->clk), "apb3-clock"));
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
+        sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
+    }
+
     /*
      * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
      * specified, but this is a programming error.
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
     create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/npcm7xx_pwm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx PWM Module
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/irq.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/npcm7xx_pwm.h"
+#include "hw/registerfields.h"
+#include "migration/vmstate.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+REG32(NPCM7XX_PWM_PPR, 0x00);
+REG32(NPCM7XX_PWM_CSR, 0x04);
+REG32(NPCM7XX_PWM_PCR, 0x08);
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
+REG32(NPCM7XX_PWM_CMR0, 0x10);
+REG32(NPCM7XX_PWM_PDR0, 0x14);
+REG32(NPCM7XX_PWM_CNR1, 0x18);
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
+REG32(NPCM7XX_PWM_PDR1, 0x20);
+REG32(NPCM7XX_PWM_CNR2, 0x24);
+REG32(NPCM7XX_PWM_CMR2, 0x28);
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
+REG32(NPCM7XX_PWM_CNR3, 0x30);
+REG32(NPCM7XX_PWM_CMR3, 0x34);
+REG32(NPCM7XX_PWM_PDR3, 0x38);
+REG32(NPCM7XX_PWM_PIER, 0x3c);
+REG32(NPCM7XX_PWM_PIIR, 0x40);
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
+
+/* Register field definitions. */
+#define NPCM7XX_PPR(rv, index)      extract32((rv), npcm7xx_ppr_base[index], 8)
+#define NPCM7XX_CSR(rv, index)      extract32((rv), npcm7xx_csr_base[index], 3)
+#define NPCM7XX_CH(rv, index)       extract32((rv), npcm7xx_ch_base[index], 4)
+#define NPCM7XX_CH_EN               BIT(0)
+#define NPCM7XX_CH_INV              BIT(2)
+#define NPCM7XX_CH_MOD              BIT(3)
+
+/* Offset of each PWM channel's prescaler in the PPR register. */
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
+/* Offset of each PWM channel's clock selector in the CSR register. */
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
+/* Offset of each PWM channel's control variable in the PCR register. */
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
+
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
+{
+    uint32_t ppr;
+    uint32_t csr;
+    uint32_t freq;
+
+    if (!p->running) {
+        return 0;
+    }
+
+    csr = NPCM7XX_CSR(p->module->csr, p->index);
+    ppr = NPCM7XX_PPR(p->module->ppr, p->index);
+    freq = clock_get_hz(p->module->clock);
+    freq /= ppr + 1;
+    /* csr can only be 0~4 */
+    if (csr > 4) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid csr value %u\n",
+                      __func__, csr);
+        csr = 4;
+    }
+    /* freq won't be changed if csr == 4. */
+    if (csr < 4) {
+        freq >>= csr + 1;
+    }
+
+    return freq / (p->cnr + 1);
+}
+
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
+{
+    uint64_t duty;
+
+    if (p->running) {
+        if (p->cnr == 0) {
+            duty = 0;
+        } else if (p->cmr >= p->cnr) {
+            duty = NPCM7XX_PWM_MAX_DUTY;
+        } else {
+            duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
+        }
+    } else {
+        duty = 0;
+    }
+
+    if (p->inverted) {
+        duty = NPCM7XX_PWM_MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
+{
+    uint32_t freq = npcm7xx_pwm_calculate_freq(p);
+
+    if (freq != p->freq) {
+        trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
+                                      p->index, p->freq, freq);
+        p->freq = freq;
+    }
+}
+
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
+{
+    uint32_t duty = npcm7xx_pwm_calculate_duty(p);
+
+    if (duty != p->duty) {
+        trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
+                                      p->index, p->duty, duty);
+        p->duty = duty;
+    }
+}
+
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
+{
+    npcm7xx_pwm_update_freq(p);
+    npcm7xx_pwm_update_duty(p);
+}
+
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
+{
+    int i;
+    uint32_t old_ppr = s->ppr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->ppr = new_ppr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
+{
+    int i;
+    uint32_t old_csr = s->csr;
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
+    s->csr = new_csr;
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
+            npcm7xx_pwm_update_freq(&s->pwm[i]);
+        }
+    }
+}
+
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
+{
+    int i;
+    bool inverted;
+    uint32_t pcr;
+    NPCM7xxPWM *p;
+
+    s->pcr = new_pcr;
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        p = &s->pwm[i];
+        pcr = NPCM7XX_CH(new_pcr, i);
+        inverted = pcr & NPCM7XX_CH_INV;
+
+        /*
+         * We only run a PWM channel with toggle mode. Single-shot mode does not
+         * generate frequency and duty-cycle values.
+         */
+        if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
+            if (p->running) {
+                /* Re-run this PWM channel if inverted changed. */
+                if (p->inverted ^ inverted) {
+                    p->inverted = inverted;
+                    npcm7xx_pwm_update_duty(p);
+                }
+            } else {
+                /* Run this PWM channel. */
+                p->running = true;
+                p->inverted = inverted;
+                npcm7xx_pwm_update_output(p);
+            }
+        } else {
+            /* Clear this PWM channel. */
+            p->running = false;
+            p->inverted = inverted;
+            npcm7xx_pwm_update_output(p);
+        }
+    }
+
+}
+
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+        return 0;
+    case A_NPCM7XX_PWM_CNR1:
+        return 1;
+    case A_NPCM7XX_PWM_CNR2:
+        return 2;
+    case A_NPCM7XX_PWM_CNR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_CMR0:
+        return 0;
+    case A_NPCM7XX_PWM_CMR1:
+        return 1;
+    case A_NPCM7XX_PWM_CMR2:
+        return 2;
+    case A_NPCM7XX_PWM_CMR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
+{
+    switch (offset) {
+    case A_NPCM7XX_PWM_PWDR0:
+        return 0;
+    case A_NPCM7XX_PWM_PWDR1:
+        return 1;
+    case A_NPCM7XX_PWM_PWDR2:
+        return 2;
+    case A_NPCM7XX_PWM_PWDR3:
+        return 3;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    uint64_t value = 0;
+
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        value = s->ppr;
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        value = s->csr;
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        value = s->pcr;
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        value = s->pier;
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        value = s->piir;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
+    return value;
+}
+
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
+                                uint64_t v, unsigned size)
+{
+    NPCM7xxPWMState *s = opaque;
+    NPCM7xxPWM *p;
+    uint32_t value = v;
+
+    trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
+    switch (offset) {
+    case A_NPCM7XX_PWM_CNR0:
+    case A_NPCM7XX_PWM_CNR1:
+    case A_NPCM7XX_PWM_CNR2:
+    case A_NPCM7XX_PWM_CNR3:
+        p = &s->pwm[npcm7xx_cnr_index(offset)];
+        p->cnr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_CMR0:
+    case A_NPCM7XX_PWM_CMR1:
+    case A_NPCM7XX_PWM_CMR2:
+    case A_NPCM7XX_PWM_CMR3:
+        p = &s->pwm[npcm7xx_cmr_index(offset)];
+        p->cmr = value;
+        npcm7xx_pwm_update_output(p);
+        break;
+
+    case A_NPCM7XX_PWM_PDR0:
+    case A_NPCM7XX_PWM_PDR1:
+    case A_NPCM7XX_PWM_PDR2:
+    case A_NPCM7XX_PWM_PDR3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PWDR0:
+    case A_NPCM7XX_PWM_PWDR1:
+    case A_NPCM7XX_PWM_PWDR2:
+    case A_NPCM7XX_PWM_PWDR3:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PPR:
+        npcm7xx_pwm_write_ppr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_CSR:
+        npcm7xx_pwm_write_csr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PCR:
+        npcm7xx_pwm_write_pcr(s, value);
+        break;
+
+    case A_NPCM7XX_PWM_PIER:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    case A_NPCM7XX_PWM_PIIR:
+        qemu_log_mask(LOG_UNIMP,
+                     "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
+                     __func__, offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+}
+
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
+    .read       = npcm7xx_pwm_read,
+    .write      = npcm7xx_pwm_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+
+        p->cnr = 0x00000000;
+        p->cmr = 0x00000000;
+        p->pdr = 0x00000000;
+        p->pwdr = 0x00000000;
+    }
+
+    s->ppr = 0x00000000;
+    s->csr = 0x00000000;
+    s->pcr = 0x00000000;
+    s->pier = 0x00000000;
+    s->piir = 0x00000000;
+}
+
+static void npcm7xx_pwm_hold_reset(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        qemu_irq_lower(s->pwm[i].irq);
+    }
+}
+
+static void npcm7xx_pwm_init(Object *obj)
+{
+    NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
+        NPCM7xxPWM *p = &s->pwm[i];
+        p->module = s;
+        p->index = i;
+        sysbus_init_irq(sbd, &p->irq);
+    }
+
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
+                          TYPE_NPCM7XX_PWM, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+    s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
+
+    for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
+        object_property_add_uint32_ptr(obj, "freq[*]",
+                &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
+        object_property_add_uint32_ptr(obj, "duty[*]",
+                &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_pwm = {
+    .name = "npcm7xx-pwm",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL(running, NPCM7xxPWM),
+        VMSTATE_BOOL(inverted, NPCM7xxPWM),
+        VMSTATE_UINT8(index, NPCM7xxPWM),
+        VMSTATE_UINT32(cnr, NPCM7xxPWM),
+        VMSTATE_UINT32(cmr, NPCM7xxPWM),
+        VMSTATE_UINT32(pdr, NPCM7xxPWM),
+        VMSTATE_UINT32(pwdr, NPCM7xxPWM),
+        VMSTATE_UINT32(freq, NPCM7xxPWM),
+        VMSTATE_UINT32(duty, NPCM7xxPWM),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
+    .name = "npcm7xx-pwm-module",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_CLOCK(clock, NPCM7xxPWMState),
+        VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
+                             NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
+                             NPCM7xxPWM),
+        VMSTATE_UINT32(ppr, NPCM7xxPWMState),
+        VMSTATE_UINT32(csr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pcr, NPCM7xxPWMState),
+        VMSTATE_UINT32(pier, NPCM7xxPWMState),
+        VMSTATE_UINT32(piir, NPCM7xxPWMState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM7xx PWM Controller";
+    dc->vmsd = &vmstate_npcm7xx_pwm_module;
+    rc->phases.enter = npcm7xx_pwm_enter_reset;
+    rc->phases.hold = npcm7xx_pwm_hold_reset;
+}
+
+static const TypeInfo npcm7xx_pwm_info = {
+    .name               = TYPE_NPCM7XX_PWM,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxPWMState),
+    .class_init         = npcm7xx_pwm_class_init,
+    .instance_init      = npcm7xx_pwm_init,
+};
+
+static void npcm7xx_pwm_register_type(void)
+{
+    type_register_static(&npcm7xx_pwm_info);
+}
+type_init(npcm7xx_pwm_register_type);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
 softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
   'npcm7xx_clk.c',
   'npcm7xx_gcr.c',
+  'npcm7xx_pwm.c',
   'npcm7xx_rng.c',
 ))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
 npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
 
+# npcm7xx_pwm.c
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
+
 # stm32f4xx_syscfg.c
 stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

We add a qtest for the PWM in the previous patch. It proves it works as
expected.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
 tests/qtest/meson.build        |   1 +
 2 files changed, 491 insertions(+)
 create mode 100644 tests/qtest/npcm7xx_pwm-test.c

diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/npcm7xx_pwm-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for Nuvoton NPCM7xx PWM Modules.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "libqos/libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qnum.h"
+
+#define REF_HZ          25000000
+
+/* Register field definitions. */
+#define CH_EN           BIT(0)
+#define CH_INV          BIT(2)
+#define CH_MOD          BIT(3)
+
+/* Registers shared between all PWMs in a module */
+#define PPR             0x00
+#define CSR             0x04
+#define PCR             0x08
+#define PIER            0x3c
+#define PIIR            0x40
+
+/* CLK module related */
+#define CLK_BA          0xf0801000
+#define CLKSEL          0x04
+#define CLKDIV1         0x08
+#define CLKDIV2         0x2c
+#define PLLCON0         0x0c
+#define PLLCON1         0x10
+#define PLL_INDV(rv)    extract32((rv), 0, 6)
+#define PLL_FBDV(rv)    extract32((rv), 16, 12)
+#define PLL_OTDV1(rv)   extract32((rv), 8, 3)
+#define PLL_OTDV2(rv)   extract32((rv), 13, 3)
+#define APB3CKDIV(rv)   extract32((rv), 28, 2)
+#define CLK2CKDIV(rv)   extract32((rv), 0, 1)
+#define CLK4CKDIV(rv)   extract32((rv), 26, 2)
+#define CPUCKSEL(rv)    extract32((rv), 0, 2)
+
+#define MAX_DUTY        1000000
+
+typedef struct PWMModule {
+    int irq;
+    uint64_t base_addr;
+} PWMModule;
+
+typedef struct PWM {
+    uint32_t cnr_offset;
+    uint32_t cmr_offset;
+    uint32_t pdr_offset;
+    uint32_t pwdr_offset;
+} PWM;
+
+typedef struct TestData {
+    const PWMModule *module;
+    const PWM *pwm;
+} TestData;
+
+static const PWMModule pwm_module_list[] = {
+    {
+        .irq        = 93,
+        .base_addr  = 0xf0103000
+    },
+    {
+        .irq        = 94,
+        .base_addr  = 0xf0104000
+    }
+};
+
+static const PWM pwm_list[] = {
+    {
+        .cnr_offset     = 0x0c,
+        .cmr_offset     = 0x10,
+        .pdr_offset     = 0x14,
+        .pwdr_offset    = 0x44,
+    },
+    {
+        .cnr_offset     = 0x18,
+        .cmr_offset     = 0x1c,
+        .pdr_offset     = 0x20,
+        .pwdr_offset    = 0x48,
+    },
+    {
+        .cnr_offset     = 0x24,
+        .cmr_offset     = 0x28,
+        .pdr_offset     = 0x2c,
+        .pwdr_offset    = 0x4c,
+    },
+    {
+        .cnr_offset     = 0x30,
+        .cmr_offset     = 0x34,
+        .pdr_offset     = 0x38,
+        .pwdr_offset    = 0x50,
+    },
+};
+
+static const int ppr_base[] = { 0, 0, 8, 8 };
+static const int csr_base[] = { 0, 4, 8, 12 };
+static const int pcr_base[] = { 0, 8, 12, 16 };
+
+static const uint32_t ppr_list[] = {
+    0,
+    1,
+    10,
+    100,
+    255, /* Max possible value. */
+};
+
+static const uint32_t csr_list[] = {
+    0,
+    1,
+    2,
+    3,
+    4, /* Max possible value. */
+};
+
+static const uint32_t cnr_list[] = {
+    0,
+    1,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+static const uint32_t cmr_list[] = {
+    0,
+    1,
+    10,
+    50,
+    100,
+    150,
+    200,
+    1000,
+    10000,
+    65535, /* Max possible value. */
+};
+
+/* Returns the index of the PWM module. */
+static int pwm_module_index(const PWMModule *module)
+{
+    ptrdiff_t diff = module - pwm_module_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
+
+    return diff;
+}
+
+/* Returns the index of the PWM entry. */
+static int pwm_index(const PWM *pwm)
+{
+    ptrdiff_t diff = pwm - pwm_list;
+
+    g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
+
+    return diff;
+}
+
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
+{
+    QDict *response;
+
+    g_test_message("Getting properties %s from %s", name, path);
+    response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
+            " 'arguments': { 'path': %s, 'property': %s}}",
+            path, name);
+    /* The qom set message returns successfully. */
+    g_assert_true(qdict_haskey(response, "return"));
+    return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
+}
+
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "freq[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
+{
+    char path[100];
+    char name[100];
+
+    sprintf(path, "/machine/soc/pwm[%d]", module_index);
+    sprintf(name, "duty[%d]", pwm_index);
+
+    return pwm_qom_get(qts, path, name);
+}
+
+static uint32_t get_pll(uint32_t con)
+{
+    return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
+            * PLL_OTDV2(con));
+}
+
+static uint64_t read_pclk(QTestState *qts)
+{
+    uint64_t freq = REF_HZ;
+    uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
+    uint32_t pllcon;
+    uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
+    uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
+
+    switch (CPUCKSEL(clksel)) {
+    case 0:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
+        freq = get_pll(pllcon);
+        break;
+    case 1:
+        pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
+        freq = get_pll(pllcon);
+        break;
+    case 2:
+        break;
+    case 3:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
+
+    return freq;
+}
+
+static uint32_t pwm_selector(uint32_t csr)
+{
+    switch (csr) {
+    case 0:
+        return 2;
+    case 1:
+        return 4;
+    case 2:
+        return 8;
+    case 3:
+        return 16;
+    case 4:
+        return 1;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
+        uint32_t cnr)
+{
+    return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
+}
+
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
+{
+    uint64_t duty;
+
+    if (cnr == 0) {
+        /* PWM is stopped. */
+        duty = 0;
+    } else if (cmr >= cnr) {
+        duty = MAX_DUTY;
+    } else {
+        duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
+    }
+
+    if (inverted) {
+        duty = MAX_DUTY - duty;
+    }
+
+    return duty;
+}
+
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
+{
+    return qtest_readl(qts, td->module->base_addr + offset);
+}
+
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
+        uint32_t value)
+{
+    qtest_writel(qts, td->module->base_addr + offset, value);
+}
+
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
+}
+
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
+}
+
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
+{
+    return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
+}
+
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
+}
+
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cnr_offset);
+}
+
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cnr_offset, value);
+}
+
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
+{
+    return pwm_read(qts, td, td->pwm->cmr_offset);
+}
+
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
+{
+    pwm_write(qts, td, td->pwm->cmr_offset, value);
+}
+
+/* Check pwm registers can be reset to default value */
+static void test_init(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+
+    g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+    g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+
+    qtest_quit(qts);
+}
+
+/* One-shot mode should not change frequency and duty cycle. */
+static void test_oneshot(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr;
+    int i, j;
+
+    pcr = CH_EN;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+            pwm_write_pcr(qts, td, pcr);
+
+            g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+            g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+            g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+            g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
+            g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+/* In toggle mode, the PWM generates correct outputs. */
+static void test_toggle(gconstpointer test_data)
+{
+    const TestData *td = test_data;
+    QTestState *qts = qtest_init("-machine quanta-gsj");
+    int module = pwm_module_index(td->module);
+    int pwm = pwm_index(td->pwm);
+    uint32_t ppr, csr, pcr, cnr, cmr;
+    int i, j, k, l;
+    uint64_t expected_freq, expected_duty;
+
+    pcr = CH_EN | CH_MOD;
+    for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
+        ppr = ppr_list[i];
+        pwm_write_ppr(qts, td, ppr);
+
+        for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
+            csr = csr_list[j];
+            pwm_write_csr(qts, td, csr);
+
+            for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
+                cnr = cnr_list[k];
+                pwm_write_cnr(qts, td, cnr);
+
+                for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
+                    cmr = cmr_list[l];
+                    pwm_write_cmr(qts, td, cmr);
+                    expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
+                    expected_duty = pwm_compute_duty(cnr, cmr, false);
+
+                    pwm_write_pcr(qts, td, pcr);
+                    g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
+                    g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
+                    g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
+                    g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                    /* Test inverted mode */
+                    expected_duty = pwm_compute_duty(cnr, cmr, true);
+                    pwm_write_pcr(qts, td, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
+                    g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
+                            ==, expected_duty);
+                    if (expected_duty != 0 && expected_duty != 100) {
+                        /* Duty cycle with 0 or 100 doesn't need frequency. */
+                        g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
+                                ==, expected_freq);
+                    }
+
+                }
+            }
+        }
+    }
+
+    qtest_quit(qts);
+}
+
+static void pwm_add_test(const char *name, const TestData* td,
+        GTestDataFunc fn)
+{
+    g_autofree char *full_name = g_strdup_printf(
+            "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
+            pwm_index(td->pwm), name);
+    qtest_add_data_func(full_name, td, fn);
+}
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
+
+int main(int argc, char **argv)
+{
+    TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
+
+    g_test_init(&argc, &argv, NULL);
+
+    for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
+        for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
+            TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
+
+            td->module = &pwm_module_list[i];
+            td->pwm = &pwm_list[j];
+
+            add_test(init, td);
+            add_test(oneshot, td);
+            add_test(toggle, td);
+        }
+    }
+
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
 qtests_npcm7xx = \
   ['npcm7xx_adc-test',
    'npcm7xx_gpio-test',
+   'npcm7xx_pwm-test',
    'npcm7xx_rng-test',
    'npcm7xx_timer-test',
    'npcm7xx_watchdog_timer-test']
-- 
2.20.1

From: Hao Wu <wuhaotsh@google.com>

A device shouldn't access its parent object which is QOM internal.
Instead it should use type cast for this purporse. This patch fixes this
issue for all NPCM7XX Devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 2 +-
 hw/mem/npcm7xx_mc.c     | 2 +-
 hw/misc/npcm7xx_clk.c   | 2 +-
 hw/misc/npcm7xx_gcr.c   | 2 +-
 hw/misc/npcm7xx_rng.c   | 2 +-
 hw/nvram/npcm7xx_otp.c  | 2 +-
 hw/ssi/npcm7xx_fiu.c    | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
                                         uint32_t hw_straps)
 {
     NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
-    MachineClass *mc = &nmc->parent;
+    MachineClass *mc = MACHINE_CLASS(nmc);
     Object *obj;
 
     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/mem/npcm7xx_mc.c
+++ b/hw/mem/npcm7xx_mc.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
 
     memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
                           NPCM7XX_MC_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->mmio);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
 }
 
 static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_clk.c
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
                           TYPE_NPCM7XX_CLK, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static int npcm7xx_clk_post_load(void *opaque, int version_id)
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_gcr.c
+++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
                           TYPE_NPCM7XX_GCR, 4 * KiB);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_gcr = {
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/npcm7xx_rng.c
+++ b/hw/misc/npcm7xx_rng.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
 
     memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
                           NPCM7XX_RNG_REGS_SIZE);
-    sysbus_init_mmio(&s->parent, &s->iomem);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 }
 
 static const VMStateDescription vmstate_npcm7xx_rng = {
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/npcm7xx_otp.c
+++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
     NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
     memset(s->array, 0, sizeof(s->array));
 
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
 static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
 {
     NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
-    SysBusDevice *sbd = &s->parent;
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     int i;
 
     if (s->cs_count <= 0) {
-- 
2.20.1

From: Roman Bolshakov <r.bolshakov@yadro.com>

ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
      [-Wdeprecated-declarations]
        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
                                           ^
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
      'openFile:' has been explicitly marked deprecated here
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
^

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 ui/cocoa.m | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/ui/cocoa.m b/ui/cocoa.m
index XXXXXXX..XXXXXXX 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
     /* Where to look for local files */
     NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
     NSString *full_file_path;
+    NSURL *full_file_url;
 
     /* iterate thru the possible paths until the file is found */
     int index;
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
         full_file_path = [full_file_path stringByDeletingLastPathComponent];
         full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
                           path_array[index], filename];
-        if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
+        full_file_url = [NSURL fileURLWithPath: full_file_path
+                                   isDirectory: false];
+        if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
             return;
         }
     }
-- 
2.20.1