[Qemu-devel] [PULL 00/13] target-arm queue
[PULL 00/16] target-arm queue
1
A random mix of items here, nothing very major.
1
Patches for rc1: nothing major, just some minor bugfixes and
2
code cleanups.
2
3
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
6
7
7
The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
8
9
9
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)
10
are available in the Git repository at:
10
11
11
are available in the git repository at:
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
12
13
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
14
15
15
for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
16
17
stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm:
19
target-arm queue:
21
* new "unimplemented" device for stubbing out devices in a
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
22
system model so accesses can be logged
21
* Minor coding style fixes
23
* stellaris: document the SoC memory map
22
* docs: add some notes on the sbsa-ref machine
24
* arm: create instruction syndromes for AArch32 data aborts
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
25
* arm: Correctly handle watchpoints for BE32 CPUs
24
* target/arm: Fix neon VTBL/VTBX for len > 1
26
* Fix Thumb-1 BE32 execution and disassembly
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
27
* arm: Add cfgend parameter for ARM CPU selection
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
28
* sd: sdhci: check data length during dma_memory_read
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
29
* aspeed: add a watchdog controller
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
30
* integratorcp: adding vmstate for save/restore
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
31
33
32
----------------------------------------------------------------
34
----------------------------------------------------------------
33
Cédric Le Goater (2):
35
Alex Bennée (1):
34
wdt: Add Aspeed watchdog device model
36
docs: add some notes on the sbsa-ref machine
35
aspeed: add a watchdog controller
36
37
37
Julian Brown (4):
38
AlexChen (1):
38
hw/arm/integratorcp: Support specifying features via -cpu
39
ssi: Fix bad printf format specifiers
39
target/arm: Add cfgend parameter for ARM CPU selection.
40
Fix Thumb-1 BE32 execution and disassembly.
41
arm: Correctly handle watchpoints for BE32 CPUs
42
40
43
Pavel Dovgalyuk (1):
41
Andrew Jones (1):
44
integratorcp: adding vmstate for save/restore
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
45
43
46
Peter Maydell (5):
44
Havard Skinnemoen (1):
47
target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
45
tests/qtest/npcm7xx_rng-test: count runs properly
48
target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
49
stellaris: Document memory map and which SoC devices are unimplemented
50
hw/misc: New "unimplemented" sysbus device
51
stellaris: Use the 'unimplemented' device for parts we don't implement
52
46
53
Prasad J Pandit (1):
47
Peter Maydell (2):
54
sd: sdhci: check data length during dma_memory_read
48
hw/arm/nseries: Check return value from load_image_targphys()
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
55
50
56
hw/misc/Makefile.objs | 2 +
51
Philippe Mathieu-Daudé (6):
57
hw/watchdog/Makefile.objs | 1 +
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
58
include/disas/bfd.h | 7 ++
53
hw/arm/armsse: Correct expansion MPC interrupt lines
59
include/hw/arm/aspeed_soc.h | 2 +
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
60
include/hw/misc/unimp.h | 39 +++++++
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
61
include/hw/watchdog/wdt_aspeed.h | 32 ++++++
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
62
include/qom/cpu.h | 3 +
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
63
target/arm/arm_ldst.h | 10 +-
64
target/arm/cpu.h | 7 ++
65
target/arm/internals.h | 5 +
66
target/arm/translate.h | 14 +++
67
disas.c | 1 +
68
exec.c | 1 +
69
hw/arm/aspeed_soc.c | 13 +++
70
hw/arm/integratorcp.c | 78 +++++++++++++-
71
hw/arm/stellaris.c | 48 +++++++++
72
hw/misc/unimp.c | 107 +++++++++++++++++++
73
hw/sd/sdhci.c | 2 +-
74
hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++
75
qom/cpu.c | 6 ++
76
target/arm/cpu.c | 39 +++++++
77
target/arm/op_helper.c | 22 ++++
78
target/arm/translate-a64.c | 14 ---
79
target/arm/translate.c | 193 ++++++++++++++++++++++++---------
80
24 files changed, 801 insertions(+), 70 deletions(-)
81
create mode 100644 include/hw/misc/unimp.h
82
create mode 100644 include/hw/watchdog/wdt_aspeed.h
83
create mode 100644 hw/misc/unimp.c
84
create mode 100644 hw/watchdog/wdt_aspeed.c
85
58
59
Richard Henderson (1):
60
target/arm: Fix neon VTBL/VTBX for len > 1
61
62
Xinhao Zhang (3):
63
target/arm: add spaces around operator
64
target/arm: Don't use '#' flag of printf format
65
target/arm: add space before the open parenthesis '('
66
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
New patch
[PULL 01/16] hw/arm/Kconfig: ARM_V7M depends on PTIMER
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
5
in the build when building armv7m_systick.
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/Kconfig | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/Kconfig
18
+++ b/hw/arm/Kconfig
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
20
21
config ARM_V7M
22
bool
23
+ select PTIMER
24
25
config ALLWINNER_A10
26
bool
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
[PULL 02/16] ssi: Fix bad printf format specifiers
1
From: AlexChen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 5FA280F5.8060902@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/ssi/imx_spi.c | 2 +-
13
hw/ssi/xilinx_spi.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/imx_spi.c
19
+++ b/hw/ssi/imx_spi.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
21
case ECSPI_MSGDATA:
22
return "ECSPI_MSGDATA";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
27
}
28
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/ssi/xilinx_spi.c
32
+++ b/hw/ssi/xilinx_spi.c
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
34
irq chain unless things really changed. */
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/13] target/arm: Add cfgend parameter for ARM CPU selection.
[PULL 03/16] target/arm: add spaces around operator
1
From: Julian Brown <julian@codesourcery.com>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
Add a new "cfgend" property which selects whether the CPU resets into
3
Fix code style. Operator needs spaces both sides.
4
big-endian mode or not. This setting affects whether we reset with
5
SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set.
6
4
7
Signed-off-by: Julian Brown <julian@codesourcery.com>
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
8
Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
9
[PMM: use error_report_err() rather than error_report();
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
10
move the integratorcp changes to their own patch;
11
drop an unnecessary extra #include;
12
rephrase commit message accordingly;
13
move setting of reset_sctlr above registration of cpregs
14
so it actually has an effect]
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
10
---
18
target/arm/cpu.h | 7 +++++++
11
target/arm/arch_dump.c | 8 ++++----
19
target/arm/cpu.c | 13 +++++++++++++
12
target/arm/arm-semi.c | 8 ++++----
20
2 files changed, 20 insertions(+)
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
21
15
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
23
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
18
--- a/target/arm/arch_dump.c
25
+++ b/target/arm/cpu.h
19
+++ b/target/arm/arch_dump.c
26
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
27
int gic_vpribits; /* number of virtual priority bits */
21
28
int gic_vprebits; /* number of virtual preemption bits */
22
for (i = 0; i < 32; ++i) {
29
23
uint64_t *q = aa64_vfp_qreg(env, i);
30
+ /* Whether the cfgend input is high (i.e. this CPU should reset into
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
31
+ * big-endian mode). This setting isn't used directly: instead it modifies
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
32
+ * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
33
+ * architecture version.
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
34
+ */
28
}
35
+ bool cfgend;
29
36
+
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
37
ARMELChangeHook *el_change_hook;
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
38
void *el_change_hook_opaque;
32
*/
39
};
33
for (i = 0; i < 32; ++i) {
40
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
34
uint64_t tmp = note.vfp.vregs[2*i];
41
index XXXXXXX..XXXXXXX 100644
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
42
--- a/target/arm/cpu.c
36
- note.vfp.vregs[2*i+1] = tmp;
43
+++ b/target/arm/cpu.c
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
44
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el2_property =
38
+ note.vfp.vregs[2 * i + 1] = tmp;
45
static Property arm_cpu_has_el3_property =
46
DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
47
48
+static Property arm_cpu_cfgend_property =
49
+ DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
50
+
51
/* use property name "pmu" to match other archs and virt tools */
52
static Property arm_cpu_has_pmu_property =
53
DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
54
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
55
}
39
}
56
}
40
}
57
41
58
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
59
+ &error_abort);
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
87
uint32_t sum;
88
sum = do_usad(a, b);
89
sum += do_usad(a >> 8, b >> 8);
90
- sum += do_usad(a >> 16, b >>16);
91
+ sum += do_usad(a >> 16, b >> 16);
92
sum += do_usad(a >> 24, b >> 24);
93
return sum;
60
}
94
}
61
62
static void arm_cpu_finalizefn(Object *obj)
63
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
64
cpu->reset_sctlr |= (1 << 13);
65
}
66
67
+ if (cpu->cfgend) {
68
+ if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
69
+ cpu->reset_sctlr |= SCTLR_EE;
70
+ } else {
71
+ cpu->reset_sctlr |= SCTLR_B;
72
+ }
73
+ }
74
+
75
if (!cpu->has_el3) {
76
/* If the has_el3 CPU property is disabled then we need to disable the
77
* feature.
78
--
95
--
79
2.7.4
96
2.20.1
80
97
81
98
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/13] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
[PULL 04/16] target/arm: Don't use '#' flag of printf format
1
Add support for generating the ISS (Instruction Specific Syndrome)
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
for Data Abort exceptions taken from AArch32. These syndromes are
3
used by hypervisors for example to trap and emulate memory accesses.
4
2
5
This is the equivalent for AArch32 guests of the work done for AArch64
3
Fix code style. Don't use '#' flag of printf format ('%#') in
6
guests in commit aaa1f954d4cab243.
4
format strings, use '0x' prefix instead
7
5
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
---
11
---
11
target/arm/translate.h | 14 ++++
12
target/arm/translate-a64.c | 4 ++--
12
target/arm/translate-a64.c | 14 ----
13
1 file changed, 2 insertions(+), 2 deletions(-)
13
target/arm/translate.c | 184 +++++++++++++++++++++++++++++++++------------
14
3 files changed, 149 insertions(+), 63 deletions(-)
15
14
16
diff --git a/target/arm/translate.h b/target/arm/translate.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate.h
19
+++ b/target/arm/translate.h
20
@@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s)
21
? 3 : MAX(1, s->current_el);
22
}
23
24
+static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
25
+{
26
+ /* We don't need to save all of the syndrome so we mask and shift
27
+ * out unneeded bits to help the sleb128 encoder do a better job.
28
+ */
29
+ syn &= ARM_INSN_START_WORD2_MASK;
30
+ syn >>= ARM_INSN_START_WORD2_SHIFT;
31
+
32
+ /* We check and clear insn_start_idx to catch multiple updates. */
33
+ assert(s->insn_start_idx != 0);
34
+ tcg_set_insn_param(s->insn_start_idx, 2, syn);
35
+ s->insn_start_idx = 0;
36
+}
37
+
38
/* target-specific extra values for is_jmp */
39
/* These instructions trap after executing, so the A32/T32 decoder must
40
* defer them until after the conditional execution state has been updated.
41
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
42
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
44
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
45
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
46
}
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
47
}
48
49
-static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
50
-{
51
- /* We don't need to save all of the syndrome so we mask and shift
52
- * out uneeded bits to help the sleb128 encoder do a better job.
53
- */
54
- syn &= ARM_INSN_START_WORD2_MASK;
55
- syn >>= ARM_INSN_START_WORD2_SHIFT;
56
-
57
- /* We check and clear insn_start_idx to catch multiple updates. */
58
- assert(s->insn_start_idx != 0);
59
- tcg_set_insn_param(s->insn_start_idx, 2, syn);
60
- s->insn_start_idx = 0;
61
-}
62
-
63
static void unallocated_encoding(DisasContext *s)
64
{
65
/* Unallocated and reserved encodings are uncategorized */
66
diff --git a/target/arm/translate.c b/target/arm/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/translate.c
69
+++ b/target/arm/translate.c
70
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
71
a64_translate_init();
72
}
73
74
+/* Flags for the disas_set_da_iss info argument:
75
+ * lower bits hold the Rt register number, higher bits are flags.
76
+ */
77
+typedef enum ISSInfo {
78
+ ISSNone = 0,
79
+ ISSRegMask = 0x1f,
80
+ ISSInvalid = (1 << 5),
81
+ ISSIsAcqRel = (1 << 6),
82
+ ISSIsWrite = (1 << 7),
83
+ ISSIs16Bit = (1 << 8),
84
+} ISSInfo;
85
+
86
+/* Save the syndrome information for a Data Abort */
87
+static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
88
+{
89
+ uint32_t syn;
90
+ int sas = memop & MO_SIZE;
91
+ bool sse = memop & MO_SIGN;
92
+ bool is_acqrel = issinfo & ISSIsAcqRel;
93
+ bool is_write = issinfo & ISSIsWrite;
94
+ bool is_16bit = issinfo & ISSIs16Bit;
95
+ int srt = issinfo & ISSRegMask;
96
+
97
+ if (issinfo & ISSInvalid) {
98
+ /* Some callsites want to conditionally provide ISS info,
99
+ * eg "only if this was not a writeback"
100
+ */
101
+ return;
102
+ }
103
+
104
+ if (srt == 15) {
105
+ /* For AArch32, insns where the src/dest is R15 never generate
106
+ * ISS information. Catching that here saves checking at all
107
+ * the call sites.
108
+ */
109
+ return;
110
+ }
111
+
112
+ syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,
113
+ 0, 0, 0, is_write, 0, is_16bit);
114
+ disas_set_insn_syndrome(s, syn);
115
+}
116
+
117
static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
118
{
119
/* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
120
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
121
TCGv_i32 a32, int index) \
122
{ \
123
gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
124
+} \
125
+static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
126
+ TCGv_i32 val, \
127
+ TCGv_i32 a32, int index, \
128
+ ISSInfo issinfo) \
129
+{ \
130
+ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
131
+ disas_set_da_iss(s, OPC, issinfo); \
132
}
133
134
#define DO_GEN_ST(SUFF, OPC) \
135
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
136
TCGv_i32 a32, int index) \
137
{ \
138
gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
139
+} \
140
+static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
141
+ TCGv_i32 val, \
142
+ TCGv_i32 a32, int index, \
143
+ ISSInfo issinfo) \
144
+{ \
145
+ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
146
+ disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
147
}
148
149
static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
150
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
151
tmp = tcg_temp_new_i32();
152
switch (op1) {
153
case 0: /* lda */
154
- gen_aa32_ld32u(s, tmp, addr,
155
- get_mem_index(s));
156
+ gen_aa32_ld32u_iss(s, tmp, addr,
157
+ get_mem_index(s),
158
+ rd | ISSIsAcqRel);
159
break;
160
case 2: /* ldab */
161
- gen_aa32_ld8u(s, tmp, addr,
162
- get_mem_index(s));
163
+ gen_aa32_ld8u_iss(s, tmp, addr,
164
+ get_mem_index(s),
165
+ rd | ISSIsAcqRel);
166
break;
167
case 3: /* ldah */
168
- gen_aa32_ld16u(s, tmp, addr,
169
- get_mem_index(s));
170
+ gen_aa32_ld16u_iss(s, tmp, addr,
171
+ get_mem_index(s),
172
+ rd | ISSIsAcqRel);
173
break;
174
default:
175
abort();
176
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
177
tmp = load_reg(s, rm);
178
switch (op1) {
179
case 0: /* stl */
180
- gen_aa32_st32(s, tmp, addr,
181
- get_mem_index(s));
182
+ gen_aa32_st32_iss(s, tmp, addr,
183
+ get_mem_index(s),
184
+ rm | ISSIsAcqRel);
185
break;
186
case 2: /* stlb */
187
- gen_aa32_st8(s, tmp, addr,
188
- get_mem_index(s));
189
+ gen_aa32_st8_iss(s, tmp, addr,
190
+ get_mem_index(s),
191
+ rm | ISSIsAcqRel);
192
break;
193
case 3: /* stlh */
194
- gen_aa32_st16(s, tmp, addr,
195
- get_mem_index(s));
196
+ gen_aa32_st16_iss(s, tmp, addr,
197
+ get_mem_index(s),
198
+ rm | ISSIsAcqRel);
199
break;
200
default:
201
abort();
202
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
203
bool wbit = insn & (1 << 21);
204
bool pbit = insn & (1 << 24);
205
bool doubleword = false;
206
+ ISSInfo issinfo;
207
+
208
/* Misc load/store */
209
rn = (insn >> 16) & 0xf;
210
rd = (insn >> 12) & 0xf;
211
212
+ /* ISS not valid if writeback */
213
+ issinfo = (pbit & !wbit) ? rd : ISSInvalid;
214
+
215
if (!load && (sh & 2)) {
216
/* doubleword */
217
ARCH(5TE);
218
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
219
tmp = tcg_temp_new_i32();
220
switch (sh) {
221
case 1:
222
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
223
+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
224
+ issinfo);
225
break;
226
case 2:
227
- gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
228
+ gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
229
+ issinfo);
230
break;
231
default:
232
case 3:
233
- gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
234
+ gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
235
+ issinfo);
236
break;
237
}
238
} else {
239
/* store */
240
tmp = load_reg(s, rd);
241
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
242
+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
243
tcg_temp_free_i32(tmp);
244
}
245
/* Perform base writeback before the loaded value to
246
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
247
/* load */
248
tmp = tcg_temp_new_i32();
249
if (insn & (1 << 22)) {
250
- gen_aa32_ld8u(s, tmp, tmp2, i);
251
+ gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
252
} else {
253
- gen_aa32_ld32u(s, tmp, tmp2, i);
254
+ gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
255
}
256
} else {
257
/* store */
258
tmp = load_reg(s, rd);
259
if (insn & (1 << 22)) {
260
- gen_aa32_st8(s, tmp, tmp2, i);
261
+ gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
262
} else {
263
- gen_aa32_st32(s, tmp, tmp2, i);
264
+ gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
265
}
266
tcg_temp_free_i32(tmp);
267
}
268
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
269
tmp = tcg_temp_new_i32();
270
switch (op) {
271
case 0: /* ldab */
272
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
273
+ gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
274
+ rs | ISSIsAcqRel);
275
break;
276
case 1: /* ldah */
277
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
278
+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
279
+ rs | ISSIsAcqRel);
280
break;
281
case 2: /* lda */
282
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
283
+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
284
+ rs | ISSIsAcqRel);
285
break;
286
default:
287
abort();
288
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
289
tmp = load_reg(s, rs);
290
switch (op) {
291
case 0: /* stlb */
292
- gen_aa32_st8(s, tmp, addr, get_mem_index(s));
293
+ gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
294
+ rs | ISSIsAcqRel);
295
break;
296
case 1: /* stlh */
297
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
298
+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
299
+ rs | ISSIsAcqRel);
300
break;
301
case 2: /* stl */
302
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
303
+ gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
304
+ rs | ISSIsAcqRel);
305
break;
306
default:
307
abort();
308
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
309
int postinc = 0;
310
int writeback = 0;
311
int memidx;
312
+ ISSInfo issinfo;
313
+
314
if ((insn & 0x01100000) == 0x01000000) {
315
if (disas_neon_ls_insn(s, insn)) {
316
goto illegal_op;
317
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
318
}
319
}
320
}
321
+
322
+ issinfo = writeback ? ISSInvalid : rs;
323
+
324
if (insn & (1 << 20)) {
325
/* Load. */
326
tmp = tcg_temp_new_i32();
327
switch (op) {
328
case 0:
329
- gen_aa32_ld8u(s, tmp, addr, memidx);
330
+ gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
331
break;
332
case 4:
333
- gen_aa32_ld8s(s, tmp, addr, memidx);
334
+ gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
335
break;
336
case 1:
337
- gen_aa32_ld16u(s, tmp, addr, memidx);
338
+ gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
339
break;
340
case 5:
341
- gen_aa32_ld16s(s, tmp, addr, memidx);
342
+ gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
343
break;
344
case 2:
345
- gen_aa32_ld32u(s, tmp, addr, memidx);
346
+ gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
347
break;
21
break;
348
default:
22
default:
349
tcg_temp_free_i32(tmp);
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
350
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
351
tmp = load_reg(s, rs);
25
__func__, insn, fpopcode, s->pc_curr);
352
switch (op) {
26
g_assert_not_reached();
353
case 0:
27
}
354
- gen_aa32_st8(s, tmp, addr, memidx);
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
355
+ gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
29
case 0x7f: /* FSQRT (vector) */
356
break;
30
break;
357
case 1:
31
default:
358
- gen_aa32_st16(s, tmp, addr, memidx);
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
359
+ gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
360
break;
34
g_assert_not_reached();
361
case 2:
35
}
362
- gen_aa32_st32(s, tmp, addr, memidx);
36
363
+ gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
364
break;
365
default:
366
tcg_temp_free_i32(tmp);
367
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
368
addr = tcg_temp_new_i32();
369
tcg_gen_movi_i32(addr, val);
370
tmp = tcg_temp_new_i32();
371
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
372
+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
373
+ rd | ISSIs16Bit);
374
tcg_temp_free_i32(addr);
375
store_reg(s, rd, tmp);
376
break;
377
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
378
379
switch (op) {
380
case 0: /* str */
381
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
382
+ gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
383
break;
384
case 1: /* strh */
385
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
386
+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
387
break;
388
case 2: /* strb */
389
- gen_aa32_st8(s, tmp, addr, get_mem_index(s));
390
+ gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
391
break;
392
case 3: /* ldrsb */
393
- gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
394
+ gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
395
break;
396
case 4: /* ldr */
397
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
398
+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
399
break;
400
case 5: /* ldrh */
401
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
402
+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
403
break;
404
case 6: /* ldrb */
405
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
406
+ gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
407
break;
408
case 7: /* ldrsh */
409
- gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
410
+ gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
411
break;
412
}
413
if (op >= 3) { /* load */
414
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
415
if (insn & (1 << 11)) {
416
/* load */
417
tmp = tcg_temp_new_i32();
418
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
419
+ gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
420
store_reg(s, rd, tmp);
421
} else {
422
/* store */
423
tmp = load_reg(s, rd);
424
- gen_aa32_st8(s, tmp, addr, get_mem_index(s));
425
+ gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
426
tcg_temp_free_i32(tmp);
427
}
428
tcg_temp_free_i32(addr);
429
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
430
if (insn & (1 << 11)) {
431
/* load */
432
tmp = tcg_temp_new_i32();
433
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
434
+ gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
435
store_reg(s, rd, tmp);
436
} else {
437
/* store */
438
tmp = load_reg(s, rd);
439
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
440
+ gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
441
tcg_temp_free_i32(tmp);
442
}
443
tcg_temp_free_i32(addr);
444
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
445
if (insn & (1 << 11)) {
446
/* load */
447
tmp = tcg_temp_new_i32();
448
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
449
+ gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
450
store_reg(s, rd, tmp);
451
} else {
452
/* store */
453
tmp = load_reg(s, rd);
454
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
455
+ gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
456
tcg_temp_free_i32(tmp);
457
}
458
tcg_temp_free_i32(addr);
459
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
460
store_cpu_field(tmp, condexec_bits);
461
}
462
do {
463
+ dc->insn_start_idx = tcg_op_buf_count();
464
tcg_gen_insn_start(dc->pc,
465
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
466
0);
467
--
37
--
468
2.7.4
38
2.20.1
469
39
470
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
[PULL 05/16] target/arm: add space before the open parenthesis '('
1
In the ARM ldr/str decode path, rather than directly testing
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
3
bits out into wbit and pbit local flags. (We will want to
4
do more tests against them to determine whether we need to
5
provide syndrome information.)
6
2
3
Fix code style. Space required before the open parenthesis '('.
4
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
---
10
---
10
target/arm/translate.c | 9 ++++++---
11
target/arm/translate.c | 2 +-
11
1 file changed, 6 insertions(+), 3 deletions(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
18
} else {
19
- Hardware watchpoints.
19
int address_offset;
20
Hardware breakpoints have already been handled and skip this code.
20
bool load = insn & (1 << 20);
21
*/
21
+ bool wbit = insn & (1 << 21);
22
- switch(dc->base.is_jmp) {
22
+ bool pbit = insn & (1 << 24);
23
+ switch (dc->base.is_jmp) {
23
bool doubleword = false;
24
case DISAS_NEXT:
24
/* Misc load/store */
25
case DISAS_TOO_MANY:
25
rn = (insn >> 16) & 0xf;
26
gen_goto_tb(dc, 1, dc->base.pc_next);
26
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
27
}
28
29
addr = load_reg(s, rn);
30
- if (insn & (1 << 24))
31
+ if (pbit) {
32
gen_add_datah_offset(s, insn, 0, addr);
33
+ }
34
address_offset = 0;
35
36
if (doubleword) {
37
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
38
ensure correct behavior with overlapping index registers.
39
ldrd with base writeback is undefined if the
40
destination and index registers overlap. */
41
- if (!(insn & (1 << 24))) {
42
+ if (!pbit) {
43
gen_add_datah_offset(s, insn, address_offset, addr);
44
store_reg(s, rn, addr);
45
- } else if (insn & (1 << 21)) {
46
+ } else if (wbit) {
47
if (address_offset)
48
tcg_gen_addi_i32(addr, addr, address_offset);
49
store_reg(s, rn, addr);
50
--
27
--
51
2.7.4
28
2.20.1
52
29
53
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/13] wdt: Add Aspeed watchdog device model
[PULL 06/16] docs: add some notes on the sbsa-ref machine
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
The Aspeed SoC includes a set of watchdog timers using 32-bit
3
We should at least document what this machine is about.
4
decrement counters, which can be based either on the APB clock or
5
a 1 MHz clock.
6
4
7
The watchdog timer is designed to prevent system deadlock and, in
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
8
general, it should be restarted before timeout. When a timeout occurs,
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
different types of signals can be generated, ARM reset, SOC reset,
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
10
System reset, CPU Interrupt, external signal or boot from alternate
8
Cc: Leif Lindholm <leif@nuviainc.com>
11
block. The current model only performs the system reset function as
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
12
this is used by U-Boot and Linux.
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
13
11
[PMM: fixed filename mismatch]
14
Signed-off-by: Joel Stanley <joel@jms.id.au>
15
Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org
16
[clg: - fixed compile breakage
17
- fixed io region size
18
- added watchdog_perform_action() on timer expiry
19
- wrote a commit log
20
- merged fixes from Andrew Jeffery to scale the reload value ]
21
Signed-off-by: Cédric Le Goater <clg@kaod.org>
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
13
---
25
hw/watchdog/Makefile.objs | 1 +
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
26
include/hw/watchdog/wdt_aspeed.h | 32 ++++++
15
docs/system/target-arm.rst | 1 +
27
hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++
16
2 files changed, 33 insertions(+)
28
3 files changed, 258 insertions(+)
17
create mode 100644 docs/system/arm/sbsa.rst
29
create mode 100644 include/hw/watchdog/wdt_aspeed.h
30
create mode 100644 hw/watchdog/wdt_aspeed.c
31
18
32
diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/watchdog/Makefile.objs
35
+++ b/hw/watchdog/Makefile.objs
36
@@ -XXX,XX +XXX,XX @@ common-obj-y += watchdog.o
37
common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
38
common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
39
common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
40
+common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
41
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
42
new file mode 100644
20
new file mode 100644
43
index XXXXXXX..XXXXXXX
21
index XXXXXXX..XXXXXXX
44
--- /dev/null
22
--- /dev/null
45
+++ b/include/hw/watchdog/wdt_aspeed.h
23
+++ b/docs/system/arm/sbsa.rst
46
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
47
+/*
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
48
+ * ASPEED Watchdog Controller
26
+==================================================================
49
+ *
50
+ * Copyright (C) 2016-2017 IBM Corp.
51
+ *
52
+ * This code is licensed under the GPL version 2 or later. See the
53
+ * COPYING file in the top-level directory.
54
+ */
55
+#ifndef ASPEED_WDT_H
56
+#define ASPEED_WDT_H
57
+
27
+
58
+#include "hw/sysbus.h"
28
+While the `virt` board is a generic board platform that doesn't match
29
+any real hardware the `sbsa-ref` board intends to look like real
30
+hardware. The `Server Base System Architecture
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
59
+
39
+
60
+#define TYPE_ASPEED_WDT "aspeed.wdt"
40
+It is intended to be a machine for developing firmware and testing
61
+#define ASPEED_WDT(obj) \
41
+standards compliance with operating systems.
62
+ OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
63
+
42
+
64
+#define ASPEED_WDT_REGS_MAX (0x20 / 4)
43
+Supported devices
44
+"""""""""""""""""
65
+
45
+
66
+typedef struct AspeedWDTState {
46
+The sbsa-ref board supports:
67
+ /*< private >*/
68
+ SysBusDevice parent_obj;
69
+ QEMUTimer *timer;
70
+
47
+
71
+ /*< public >*/
48
+ - A configurable number of AArch64 CPUs
72
+ MemoryRegion iomem;
49
+ - GIC version 3
73
+ uint32_t regs[ASPEED_WDT_REGS_MAX];
50
+ - System bus AHCI controller
51
+ - System bus EHCI controller
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
74
+
56
+
75
+ uint32_t pclk_freq;
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
76
+} AspeedWDTState;
58
index XXXXXXX..XXXXXXX 100644
77
+
59
--- a/docs/system/target-arm.rst
78
+#endif /* ASPEED_WDT_H */
60
+++ b/docs/system/target-arm.rst
79
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
80
new file mode 100644
62
arm/mps2
81
index XXXXXXX..XXXXXXX
63
arm/musca
82
--- /dev/null
64
arm/realview
83
+++ b/hw/watchdog/wdt_aspeed.c
65
+ arm/sbsa
84
@@ -XXX,XX +XXX,XX @@
66
arm/versatile
85
+/*
67
arm/vexpress
86
+ * ASPEED Watchdog Controller
68
arm/aspeed
87
+ *
88
+ * Copyright (C) 2016-2017 IBM Corp.
89
+ *
90
+ * This code is licensed under the GPL version 2 or later. See the
91
+ * COPYING file in the top-level directory.
92
+ */
93
+
94
+#include "qemu/osdep.h"
95
+#include "qemu/log.h"
96
+#include "sysemu/watchdog.h"
97
+#include "hw/sysbus.h"
98
+#include "qemu/timer.h"
99
+#include "hw/watchdog/wdt_aspeed.h"
100
+
101
+#define WDT_STATUS (0x00 / 4)
102
+#define WDT_RELOAD_VALUE (0x04 / 4)
103
+#define WDT_RESTART (0x08 / 4)
104
+#define WDT_CTRL (0x0C / 4)
105
+#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
106
+#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
107
+#define WDT_CTRL_1MHZ_CLK BIT(4)
108
+#define WDT_CTRL_WDT_EXT BIT(3)
109
+#define WDT_CTRL_WDT_INTR BIT(2)
110
+#define WDT_CTRL_RESET_SYSTEM BIT(1)
111
+#define WDT_CTRL_ENABLE BIT(0)
112
+
113
+#define WDT_TIMEOUT_STATUS (0x10 / 4)
114
+#define WDT_TIMEOUT_CLEAR (0x14 / 4)
115
+#define WDT_RESET_WDITH (0x18 / 4)
116
+
117
+#define WDT_RESTART_MAGIC 0x4755
118
+
119
+static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
120
+{
121
+ return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
122
+}
123
+
124
+static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
125
+{
126
+ AspeedWDTState *s = ASPEED_WDT(opaque);
127
+
128
+ offset >>= 2;
129
+
130
+ switch (offset) {
131
+ case WDT_STATUS:
132
+ return s->regs[WDT_STATUS];
133
+ case WDT_RELOAD_VALUE:
134
+ return s->regs[WDT_RELOAD_VALUE];
135
+ case WDT_RESTART:
136
+ qemu_log_mask(LOG_GUEST_ERROR,
137
+ "%s: read from write-only reg at offset 0x%"
138
+ HWADDR_PRIx "\n", __func__, offset);
139
+ return 0;
140
+ case WDT_CTRL:
141
+ return s->regs[WDT_CTRL];
142
+ case WDT_TIMEOUT_STATUS:
143
+ case WDT_TIMEOUT_CLEAR:
144
+ case WDT_RESET_WDITH:
145
+ qemu_log_mask(LOG_UNIMP,
146
+ "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
147
+ __func__, offset);
148
+ return 0;
149
+ default:
150
+ qemu_log_mask(LOG_GUEST_ERROR,
151
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
152
+ __func__, offset);
153
+ return 0;
154
+ }
155
+
156
+}
157
+
158
+static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
159
+{
160
+ uint32_t reload;
161
+
162
+ if (pclk) {
163
+ reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
164
+ s->pclk_freq);
165
+ } else {
166
+ reload = s->regs[WDT_RELOAD_VALUE] * 1000;
167
+ }
168
+
169
+ if (aspeed_wdt_is_enabled(s)) {
170
+ timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
171
+ }
172
+}
173
+
174
+static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
175
+ unsigned size)
176
+{
177
+ AspeedWDTState *s = ASPEED_WDT(opaque);
178
+ bool enable = data & WDT_CTRL_ENABLE;
179
+
180
+ offset >>= 2;
181
+
182
+ switch (offset) {
183
+ case WDT_STATUS:
184
+ qemu_log_mask(LOG_GUEST_ERROR,
185
+ "%s: write to read-only reg at offset 0x%"
186
+ HWADDR_PRIx "\n", __func__, offset);
187
+ break;
188
+ case WDT_RELOAD_VALUE:
189
+ s->regs[WDT_RELOAD_VALUE] = data;
190
+ break;
191
+ case WDT_RESTART:
192
+ if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
193
+ s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
194
+ aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
195
+ }
196
+ break;
197
+ case WDT_CTRL:
198
+ if (enable && !aspeed_wdt_is_enabled(s)) {
199
+ s->regs[WDT_CTRL] = data;
200
+ aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
201
+ } else if (!enable && aspeed_wdt_is_enabled(s)) {
202
+ s->regs[WDT_CTRL] = data;
203
+ timer_del(s->timer);
204
+ }
205
+ break;
206
+ case WDT_TIMEOUT_STATUS:
207
+ case WDT_TIMEOUT_CLEAR:
208
+ case WDT_RESET_WDITH:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
211
+ __func__, offset);
212
+ break;
213
+ default:
214
+ qemu_log_mask(LOG_GUEST_ERROR,
215
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
216
+ __func__, offset);
217
+ }
218
+ return;
219
+}
220
+
221
+static WatchdogTimerModel model = {
222
+ .wdt_name = TYPE_ASPEED_WDT,
223
+ .wdt_description = "Aspeed watchdog device",
224
+};
225
+
226
+static const VMStateDescription vmstate_aspeed_wdt = {
227
+ .name = "vmstate_aspeed_wdt",
228
+ .version_id = 0,
229
+ .minimum_version_id = 0,
230
+ .fields = (VMStateField[]) {
231
+ VMSTATE_TIMER_PTR(timer, AspeedWDTState),
232
+ VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
233
+ VMSTATE_END_OF_LIST()
234
+ }
235
+};
236
+
237
+static const MemoryRegionOps aspeed_wdt_ops = {
238
+ .read = aspeed_wdt_read,
239
+ .write = aspeed_wdt_write,
240
+ .endianness = DEVICE_LITTLE_ENDIAN,
241
+ .valid.min_access_size = 4,
242
+ .valid.max_access_size = 4,
243
+ .valid.unaligned = false,
244
+};
245
+
246
+static void aspeed_wdt_reset(DeviceState *dev)
247
+{
248
+ AspeedWDTState *s = ASPEED_WDT(dev);
249
+
250
+ s->regs[WDT_STATUS] = 0x3EF1480;
251
+ s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
252
+ s->regs[WDT_RESTART] = 0;
253
+ s->regs[WDT_CTRL] = 0;
254
+
255
+ timer_del(s->timer);
256
+}
257
+
258
+static void aspeed_wdt_timer_expired(void *dev)
259
+{
260
+ AspeedWDTState *s = ASPEED_WDT(dev);
261
+
262
+ qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
263
+ watchdog_perform_action();
264
+ timer_del(s->timer);
265
+}
266
+
267
+#define PCLK_HZ 24000000
268
+
269
+static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
270
+{
271
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
272
+ AspeedWDTState *s = ASPEED_WDT(dev);
273
+
274
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
275
+
276
+ /* FIXME: This setting should be derived from the SCU hw strapping
277
+ * register SCU70
278
+ */
279
+ s->pclk_freq = PCLK_HZ;
280
+
281
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
282
+ TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
283
+ sysbus_init_mmio(sbd, &s->iomem);
284
+}
285
+
286
+static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
287
+{
288
+ DeviceClass *dc = DEVICE_CLASS(klass);
289
+
290
+ dc->realize = aspeed_wdt_realize;
291
+ dc->reset = aspeed_wdt_reset;
292
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
293
+ dc->vmsd = &vmstate_aspeed_wdt;
294
+}
295
+
296
+static const TypeInfo aspeed_wdt_info = {
297
+ .parent = TYPE_SYS_BUS_DEVICE,
298
+ .name = TYPE_ASPEED_WDT,
299
+ .instance_size = sizeof(AspeedWDTState),
300
+ .class_init = aspeed_wdt_class_init,
301
+};
302
+
303
+static void wdt_aspeed_register_types(void)
304
+{
305
+ watchdog_add_model(&model);
306
+ type_register_static(&aspeed_wdt_info);
307
+}
308
+
309
+type_init(wdt_aspeed_register_types)
310
--
69
--
311
2.7.4
70
2.20.1
312
71
313
72
diff view generated by jsdifflib
New patch
[PULL 07/16] hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
When using a Cortex-A15, the Virt machine does not use any
4
MPCore peripherals. Remove the dependency.
5
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/Kconfig | 1 -
14
1 file changed, 1 deletion(-)
15
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Kconfig
19
+++ b/hw/arm/Kconfig
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
21
imply VFIO_PLATFORM
22
imply VFIO_XGMAC
23
imply TPM_TIS_SYSBUS
24
- select A15MPCORE
25
select ACPI
26
select ARM_SMMUV3
27
select GPIO_KEY
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/13] arm: Correctly handle watchpoints for BE32 CPUs
[PULL 08/16] target/arm: Fix neon VTBL/VTBX for len > 1
1
From: Julian Brown <julian@codesourcery.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
In BE32 mode, sub-word size watchpoints can fail to trigger because the
3
The helper function did not get updated when we reorganized
4
address of the access is adjusted in the opcode helpers before being
4
the vector register file for SVE. Since then, the neon dregs
5
compared with the watchpoint registers. This patch reverses the address
5
are non-sequential and cannot be simply indexed.
6
adjustment before performing the comparison with the help of a new CPUClass
7
hook.
8
6
9
This version of the patch augments and tidies up comments a little.
7
At the same time, make the helper function operate on 64-bit
8
quantities so that we do not have to call it twice.
10
9
11
Signed-off-by: Julian Brown <julian@codesourcery.com>
10
Fixes: c39c2b9043e
12
Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
17
---
16
include/qom/cpu.h | 3 +++
18
target/arm/helper.h | 2 +-
17
target/arm/internals.h | 5 +++++
19
target/arm/op_helper.c | 23 +++++++++--------
18
exec.c | 1 +
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
19
qom/cpu.c | 6 ++++++
21
3 files changed, 29 insertions(+), 40 deletions(-)
20
target/arm/cpu.c | 3 +++
21
target/arm/op_helper.c | 22 ++++++++++++++++++++++
22
6 files changed, 40 insertions(+)
23
22
24
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
25
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
26
--- a/include/qom/cpu.h
25
--- a/target/arm/helper.h
27
+++ b/include/qom/cpu.h
26
+++ b/target/arm/helper.h
28
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
29
* @cpu_exec_exit: Callback for cpu_exec cleanup.
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
30
* @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
31
* @disas_set_info: Setup architecture specific components of disassembly info
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
32
+ * @adjust_watchpoint_address: Perform a target-specific adjustment to an
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
33
+ * address before attempting to match it against watchpoints.
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
34
*
33
35
* Represents a CPU family or model.
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
36
*/
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
38
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
39
40
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
41
+ vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
42
} CPUClass;
43
44
#ifdef HOST_WORDS_BIGENDIAN
45
diff --git a/target/arm/internals.h b/target/arm/internals.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/internals.h
48
+++ b/target/arm/internals.h
49
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu);
50
/* Callback function for checking if a watchpoint should trigger. */
51
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
52
53
+/* Adjust addresses (in BE32 mode) before testing against watchpoint
54
+ * addresses.
55
+ */
56
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
57
+
58
/* Callback function for when a watchpoint or breakpoint triggers. */
59
void arm_debug_excp_handler(CPUState *cs);
60
61
diff --git a/exec.c b/exec.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/exec.c
64
+++ b/exec.c
65
@@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
66
return;
67
}
68
vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
69
+ vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
70
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
71
if (cpu_watchpoint_address_matches(wp, vaddr, len)
72
&& (wp->flags & flags)) {
73
diff --git a/qom/cpu.c b/qom/cpu.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/qom/cpu.c
76
+++ b/qom/cpu.c
77
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
78
return cpu->cpu_index;
79
}
80
81
+static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
82
+{
83
+ return addr;
84
+}
85
+
86
static void cpu_class_init(ObjectClass *klass, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(klass);
89
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
90
k->cpu_exec_enter = cpu_common_noop;
91
k->cpu_exec_exit = cpu_common_noop;
92
k->cpu_exec_interrupt = cpu_common_exec_interrupt;
93
+ k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
94
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
95
dc->realize = cpu_common_realizefn;
96
dc->unrealize = cpu_common_unrealizefn;
97
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
98
index XXXXXXX..XXXXXXX 100644
99
--- a/target/arm/cpu.c
100
+++ b/target/arm/cpu.c
101
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
102
cc->gdb_stop_before_watchpoint = true;
103
cc->debug_excp_handler = arm_debug_excp_handler;
104
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
105
+#if !defined(CONFIG_USER_ONLY)
106
+ cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
107
+#endif
108
109
cc->disas_set_info = arm_disas_set_info;
110
}
111
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
112
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/op_helper.c
38
--- a/target/arm/op_helper.c
114
+++ b/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
115
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
116
return check_watchpoints(cpu);
41
cpu_loop_exit_restore(cs, ra);
117
}
42
}
118
43
119
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
120
+{
45
- uint32_t maxindex)
121
+ ARMCPU *cpu = ARM_CPU(cs);
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
122
+ CPUARMState *env = &cpu->env;
47
+ uint64_t ireg, uint64_t def)
48
{
49
- uint32_t val, shift;
50
- uint64_t *table = vn;
51
+ uint64_t tmp, val = 0;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
53
+ uint32_t base_reg = desc >> 2;
54
+ uint32_t shift, index, reg;
55
56
- val = 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
123
+
141
+
124
+ /* In BE32 system mode, target memory is stored byteswapped (on a
142
+ tcg_temp_free_i64(def);
125
+ * little-endian host system), and by the time we reach here (via an
143
+ tcg_temp_free_i64(val);
126
+ * opcode helper) the addresses of subword accesses have been adjusted
144
+ tcg_temp_free_i32(desc);
127
+ * to account for that, which means that watchpoints will not match.
145
return true;
128
+ * Undo the adjustment here.
146
}
129
+ */
147
130
+ if (arm_sctlr_b(env)) {
131
+ if (len == 1) {
132
+ addr ^= 3;
133
+ } else if (len == 2) {
134
+ addr ^= 2;
135
+ }
136
+ }
137
+
138
+ return addr;
139
+}
140
+
141
void arm_debug_excp_handler(CPUState *cs)
142
{
143
/* Called by core code when a watchpoint or breakpoint fires;
144
--
148
--
145
2.7.4
149
2.20.1
146
150
147
151
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/13] stellaris: Use the 'unimplemented' device for parts we don't implement
[PULL 09/16] hw/arm/armsse: Correct expansion MPC interrupt lines
1
Use the 'unimplemented' dummy device to cover regions of the
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
SoC device memory map which we don't have proper device
3
implementations for yet.
4
2
3
We can use one MPC per SRAM bank, but we currently only wire the
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org
8
---
11
---
9
hw/arm/stellaris.c | 14 ++++++++++++++
12
hw/arm/armsse.c | 3 ++-
10
1 file changed, 14 insertions(+)
13
1 file changed, 2 insertions(+), 1 deletion(-)
11
14
12
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/stellaris.c
17
--- a/hw/arm/armsse.c
15
+++ b/hw/arm/stellaris.c
18
+++ b/hw/arm/armsse.c
16
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
17
#include "exec/address-spaces.h"
20
qdev_get_gpio_in(dev_splitter, 0));
18
#include "sysemu/sysemu.h"
21
qdev_connect_gpio_out(dev_splitter, 0,
19
#include "hw/char/pl011.h"
22
qdev_get_gpio_in_named(dev_secctl,
20
+#include "hw/misc/unimp.h"
23
- "mpc_status", 0));
21
24
+ "mpc_status",
22
#define GPIO_A 0
25
+ i - IOTS_NUM_EXP_MPC));
23
#define GPIO_B 1
24
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
25
}
26
}
26
}
27
}
27
28
+
28
qdev_connect_gpio_out(dev_splitter, 1,
29
+ /* Add dummy regions for the devices we don't implement yet,
30
+ * so guest accesses don't cause unlogged crashes.
31
+ */
32
+ create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
33
+ create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
34
+ create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
35
+ create_unimplemented_device("PWM", 0x40028000, 0x1000);
36
+ create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
37
+ create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
38
+ create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
39
+ create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
40
+ create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
41
}
42
43
/* FIXME: Figure out how to generate these from stellaris_boards. */
44
--
29
--
45
2.7.4
30
2.20.1
46
31
47
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/13] integratorcp: adding vmstate for save/restore
[PULL 10/16] hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
1
From: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
VMState added by this patch preserves correct
3
The system configuration controller (SYSCFG) doesn't have
4
loading of the integratorcp device state.
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
Remove the invalid code.
5
6
6
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
7
Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
[PMM: removed unnecessary minimum_version_id_old lines]
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
hw/arm/integratorcp.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
13
1 file changed, 59 insertions(+)
14
hw/arm/stm32f205_soc.c | 1 -
15
hw/misc/stm32f2xx_syscfg.c | 2 --
16
3 files changed, 5 deletions(-)
14
17
15
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/integratorcp.c
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
18
+++ b/hw/arm/integratorcp.c
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
19
@@ -XXX,XX +XXX,XX @@ static uint8_t integrator_spd[128] = {
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
20
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
23
uint32_t syscfg_exticr3;
24
uint32_t syscfg_exticr4;
25
uint32_t syscfg_cmpcr;
26
-
27
- qemu_irq irq;
21
};
28
};
22
29
23
+static const VMStateDescription vmstate_integratorcm = {
30
#endif /* HW_STM32F2XX_SYSCFG_H */
24
+ .name = "integratorcm",
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
25
+ .version_id = 1,
32
index XXXXXXX..XXXXXXX 100644
26
+ .minimum_version_id = 1,
33
--- a/hw/arm/stm32f205_soc.c
27
+ .fields = (VMStateField[]) {
34
+++ b/hw/arm/stm32f205_soc.c
28
+ VMSTATE_UINT32(cm_osc, IntegratorCMState),
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
29
+ VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
36
}
30
+ VMSTATE_UINT32(cm_lock, IntegratorCMState),
37
busdev = SYS_BUS_DEVICE(dev);
31
+ VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
38
sysbus_mmio_map(busdev, 0, 0x40013800);
32
+ VMSTATE_UINT32(cm_sdram, IntegratorCMState),
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
33
+ VMSTATE_UINT32(cm_init, IntegratorCMState),
40
34
+ VMSTATE_UINT32(cm_flags, IntegratorCMState),
41
/* Attach UART (uses USART registers) and USART controllers */
35
+ VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
42
for (i = 0; i < STM_NUM_USARTS; i++) {
36
+ VMSTATE_UINT32(int_level, IntegratorCMState),
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
37
+ VMSTATE_UINT32(irq_enabled, IntegratorCMState),
44
index XXXXXXX..XXXXXXX 100644
38
+ VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
45
--- a/hw/misc/stm32f2xx_syscfg.c
39
+ VMSTATE_END_OF_LIST()
46
+++ b/hw/misc/stm32f2xx_syscfg.c
40
+ }
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
41
+};
42
+
43
static uint64_t integratorcm_read(void *opaque, hwaddr offset,
44
unsigned size)
45
{
48
{
46
@@ -XXX,XX +XXX,XX @@ typedef struct icp_pic_state {
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
47
qemu_irq parent_fiq;
50
48
} icp_pic_state;
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
49
52
-
50
+static const VMStateDescription vmstate_icp_pic = {
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
51
+ .name = "icp_pic",
54
TYPE_STM32F2XX_SYSCFG, 0x400);
52
+ .version_id = 1,
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
53
+ .minimum_version_id = 1,
54
+ .fields = (VMStateField[]) {
55
+ VMSTATE_UINT32(level, icp_pic_state),
56
+ VMSTATE_UINT32(irq_enabled, icp_pic_state),
57
+ VMSTATE_UINT32(fiq_enabled, icp_pic_state),
58
+ VMSTATE_END_OF_LIST()
59
+ }
60
+};
61
+
62
static void icp_pic_update(icp_pic_state *s)
63
{
64
uint32_t flags;
65
@@ -XXX,XX +XXX,XX @@ typedef struct ICPCtrlRegsState {
66
#define ICP_INTREG_WPROT (1 << 0)
67
#define ICP_INTREG_CARDIN (1 << 3)
68
69
+static const VMStateDescription vmstate_icp_control = {
70
+ .name = "icp_control",
71
+ .version_id = 1,
72
+ .minimum_version_id = 1,
73
+ .fields = (VMStateField[]) {
74
+ VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
75
+ VMSTATE_END_OF_LIST()
76
+ }
77
+};
78
+
79
static uint64_t icp_control_read(void *opaque, hwaddr offset,
80
unsigned size)
81
{
82
@@ -XXX,XX +XXX,XX @@ static void core_class_init(ObjectClass *klass, void *data)
83
84
dc->props = core_properties;
85
dc->realize = integratorcm_realize;
86
+ dc->vmsd = &vmstate_integratorcm;
87
+}
88
+
89
+static void icp_pic_class_init(ObjectClass *klass, void *data)
90
+{
91
+ DeviceClass *dc = DEVICE_CLASS(klass);
92
+
93
+ dc->vmsd = &vmstate_icp_pic;
94
+}
95
+
96
+static void icp_control_class_init(ObjectClass *klass, void *data)
97
+{
98
+ DeviceClass *dc = DEVICE_CLASS(klass);
99
+
100
+ dc->vmsd = &vmstate_icp_control;
101
}
102
103
static const TypeInfo core_info = {
104
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_pic_info = {
105
.parent = TYPE_SYS_BUS_DEVICE,
106
.instance_size = sizeof(icp_pic_state),
107
.instance_init = icp_pic_init,
108
+ .class_init = icp_pic_class_init,
109
};
110
111
static const TypeInfo icp_ctrl_regs_info = {
112
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_ctrl_regs_info = {
113
.parent = TYPE_SYS_BUS_DEVICE,
114
.instance_size = sizeof(ICPCtrlRegsState),
115
.instance_init = icp_control_init,
116
+ .class_init = icp_control_class_init,
117
};
118
119
static void integratorcp_register_types(void)
120
--
56
--
121
2.7.4
57
2.20.1
122
58
123
59
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/13] aspeed: add a watchdog controller
[PULL 11/16] hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This enables reboot of a guest from U-Boot and Linux.
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
4
OMAP2 chip support") takes care of creating the 3 UARTs.
4
5
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
6
Reviewed-by: Joel Stanley <joel@jms.id.au>
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
7
Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
21
---
10
include/hw/arm/aspeed_soc.h | 2 ++
22
hw/arm/nseries.c | 11 -----------
11
hw/arm/aspeed_soc.c | 13 +++++++++++++
23
1 file changed, 11 deletions(-)
12
2 files changed, 15 insertions(+)
13
24
14
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/arm/aspeed_soc.h
27
--- a/hw/arm/nseries.c
17
+++ b/include/hw/arm/aspeed_soc.h
28
+++ b/hw/arm/nseries.c
18
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
19
#include "hw/timer/aspeed_timer.h"
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
20
#include "hw/i2c/aspeed_i2c.h"
21
#include "hw/ssi/aspeed_smc.h"
22
+#include "hw/watchdog/wdt_aspeed.h"
23
24
#define ASPEED_SPIS_NUM 2
25
26
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
27
AspeedSMCState fmc;
28
AspeedSMCState spi[ASPEED_SPIS_NUM];
29
AspeedSDMCState sdmc;
30
+ AspeedWDTState wdt;
31
} AspeedSoCState;
32
33
#define TYPE_ASPEED_SOC "aspeed-soc"
34
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/aspeed_soc.c
37
+++ b/hw/arm/aspeed_soc.c
38
@@ -XXX,XX +XXX,XX @@
39
#define ASPEED_SOC_SCU_BASE 0x1E6E2000
40
#define ASPEED_SOC_SRAM_BASE 0x1E720000
41
#define ASPEED_SOC_TIMER_BASE 0x1E782000
42
+#define ASPEED_SOC_WDT_BASE 0x1E785000
43
#define ASPEED_SOC_I2C_BASE 0x1E78A000
44
45
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
46
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
47
sc->info->silicon_rev);
48
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
49
"ram-size", &error_abort);
50
+
51
+ object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
52
+ object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
53
+ qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
54
}
31
}
55
32
56
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
33
-static void n8x0_uart_setup(struct n800_s *s)
57
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
34
-{
58
return;
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
36
- /*
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
38
- * here, but this code has been removed with the bluetooth backend.
39
- */
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
41
-}
42
-
43
static void n8x0_usb_setup(struct n800_s *s)
44
{
45
SysBusDevice *dev;
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
47
n8x0_spi_setup(s);
48
n8x0_dss_setup(s);
49
n8x0_cbus_setup(s);
50
- n8x0_uart_setup(s);
51
if (machine_usb(machine)) {
52
n8x0_usb_setup(s);
59
}
53
}
60
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
61
+
62
+ /* Watch dog */
63
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
64
+ if (err) {
65
+ error_propagate(errp, err);
66
+ return;
67
+ }
68
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
69
}
70
71
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
72
--
54
--
73
2.7.4
55
2.20.1
74
56
75
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/13] Fix Thumb-1 BE32 execution and disassembly.
[PULL 12/16] hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
1
From: Julian Brown <julian@codesourcery.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Thumb-1 code has some issues in BE32 mode (as currently implemented). In
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
short, since bytes are swapped within words at load time for BE32
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
executables, this also swaps pairs of adjacent Thumb-1 instructions.
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
6
9
7
This patch un-swaps those pairs of instructions again, both for execution,
10
This kind of wiring needs an explicitly created OR gate; add one.
8
and for disassembly. (The previous version of the patch always read four
9
bytes in arm_read_memory_func and then extracted the proper two bytes,
10
in a probably misguided attempt to match the behaviour of actual hardware
11
as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for
12
instruction fetches". It's less complicated to just read the correct
13
two bytes though.)
14
11
15
Signed-off-by: Julian Brown <julian@codesourcery.com>
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
17
---
20
include/disas/bfd.h | 7 +++++++
18
hw/arm/musicpal.c | 17 +++++++++++++----
21
target/arm/arm_ldst.h | 10 +++++++++-
19
hw/arm/Kconfig | 1 +
22
disas.c | 1 +
20
2 files changed, 14 insertions(+), 4 deletions(-)
23
target/arm/cpu.c | 23 +++++++++++++++++++++++
24
4 files changed, 40 insertions(+), 1 deletion(-)
25
21
26
diff --git a/include/disas/bfd.h b/include/disas/bfd.h
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
27
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
28
--- a/include/disas/bfd.h
24
--- a/hw/arm/musicpal.c
29
+++ b/include/disas/bfd.h
25
+++ b/hw/arm/musicpal.c
30
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
26
@@ -XXX,XX +XXX,XX @@
31
The bottom 16 bits are for the internal use of the disassembler. */
27
#include "ui/console.h"
32
unsigned long flags;
28
#include "hw/i2c/i2c.h"
33
#define INSN_HAS_RELOC    0x80000000
29
#include "hw/irq.h"
34
+#define INSN_ARM_BE32    0x00010000
30
+#include "hw/or-irq.h"
35
PTR private_data;
31
#include "hw/audio/wm8750.h"
36
32
#include "sysemu/block-backend.h"
37
/* Function used to get bytes to disassemble. MEMADDR is the
33
#include "sysemu/runstate.h"
38
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
34
@@ -XXX,XX +XXX,XX @@
39
(bfd_vma memaddr, bfd_byte *myaddr, int length,
35
#define MP_TIMER4_IRQ 7
40
     struct disassemble_info *info);
36
#define MP_EHCI_IRQ 8
41
37
#define MP_ETH_IRQ 9
42
+ /* A place to stash the real read_memory_func if read_memory_func wants to
38
-#define MP_UART1_IRQ 11
43
+ do some funky address arithmetic or similar (e.g. for ARM BE32 mode). */
39
-#define MP_UART2_IRQ 11
44
+ int (*read_memory_inner_func)
40
+#define MP_UART_SHARED_IRQ 11
45
+ (bfd_vma memaddr, bfd_byte *myaddr, int length,
41
#define MP_GPIO_IRQ 12
46
+ struct disassemble_info *info);
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
47
+
62
+
48
/* Function which should be called if we get an error that we can't
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
49
recover from. STATUS is the errno value from read_memory_func and
64
+ qdev_get_gpio_in(uart_orgate, 0),
50
MEMADDR is the address that we were trying to read. INFO is a
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
51
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
68
+ qdev_get_gpio_in(uart_orgate, 1),
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
70
71
/* Register flash */
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
52
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/arm_ldst.h
74
--- a/hw/arm/Kconfig
54
+++ b/target/arm/arm_ldst.h
75
+++ b/hw/arm/Kconfig
55
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
56
static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
77
57
bool sctlr_b)
78
config MUSICPAL
58
{
79
bool
59
- uint16_t insn = cpu_lduw_code(env, addr);
80
+ select OR_IRQ
60
+ uint16_t insn;
81
select BITBANG_I2C
61
+#ifndef CONFIG_USER_ONLY
82
select MARVELL_88W8618
62
+ /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
83
select PTIMER
63
+ within each word. Undo that now. */
64
+ if (sctlr_b) {
65
+ addr ^= 2;
66
+ }
67
+#endif
68
+ insn = cpu_lduw_code(env, addr);
69
if (bswap_code(sctlr_b)) {
70
return bswap16(insn);
71
}
72
diff --git a/disas.c b/disas.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/disas.c
75
+++ b/disas.c
76
@@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
77
78
s.cpu = cpu;
79
s.info.read_memory_func = target_read_memory;
80
+ s.info.read_memory_inner_func = NULL;
81
s.info.buffer_vma = code;
82
s.info.buffer_length = size;
83
s.info.print_address_func = generic_print_address;
84
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/arm/cpu.c
87
+++ b/target/arm/cpu.c
88
@@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
89
return print_insn_arm(pc | 1, info);
90
}
91
92
+static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
93
+ int length, struct disassemble_info *info)
94
+{
95
+ assert(info->read_memory_inner_func);
96
+ assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
97
+
98
+ if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
99
+ assert(info->endian == BFD_ENDIAN_LITTLE);
100
+ return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
101
+ info);
102
+ } else {
103
+ return info->read_memory_inner_func(memaddr, b, length, info);
104
+ }
105
+}
106
+
107
static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
108
{
109
ARMCPU *ac = ARM_CPU(cpu);
110
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
111
info->endian = BFD_ENDIAN_BIG;
112
#endif
113
}
114
+ if (info->read_memory_inner_func == NULL) {
115
+ info->read_memory_inner_func = info->read_memory_func;
116
+ info->read_memory_func = arm_read_memory_func;
117
+ }
118
+ info->flags &= ~INSN_ARM_BE32;
119
+ if (arm_sctlr_b(env)) {
120
+ info->flags |= INSN_ARM_BE32;
121
+ }
122
}
123
124
static void arm_cpu_initfn(Object *obj)
125
--
84
--
126
2.7.4
85
2.20.1
127
86
128
87
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/13] hw/arm/integratorcp: Support specifying features via -cpu
[PULL 13/16] hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
1
From: Julian Brown <julian@codesourcery.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Since the integratorcp board creates the CPU object directly
3
We don't need to fill the full pic[] array if we only use
4
rather than via cpu_arm_init(), we have to call the CPU
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
class parse_features() method ourselves if we want to
5
when necessary.
6
support the user passing features via the -cpu command
7
line argument as well as just the cpu name. Do so.
8
6
9
Signed-off-by: Julian Brown <julian@codesourcery.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
[PMM: split out into its own patch]
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
hw/arm/integratorcp.c | 19 +++++++++++++++++--
12
hw/arm/musicpal.c | 25 +++++++++++++------------
15
1 file changed, 17 insertions(+), 2 deletions(-)
13
1 file changed, 13 insertions(+), 12 deletions(-)
16
14
17
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/integratorcp.c
17
--- a/hw/arm/musicpal.c
20
+++ b/hw/arm/integratorcp.c
18
+++ b/hw/arm/musicpal.c
21
@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
22
const char *kernel_filename = machine->kernel_filename;
20
static void musicpal_init(MachineState *machine)
23
const char *kernel_cmdline = machine->kernel_cmdline;
21
{
24
const char *initrd_filename = machine->initrd_filename;
25
+ char **cpustr;
26
ObjectClass *cpu_oc;
27
+ CPUClass *cc;
28
Object *cpuobj;
29
ARMCPU *cpu;
22
ARMCPU *cpu;
30
+ const char *typename;
23
- qemu_irq pic[32];
31
MemoryRegion *address_space_mem = get_system_memory();
24
DeviceState *dev;
32
MemoryRegion *ram = g_new(MemoryRegion, 1);
25
+ DeviceState *pic;
33
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
26
DeviceState *uart_orgate;
34
qemu_irq pic[32];
27
DeviceState *i2c_dev;
35
DeviceState *dev, *sic, *icp;
28
DeviceState *lcd_dev;
36
int i;
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
37
+ Error *err = NULL;
30
&error_fatal);
38
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
39
if (!cpu_model) {
32
40
cpu_model = "arm926";
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
41
}
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
42
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
43
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
36
- for (i = 0; i < 32; i++) {
44
+ cpustr = g_strsplit(cpu_model, ",", 2);
37
- pic[i] = qdev_get_gpio_in(dev, i);
45
+
38
- }
46
+ cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
47
if (!cpu_oc) {
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
48
fprintf(stderr, "Unable to find CPU definition\n");
41
- pic[MP_TIMER4_IRQ], NULL);
49
exit(1);
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
50
}
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
51
+ typename = object_class_get_name(cpu_oc);
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
52
+
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
53
+ cc = CPU_CLASS(cpu_oc);
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
54
+ cc->parse_features(typename, cpustr[1], &err);
47
55
+ g_strfreev(cpustr);
48
/* Logically OR both UART IRQs together */
56
+ if (err) {
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
57
+ error_report_err(err);
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
58
+ exit(1);
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
59
+ }
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
60
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
61
- cpuobj = object_new(object_class_get_name(cpu_oc));
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
62
+ cpuobj = object_new(typename);
55
63
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
64
/* By default ARM1176 CPUs have EL3 enabled. This board does not
57
qdev_get_gpio_in(uart_orgate, 0),
65
* currently support EL3 so the CPU EL3 property is disabled before
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
59
OBJECT(get_system_memory()), &error_fatal);
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
65
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
67
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
69
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
71
- pic[MP_GPIO_IRQ]);
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
75
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
77
NULL);
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
66
--
85
--
67
2.7.4
86
2.20.1
68
87
69
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/13] stellaris: Document memory map and which SoC devices are unimplemented
[PULL 14/16] hw/arm/nseries: Check return value from load_image_targphys()
1
Add a comment documenting the memory map of the SoC devices and which
1
The nseries machines have a codepath that allows them to load a
2
are not implemented.
2
secondary bootloader. This code wasn't checking that the
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
3
5
6
While we're in the vicinity, fix the comment style of the
7
comment documenting what this image load is doing.
8
9
Fixes: Coverity CID 1192904
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
6
---
13
---
7
hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++
14
hw/arm/nseries.c | 15 +++++++++++----
8
1 file changed, 34 insertions(+)
15
1 file changed, 11 insertions(+), 4 deletions(-)
9
16
10
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/stellaris.c
19
--- a/hw/arm/nseries.c
13
+++ b/hw/arm/stellaris.c
20
+++ b/hw/arm/nseries.c
14
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
15
0x40024000, 0x40025000, 0x40026000};
22
/* No, wait, better start at the ROM. */
16
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
17
24
18
+ /* Memory map of SoC devices, from
25
- /* This is intended for loading the `secondary.bin' program from
19
+ * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
26
+ /*
20
+ * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
27
+ * This is intended for loading the `secondary.bin' program from
21
+ *
28
* Nokia images (the NOLO bootloader). The entry point seems
22
+ * 40000000 wdtimer (unimplemented)
29
* to be at OMAP2_Q2_BASE + 0x400000.
23
+ * 40002000 i2c (unimplemented)
30
*
24
+ * 40004000 GPIO
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
25
+ * 40005000 GPIO
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
26
+ * 40006000 GPIO
33
*
27
+ * 40007000 GPIO
34
* The code above is for loading the `zImage' file from Nokia
28
+ * 40008000 SSI
35
- * images. */
29
+ * 4000c000 UART
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
30
+ * 4000d000 UART
37
- machine->ram_size - 0x400000);
31
+ * 4000e000 UART
38
+ * images.
32
+ * 40020000 i2c
39
+ */
33
+ * 40021000 i2c (unimplemented)
40
+ if (load_image_targphys(option_rom[0].name,
34
+ * 40024000 GPIO
41
+ OMAP2_Q2_BASE + 0x400000,
35
+ * 40025000 GPIO
42
+ machine->ram_size - 0x400000) < 0) {
36
+ * 40026000 GPIO
43
+ error_report("Failed to load secondary bootloader %s",
37
+ * 40028000 PWM (unimplemented)
44
+ option_rom[0].name);
38
+ * 4002c000 QEI (unimplemented)
45
+ exit(EXIT_FAILURE);
39
+ * 4002d000 QEI (unimplemented)
46
+ }
40
+ * 40030000 gptimer
47
41
+ * 40031000 gptimer
48
n800_setup_nolo_tags(nolo_tags);
42
+ * 40032000 gptimer
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
43
+ * 40033000 gptimer
44
+ * 40038000 ADC
45
+ * 4003c000 analogue comparator (unimplemented)
46
+ * 40048000 ethernet
47
+ * 400fc000 hibernation module (unimplemented)
48
+ * 400fd000 flash memory control (unimplemented)
49
+ * 400fe000 system control
50
+ */
51
+
52
DeviceState *gpio_dev[7], *nvic;
53
qemu_irq gpio_in[7][8];
54
qemu_irq gpio_out[7][8];
55
--
50
--
56
2.7.4
51
2.20.1
57
52
58
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/13] sd: sdhci: check data length during dma_memory_read
[PULL 15/16] tests/qtest/npcm7xx_rng-test: count runs properly
1
From: Prasad J Pandit <pjp@fedoraproject.org>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
While doing multi block SDMA transfer in routine
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
4
'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting
4
plus one. Currently, it's counting the number of times these transitions
5
index 'begin' and data length 's->data_count' could end up to be same.
5
do _not_ happen, plus one.
6
This could lead to an OOB access issue. Correct transfer data length
7
to avoid it.
8
6
9
Cc: qemu-stable@nongnu.org
7
Source:
10
Reported-by: Jiang Xin <jiangxin1@huawei.com>
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
11
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20170130064736.9236-1-ppandit@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
15
---
16
hw/sd/sdhci.c | 2 +-
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
18
19
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/sd/sdhci.c
21
--- a/tests/qtest/npcm7xx_rng-test.c
22
+++ b/hw/sd/sdhci.c
22
+++ b/tests/qtest/npcm7xx_rng-test.c
23
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
24
boundary_count -= block_size - begin;
24
pi = (double)nr_ones / nr_bits;
25
}
25
26
dma_memory_read(&address_space_memory, s->sdmasysad,
26
for (k = 0; k < nr_bits - 1; k++) {
27
- &s->fifo_buffer[begin], s->data_count);
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
28
+ &s->fifo_buffer[begin], s->data_count - begin);
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
29
s->sdmasysad += s->data_count - begin;
29
}
30
if (s->data_count == block_size) {
30
vn_obs += 1;
31
for (n = 0; n < block_size; n++) {
31
32
--
32
--
33
2.7.4
33
2.20.1
34
34
35
35
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/13] hw/misc: New "unimplemented" sysbus device
[PULL 16/16] target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
1
Create a new "unimplemented" sysbus device, which simply accepts
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
2
all read and write accesses, and implements them as read-as-zero,
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
write-ignored, with logging of the access as LOG_UNIMP.
3
trans function up above the access check.
4
5
This is useful for stubbing out bits of an SoC or board model
6
which haven't been written yet.
7
4
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
11
---
8
---
12
hw/misc/Makefile.objs | 2 +
9
target/arm/translate-neon.c.inc | 8 ++++----
13
include/hw/misc/unimp.h | 39 ++++++++++++++++++
10
1 file changed, 4 insertions(+), 4 deletions(-)
14
hw/misc/unimp.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
15
3 files changed, 148 insertions(+)
16
create mode 100644 include/hw/misc/unimp.h
17
create mode 100644 hw/misc/unimp.c
18
11
19
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/Makefile.objs
14
--- a/target/arm/translate-neon.c.inc
22
+++ b/hw/misc/Makefile.objs
15
+++ b/target/arm/translate-neon.c.inc
23
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
24
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
17
return false;
25
common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
18
}
26
19
27
+common-obj-y += unimp.o
20
- if (!vfp_access_check(s)) {
28
+
21
- return true;
29
obj-$(CONFIG_VMPORT) += vmport.o
22
- }
30
23
-
31
# ARM devices
24
if ((a->vn + a->len + 1) > 32) {
32
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
25
/*
33
new file mode 100644
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
34
index XXXXXXX..XXXXXXX
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
35
--- /dev/null
28
return false;
36
+++ b/include/hw/misc/unimp.h
29
}
37
@@ -XXX,XX +XXX,XX @@
30
38
+/*
31
+ if (!vfp_access_check(s)) {
39
+ * "Unimplemented" device
32
+ return true;
40
+ *
41
+ * Copyright Linaro Limited, 2017
42
+ * Written by Peter Maydell
43
+ */
44
+
45
+#ifndef HW_MISC_UNIMP_H
46
+#define HW_MISC_UNIMP_H
47
+
48
+#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
49
+
50
+/**
51
+ * create_unimplemented_device: create and map a dummy device
52
+ * @name: name of the device for debug logging
53
+ * @base: base address of the device's MMIO region
54
+ * @size: size of the device's MMIO region
55
+ *
56
+ * This utility function creates and maps an instance of unimplemented-device,
57
+ * which is a dummy device which simply logs all guest accesses to
58
+ * it via the qemu_log LOG_UNIMP debug log.
59
+ * The device is mapped at priority -1000, which means that you can
60
+ * use it to cover a large region and then map other devices on top of it
61
+ * if necessary.
62
+ */
63
+static inline void create_unimplemented_device(const char *name,
64
+ hwaddr base,
65
+ hwaddr size)
66
+{
67
+ DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
68
+
69
+ qdev_prop_set_string(dev, "name", name);
70
+ qdev_prop_set_uint64(dev, "size", size);
71
+ qdev_init_nofail(dev);
72
+
73
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
74
+}
75
+
76
+#endif
77
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/hw/misc/unimp.c
82
@@ -XXX,XX +XXX,XX @@
83
+/* "Unimplemented" device
84
+ *
85
+ * This is a dummy device which accepts and logs all accesses.
86
+ * It's useful for stubbing out regions of an SoC or board
87
+ * map which correspond to devices that have not yet been
88
+ * implemented. This is often sufficient to placate initial
89
+ * guest device driver probing such that the system will
90
+ * come up.
91
+ *
92
+ * Copyright Linaro Limited, 2017
93
+ * Written by Peter Maydell
94
+ */
95
+
96
+#include "qemu/osdep.h"
97
+#include "hw/hw.h"
98
+#include "hw/sysbus.h"
99
+#include "hw/misc/unimp.h"
100
+#include "qemu/log.h"
101
+#include "qapi/error.h"
102
+
103
+#define UNIMPLEMENTED_DEVICE(obj) \
104
+ OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)
105
+
106
+typedef struct {
107
+ SysBusDevice parent_obj;
108
+ MemoryRegion iomem;
109
+ char *name;
110
+ uint64_t size;
111
+} UnimplementedDeviceState;
112
+
113
+static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
114
+{
115
+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
116
+
117
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
118
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
119
+ s->name, size, offset);
120
+ return 0;
121
+}
122
+
123
+static void unimp_write(void *opaque, hwaddr offset,
124
+ uint64_t value, unsigned size)
125
+{
126
+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
127
+
128
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
129
+ "(size %d, value 0x%" PRIx64
130
+ ", offset 0x%" HWADDR_PRIx ")\n",
131
+ s->name, size, value, offset);
132
+}
133
+
134
+static const MemoryRegionOps unimp_ops = {
135
+ .read = unimp_read,
136
+ .write = unimp_write,
137
+ .impl.min_access_size = 1,
138
+ .impl.max_access_size = 8,
139
+ .valid.min_access_size = 1,
140
+ .valid.max_access_size = 8,
141
+ .endianness = DEVICE_NATIVE_ENDIAN,
142
+};
143
+
144
+static void unimp_realize(DeviceState *dev, Error **errp)
145
+{
146
+ UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);
147
+
148
+ if (s->size == 0) {
149
+ error_setg(errp, "property 'size' not specified or zero");
150
+ return;
151
+ }
33
+ }
152
+
34
+
153
+ if (s->name == NULL) {
35
desc = tcg_const_i32((a->vn << 2) | a->len);
154
+ error_setg(errp, "property 'name' not specified");
36
def = tcg_temp_new_i64();
155
+ return;
37
if (a->op) {
156
+ }
157
+
158
+ memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
159
+ s->name, s->size);
160
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
161
+}
162
+
163
+static Property unimp_properties[] = {
164
+ DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),
165
+ DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),
166
+ DEFINE_PROP_END_OF_LIST(),
167
+};
168
+
169
+static void unimp_class_init(ObjectClass *klass, void *data)
170
+{
171
+ DeviceClass *dc = DEVICE_CLASS(klass);
172
+
173
+ dc->realize = unimp_realize;
174
+ dc->props = unimp_properties;
175
+}
176
+
177
+static const TypeInfo unimp_info = {
178
+ .name = TYPE_UNIMPLEMENTED_DEVICE,
179
+ .parent = TYPE_SYS_BUS_DEVICE,
180
+ .instance_size = sizeof(UnimplementedDeviceState),
181
+ .class_init = unimp_class_init,
182
+};
183
+
184
+static void unimp_register_types(void)
185
+{
186
+ type_register_static(&unimp_info);
187
+}
188
+
189
+type_init(unimp_register_types)
190
--
38
--
191
2.7.4
39
2.20.1
192
40
193
41
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.