Series comparison

-[Qemu-devel] [PULL 00/13] target-arm queue
+[Qemu-devel] [PULL 00/12] target-arm queue
-A random mix of items here, nothing very major.
+Not very much here, but several people have fallen over
 the vector operation segfault bug, so let's get the fix
 into master.
 thanks
 -- PMM
+The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
-The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:
+  Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
-  Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)
+are available in the Git repository at:
-are available in the git repository at:
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207
+for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
-for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:
+  hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
   stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)
 ----------------------------------------------------------------
-target-arm:
+target-arm queue:
- * new "unimplemented" device for stubbing out devices in a
+ * exynos4210: QOM'ify the Exynos4210 SoC
-   system model so accesses can be logged
+ * exynos4210: Add DMA support for the Exynos4210
- * stellaris: document the SoC memory map
+ * arm_gicv3: Fix writes to ICC_CTLR_EL3
- * arm: create instruction syndromes for AArch32 data aborts
+ * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
- * arm: Correctly handle watchpoints for BE32 CPUs
+ * target/arm: Fix vector operation segfault
- * Fix Thumb-1 BE32 execution and disassembly
+ * target/arm: Minor improvements to BFXIL, EXTR
  * arm: Add cfgend parameter for ARM CPU selection
  * sd: sdhci: check data length during dma_memory_read
  * aspeed: add a watchdog controller
  * integratorcp: adding vmstate for save/restore
 ----------------------------------------------------------------
-Cédric Le Goater (2):
+Alistair Francis (1):
-      wdt: Add Aspeed watchdog device model
+      target/arm: Fix vector operation segfault
       aspeed: add a watchdog controller
-Julian Brown (4):
+Guenter Roeck (1):
-      hw/arm/integratorcp: Support specifying features via -cpu
+      hw/arm/exynos4210: Add DMA support for the Exynos4210
       target/arm: Add cfgend parameter for ARM CPU selection.
       Fix Thumb-1 BE32 execution and disassembly.
       arm: Correctly handle watchpoints for BE32 CPUs
 Pavel Dovgalyuk (1):
       integratorcp: adding vmstate for save/restore
 Peter Maydell (5):
-      target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
+      arm: Move system_clock_scale to armv7m_systick.h
-      target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
+      arm: Remove unnecessary includes of hw/arm/arm.h
-      stellaris: Document memory map and which SoC devices are unimplemented
+      arm: Rename hw/arm/arm.h to hw/arm/boot.h
-      hw/misc: New "unimplemented" sysbus device
+      hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
-      stellaris: Use the 'unimplemented' device for parts we don't implement
+      hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
-Prasad J Pandit (1):
+Philippe Mathieu-Daudé (3):
-      sd: sdhci: check data length during dma_memory_read
+      hw/arm/exynos4: Remove unuseful debug code
       hw/arm/exynos4: Use the IEC binary prefix definitions
       hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
- hw/misc/Makefile.objs            |   2 +
+Richard Henderson (2):
- hw/watchdog/Makefile.objs        |   1 +
+      target/arm: Use extract2 for EXTR
- include/disas/bfd.h              |   7 ++
+      target/arm: Simplify BFXIL expansion
  include/hw/arm/aspeed_soc.h      |   2 +
  include/hw/misc/unimp.h          |  39 +++++++
  include/hw/watchdog/wdt_aspeed.h |  32 ++++++
  include/qom/cpu.h                |   3 +
  target/arm/arm_ldst.h            |  10 +-
  target/arm/cpu.h                 |   7 ++
  target/arm/internals.h           |   5 +
  target/arm/translate.h           |  14 +++
  disas.c                          |   1 +
  exec.c                           |   1 +
  hw/arm/aspeed_soc.c              |  13 +++
  hw/arm/integratorcp.c            |  78 +++++++++++++-
  hw/arm/stellaris.c               |  48 +++++++++
  hw/misc/unimp.c                  | 107 +++++++++++++++++++
  hw/sd/sdhci.c                    |   2 +-
  hw/watchdog/wdt_aspeed.c         | 225 +++++++++++++++++++++++++++++++++++++++
  qom/cpu.c                        |   6 ++
  target/arm/cpu.c                 |  39 +++++++
  target/arm/op_helper.c           |  22 ++++
  target/arm/translate-a64.c       |  14 ---
  target/arm/translate.c           | 193 ++++++++++++++++++++++++---------
 files changed, 801 insertions(+), 70 deletions(-)
  create mode 100644 include/hw/misc/unimp.h
  create mode 100644 include/hw/watchdog/wdt_aspeed.h
  create mode 100644 hw/misc/unimp.c
  create mode 100644 hw/watchdog/wdt_aspeed.c
+ include/hw/arm/allwinner-a10.h    |  2 +-
+ include/hw/arm/aspeed_soc.h       |  1 -
+ include/hw/arm/bcm2836.h          |  1 -
+ include/hw/arm/{arm.h => boot.h}  | 12 +++------
+ include/hw/arm/exynos4210.h       |  9 +++++--
+ include/hw/arm/fsl-imx25.h        |  2 +-
+ include/hw/arm/fsl-imx31.h        |  2 +-
+ include/hw/arm/fsl-imx6.h         |  2 +-
+ include/hw/arm/fsl-imx6ul.h       |  2 +-
+ include/hw/arm/fsl-imx7.h         |  2 +-
+ include/hw/arm/virt.h             |  2 +-
+ include/hw/arm/xlnx-versal.h      |  2 +-
+ include/hw/arm/xlnx-zynqmp.h      |  2 +-
+ include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
+ hw/arm/armsse.c                   |  2 +-
+ hw/arm/armv7m.c                   |  2 +-
+ hw/arm/aspeed.c                   |  2 +-
+ hw/arm/boot.c                     |  2 +-
+ hw/arm/collie.c                   |  2 +-
+ hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
+ hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
+ hw/arm/highbank.c                 |  2 +-
+ hw/arm/integratorcp.c             |  2 +-
+ hw/arm/mainstone.c                |  2 +-
+ hw/arm/microbit.c                 |  2 +-
+ hw/arm/mps2-tz.c                  |  2 +-
+ hw/arm/mps2.c                     |  2 +-
+ hw/arm/msf2-soc.c                 |  1 -
+ hw/arm/msf2-som.c                 |  2 +-
+ hw/arm/musca.c                    |  2 +-
+ hw/arm/musicpal.c                 |  2 +-
+ hw/arm/netduino2.c                |  2 +-
+ hw/arm/nrf51_soc.c                |  2 +-
+ hw/arm/nseries.c                  |  2 +-
+ hw/arm/omap1.c                    |  2 +-
+ hw/arm/omap2.c                    |  2 +-
+ hw/arm/omap_sx1.c                 |  2 +-
+ hw/arm/palm.c                     |  2 +-
+ hw/arm/raspi.c                    |  2 +-
+ hw/arm/realview.c                 |  2 +-
+ hw/arm/spitz.c                    |  2 +-
+ hw/arm/stellaris.c                |  2 +-
+ hw/arm/stm32f205_soc.c            |  2 +-
+ hw/arm/strongarm.c                |  2 +-
+ hw/arm/tosa.c                     |  2 +-
+ hw/arm/versatilepb.c              |  2 +-
+ hw/arm/vexpress.c                 |  2 +-
+ hw/arm/virt.c                     |  2 +-
+ hw/arm/xilinx_zynq.c              |  2 +-
+ hw/arm/xlnx-versal.c              |  2 +-
+ hw/arm/z2.c                       |  2 +-
+ hw/intc/arm_gicv3_cpuif.c         |  6 ++---
+ hw/intc/armv7m_nvic.c             |  1 -
+ target/arm/arm-semi.c             |  1 -
+ target/arm/cpu.c                  |  1 -
+ target/arm/cpu64.c                |  1 -
+ target/arm/kvm.c                  |  1 -
+ target/arm/kvm32.c                |  1 -
+ target/arm/kvm64.c                |  1 -
+ target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
+ target/arm/translate.c            |  4 +--
+files changed, 164 insertions(+), 123 deletions(-)
+ rename include/hw/arm/{arm.h => boot.h} (96%)

-[Qemu-devel] [PULL 10/13] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
+[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
-Add support for generating the ISS (Instruction Specific Syndrome)
+From: Richard Henderson <richard.henderson@linaro.org>
 for Data Abort exceptions taken from AArch32. These syndromes are
 used by hypervisors for example to trap and emulate memory accesses.
-This is the equivalent for AArch32 guests of the work done for AArch64
+This is, after all, how we implement extract2 in tcg/aarch64.
 guests in commit aaa1f954d4cab243.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 ---
- target/arm/translate.h     |  14 ++++
+ target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
- target/arm/translate-a64.c |  14 ----
+file changed, 20 insertions(+), 18 deletions(-)
  target/arm/translate.c     | 184 +++++++++++++++++++++++++++++++++------------
 files changed, 149 insertions(+), 63 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s)
-             ? 3 : MAX(1, s->current_el);
- }
-+static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
-+{
-+    /* We don't need to save all of the syndrome so we mask and shift
-+     * out unneeded bits to help the sleb128 encoder do a better job.
-+     */
-+    syn &= ARM_INSN_START_WORD2_MASK;
-+    syn >>= ARM_INSN_START_WORD2_SHIFT;
-+
-+    /* We check and clear insn_start_idx to catch multiple updates.  */
-+    assert(s->insn_start_idx != 0);
-+    tcg_set_insn_param(s->insn_start_idx, 2, syn);
-+    s->insn_start_idx = 0;
-+}
-+
- /* target-specific extra values for is_jmp */
- /* These instructions trap after executing, so the A32/T32 decoder must
-  * defer them until after the conditional execution state has been updated.
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
+@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
-     }
+             } else {
- }
+                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
+             }
--static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+-        } else if (rm == rn) { /* ROR */
--{
+-            tcg_rm = cpu_reg(s, rm);
--    /* We don't need to save all of the syndrome so we mask and shift
+-            if (sf) {
--     * out uneeded bits to help the sleb128 encoder do a better job.
+-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
--     */
+-            } else {
--    syn &= ARM_INSN_START_WORD2_MASK;
+-                TCGv_i32 tmp = tcg_temp_new_i32();
--    syn >>= ARM_INSN_START_WORD2_SHIFT;
+-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
--
+-                tcg_gen_rotri_i32(tmp, tmp, imm);
--    /* We check and clear insn_start_idx to catch multiple updates.  */
+-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
--    assert(s->insn_start_idx != 0);
+-                tcg_temp_free_i32(tmp);
--    tcg_set_insn_param(s->insn_start_idx, 2, syn);
+-            }
--    s->insn_start_idx = 0;
+         } else {
--}
+-            tcg_rm = read_cpu_reg(s, rm, sf);
--
+-            tcg_rn = read_cpu_reg(s, rn, sf);
- static void unallocated_encoding(DisasContext *s)
+-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
- {
+-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
-     /* Unallocated and reserved encodings are uncategorized */
+-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+-            if (!sf) {
-index XXXXXXX..XXXXXXX 100644
+-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
---- a/target/arm/translate.c
++            tcg_rm = cpu_reg(s, rm);
-+++ b/target/arm/translate.c
++            tcg_rn = cpu_reg(s, rn);
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
      a64_translate_init();
  }
 +/* Flags for the disas_set_da_iss info argument:
 + * lower bits hold the Rt register number, higher bits are flags.
 + */
 +typedef enum ISSInfo {
 +    ISSNone = 0,
 +    ISSRegMask = 0x1f,
 +    ISSInvalid = (1 << 5),
 +    ISSIsAcqRel = (1 << 6),
 +    ISSIsWrite = (1 << 7),
 +    ISSIs16Bit = (1 << 8),
 +} ISSInfo;
 +
-+/* Save the syndrome information for a Data Abort */
++            if (sf) {
-+static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
++                /* Specialization to ROR happens in EXTRACT2.  */
-+{
++                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
-+    uint32_t syn;
++            } else {
-+    int sas = memop & MO_SIZE;
++                TCGv_i32 t0 = tcg_temp_new_i32();
 +    bool sse = memop & MO_SIGN;
 +    bool is_acqrel = issinfo & ISSIsAcqRel;
 +    bool is_write = issinfo & ISSIsWrite;
 +    bool is_16bit = issinfo & ISSIs16Bit;
 +    int srt = issinfo & ISSRegMask;
 +
-+    if (issinfo & ISSInvalid) {
++                tcg_gen_extrl_i64_i32(t0, tcg_rm);
-+        /* Some callsites want to conditionally provide ISS info,
++                if (rm == rn) {
-+         * eg "only if this was not a writeback"
++                    tcg_gen_rotri_i32(t0, t0, imm);
-+         */
++                } else {
-+        return;
++                    TCGv_i32 t1 = tcg_temp_new_i32();
-+    }
++                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
-+
++                    tcg_gen_extract2_i32(t0, t0, t1, imm);
-+    if (srt == 15) {
++                    tcg_temp_free_i32(t1);
-+        /* For AArch32, insns where the src/dest is R15 never generate
++                }
-+         * ISS information. Catching that here saves checking at all
++                tcg_gen_extu_i32_i64(tcg_rd, t0);
-+         * the call sites.
++                tcg_temp_free_i32(t0);
 +         */
 +        return;
 +    }
 +
 +    syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,
 +                                  0, 0, 0, is_write, 0, is_16bit);
 +    disas_set_insn_syndrome(s, syn);
 +}
 +
  static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
  {
      /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val,      \
                                       TCGv_i32 a32, int index)            \
  {                                                                        \
      gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
 +}                                                                        \
 +static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s,              \
 +                                           TCGv_i32 val,                 \
 +                                           TCGv_i32 a32, int index,      \
 +                                           ISSInfo issinfo)              \
 +{                                                                        \
 +    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
 +    disas_set_da_iss(s, OPC, issinfo);                                   \
  }
  #define DO_GEN_ST(SUFF, OPC)                                             \
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val,      \
                                       TCGv_i32 a32, int index)            \
  {                                                                        \
      gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
 +}                                                                        \
 +static inline void gen_aa32_st##SUFF##_iss(DisasContext *s,              \
 +                                           TCGv_i32 val,                 \
 +                                           TCGv_i32 a32, int index,      \
 +                                           ISSInfo issinfo)              \
 +{                                                                        \
 +    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
 +    disas_set_da_iss(s, OPC, issinfo | ISSIsWrite);                      \
  }
  static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                  tmp = tcg_temp_new_i32();
                                  switch (op1) {
                                  case 0: /* lda */
 -                                    gen_aa32_ld32u(s, tmp, addr,
 -                                                   get_mem_index(s));
 +                                    gen_aa32_ld32u_iss(s, tmp, addr,
 +                                                       get_mem_index(s),
 +                                                       rd | ISSIsAcqRel);
                                      break;
                                  case 2: /* ldab */
 -                                    gen_aa32_ld8u(s, tmp, addr,
 -                                                  get_mem_index(s));
 +                                    gen_aa32_ld8u_iss(s, tmp, addr,
 +                                                      get_mem_index(s),
 +                                                      rd | ISSIsAcqRel);
                                      break;
                                  case 3: /* ldah */
 -                                    gen_aa32_ld16u(s, tmp, addr,
 -                                                   get_mem_index(s));
 +                                    gen_aa32_ld16u_iss(s, tmp, addr,
 +                                                       get_mem_index(s),
 +                                                       rd | ISSIsAcqRel);
                                      break;
                                  default:
                                      abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                  tmp = load_reg(s, rm);
                                  switch (op1) {
                                  case 0: /* stl */
 -                                    gen_aa32_st32(s, tmp, addr,
 -                                                  get_mem_index(s));
 +                                    gen_aa32_st32_iss(s, tmp, addr,
 +                                                      get_mem_index(s),
 +                                                      rm | ISSIsAcqRel);
                                      break;
                                  case 2: /* stlb */
 -                                    gen_aa32_st8(s, tmp, addr,
 -                                                 get_mem_index(s));
 +                                    gen_aa32_st8_iss(s, tmp, addr,
 +                                                     get_mem_index(s),
 +                                                     rm | ISSIsAcqRel);
                                      break;
                                  case 3: /* stlh */
 -                                    gen_aa32_st16(s, tmp, addr,
 -                                                  get_mem_index(s));
 +                                    gen_aa32_st16_iss(s, tmp, addr,
 +                                                      get_mem_index(s),
 +                                                      rm | ISSIsAcqRel);
                                      break;
                                  default:
                                      abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                  bool wbit = insn & (1 << 21);
                  bool pbit = insn & (1 << 24);
                  bool doubleword = false;
 +                ISSInfo issinfo;
 +
                  /* Misc load/store */
                  rn = (insn >> 16) & 0xf;
                  rd = (insn >> 12) & 0xf;
 +                /* ISS not valid if writeback */
 +                issinfo = (pbit & !wbit) ? rd : ISSInvalid;
 +
                  if (!load && (sh & 2)) {
                      /* doubleword */
                      ARCH(5TE);
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                      tmp = tcg_temp_new_i32();
                      switch (sh) {
                      case 1:
 -                        gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +                        gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
 +                                           issinfo);
                          break;
                      case 2:
 -                        gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
 +                        gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
 +                                          issinfo);
                          break;
                      default:
                      case 3:
 -                        gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
 +                        gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
 +                                           issinfo);
                          break;
                      }
                  } else {
                      /* store */
                      tmp = load_reg(s, rd);
 -                    gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +                    gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
                      tcg_temp_free_i32(tmp);
                  }
                  /* Perform base writeback before the loaded value to
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                  /* load */
                  tmp = tcg_temp_new_i32();
                  if (insn & (1 << 22)) {
 -                    gen_aa32_ld8u(s, tmp, tmp2, i);
 +                    gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
                  } else {
 -                    gen_aa32_ld32u(s, tmp, tmp2, i);
 +                    gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
                  }
              } else {
                  /* store */
                  tmp = load_reg(s, rd);
                  if (insn & (1 << 22)) {
 -                    gen_aa32_st8(s, tmp, tmp2, i);
 +                    gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
                  } else {
 -                    gen_aa32_st32(s, tmp, tmp2, i);
 +                    gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
                  }
                  tcg_temp_free_i32(tmp);
              }
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                          tmp = tcg_temp_new_i32();
                          switch (op) {
                          case 0: /* ldab */
 -                            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
 +                                              rs | ISSIsAcqRel);
                              break;
                          case 1: /* ldah */
 -                            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
 +                                               rs | ISSIsAcqRel);
                              break;
                          case 2: /* lda */
 -                            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
 +                                               rs | ISSIsAcqRel);
                              break;
                          default:
                              abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                          tmp = load_reg(s, rs);
                          switch (op) {
                          case 0: /* stlb */
 -                            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
 +                                             rs | ISSIsAcqRel);
                              break;
                          case 1: /* stlh */
 -                            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
 +                                              rs | ISSIsAcqRel);
                              break;
                          case 2: /* stl */
 -                            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 +                            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
 +                                              rs | ISSIsAcqRel);
                              break;
                          default:
                              abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
          int postinc = 0;
          int writeback = 0;
          int memidx;
 +        ISSInfo issinfo;
 +
          if ((insn & 0x01100000) == 0x01000000) {
              if (disas_neon_ls_insn(s, insn)) {
                  goto illegal_op;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                  }
              }
          }
-+
+     }
 +        issinfo = writeback ? ISSInvalid : rs;
 +
          if (insn & (1 << 20)) {
              /* Load.  */
              tmp = tcg_temp_new_i32();
              switch (op) {
              case 0:
 -                gen_aa32_ld8u(s, tmp, addr, memidx);
 +                gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 4:
 -                gen_aa32_ld8s(s, tmp, addr, memidx);
 +                gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 1:
 -                gen_aa32_ld16u(s, tmp, addr, memidx);
 +                gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 5:
 -                gen_aa32_ld16s(s, tmp, addr, memidx);
 +                gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 2:
 -                gen_aa32_ld32u(s, tmp, addr, memidx);
 +                gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
                  break;
              default:
                  tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
              tmp = load_reg(s, rs);
              switch (op) {
              case 0:
 -                gen_aa32_st8(s, tmp, addr, memidx);
 +                gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 1:
 -                gen_aa32_st16(s, tmp, addr, memidx);
 +                gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
                  break;
              case 2:
 -                gen_aa32_st32(s, tmp, addr, memidx);
 +                gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
                  break;
              default:
                  tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
              addr = tcg_temp_new_i32();
              tcg_gen_movi_i32(addr, val);
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
 +                               rd | ISSIs16Bit);
              tcg_temp_free_i32(addr);
              store_reg(s, rd, tmp);
              break;
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          switch (op) {
          case 0: /* str */
 -            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 1: /* strh */
 -            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 2: /* strb */
 -            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 3: /* ldrsb */
 -            gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 4: /* ldr */
 -            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 5: /* ldrh */
 -            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 6: /* ldrb */
 -            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          case 7: /* ldrsh */
 -            gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              break;
          }
          if (op >= 3) { /* load */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          if (insn & (1 << 11)) {
              /* load */
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              store_reg(s, rd, tmp);
          } else {
              /* store */
              tmp = load_reg(s, rd);
 -            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              tcg_temp_free_i32(tmp);
          }
          tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          if (insn & (1 << 11)) {
              /* load */
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              store_reg(s, rd, tmp);
          } else {
              /* store */
              tmp = load_reg(s, rd);
 -            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              tcg_temp_free_i32(tmp);
          }
          tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
          if (insn & (1 << 11)) {
              /* load */
              tmp = tcg_temp_new_i32();
 -            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              store_reg(s, rd, tmp);
          } else {
              /* store */
              tmp = load_reg(s, rd);
 -            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
 +            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
              tcg_temp_free_i32(tmp);
          }
          tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
          store_cpu_field(tmp, condexec_bits);
        }
      do {
 +        dc->insn_start_idx = tcg_op_buf_count();
          tcg_gen_insn_start(dc->pc,
                             (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
 );
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 05/13] hw/arm/integratorcp: Support specifying features via -cpu
+[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
-From: Julian Brown <julian@codesourcery.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Since the integratorcp board creates the CPU object directly
+The mask implied by the extract is redundant with the one
-rather than via cpu_arm_init(), we have to call the CPU
+implied by the deposit.  Also, fix spelling of BFXIL.
 class parse_features() method ourselves if we want to
 support the user passing features via the -cpu command
 line argument as well as just the cpu name. Do so.
-Signed-off-by: Julian Brown <julian@codesourcery.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-[PMM: split out into its own patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/integratorcp.c | 19 +++++++++++++++++--
+ target/arm/translate-a64.c | 6 +++---
-file changed, 17 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/integratorcp.c
+--- a/target/arm/translate-a64.c
-+++ b/hw/arm/integratorcp.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
-     const char *kernel_filename = machine->kernel_filename;
+             tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
-     const char *kernel_cmdline = machine->kernel_cmdline;
+             return;
-     const char *initrd_filename = machine->initrd_filename;
+         }
-+    char **cpustr;
+-        /* opc == 1, BXFIL fall through to deposit */
-     ObjectClass *cpu_oc;
+-        tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
-+    CPUClass *cc;
++        /* opc == 1, BFXIL fall through to deposit */
-     Object *cpuobj;
++        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
-     ARMCPU *cpu;
+         pos = 0;
-+    const char *typename;
+     } else {
-     MemoryRegion *address_space_mem = get_system_memory();
+         /* Handle the ri > si case with a deposit
-     MemoryRegion *ram = g_new(MemoryRegion, 1);
+@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
-     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
+         len = ri;
      qemu_irq pic[32];
      DeviceState *dev, *sic, *icp;
      int i;
 +    Error *err = NULL;
      if (!cpu_model) {
          cpu_model = "arm926";
      }
--    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
+-    if (opc == 1) { /* BFM, BXFIL */
-+    cpustr = g_strsplit(cpu_model, ",", 2);
++    if (opc == 1) { /* BFM, BFXIL */
-+
+         tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
-+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
+     } else {
-     if (!cpu_oc) {
+         /* SBFM or UBFM: We start with zero, and we haven't modified
          fprintf(stderr, "Unable to find CPU definition\n");
          exit(1);
      }
 +    typename = object_class_get_name(cpu_oc);
 +
 +    cc = CPU_CLASS(cpu_oc);
 +    cc->parse_features(typename, cpustr[1], &err);
 +    g_strfreev(cpustr);
 +    if (err) {
 +        error_report_err(err);
 +        exit(1);
 +    }
 -    cpuobj = object_new(object_class_get_name(cpu_oc));
 +    cpuobj = object_new(typename);
      /* By default ARM1176 CPUs have EL3 enabled.  This board does not
       * currently support EL3 so the CPU EL3 property is disabled before
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 09/13] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
+[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
-In the ARM ldr/str decode path, rather than directly testing
+From: Alistair Francis <alistair.francis@wdc.com>
 "insn & (1 << 21)" and "insn & (1 << 24)", abstract these
 bits out into wbit and pbit local flags. (We will want to
 do more tests against them to determine whether we need to
 provide syndrome information.)
+Commit 89e68b575 "target/arm: Use vector operations for saturation"
+causes this abort() when booting QEMU ARM with a Cortex-A15:
+0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
+0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
+0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
+0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
+0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
+0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
+0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
+0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
+0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
+0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
+0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
+0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
+0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
+0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
+0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
+0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
+This patch ensures that we don't hit the abort() in the second switch
+case in disas_neon_data_insn() as we will return from the first case.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 ---
- target/arm/translate.c | 9 ++++++---
+ target/arm/translate.c | 4 ++--
-file changed, 6 insertions(+), 3 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             } else {
+             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                 int address_offset;
+                            rn_ofs, rm_ofs, vec_size, vec_size,
-                 bool load = insn & (1 << 20);
+                            (u ? uqadd_op : sqadd_op) + size);
-+                bool wbit = insn & (1 << 21);
+-            break;
-+                bool pbit = insn & (1 << 24);
++            return 0;
-                 bool doubleword = false;
-                 /* Misc load/store */
+         case NEON_3R_VQSUB:
-                 rn = (insn >> 16) & 0xf;
+             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+                            rn_ofs, rm_ofs, vec_size, vec_size,
-                 }
+                            (u ? uqsub_op : sqsub_op) + size);
+-            break;
-                 addr = load_reg(s, rn);
++            return 0;
--                if (insn & (1 << 24))
-+                if (pbit) {
+         case NEON_3R_VMUL: /* VMUL */
-                     gen_add_datah_offset(s, insn, 0, addr);
+             if (u) {
 +                }
                  address_offset = 0;
                  if (doubleword) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     ensure correct behavior with overlapping index registers.
                     ldrd with base writeback is undefined if the
                     destination and index registers overlap.  */
 -                if (!(insn & (1 << 24))) {
 +                if (!pbit) {
                      gen_add_datah_offset(s, insn, address_offset, addr);
                      store_reg(s, rn, addr);
 -                } else if (insn & (1 << 21)) {
 +                } else if (wbit) {
                      if (address_offset)
                          tcg_gen_addi_i32(addr, addr, address_offset);
                      store_reg(s, rn, addr);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 12/13] hw/misc: New "unimplemented" sysbus device
+[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
-Create a new "unimplemented" sysbus device, which simply accepts
+The system_clock_scale global is used only by the armv7m systick
-all read and write accesses, and implements them as read-as-zero,
+device; move the extern declaration to the armv7m_systick.h header,
-write-ignored, with logging of the access as LOG_UNIMP.
+and expand the comment to explain what it is and that it should
+ideally be replaced with a different approach.
 This is useful for stubbing out bits of an SoC or board model
 which haven't been written yet.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
 ---
- hw/misc/Makefile.objs   |   2 +
+ include/hw/arm/arm.h              |  4 ----
- include/hw/misc/unimp.h |  39 ++++++++++++++++++
+ include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
- hw/misc/unimp.c         | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
+files changed, 22 insertions(+), 4 deletions(-)
 files changed, 148 insertions(+)
  create mode 100644 include/hw/misc/unimp.h
  create mode 100644 hw/misc/unimp.c
-diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
+diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/include/hw/arm/arm.h
-+++ b/hw/misc/Makefile.objs
++++ b/include/hw/arm/arm.h
-@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
+@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
- common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
+                                             const struct arm_boot_info *info,
- common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
+                                             hwaddr mvbar_addr);
-+common-obj-y += unimp.o
+-/* Multiplication factor to convert from system clock ticks to qemu timer
 -   ticks.  */
 -extern int system_clock_scale;
 -
  #endif /* HW_ARM_H */
 diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/timer/armv7m_systick.h
 +++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
      qemu_irq irq;
  } SysTickState;
 +/*
 + * Multiplication factor to convert from system clock ticks to qemu timer
 + * ticks. This should be set (by board code, usually) to a value
 + * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
 + * in Hz of the CPU.
 + *
 + * This value is used by the systick device when it is running in
 + * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
 + * set how fast the timer should tick.
 + *
 + * TODO: we should refactor this so that rather than using a global
 + * we use a device property or something similar. This is complicated
 + * because (a) the property would need to be plumbed through from the
 + * board code down through various layers to the systick device
 + * and (b) the property needs to be modifiable after realize, because
 + * the stellaris board uses this to implement the behaviour where the
 + * guest can reprogram the PLL registers to downclock the CPU, and the
 + * systick device needs to react accordingly. Possibly this should
 + * be deferred until we have a good API for modelling clock trees.
 + */
 +extern int system_clock_scale;
 +
- obj-$(CONFIG_VMPORT) += vmport.o
+ #endif
  # ARM devices
 diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/unimp.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * "Unimplemented" device
 + *
 + * Copyright Linaro Limited, 2017
 + * Written by Peter Maydell
 + */
 +
 +#ifndef HW_MISC_UNIMP_H
 +#define HW_MISC_UNIMP_H
 +
 +#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
 +
 +/**
 + * create_unimplemented_device: create and map a dummy device
 + * @name: name of the device for debug logging
 + * @base: base address of the device's MMIO region
 + * @size: size of the device's MMIO region
 + *
 + * This utility function creates and maps an instance of unimplemented-device,
 + * which is a dummy device which simply logs all guest accesses to
 + * it via the qemu_log LOG_UNIMP debug log.
 + * The device is mapped at priority -1000, which means that you can
 + * use it to cover a large region and then map other devices on top of it
 + * if necessary.
 + */
 +static inline void create_unimplemented_device(const char *name,
 +                                               hwaddr base,
 +                                               hwaddr size)
 +{
 +    DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
 +
 +    qdev_prop_set_string(dev, "name", name);
 +    qdev_prop_set_uint64(dev, "size", size);
 +    qdev_init_nofail(dev);
 +
 +    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
 +}
 +
 +#endif
 diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/unimp.c
@@ -XXX,XX +XXX,XX @@
 +/* "Unimplemented" device
 + *
 + * This is a dummy device which accepts and logs all accesses.
 + * It's useful for stubbing out regions of an SoC or board
 + * map which correspond to devices that have not yet been
 + * implemented. This is often sufficient to placate initial
 + * guest device driver probing such that the system will
 + * come up.
 + *
 + * Copyright Linaro Limited, 2017
 + * Written by Peter Maydell
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/hw.h"
 +#include "hw/sysbus.h"
 +#include "hw/misc/unimp.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +
 +#define UNIMPLEMENTED_DEVICE(obj) \
 +    OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)
 +
 +typedef struct {
 +    SysBusDevice parent_obj;
 +    MemoryRegion iomem;
 +    char *name;
 +    uint64_t size;
 +} UnimplementedDeviceState;
 +
 +static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
 +
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
 +                  "(size %d, offset 0x%" HWADDR_PRIx ")\n",
 +                  s->name, size, offset);
 +    return 0;
 +}
 +
 +static void unimp_write(void *opaque, hwaddr offset,
 +                        uint64_t value, unsigned size)
 +{
 +    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
 +
 +    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
 +                  "(size %d, value 0x%" PRIx64
 +                  ", offset 0x%" HWADDR_PRIx ")\n",
 +                  s->name, size, value, offset);
 +}
 +
 +static const MemoryRegionOps unimp_ops = {
 +    .read = unimp_read,
 +    .write = unimp_write,
 +    .impl.min_access_size = 1,
 +    .impl.max_access_size = 8,
 +    .valid.min_access_size = 1,
 +    .valid.max_access_size = 8,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +};
 +
 +static void unimp_realize(DeviceState *dev, Error **errp)
 +{
 +    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);
 +
 +    if (s->size == 0) {
 +        error_setg(errp, "property 'size' not specified or zero");
 +        return;
 +    }
 +
 +    if (s->name == NULL) {
 +        error_setg(errp, "property 'name' not specified");
 +        return;
 +    }
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
 +                          s->name, s->size);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 +}
 +
 +static Property unimp_properties[] = {
 +    DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),
 +    DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void unimp_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = unimp_realize;
 +    dc->props = unimp_properties;
 +}
 +
 +static const TypeInfo unimp_info = {
 +    .name = TYPE_UNIMPLEMENTED_DEVICE,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(UnimplementedDeviceState),
 +    .class_init = unimp_class_init,
 +};
 +
 +static void unimp_register_types(void)
 +{
 +    type_register_static(&unimp_info);
 +}
 +
 +type_init(unimp_register_types)
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 08/13] arm: Correctly handle watchpoints for BE32 CPUs
+[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
-From: Julian Brown <julian@codesourcery.com>
+The hw/arm/arm.h header now only includes declarations relating
 to boot.c code, so it is only needed by Arm board or SoC code.
 Remove some unnecessary inclusions of it from target/arm files
 and from hw/intc/armv7m_nvic.c.
-In BE32 mode, sub-word size watchpoints can fail to trigger because the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-address of the access is adjusted in the opcode helpers before being
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-compared with the watchpoint registers.  This patch reverses the address
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-adjustment before performing the comparison with the help of a new CPUClass
+Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
-hook.
+---
  hw/intc/armv7m_nvic.c | 1 -
  target/arm/arm-semi.c | 1 -
  target/arm/cpu.c      | 1 -
  target/arm/cpu64.c    | 1 -
  target/arm/kvm.c      | 1 -
  target/arm/kvm32.c    | 1 -
  target/arm/kvm64.c    | 1 -
 files changed, 7 deletions(-)
-This version of the patch augments and tidies up comments a little.
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 Signed-off-by: Julian Brown <julian@codesourcery.com>
 Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/qom/cpu.h      |  3 +++
  target/arm/internals.h |  5 +++++
  exec.c                 |  1 +
  qom/cpu.c              |  6 ++++++
  target/arm/cpu.c       |  3 +++
  target/arm/op_helper.c | 22 ++++++++++++++++++++++
 files changed, 40 insertions(+)
 diff --git a/include/qom/cpu.h b/include/qom/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/qom/cpu.h
+--- a/hw/intc/armv7m_nvic.c
-+++ b/include/qom/cpu.h
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
+@@ -XXX,XX +XXX,XX @@
-  * @cpu_exec_exit: Callback for cpu_exec cleanup.
+ #include "cpu.h"
-  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
+ #include "hw/sysbus.h"
-  * @disas_set_info: Setup architecture specific components of disassembly info
+ #include "qemu/timer.h"
-+ * @adjust_watchpoint_address: Perform a target-specific adjustment to an
+-#include "hw/arm/arm.h"
-+ * address before attempting to match it against watchpoints.
+ #include "hw/intc/armv7m_nvic.h"
-  *
+ #include "target/arm/cpu.h"
-  * Represents a CPU family or model.
+ #include "exec/exec-all.h"
-  */
+diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
      bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
      void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
 +    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
  } CPUClass;
  #ifdef HOST_WORDS_BIGENDIAN
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/target/arm/arm-semi.c
-+++ b/target/arm/internals.h
++++ b/target/arm/arm-semi.c
-@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu);
+@@ -XXX,XX +XXX,XX @@
- /* Callback function for checking if a watchpoint should trigger. */
+ #else
- bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+ #include "qemu-common.h"
+ #include "exec/gdbstub.h"
-+/* Adjust addresses (in BE32 mode) before testing against watchpoint
+-#include "hw/arm/arm.h"
-+ * addresses.
+ #include "qemu/cutils.h"
-+ */
+ #endif
-+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
 +
  /* Callback function for when a watchpoint or breakpoint triggers. */
  void arm_debug_excp_handler(CPUState *cs);
 diff --git a/exec.c b/exec.c
 index XXXXXXX..XXXXXXX 100644
 --- a/exec.c
 +++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
          return;
      }
      vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
 +    vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
      QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
          if (cpu_watchpoint_address_matches(wp, vaddr, len)
              && (wp->flags & flags)) {
 diff --git a/qom/cpu.c b/qom/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/qom/cpu.c
 +++ b/qom/cpu.c
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
      return cpu->cpu_index;
  }
 +static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
 +{
 +    return addr;
 +}
 +
  static void cpu_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
      k->cpu_exec_enter = cpu_common_noop;
      k->cpu_exec_exit = cpu_common_noop;
      k->cpu_exec_interrupt = cpu_common_exec_interrupt;
 +    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
      set_bit(DEVICE_CATEGORY_CPU, dc->categories);
      dc->realize = cpu_common_realizefn;
      dc->unrealize = cpu_common_unrealizefn;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@
-     cc->gdb_stop_before_watchpoint = true;
+ #if !defined(CONFIG_USER_ONLY)
-     cc->debug_excp_handler = arm_debug_excp_handler;
+ #include "hw/loader.h"
-     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
+ #endif
-+#if !defined(CONFIG_USER_ONLY)
+-#include "hw/arm/arm.h"
-+    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+ #include "sysemu/sysemu.h"
-+#endif
+ #include "sysemu/hw_accel.h"
+ #include "kvm_arm.h"
-     cc->disas_set_info = arm_disas_set_info;
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
  }
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/op_helper.c
+--- a/target/arm/cpu64.c
-+++ b/target/arm/op_helper.c
++++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+@@ -XXX,XX +XXX,XX @@
-     return check_watchpoints(cpu);
+ #if !defined(CONFIG_USER_ONLY)
- }
+ #include "hw/loader.h"
+ #endif
-+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
+-#include "hw/arm/arm.h"
-+{
+ #include "sysemu/sysemu.h"
-+    ARMCPU *cpu = ARM_CPU(cs);
+ #include "sysemu/kvm.h"
-+    CPUARMState *env = &cpu->env;
+ #include "kvm_arm.h"
-+
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
-+    /* In BE32 system mode, target memory is stored byteswapped (on a
+index XXXXXXX..XXXXXXX 100644
-+     * little-endian host system), and by the time we reach here (via an
+--- a/target/arm/kvm.c
-+     * opcode helper) the addresses of subword accesses have been adjusted
++++ b/target/arm/kvm.c
-+     * to account for that, which means that watchpoints will not match.
+@@ -XXX,XX +XXX,XX @@
-+     * Undo the adjustment here.
+ #include "cpu.h"
-+     */
+ #include "trace.h"
-+    if (arm_sctlr_b(env)) {
+ #include "internals.h"
-+        if (len == 1) {
+-#include "hw/arm/arm.h"
-+            addr ^= 3;
+ #include "hw/pci/pci.h"
-+        } else if (len == 2) {
+ #include "exec/memattrs.h"
-+            addr ^= 2;
+ #include "exec/address-spaces.h"
-+        }
+diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
-+    }
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/target/arm/kvm32.c
-+    return addr;
++++ b/target/arm/kvm32.c
-+}
+@@ -XXX,XX +XXX,XX @@
-+
+ #include "sysemu/kvm.h"
- void arm_debug_excp_handler(CPUState *cs)
+ #include "kvm_arm.h"
- {
+ #include "internals.h"
-     /* Called by core code when a watchpoint or breakpoint fires;
+-#include "hw/arm/arm.h"
  #include "qemu/log.h"
  static inline void set_feature(uint64_t *features, int feature)
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/kvm.h"
  #include "kvm_arm.h"
  #include "internals.h"
 -#include "hw/arm/arm.h"
  static bool have_guest_debug;
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 13/13] stellaris: Use the 'unimplemented' device for parts we don't implement
+[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
-Use the 'unimplemented' dummy device to cover regions of the
+The header file hw/arm/arm.h now includes only declarations
-SoC device memory map which we don't have proper device
+relating to hw/arm/boot.c functionality. Rename it accordingly,
-implementations for yet.
+and adjust its header comment.
 The bulk of this commit was created via
  perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
 In a few cases we can just delete the #include:
 hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
 include/hw/arm/bcm2836.h did not require it.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
 ---
- hw/arm/stellaris.c | 14 ++++++++++++++
+ include/hw/arm/allwinner-a10.h   | 2 +-
-file changed, 14 insertions(+)
+ include/hw/arm/aspeed_soc.h      | 1 -
  include/hw/arm/bcm2836.h         | 1 -
  include/hw/arm/{arm.h => boot.h} | 8 ++++----
  include/hw/arm/fsl-imx25.h       | 2 +-
  include/hw/arm/fsl-imx31.h       | 2 +-
  include/hw/arm/fsl-imx6.h        | 2 +-
  include/hw/arm/fsl-imx6ul.h      | 2 +-
  include/hw/arm/fsl-imx7.h        | 2 +-
  include/hw/arm/virt.h            | 2 +-
  include/hw/arm/xlnx-versal.h     | 2 +-
  include/hw/arm/xlnx-zynqmp.h     | 2 +-
  hw/arm/armsse.c                  | 2 +-
  hw/arm/armv7m.c                  | 2 +-
  hw/arm/aspeed.c                  | 2 +-
  hw/arm/boot.c                    | 2 +-
  hw/arm/collie.c                  | 2 +-
  hw/arm/exynos4210.c              | 2 +-
  hw/arm/exynos4_boards.c          | 2 +-
  hw/arm/highbank.c                | 2 +-
  hw/arm/integratorcp.c            | 2 +-
  hw/arm/mainstone.c               | 2 +-
  hw/arm/microbit.c                | 2 +-
  hw/arm/mps2-tz.c                 | 2 +-
  hw/arm/mps2.c                    | 2 +-
  hw/arm/msf2-soc.c                | 1 -
  hw/arm/msf2-som.c                | 2 +-
  hw/arm/musca.c                   | 2 +-
  hw/arm/musicpal.c                | 2 +-
  hw/arm/netduino2.c               | 2 +-
  hw/arm/nrf51_soc.c               | 2 +-
  hw/arm/nseries.c                 | 2 +-
  hw/arm/omap1.c                   | 2 +-
  hw/arm/omap2.c                   | 2 +-
  hw/arm/omap_sx1.c                | 2 +-
  hw/arm/palm.c                    | 2 +-
  hw/arm/raspi.c                   | 2 +-
  hw/arm/realview.c                | 2 +-
  hw/arm/spitz.c                   | 2 +-
  hw/arm/stellaris.c               | 2 +-
  hw/arm/stm32f205_soc.c           | 2 +-
  hw/arm/strongarm.c               | 2 +-
  hw/arm/tosa.c                    | 2 +-
  hw/arm/versatilepb.c             | 2 +-
  hw/arm/vexpress.c                | 2 +-
  hw/arm/virt.c                    | 2 +-
  hw/arm/xilinx_zynq.c             | 2 +-
  hw/arm/xlnx-versal.c             | 2 +-
  hw/arm/z2.c                      | 2 +-
 files changed, 49 insertions(+), 52 deletions(-)
  rename include/hw/arm/{arm.h => boot.h} (98%)
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/allwinner-a10.h
++++ b/include/hw/arm/allwinner-a10.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "qemu/error-report.h"
+ #include "hw/char/serial.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/timer/allwinner-a10-pit.h"
+ #include "hw/intc/allwinner-a10-pic.h"
+ #include "hw/net/allwinner_emac.h"
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/aspeed_soc.h
++++ b/include/hw/arm/aspeed_soc.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef ASPEED_SOC_H
+ #define ASPEED_SOC_H
+-#include "hw/arm/arm.h"
+ #include "hw/intc/aspeed_vic.h"
+ #include "hw/misc/aspeed_scu.h"
+ #include "hw/misc/aspeed_sdmc.h"
+diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/bcm2836.h
++++ b/include/hw/arm/bcm2836.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef BCM2836_H
+ #define BCM2836_H
+-#include "hw/arm/arm.h"
+ #include "hw/arm/bcm2835_peripherals.h"
+ #include "hw/intc/bcm2836_control.h"
+diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
+similarity index 98%
+rename from include/hw/arm/arm.h
+rename to include/hw/arm/boot.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/arm.h
++++ b/include/hw/arm/boot.h
+@@ -XXX,XX +XXX,XX @@
+ /*
+- * Misc ARM declarations
++ * ARM kernel loader.
+  *
+  * Copyright (c) 2006 CodeSourcery.
+  * Written by Paul Brook
+@@ -XXX,XX +XXX,XX @@
+  *
+  */
+-#ifndef HW_ARM_H
+-#define HW_ARM_H
++#ifndef HW_ARM_BOOT_H
++#define HW_ARM_BOOT_H
+ #include "exec/memory.h"
+ #include "target/arm/cpu-qom.h"
+@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
+                                             const struct arm_boot_info *info,
+                                             hwaddr mvbar_addr);
+-#endif /* HW_ARM_H */
++#endif /* HW_ARM_BOOT_H */
+diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx25.h
++++ b/include/hw/arm/fsl-imx25.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX25_H
+ #define FSL_IMX25_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/imx_avic.h"
+ #include "hw/misc/imx25_ccm.h"
+ #include "hw/char/imx_serial.h"
+diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx31.h
++++ b/include/hw/arm/fsl-imx31.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX31_H
+ #define FSL_IMX31_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/imx_avic.h"
+ #include "hw/misc/imx31_ccm.h"
+ #include "hw/char/imx_serial.h"
+diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6.h
++++ b/include/hw/arm/fsl-imx6.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX6_H
+ #define FSL_IMX6_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/cpu/a9mpcore.h"
+ #include "hw/misc/imx6_ccm.h"
+ #include "hw/misc/imx6_src.h"
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX6UL_H
+ #define FSL_IMX6UL_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/cpu/a15mpcore.h"
+ #include "hw/misc/imx6ul_ccm.h"
+ #include "hw/misc/imx6_src.h"
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx7.h
++++ b/include/hw/arm/fsl-imx7.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef FSL_IMX7_H
+ #define FSL_IMX7_H
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/cpu/a15mpcore.h"
+ #include "hw/intc/imx_gpcv2.h"
+ #include "hw/misc/imx7_ccm.h"
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/virt.h
++++ b/include/hw/arm/virt.h
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/hwaddr.h"
+ #include "qemu/notify.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/block/flash.h"
+ #include "sysemu/kvm.h"
+ #include "hw/intc/arm_gicv3_common.h"
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-versal.h
++++ b/include/hw/arm/xlnx-versal.h
+@@ -XXX,XX +XXX,XX @@
+ #define XLNX_VERSAL_H
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/arm_gicv3.h"
+ #define TYPE_XLNX_VERSAL "xlnx-versal"
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
+@@ -XXX,XX +XXX,XX @@
+ #ifndef XLNX_ZYNQMP_H
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/intc/arm_gic.h"
+ #include "hw/net/cadence_gem.h"
+ #include "hw/char/cadence_uart.h"
+diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/armsse.c
++++ b/hw/arm/armsse.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/registerfields.h"
+ #include "hw/arm/armsse.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ /* Format of the System Information block SYS_CONFIG register */
+ typedef enum SysConfigFormat {
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/armv7m.c
++++ b/hw/arm/armv7m.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/loader.h"
+ #include "elf.h"
+ #include "sysemu/qtest.h"
+diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed.c
++++ b/hw/arm/aspeed.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "exec/address-spaces.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/aspeed.h"
+ #include "hw/arm/aspeed_soc.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/boot.c
++++ b/hw/arm/boot.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include <libfdt.h>
+ #include "hw/hw.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/linux-boot-if.h"
+ #include "sysemu/kvm.h"
+ #include "sysemu/sysemu.h"
+diff --git a/hw/arm/collie.c b/hw/arm/collie.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/collie.c
++++ b/hw/arm/collie.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/boards.h"
+ #include "strongarm.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/block/flash.h"
+ #include "exec/address-spaces.h"
+ #include "cpu.h"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/boards.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/loader.h"
+ #include "hw/arm/exynos4210.h"
+ #include "hw/sd/sdhci.h"
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4_boards.c
++++ b/hw/arm/exynos4_boards.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/sysemu.h"
+ #include "hw/sysbus.h"
+ #include "net/net.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "exec/address-spaces.h"
+ #include "hw/arm/exynos4210.h"
+ #include "hw/net/lan9118.h"
+diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/highbank.c
++++ b/hw/arm/highbank.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/loader.h"
+ #include "net/net.h"
+ #include "sysemu/kvm.h"
+diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/integratorcp.c
++++ b/hw/arm/integratorcp.c
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/misc/arm_integrator_debug.h"
+ #include "hw/net/smc91c111.h"
+ #include "net/net.h"
+diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mainstone.c
++++ b/hw/arm/mainstone.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "hw/hw.h"
+ #include "hw/arm/pxa.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "net/net.h"
+ #include "hw/net/smc91c111.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/microbit.c
++++ b/hw/arm/microbit.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "sysemu/sysemu.h"
+ #include "exec/address-spaces.h"
+diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mps2-tz.c
++++ b/hw/arm/mps2-tz.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu/error-report.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/armv7m.h"
+ #include "hw/or-irq.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mps2.c
++++ b/hw/arm/mps2.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu/error-report.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/armv7m.h"
+ #include "hw/or-irq.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/msf2-soc.c
++++ b/hw/arm/msf2-soc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/units.h"
+ #include "qapi/error.h"
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
+ #include "exec/address-spaces.h"
+ #include "hw/char/serial.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/msf2-som.c
++++ b/hw/arm/msf2-som.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "qemu/error-report.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "exec/address-spaces.h"
+ #include "hw/arm/msf2-soc.h"
+ #include "cpu.h"
+diff --git a/hw/arm/musca.c b/hw/arm/musca.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/musca.c
++++ b/hw/arm/musca.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "exec/address-spaces.h"
+ #include "sysemu/sysemu.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/armsse.h"
+ #include "hw/boards.h"
+ #include "hw/char/pl011.h"
+diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/musicpal.c
++++ b/hw/arm/musicpal.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "net/net.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/netduino2.c
++++ b/hw/arm/netduino2.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/boards.h"
+ #include "qemu/error-report.h"
+ #include "hw/arm/stm32f205_soc.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ static void netduino2_init(MachineState *machine)
+ {
+diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/nrf51_soc.c
++++ b/hw/arm/nrf51_soc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
+ #include "qemu-common.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/sysbus.h"
+ #include "hw/boards.h"
+ #include "hw/misc/unimp.h"
+diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/nseries.c
++++ b/hw/arm/nseries.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/bswap.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/arm/omap.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/irq.h"
+ #include "ui/console.h"
+ #include "hw/boards.h"
+diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap1.c
++++ b/hw/arm/omap1.c
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
+ #include "hw/boards.h"
+ #include "hw/hw.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/omap.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/arm/soc_dma.h"
+diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap2.c
++++ b/hw/arm/omap2.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/qtest.h"
+ #include "hw/boards.h"
+ #include "hw/hw.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/omap.h"
+ #include "sysemu/sysemu.h"
+ #include "qemu/timer.h"
+diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap_sx1.c
++++ b/hw/arm/omap_sx1.c
+@@ -XXX,XX +XXX,XX @@
+ #include "ui/console.h"
+ #include "hw/arm/omap.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/block/flash.h"
+ #include "sysemu/qtest.h"
+ #include "exec/address-spaces.h"
+diff --git a/hw/arm/palm.c b/hw/arm/palm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/palm.c
++++ b/hw/arm/palm.c
+@@ -XXX,XX +XXX,XX @@
+ #include "ui/console.h"
+ #include "hw/arm/omap.h"
+ #include "hw/boards.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/input/tsc2xxx.h"
+ #include "hw/loader.h"
+ #include "exec/address-spaces.h"
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/raspi.c
++++ b/hw/arm/raspi.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/error-report.h"
+ #include "hw/boards.h"
+ #include "hw/loader.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "sysemu/sysemu.h"
+ #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
+diff --git a/hw/arm/realview.c b/hw/arm/realview.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/realview.c
++++ b/hw/arm/realview.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "hw/arm/primecell.h"
+ #include "hw/net/lan9118.h"
+ #include "hw/net/smc91c111.h"
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qapi/error.h"
+ #include "hw/hw.h"
+ #include "hw/arm/pxa.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
+ #include "sysemu/sysemu.h"
+ #include "hw/pcmcia.h"
+ #include "hw/i2c/i2c.h"
 diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/stellaris.c
 +++ b/hw/arm/stellaris.c
 @@ -XXX,XX +XXX,XX @@
- #include "exec/address-spaces.h"
+ #include "qapi/error.h"
- #include "sysemu/sysemu.h"
+ #include "hw/sysbus.h"
- #include "hw/char/pl011.h"
+ #include "hw/ssi/ssi.h"
-+#include "hw/misc/unimp.h"
+-#include "hw/arm/arm.h"
++#include "hw/arm/boot.h"
- #define GPIO_A 0
+ #include "qemu/timer.h"
- #define GPIO_B 1
+ #include "hw/i2c/i2c.h"
-@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
+ #include "net/net.h"
-             }
+diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
-         }
+index XXXXXXX..XXXXXXX 100644
-     }
+--- a/hw/arm/stm32f205_soc.c
-+
++++ b/hw/arm/stm32f205_soc.c
-+    /* Add dummy regions for the devices we don't implement yet,
+@@ -XXX,XX +XXX,XX @@
-+     * so guest accesses don't cause unlogged crashes.
+ #include "qemu/osdep.h"
-+     */
+ #include "qapi/error.h"
-+    create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
+ #include "qemu-common.h"
-+    create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
+-#include "hw/arm/arm.h"
-+    create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
++#include "hw/arm/boot.h"
-+    create_unimplemented_device("PWM", 0x40028000, 0x1000);
+ #include "exec/address-spaces.h"
-+    create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
+ #include "hw/arm/stm32f205_soc.h"
-+    create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
-+    create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
+diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
-+    create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
+index XXXXXXX..XXXXXXX 100644
-+    create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
+--- a/hw/arm/strongarm.c
- }
++++ b/hw/arm/strongarm.c
+@@ -XXX,XX +XXX,XX @@
- /* FIXME: Figure out how to generate these from stellaris_boards.  */
+ #include "hw/sysbus.h"
  #include "strongarm.h"
  #include "qemu/error-report.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "chardev/char-fe.h"
  #include "chardev/char-serial.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/tosa.c
 +++ b/hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/sharpsl.h"
  #include "hw/pcmcia.h"
  #include "hw/boards.h"
 diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/versatilepb.c
 +++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/net/smc91c111.h"
  #include "net/net.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/vexpress.c
 +++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/primecell.h"
  #include "hw/net/lan9118.h"
  #include "hw/i2c/i2c.h"
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/option.h"
  #include "qapi/error.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/primecell.h"
  #include "hw/arm/virt.h"
  #include "hw/block/flash.h"
 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xilinx_zynq.c
 +++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "net/net.h"
  #include "exec/address-spaces.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
  #include "net/net.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "kvm_arm.h"
  #include "hw/misc/unimp.h"
  #include "hw/intc/arm_gicv3_common.h"
 diff --git a/hw/arm/z2.c b/hw/arm/z2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/z2.c
 +++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/i2c/i2c.h"
  #include "hw/ssi/ssi.h"
  #include "hw/boards.h"
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 11/13] stellaris: Document memory map and which SoC devices are unimplemented
+[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
-Add a comment documenting the memory map of the SoC devices and which
+In ich_vmcr_write() we enforce "writes of BPR fields to less than
-are not implemented.
+their minimum sets them to the minimum" by doing a "read vbpr and
 write it back" operation.  A typo here meant that we weren't handling
 writes to these fields correctly, because we were reading from VBPR0
 but writing to VBPR1.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
 ---
- hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++
+ hw/intc/arm_gicv3_cpuif.c | 2 +-
-file changed, 34 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/stellaris.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/arm/stellaris.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
+@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-x40024000, 0x40025000, 0x40026000};
+     /* Enforce "writing BPRs to less than minimum sets them to the minimum"
-     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
+      * by reading and writing back the fields.
+      */
-+    /* Memory map of SoC devices, from
+-    write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
-+     * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
++    write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
-+     * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
+     write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
-+     *
-+     * 40000000 wdtimer (unimplemented)
+     gicv3_cpuif_virt_update(cs);
 +     * 40002000 i2c (unimplemented)
 +     * 40004000 GPIO
 +     * 40005000 GPIO
 +     * 40006000 GPIO
 +     * 40007000 GPIO
 +     * 40008000 SSI
 +     * 4000c000 UART
 +     * 4000d000 UART
 +     * 4000e000 UART
 +     * 40020000 i2c
 +     * 40021000 i2c (unimplemented)
 +     * 40024000 GPIO
 +     * 40025000 GPIO
 +     * 40026000 GPIO
 +     * 40028000 PWM (unimplemented)
 +     * 4002c000 QEI (unimplemented)
 +     * 4002d000 QEI (unimplemented)
 +     * 40030000 gptimer
 +     * 40031000 gptimer
 +     * 40032000 gptimer
 +     * 40033000 gptimer
 +     * 40038000 ADC
 +     * 4003c000 analogue comparator (unimplemented)
 +     * 40048000 ethernet
 +     * 400fc000 hibernation module (unimplemented)
 +     * 400fd000 flash memory control (unimplemented)
 +     * 400fe000 system control
 +     */
 +
      DeviceState *gpio_dev[7], *nvic;
      qemu_irq gpio_in[7][8];
      qemu_irq gpio_out[7][8];
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 06/13] target/arm: Add cfgend parameter for ARM CPU selection.
+[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
-From: Julian Brown <julian@codesourcery.com>
+The ICC_CTLR_EL3 register includes some bits which are aliases
 of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
 to keep those bits in the cs->icc_ctlr_el1[] struct fields.
 Unfortunately a missing '~' in the code to update the bits
 in those fields meant that writing to ICC_CTLR_EL3 would corrupt
 the ICC_CLTR_EL1 register values.
-Add a new "cfgend" property which selects whether the CPU resets into
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-big-endian mode or not.  This setting affects whether we reset with
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set.
+Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
 ---
  hw/intc/arm_gicv3_cpuif.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-Signed-off-by: Julian Brown <julian@codesourcery.com>
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com
 [PMM: use error_report_err() rather than error_report();
  move the integratorcp changes to their own patch;
  drop an unnecessary extra #include;
  rephrase commit message accordingly;
  move setting of reset_sctlr above registration of cpregs
  so it actually has an effect]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h |  7 +++++++
  target/arm/cpu.c | 13 +++++++++++++
 files changed, 20 insertions(+)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/target/arm/cpu.h
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     int gic_vpribits; /* number of virtual priority bits */
+     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
-     int gic_vprebits; /* number of virtual preemption bits */
+     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-+    /* Whether the cfgend input is high (i.e. this CPU should reset into
+-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
-+     * big-endian mode).  This setting isn't used directly: instead it modifies
++    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
-+     * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
+     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
-+     * architecture version.
+         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
 +     */
 +    bool cfgend;
 +
      ARMELChangeHook *el_change_hook;
      void *el_change_hook_opaque;
  };
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el2_property =
  static Property arm_cpu_has_el3_property =
              DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 +static Property arm_cpu_cfgend_property =
 +            DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 +
  /* use property name "pmu" to match other archs and virt tools */
  static Property arm_cpu_has_pmu_property =
              DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
          }
      }
+@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+    qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
+         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
 +                             &error_abort);
  }
  static void arm_cpu_finalizefn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
              cpu->reset_sctlr |= (1 << 13);
      }
-+    if (cpu->cfgend) {
+-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
-+        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
++    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
-+            cpu->reset_sctlr |= SCTLR_EE;
+     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
-+        } else {
+         cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
-+            cpu->reset_sctlr |= SCTLR_B;
+     }
 +        }
 +    }
 +
      if (!cpu->has_el3) {
          /* If the has_el3 CPU property is disabled then we need to disable the
           * feature.
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 04/13] sd: sdhci: check data length during dma_memory_read
+[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
-From: Prasad J Pandit <pjp@fedoraproject.org>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-While doing multi block SDMA transfer in routine
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-index 'begin' and data length 's->data_count' could end up to be same.
+Message-id: 20190520214342.13709-2-philmd@redhat.com
 This could lead to an OOB access issue. Correct transfer data length
 to avoid it.
 Cc: qemu-stable@nongnu.org
 Reported-by: Jiang Xin <jiangxin1@huawei.com>
 Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20170130064736.9236-1-ppandit@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/sd/sdhci.c | 2 +-
+ hw/arm/exynos4_boards.c | 24 ------------------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 24 deletions(-)
-diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/sdhci.c
+--- a/hw/arm/exynos4_boards.c
-+++ b/hw/sd/sdhci.c
++++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
+@@ -XXX,XX +XXX,XX @@
-                 boundary_count -= block_size - begin;
+ #include "hw/net/lan9118.h"
-             }
+ #include "hw/boards.h"
-             dma_memory_read(&address_space_memory, s->sdmasysad,
--                            &s->fifo_buffer[begin], s->data_count);
+-#undef DEBUG
-+                            &s->fifo_buffer[begin], s->data_count - begin);
+-
-             s->sdmasysad += s->data_count - begin;
+-//#define DEBUG
-             if (s->data_count == block_size) {
+-
-                 for (n = 0; n < block_size; n++) {
+-#ifdef DEBUG
 -    #undef PRINT_DEBUG
 -    #define  PRINT_DEBUG(fmt, args...) \
 -        do { \
 -            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
 -        } while (0)
 -#else
 -    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
 -#endif
 -
  #define SMDK_LAN9118_BASE_ADDR      0x05000000
  typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
      exynos4_board_binfo.gic_cpu_if_addr =
              EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 -    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
 -            " kernel_filename: %s\n"
 -            " kernel_cmdline: %s\n"
 -            " initrd_filename: %s\n",
 -            exynos4_board_ram_size[board_type] / 1048576,
 -            exynos4_board_ram_size[board_type],
 -            machine->kernel_filename,
 -            machine->kernel_cmdline,
 -            machine->initrd_filename);
 -
      exynos4_boards_init_ram(s, get_system_memory(),
                              exynos4_board_ram_size[board_type]);
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 01/13] integratorcp: adding vmstate for save/restore
+[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
-From: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-VMState added by this patch preserves correct
+It eases code review, unit is explicit.
 loading of the integratorcp device state.
-Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-[PMM: removed unnecessary minimum_version_id_old lines]
+Message-id: 20190520214342.13709-3-philmd@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/integratorcp.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ hw/arm/exynos4_boards.c | 5 +++--
-file changed, 59 insertions(+)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/integratorcp.c
+--- a/hw/arm/exynos4_boards.c
-+++ b/hw/arm/integratorcp.c
++++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@ static uint8_t integrator_spd[128] = {
+@@ -XXX,XX +XXX,XX @@
-xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
+  */
  #include "qemu/osdep.h"
 +#include "qemu/units.h"
  #include "qapi/error.h"
  #include "qemu/error-report.h"
  #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
  };
-+static const VMStateDescription vmstate_integratorcm = {
+ static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-+    .name = "integratorcm",
+-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-+    .version_id = 1,
+-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
-+    .minimum_version_id = 1,
++    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
-+    .fields      = (VMStateField[]) {
++    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
 +        VMSTATE_UINT32(cm_osc, IntegratorCMState),
 +        VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
 +        VMSTATE_UINT32(cm_lock, IntegratorCMState),
 +        VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
 +        VMSTATE_UINT32(cm_sdram, IntegratorCMState),
 +        VMSTATE_UINT32(cm_init, IntegratorCMState),
 +        VMSTATE_UINT32(cm_flags, IntegratorCMState),
 +        VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
 +        VMSTATE_UINT32(int_level, IntegratorCMState),
 +        VMSTATE_UINT32(irq_enabled, IntegratorCMState),
 +        VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static uint64_t integratorcm_read(void *opaque, hwaddr offset,
                                    unsigned size)
  {
@@ -XXX,XX +XXX,XX @@ typedef struct icp_pic_state {
      qemu_irq parent_fiq;
  } icp_pic_state;
 +static const VMStateDescription vmstate_icp_pic = {
 +    .name = "icp_pic",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields      = (VMStateField[]) {
 +        VMSTATE_UINT32(level, icp_pic_state),
 +        VMSTATE_UINT32(irq_enabled, icp_pic_state),
 +        VMSTATE_UINT32(fiq_enabled, icp_pic_state),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static void icp_pic_update(icp_pic_state *s)
  {
      uint32_t flags;
@@ -XXX,XX +XXX,XX @@ typedef struct ICPCtrlRegsState {
  #define ICP_INTREG_WPROT        (1 << 0)
  #define ICP_INTREG_CARDIN       (1 << 3)
 +static const VMStateDescription vmstate_icp_control = {
 +    .name = "icp_control",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields      = (VMStateField[]) {
 +        VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static uint64_t icp_control_read(void *opaque, hwaddr offset,
                                   unsigned size)
  {
@@ -XXX,XX +XXX,XX @@ static void core_class_init(ObjectClass *klass, void *data)
      dc->props = core_properties;
      dc->realize = integratorcm_realize;
 +    dc->vmsd = &vmstate_integratorcm;
 +}
 +
 +static void icp_pic_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->vmsd = &vmstate_icp_pic;
 +}
 +
 +static void icp_control_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->vmsd = &vmstate_icp_control;
  }
  static const TypeInfo core_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_pic_info = {
      .parent        = TYPE_SYS_BUS_DEVICE,
      .instance_size = sizeof(icp_pic_state),
      .instance_init = icp_pic_init,
 +    .class_init    = icp_pic_class_init,
  };
- static const TypeInfo icp_ctrl_regs_info = {
+ static struct arm_boot_info exynos4_board_binfo = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_ctrl_regs_info = {
      .parent        = TYPE_SYS_BUS_DEVICE,
      .instance_size = sizeof(ICPCtrlRegsState),
      .instance_init = icp_control_init,
 +    .class_init    = icp_control_class_init,
  };
  static void integratorcp_register_types(void)
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 07/13] Fix Thumb-1 BE32 execution and disassembly.
+[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
-From: Julian Brown <julian@codesourcery.com>
+From: Guenter Roeck <linux@roeck-us.net>
-Thumb-1 code has some issues in BE32 mode (as currently implemented). In
+QEMU already supports pl330. Instantiate it for Exynos4210.
 short, since bytes are swapped within words at load time for BE32
 executables, this also swaps pairs of adjacent Thumb-1 instructions.
-This patch un-swaps those pairs of instructions again, both for execution,
+Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
 and for disassembly. (The previous version of the patch always read four
 bytes in arm_read_memory_func and then extracted the proper two bytes,
 in a probably misguided attempt to match the behaviour of actual hardware
 as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for
 instruction fetches". It's less complicated to just read the correct
 two bytes though.)
-Signed-off-by: Julian Brown <julian@codesourcery.com>
+/ {
-Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com
+    soc: soc {
         amba {
             pdma0: pdma@12680000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12680000 0x1000>;
                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA0>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             pdma1: pdma@12690000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12690000 0x1000>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA1>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             mdma1: mdma@12850000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12850000 0x1000>;
                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_MDMA>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <1>;
             };
         };
     };
 };
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190520214342.13709-4-philmd@redhat.com
 [PMD: Do not set default qdev properties, create the controllers in the SoC
       rather than the board (Peter Maydell), add dtsi in commit message]
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/disas/bfd.h   |  7 +++++++
+ hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
- target/arm/arm_ldst.h | 10 +++++++++-
+file changed, 26 insertions(+)
  disas.c               |  1 +
  target/arm/cpu.c      | 23 +++++++++++++++++++++++
 files changed, 40 insertions(+), 1 deletion(-)
-diff --git a/include/disas/bfd.h b/include/disas/bfd.h
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/disas/bfd.h
+--- a/hw/arm/exynos4210.c
-+++ b/include/disas/bfd.h
++++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
+@@ -XXX,XX +XXX,XX @@
-      The bottom 16 bits are for the internal use of the disassembler.  */
+ /* EHCI */
-   unsigned long flags;
+ #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
- #define INSN_HAS_RELOC    0x80000000
-+#define INSN_ARM_BE32    0x00010000
++/* DMA */
-   PTR private_data;
++#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
++#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
-   /* Function used to get bytes to disassemble.  MEMADDR is the
++#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
      (bfd_vma memaddr, bfd_byte *myaddr, int length,
           struct disassemble_info *info);
 +  /* A place to stash the real read_memory_func if read_memory_func wants to
 +     do some funky address arithmetic or similar (e.g. for ARM BE32 mode).  */
 +  int (*read_memory_inner_func)
 +    (bfd_vma memaddr, bfd_byte *myaddr, int length,
 +             struct disassemble_info *info);
 +
-   /* Function which should be called if we get an error that we can't
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
-      recover from.  STATUS is the errno value from read_memory_func and
+x09, 0x00, 0x00, 0x00 };
-      MEMADDR is the address that we were trying to read.  INFO is a
-diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
+@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
-index XXXXXXX..XXXXXXX 100644
+     return (0x9 << ARM_AFF1_SHIFT) | cpu;
 --- a/target/arm/arm_ldst.h
 +++ b/target/arm/arm_ldst.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
  static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
                                       bool sctlr_b)
  {
 -    uint16_t insn = cpu_lduw_code(env, addr);
 +    uint16_t insn;
 +#ifndef CONFIG_USER_ONLY
 +    /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
 +       within each word.  Undo that now.  */
 +    if (sctlr_b) {
 +        addr ^= 2;
 +    }
 +#endif
 +    insn = cpu_lduw_code(env, addr);
      if (bswap_code(sctlr_b)) {
          return bswap16(insn);
      }
 diff --git a/disas.c b/disas.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas.c
 +++ b/disas.c
@@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
      s.cpu = cpu;
      s.info.read_memory_func = target_read_memory;
 +    s.info.read_memory_inner_func = NULL;
      s.info.buffer_vma = code;
      s.info.buffer_length = size;
      s.info.print_address_func = generic_print_address;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
    return print_insn_arm(pc | 1, info);
  }
-+static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
++static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
 +                                int length, struct disassemble_info *info)
 +{
-+    assert(info->read_memory_inner_func);
++    SysBusDevice *busdev;
-+    assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
++    DeviceState *dev;
 +
-+    if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
++    dev = qdev_create(NULL, "pl330");
-+        assert(info->endian == BFD_ENDIAN_LITTLE);
++    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
-+        return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
++    qdev_init_nofail(dev);
-+                                            info);
++    busdev = SYS_BUS_DEVICE(dev);
-+    } else {
++    sysbus_mmio_map(busdev, 0, base);
-+        return info->read_memory_inner_func(memaddr, b, length, info);
++    sysbus_connect_irq(busdev, 0, irq);
 +    }
 +}
 +
- static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
+ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
  {
-     ARMCPU *ac = ARM_CPU(cpu);
+     Exynos4210State *s = g_new0(Exynos4210State, 1);
-@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
+@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
-         info->endian = BFD_ENDIAN_BIG;
+     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
- #endif
+             s->irq_table[exynos4210_get_irq(28, 3)]);
-     }
-+    if (info->read_memory_inner_func == NULL) {
++    /*** DMA controllers ***/
-+        info->read_memory_inner_func = info->read_memory_func;
++    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
-+        info->read_memory_func = arm_read_memory_func;
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
-+    }
++    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
-+    info->flags &= ~INSN_ARM_BE32;
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
-+    if (arm_sctlr_b(env)) {
++    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
-+        info->flags |= INSN_ARM_BE32;
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
-+    }
++
      return s;
  }
- static void arm_cpu_initfn(Object *obj)
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 02/13] wdt: Add Aspeed watchdog device model
+[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
-From: Cédric Le Goater <clg@kaod.org>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-The Aspeed SoC includes a set of watchdog timers using 32-bit
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-decrement counters, which can be based either on the APB clock or
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-a 1 MHz clock.
+Message-id: 20190520214342.13709-5-philmd@redhat.com
 The watchdog timer is designed to prevent system deadlock and, in
 general, it should be restarted before timeout. When a timeout occurs,
 different types of signals can be generated, ARM reset, SOC reset,
 System reset, CPU Interrupt, external signal or boot from alternate
 block. The current model only performs the system reset function as
 this is used by U-Boot and Linux.
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org
 [clg: - fixed compile breakage
       - fixed io region size
       - added watchdog_perform_action() on timer expiry
       - wrote a commit log
       - merged fixes from Andrew Jeffery to scale the reload value ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/watchdog/Makefile.objs        |   1 +
+ include/hw/arm/exynos4210.h |  9 +++++++--
- include/hw/watchdog/wdt_aspeed.h |  32 ++++++
+ hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
- hw/watchdog/wdt_aspeed.c         | 225 +++++++++++++++++++++++++++++++++++++++
+ hw/arm/exynos4_boards.c     |  9 ++++++---
-files changed, 258 insertions(+)
+files changed, 37 insertions(+), 9 deletions(-)
  create mode 100644 include/hw/watchdog/wdt_aspeed.h
  create mode 100644 hw/watchdog/wdt_aspeed.c
-diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/Makefile.objs
+--- a/include/hw/arm/exynos4210.h
-+++ b/hw/watchdog/Makefile.objs
++++ b/include/hw/arm/exynos4210.h
-@@ -XXX,XX +XXX,XX @@ common-obj-y += watchdog.o
+@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
- common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
+ } Exynos4210Irq;
- common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
- common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
+ typedef struct Exynos4210State {
 +common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/watchdog/wdt_aspeed.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ASPEED Watchdog Controller
 + *
 + * Copyright (C) 2016-2017 IBM Corp.
 + *
 + * This code is licensed under the GPL version 2 or later. See the
 + * COPYING file in the top-level directory.
 + */
 +#ifndef ASPEED_WDT_H
 +#define ASPEED_WDT_H
 +
 +#include "hw/sysbus.h"
 +
 +#define TYPE_ASPEED_WDT "aspeed.wdt"
 +#define ASPEED_WDT(obj) \
 +    OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
 +
 +#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
 +
 +typedef struct AspeedWDTState {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
-+    QEMUTimer *timer;
++    /*< public >*/
      ARMCPU *cpu[EXYNOS4210_NCPUS];
      Exynos4210Irq irqs;
      qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
      I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
  } Exynos4210State;
 +#define TYPE_EXYNOS4210_SOC "exynos4210"
 +#define EXYNOS4210_SOC(obj) \
 +    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
 +
-+    /*< public >*/
+ void exynos4210_write_secondary(ARMCPU *cpu,
-+    MemoryRegion iomem;
+         const struct arm_boot_info *info);
-+    uint32_t regs[ASPEED_WDT_REGS_MAX];
 -Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
 -
  /* Initialize exynos4210 IRQ subsystem stub */
  qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
      sysbus_connect_irq(busdev, 0, irq);
  }
 -Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
 +static void exynos4210_realize(DeviceState *socdev, Error **errp)
  {
 -    Exynos4210State *s = g_new0(Exynos4210State, 1);
 +    Exynos4210State *s = EXYNOS4210_SOC(socdev);
 +    MemoryRegion *system_mem = get_system_memory();
      qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
      SysBusDevice *busdev;
      DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                   qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
      pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                   qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 -
 -    return s;
  }
 +
-+    uint32_t pclk_freq;
++static void exynos4210_class_init(ObjectClass *klass, void *data)
 +} AspeedWDTState;
 +
 +#endif  /* ASPEED_WDT_H */
 diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ASPEED Watchdog Controller
 + *
 + * Copyright (C) 2016-2017 IBM Corp.
 + *
 + * This code is licensed under the GPL version 2 or later. See the
 + * COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "sysemu/watchdog.h"
 +#include "hw/sysbus.h"
 +#include "qemu/timer.h"
 +#include "hw/watchdog/wdt_aspeed.h"
 +
 +#define WDT_STATUS              (0x00 / 4)
 +#define WDT_RELOAD_VALUE        (0x04 / 4)
 +#define WDT_RESTART             (0x08 / 4)
 +#define WDT_CTRL                (0x0C / 4)
 +#define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
 +#define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
 +#define   WDT_CTRL_1MHZ_CLK             BIT(4)
 +#define   WDT_CTRL_WDT_EXT              BIT(3)
 +#define   WDT_CTRL_WDT_INTR             BIT(2)
 +#define   WDT_CTRL_RESET_SYSTEM         BIT(1)
 +#define   WDT_CTRL_ENABLE               BIT(0)
 +
 +#define WDT_TIMEOUT_STATUS      (0x10 / 4)
 +#define WDT_TIMEOUT_CLEAR       (0x14 / 4)
 +#define WDT_RESET_WDITH         (0x18 / 4)
 +
 +#define WDT_RESTART_MAGIC       0x4755
 +
 +static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
 +{
 +    return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
 +}
 +
 +static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    AspeedWDTState *s = ASPEED_WDT(opaque);
 +
 +    offset >>= 2;
 +
 +    switch (offset) {
 +    case WDT_STATUS:
 +        return s->regs[WDT_STATUS];
 +    case WDT_RELOAD_VALUE:
 +        return s->regs[WDT_RELOAD_VALUE];
 +    case WDT_RESTART:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: read from write-only reg at offset 0x%"
 +                      HWADDR_PRIx "\n", __func__, offset);
 +        return 0;
 +    case WDT_CTRL:
 +        return s->regs[WDT_CTRL];
 +    case WDT_TIMEOUT_STATUS:
 +    case WDT_TIMEOUT_CLEAR:
 +    case WDT_RESET_WDITH:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        return 0;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        return 0;
 +    }
 +
 +}
 +
 +static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
 +{
 +    uint32_t reload;
 +
 +    if (pclk) {
 +        reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
 +                          s->pclk_freq);
 +    } else {
 +        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
 +    }
 +
 +    if (aspeed_wdt_is_enabled(s)) {
 +        timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
 +    }
 +}
 +
 +static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
 +                             unsigned size)
 +{
 +    AspeedWDTState *s = ASPEED_WDT(opaque);
 +    bool enable = data & WDT_CTRL_ENABLE;
 +
 +    offset >>= 2;
 +
 +    switch (offset) {
 +    case WDT_STATUS:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: write to read-only reg at offset 0x%"
 +                      HWADDR_PRIx "\n", __func__, offset);
 +        break;
 +    case WDT_RELOAD_VALUE:
 +        s->regs[WDT_RELOAD_VALUE] = data;
 +        break;
 +    case WDT_RESTART:
 +        if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
 +            s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
 +            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
 +        }
 +        break;
 +    case WDT_CTRL:
 +        if (enable && !aspeed_wdt_is_enabled(s)) {
 +            s->regs[WDT_CTRL] = data;
 +            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
 +        } else if (!enable && aspeed_wdt_is_enabled(s)) {
 +            s->regs[WDT_CTRL] = data;
 +            timer_del(s->timer);
 +        }
 +        break;
 +    case WDT_TIMEOUT_STATUS:
 +    case WDT_TIMEOUT_CLEAR:
 +    case WDT_RESET_WDITH:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +    }
 +    return;
 +}
 +
 +static WatchdogTimerModel model = {
 +    .wdt_name = TYPE_ASPEED_WDT,
 +    .wdt_description = "Aspeed watchdog device",
 +};
 +
 +static const VMStateDescription vmstate_aspeed_wdt = {
 +    .name = "vmstate_aspeed_wdt",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_TIMER_PTR(timer, AspeedWDTState),
 +        VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static const MemoryRegionOps aspeed_wdt_ops = {
 +    .read = aspeed_wdt_read,
 +    .write = aspeed_wdt_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid.min_access_size = 4,
 +    .valid.max_access_size = 4,
 +    .valid.unaligned = false,
 +};
 +
 +static void aspeed_wdt_reset(DeviceState *dev)
 +{
 +    AspeedWDTState *s = ASPEED_WDT(dev);
 +
 +    s->regs[WDT_STATUS] = 0x3EF1480;
 +    s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
 +    s->regs[WDT_RESTART] = 0;
 +    s->regs[WDT_CTRL] = 0;
 +
 +    timer_del(s->timer);
 +}
 +
 +static void aspeed_wdt_timer_expired(void *dev)
 +{
 +    AspeedWDTState *s = ASPEED_WDT(dev);
 +
 +    qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
 +    watchdog_perform_action();
 +    timer_del(s->timer);
 +}
 +
 +#define PCLK_HZ 24000000
 +
 +static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    AspeedWDTState *s = ASPEED_WDT(dev);
 +
 +    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
 +
 +    /* FIXME: This setting should be derived from the SCU hw strapping
 +     * register SCU70
 +     */
 +    s->pclk_freq = PCLK_HZ;
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
 +                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
-+    dc->realize = aspeed_wdt_realize;
++    dc->realize = exynos4210_realize;
 +    dc->reset = aspeed_wdt_reset;
 +    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 +    dc->vmsd = &vmstate_aspeed_wdt;
 +}
 +
-+static const TypeInfo aspeed_wdt_info = {
++static const TypeInfo exynos4210_info = {
 +    .name = TYPE_EXYNOS4210_SOC,
 +    .parent = TYPE_SYS_BUS_DEVICE,
-+    .name  = TYPE_ASPEED_WDT,
++    .instance_size = sizeof(Exynos4210State),
-+    .instance_size  = sizeof(AspeedWDTState),
++    .class_init = exynos4210_class_init,
 +    .class_init = aspeed_wdt_class_init,
 +};
 +
-+static void wdt_aspeed_register_types(void)
++static void exynos4210_register_types(void)
 +{
-+    watchdog_add_model(&model);
++    type_register_static(&exynos4210_info);
 +    type_register_static(&aspeed_wdt_info);
 +}
 +
-+type_init(wdt_aspeed_register_types)
++type_init(exynos4210_register_types)
 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4_boards.c
 +++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
  } Exynos4BoardType;
  typedef struct Exynos4BoardState {
 -    Exynos4210State *soc;
 +    Exynos4210State soc;
      MemoryRegion dram0_mem;
      MemoryRegion dram1_mem;
  } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
      exynos4_boards_init_ram(s, get_system_memory(),
                              exynos4_board_ram_size[board_type]);
 -    s->soc = exynos4210_init(get_system_memory());
 +    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
 +    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
 +    object_property_set_bool(OBJECT(&s->soc), true, "realized",
 +                             &error_fatal);
      return s;
  }
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
                                                        EXYNOS4_BOARD_SMDKC210);
      lan9215_init(SMDK_LAN9118_BASE_ADDR,
 -            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
 +            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
      arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
  }
 --
-.7.4
+.20.1

-[Qemu-devel] [PULL 03/13] aspeed: add a watchdog controller
+Deleted patch
-From: Cédric Le Goater <clg@kaod.org>
-This enables reboot of a guest from U-Boot and Linux.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/aspeed_soc.h |  2 ++
- hw/arm/aspeed_soc.c         | 13 +++++++++++++
-files changed, 15 insertions(+)
-diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
-+++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/timer/aspeed_timer.h"
- #include "hw/i2c/aspeed_i2c.h"
- #include "hw/ssi/aspeed_smc.h"
-+#include "hw/watchdog/wdt_aspeed.h"
- #define ASPEED_SPIS_NUM  2
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
-     AspeedSMCState fmc;
-     AspeedSMCState spi[ASPEED_SPIS_NUM];
-     AspeedSDMCState sdmc;
-+    AspeedWDTState wdt;
- } AspeedSoCState;
- #define TYPE_ASPEED_SOC "aspeed-soc"
-diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
-+++ b/hw/arm/aspeed_soc.c
-@@ -XXX,XX +XXX,XX @@
- #define ASPEED_SOC_SCU_BASE         0x1E6E2000
- #define ASPEED_SOC_SRAM_BASE        0x1E720000
- #define ASPEED_SOC_TIMER_BASE       0x1E782000
-+#define ASPEED_SOC_WDT_BASE         0x1E785000
- #define ASPEED_SOC_I2C_BASE         0x1E78A000
- static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
-                          sc->info->silicon_rev);
-     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
-                               "ram-size", &error_abort);
-+
-+    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
-+    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
-+    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
- }
- static void aspeed_soc_realize(DeviceState *dev, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
-         return;
-     }
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
-+
-+    /* Watch dog */
-+    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
-+    if (err) {
-+        error_propagate(errp, err);
-+        return;
-+    }
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
- }
- static void aspeed_soc_class_init(ObjectClass *oc, void *data)
---
-.7.4

A random mix of items here, nothing very major.

thanks
-- PMM

The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b:

Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000)

are available in the git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207

for you to fetch changes up to 7727b832886fafbdec7299eb7773dc9071bf4cdd:

stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:30:00 +0000)

----------------------------------------------------------------
target-arm:
 * new "unimplemented" device for stubbing out devices in a
   system model so accesses can be logged
 * stellaris: document the SoC memory map
 * arm: create instruction syndromes for AArch32 data aborts
 * arm: Correctly handle watchpoints for BE32 CPUs
 * Fix Thumb-1 BE32 execution and disassembly
 * arm: Add cfgend parameter for ARM CPU selection
 * sd: sdhci: check data length during dma_memory_read
 * aspeed: add a watchdog controller
 * integratorcp: adding vmstate for save/restore

----------------------------------------------------------------
Cédric Le Goater (2):
      wdt: Add Aspeed watchdog device model
      aspeed: add a watchdog controller

Julian Brown (4):
      hw/arm/integratorcp: Support specifying features via -cpu
      target/arm: Add cfgend parameter for ARM CPU selection.
      Fix Thumb-1 BE32 execution and disassembly.
      arm: Correctly handle watchpoints for BE32 CPUs

Pavel Dovgalyuk (1):
      integratorcp: adding vmstate for save/restore

Peter Maydell (5):
      target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
      target/arm: A32, T32: Create Instruction Syndromes for Data Aborts
      stellaris: Document memory map and which SoC devices are unimplemented
      hw/misc: New "unimplemented" sysbus device
      stellaris: Use the 'unimplemented' device for parts we don't implement

Prasad J Pandit (1):
      sd: sdhci: check data length during dma_memory_read

From: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru>

VMState added by this patch preserves correct
loading of the integratorcp device state.

Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Message-id: 20170131114310.6768.79416.stgit@PASHA-ISP
[PMM: removed unnecessary minimum_version_id_old lines]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/integratorcp.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@ static uint8_t integrator_spd[128] = {
    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
 };
 
+static const VMStateDescription vmstate_integratorcm = {
+    .name = "integratorcm",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(cm_osc, IntegratorCMState),
+        VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
+        VMSTATE_UINT32(cm_lock, IntegratorCMState),
+        VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
+        VMSTATE_UINT32(cm_sdram, IntegratorCMState),
+        VMSTATE_UINT32(cm_init, IntegratorCMState),
+        VMSTATE_UINT32(cm_flags, IntegratorCMState),
+        VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
+        VMSTATE_UINT32(int_level, IntegratorCMState),
+        VMSTATE_UINT32(irq_enabled, IntegratorCMState),
+        VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
                                   unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ typedef struct icp_pic_state {
     qemu_irq parent_fiq;
 } icp_pic_state;
 
+static const VMStateDescription vmstate_icp_pic = {
+    .name = "icp_pic",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(level, icp_pic_state),
+        VMSTATE_UINT32(irq_enabled, icp_pic_state),
+        VMSTATE_UINT32(fiq_enabled, icp_pic_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static void icp_pic_update(icp_pic_state *s)
 {
     uint32_t flags;
@@ -XXX,XX +XXX,XX @@ typedef struct ICPCtrlRegsState {
 #define ICP_INTREG_WPROT        (1 << 0)
 #define ICP_INTREG_CARDIN       (1 << 3)
 
+static const VMStateDescription vmstate_icp_control = {
+    .name = "icp_control",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static uint64_t icp_control_read(void *opaque, hwaddr offset,
                                  unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void core_class_init(ObjectClass *klass, void *data)
 
     dc->props = core_properties;
     dc->realize = integratorcm_realize;
+    dc->vmsd = &vmstate_integratorcm;
+}
+
+static void icp_pic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_icp_pic;
+}
+
+static void icp_control_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_icp_control;
 }
 
 static const TypeInfo core_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_pic_info = {
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(icp_pic_state),
     .instance_init = icp_pic_init,
+    .class_init    = icp_pic_class_init,
 };
 
 static const TypeInfo icp_ctrl_regs_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo icp_ctrl_regs_info = {
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(ICPCtrlRegsState),
     .instance_init = icp_control_init,
+    .class_init    = icp_control_class_init,
 };
 
 static void integratorcp_register_types(void)
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

The Aspeed SoC includes a set of watchdog timers using 32-bit
decrement counters, which can be based either on the APB clock or
a 1 MHz clock.

The watchdog timer is designed to prevent system deadlock and, in
general, it should be restarted before timeout. When a timeout occurs,
different types of signals can be generated, ARM reset, SOC reset,
System reset, CPU Interrupt, external signal or boot from alternate
block. The current model only performs the system reset function as
this is used by U-Boot and Linux.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 1485452251-1593-2-git-send-email-clg@kaod.org
[clg: - fixed compile breakage
      - fixed io region size
      - added watchdog_perform_action() on timer expiry
      - wrote a commit log
      - merged fixes from Andrew Jeffery to scale the reload value ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/watchdog/Makefile.objs        |   1 +
 include/hw/watchdog/wdt_aspeed.h |  32 ++++++
 hw/watchdog/wdt_aspeed.c         | 225 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 258 insertions(+)
 create mode 100644 include/hw/watchdog/wdt_aspeed.h
 create mode 100644 hw/watchdog/wdt_aspeed.c

diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/Makefile.objs
+++ b/hw/watchdog/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-y += watchdog.o
 common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o
 common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o
 common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o
+common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED Watchdog Controller
+ *
+ * Copyright (C) 2016-2017 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+#ifndef ASPEED_WDT_H
+#define ASPEED_WDT_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_WDT "aspeed.wdt"
+#define ASPEED_WDT(obj) \
+    OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
+
+#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
+
+typedef struct AspeedWDTState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    QEMUTimer *timer;
+
+    /*< public >*/
+    MemoryRegion iomem;
+    uint32_t regs[ASPEED_WDT_REGS_MAX];
+
+    uint32_t pclk_freq;
+} AspeedWDTState;
+
+#endif  /* ASPEED_WDT_H */
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED Watchdog Controller
+ *
+ * Copyright (C) 2016-2017 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "sysemu/watchdog.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "hw/watchdog/wdt_aspeed.h"
+
+#define WDT_STATUS              (0x00 / 4)
+#define WDT_RELOAD_VALUE        (0x04 / 4)
+#define WDT_RESTART             (0x08 / 4)
+#define WDT_CTRL                (0x0C / 4)
+#define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
+#define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
+#define   WDT_CTRL_1MHZ_CLK             BIT(4)
+#define   WDT_CTRL_WDT_EXT              BIT(3)
+#define   WDT_CTRL_WDT_INTR             BIT(2)
+#define   WDT_CTRL_RESET_SYSTEM         BIT(1)
+#define   WDT_CTRL_ENABLE               BIT(0)
+
+#define WDT_TIMEOUT_STATUS      (0x10 / 4)
+#define WDT_TIMEOUT_CLEAR       (0x14 / 4)
+#define WDT_RESET_WDITH         (0x18 / 4)
+
+#define WDT_RESTART_MAGIC       0x4755
+
+static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
+{
+    return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
+}
+
+static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
+{
+    AspeedWDTState *s = ASPEED_WDT(opaque);
+
+    offset >>= 2;
+
+    switch (offset) {
+    case WDT_STATUS:
+        return s->regs[WDT_STATUS];
+    case WDT_RELOAD_VALUE:
+        return s->regs[WDT_RELOAD_VALUE];
+    case WDT_RESTART:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: read from write-only reg at offset 0x%"
+                      HWADDR_PRIx "\n", __func__, offset);
+        return 0;
+    case WDT_CTRL:
+        return s->regs[WDT_CTRL];
+    case WDT_TIMEOUT_STATUS:
+    case WDT_TIMEOUT_CLEAR:
+    case WDT_RESET_WDITH:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+        return 0;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+        return 0;
+    }
+
+}
+
+static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
+{
+    uint32_t reload;
+
+    if (pclk) {
+        reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
+                          s->pclk_freq);
+    } else {
+        reload = s->regs[WDT_RELOAD_VALUE] * 1000;
+    }
+
+    if (aspeed_wdt_is_enabled(s)) {
+        timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
+    }
+}
+
+static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
+                             unsigned size)
+{
+    AspeedWDTState *s = ASPEED_WDT(opaque);
+    bool enable = data & WDT_CTRL_ENABLE;
+
+    offset >>= 2;
+
+    switch (offset) {
+    case WDT_STATUS:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only reg at offset 0x%"
+                      HWADDR_PRIx "\n", __func__, offset);
+        break;
+    case WDT_RELOAD_VALUE:
+        s->regs[WDT_RELOAD_VALUE] = data;
+        break;
+    case WDT_RESTART:
+        if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
+            s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
+            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
+        }
+        break;
+    case WDT_CTRL:
+        if (enable && !aspeed_wdt_is_enabled(s)) {
+            s->regs[WDT_CTRL] = data;
+            aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
+        } else if (!enable && aspeed_wdt_is_enabled(s)) {
+            s->regs[WDT_CTRL] = data;
+            timer_del(s->timer);
+        }
+        break;
+    case WDT_TIMEOUT_STATUS:
+    case WDT_TIMEOUT_CLEAR:
+    case WDT_RESET_WDITH:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+                      __func__, offset);
+    }
+    return;
+}
+
+static WatchdogTimerModel model = {
+    .wdt_name = TYPE_ASPEED_WDT,
+    .wdt_description = "Aspeed watchdog device",
+};
+
+static const VMStateDescription vmstate_aspeed_wdt = {
+    .name = "vmstate_aspeed_wdt",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER_PTR(timer, AspeedWDTState),
+        VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const MemoryRegionOps aspeed_wdt_ops = {
+    .read = aspeed_wdt_read,
+    .write = aspeed_wdt_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 4,
+    .valid.unaligned = false,
+};
+
+static void aspeed_wdt_reset(DeviceState *dev)
+{
+    AspeedWDTState *s = ASPEED_WDT(dev);
+
+    s->regs[WDT_STATUS] = 0x3EF1480;
+    s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
+    s->regs[WDT_RESTART] = 0;
+    s->regs[WDT_CTRL] = 0;
+
+    timer_del(s->timer);
+}
+
+static void aspeed_wdt_timer_expired(void *dev)
+{
+    AspeedWDTState *s = ASPEED_WDT(dev);
+
+    qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
+    watchdog_perform_action();
+    timer_del(s->timer);
+}
+
+#define PCLK_HZ 24000000
+
+static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    AspeedWDTState *s = ASPEED_WDT(dev);
+
+    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
+
+    /* FIXME: This setting should be derived from the SCU hw strapping
+     * register SCU70
+     */
+    s->pclk_freq = PCLK_HZ;
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
+                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = aspeed_wdt_realize;
+    dc->reset = aspeed_wdt_reset;
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+    dc->vmsd = &vmstate_aspeed_wdt;
+}
+
+static const TypeInfo aspeed_wdt_info = {
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .name  = TYPE_ASPEED_WDT,
+    .instance_size  = sizeof(AspeedWDTState),
+    .class_init = aspeed_wdt_class_init,
+};
+
+static void wdt_aspeed_register_types(void)
+{
+    watchdog_add_model(&model);
+    type_register_static(&aspeed_wdt_info);
+}
+
+type_init(wdt_aspeed_register_types)
-- 
2.7.4

From: Cédric Le Goater <clg@kaod.org>

This enables reboot of a guest from U-Boot and Linux.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 1485452251-1593-3-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/aspeed_soc.h |  2 ++
 hw/arm/aspeed_soc.c         | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/timer/aspeed_timer.h"
 #include "hw/i2c/aspeed_i2c.h"
 #include "hw/ssi/aspeed_smc.h"
+#include "hw/watchdog/wdt_aspeed.h"
 
 #define ASPEED_SPIS_NUM  2
 
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState {
     AspeedSMCState fmc;
     AspeedSMCState spi[ASPEED_SPIS_NUM];
     AspeedSDMCState sdmc;
+    AspeedWDTState wdt;
 } AspeedSoCState;
 
 #define TYPE_ASPEED_SOC "aspeed-soc"
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
 #define ASPEED_SOC_SRAM_BASE        0x1E720000
 #define ASPEED_SOC_TIMER_BASE       0x1E782000
+#define ASPEED_SOC_WDT_BASE         0x1E785000
 #define ASPEED_SOC_I2C_BASE         0x1E78A000
 
 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
                          sc->info->silicon_rev);
     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
                               "ram-size", &error_abort);
+
+    object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
+    object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
+    qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
 }
 
 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
         return;
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
+
+    /* Watch dog */
+    object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
 }
 
 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-- 
2.7.4

From: Prasad J Pandit <pjp@fedoraproject.org>

While doing multi block SDMA transfer in routine
'sdhci_sdma_transfer_multi_blocks', the 's->fifo_buffer' starting
index 'begin' and data length 's->data_count' could end up to be same.
This could lead to an OOB access issue. Correct transfer data length
to avoid it.

Cc: qemu-stable@nongnu.org
Reported-by: Jiang Xin <jiangxin1@huawei.com>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20170130064736.9236-1-ppandit@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/sd/sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
                 boundary_count -= block_size - begin;
             }
             dma_memory_read(&address_space_memory, s->sdmasysad,
-                            &s->fifo_buffer[begin], s->data_count);
+                            &s->fifo_buffer[begin], s->data_count - begin);
             s->sdmasysad += s->data_count - begin;
             if (s->data_count == block_size) {
                 for (n = 0; n < block_size; n++) {
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

Since the integratorcp board creates the CPU object directly
rather than via cpu_arm_init(), we have to call the CPU
class parse_features() method ourselves if we want to
support the user passing features via the -cpu command
line argument as well as just the cpu name. Do so.

Signed-off-by: Julian Brown <julian@codesourcery.com>
[PMM: split out into its own patch]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/integratorcp.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
+    char **cpustr;
     ObjectClass *cpu_oc;
+    CPUClass *cc;
     Object *cpuobj;
     ARMCPU *cpu;
+    const char *typename;
     MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *ram = g_new(MemoryRegion, 1);
     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
     qemu_irq pic[32];
     DeviceState *dev, *sic, *icp;
     int i;
+    Error *err = NULL;
 
     if (!cpu_model) {
         cpu_model = "arm926";
     }
 
-    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
+    cpustr = g_strsplit(cpu_model, ",", 2);
+
+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
     if (!cpu_oc) {
         fprintf(stderr, "Unable to find CPU definition\n");
         exit(1);
     }
+    typename = object_class_get_name(cpu_oc);
+
+    cc = CPU_CLASS(cpu_oc);
+    cc->parse_features(typename, cpustr[1], &err);
+    g_strfreev(cpustr);
+    if (err) {
+        error_report_err(err);
+        exit(1);
+    }
 
-    cpuobj = object_new(object_class_get_name(cpu_oc));
+    cpuobj = object_new(typename);
 
     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
      * currently support EL3 so the CPU EL3 property is disabled before
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

Add a new "cfgend" property which selects whether the CPU resets into
big-endian mode or not.  This setting affects whether we reset with
SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set.

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com
[PMM: use error_report_err() rather than error_report();
 move the integratorcp changes to their own patch;
 drop an unnecessary extra #include;
 rephrase commit message accordingly;
 move setting of reset_sctlr above registration of cpregs
 so it actually has an effect]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h |  7 +++++++
 target/arm/cpu.c | 13 +++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     int gic_vpribits; /* number of virtual priority bits */
     int gic_vprebits; /* number of virtual preemption bits */
 
+    /* Whether the cfgend input is high (i.e. this CPU should reset into
+     * big-endian mode).  This setting isn't used directly: instead it modifies
+     * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
+     * architecture version.
+     */
+    bool cfgend;
+
     ARMELChangeHook *el_change_hook;
     void *el_change_hook_opaque;
 };
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el2_property =
 static Property arm_cpu_has_el3_property =
             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 
+static Property arm_cpu_cfgend_property =
+            DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
+
 /* use property name "pmu" to match other archs and virt tools */
 static Property arm_cpu_has_pmu_property =
             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_post_init(Object *obj)
         }
     }
 
+    qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
+                             &error_abort);
 }
 
 static void arm_cpu_finalizefn(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
             cpu->reset_sctlr |= (1 << 13);
     }
 
+    if (cpu->cfgend) {
+        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
+            cpu->reset_sctlr |= SCTLR_EE;
+        } else {
+            cpu->reset_sctlr |= SCTLR_B;
+        }
+    }
+
     if (!cpu->has_el3) {
         /* If the has_el3 CPU property is disabled then we need to disable the
          * feature.
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

Thumb-1 code has some issues in BE32 mode (as currently implemented). In
short, since bytes are swapped within words at load time for BE32
executables, this also swaps pairs of adjacent Thumb-1 instructions.

This patch un-swaps those pairs of instructions again, both for execution,
and for disassembly. (The previous version of the patch always read four
bytes in arm_read_memory_func and then extracted the proper two bytes,
in a probably misguided attempt to match the behaviour of actual hardware
as described by e.g. the ARM9TDMI TRM, section 3.3 "Endian effects for
instruction fetches". It's less complicated to just read the correct
two bytes though.)

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: ca20462a044848000370318a8bd41dd0a4ed273f.1484929304.git.julian@codesourcery.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/disas/bfd.h   |  7 +++++++
 target/arm/arm_ldst.h | 10 +++++++++-
 disas.c               |  1 +
 target/arm/cpu.c      | 23 +++++++++++++++++++++++
 4 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/include/disas/bfd.h b/include/disas/bfd.h
index XXXXXXX..XXXXXXX 100644
--- a/include/disas/bfd.h
+++ b/include/disas/bfd.h
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
      The bottom 16 bits are for the internal use of the disassembler.  */
   unsigned long flags;
 #define INSN_HAS_RELOC	0x80000000
+#define INSN_ARM_BE32	0x00010000
   PTR private_data;
 
   /* Function used to get bytes to disassemble.  MEMADDR is the
@@ -XXX,XX +XXX,XX @@ typedef struct disassemble_info {
     (bfd_vma memaddr, bfd_byte *myaddr, int length,
 	     struct disassemble_info *info);
 
+  /* A place to stash the real read_memory_func if read_memory_func wants to
+     do some funky address arithmetic or similar (e.g. for ARM BE32 mode).  */
+  int (*read_memory_inner_func)
+    (bfd_vma memaddr, bfd_byte *myaddr, int length,
+             struct disassemble_info *info);
+
   /* Function which should be called if we get an error that we can't
      recover from.  STATUS is the errno value from read_memory_func and
      MEMADDR is the address that we were trying to read.  INFO is a
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm_ldst.h
+++ b/target/arm/arm_ldst.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
                                      bool sctlr_b)
 {
-    uint16_t insn = cpu_lduw_code(env, addr);
+    uint16_t insn;
+#ifndef CONFIG_USER_ONLY
+    /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
+       within each word.  Undo that now.  */
+    if (sctlr_b) {
+        addr ^= 2;
+    }
+#endif
+    insn = cpu_lduw_code(env, addr);
     if (bswap_code(sctlr_b)) {
         return bswap16(insn);
     }
diff --git a/disas.c b/disas.c
index XXXXXXX..XXXXXXX 100644
--- a/disas.c
+++ b/disas.c
@@ -XXX,XX +XXX,XX @@ void target_disas(FILE *out, CPUState *cpu, target_ulong code,
 
     s.cpu = cpu;
     s.info.read_memory_func = target_read_memory;
+    s.info.read_memory_inner_func = NULL;
     s.info.buffer_vma = code;
     s.info.buffer_length = size;
     s.info.print_address_func = generic_print_address;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
   return print_insn_arm(pc | 1, info);
 }
 
+static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
+                                int length, struct disassemble_info *info)
+{
+    assert(info->read_memory_inner_func);
+    assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
+
+    if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
+        assert(info->endian == BFD_ENDIAN_LITTLE);
+        return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
+                                            info);
+    } else {
+        return info->read_memory_inner_func(memaddr, b, length, info);
+    }
+}
+
 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 {
     ARMCPU *ac = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
         info->endian = BFD_ENDIAN_BIG;
 #endif
     }
+    if (info->read_memory_inner_func == NULL) {
+        info->read_memory_inner_func = info->read_memory_func;
+        info->read_memory_func = arm_read_memory_func;
+    }
+    info->flags &= ~INSN_ARM_BE32;
+    if (arm_sctlr_b(env)) {
+        info->flags |= INSN_ARM_BE32;
+    }
 }
 
 static void arm_cpu_initfn(Object *obj)
-- 
2.7.4

From: Julian Brown <julian@codesourcery.com>

In BE32 mode, sub-word size watchpoints can fail to trigger because the
address of the access is adjusted in the opcode helpers before being
compared with the watchpoint registers.  This patch reverses the address
adjustment before performing the comparison with the help of a new CPUClass
hook.

This version of the patch augments and tidies up comments a little.

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: caaf64ffc72f6ae183015337b7afdbd4b8989cb6.1484929304.git.julian@codesourcery.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/qom/cpu.h      |  3 +++
 target/arm/internals.h |  5 +++++
 exec.c                 |  1 +
 qom/cpu.c              |  6 ++++++
 target/arm/cpu.c       |  3 +++
 target/arm/op_helper.c | 22 ++++++++++++++++++++++
 6 files changed, 40 insertions(+)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock;
  * @cpu_exec_exit: Callback for cpu_exec cleanup.
  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
  * @disas_set_info: Setup architecture specific components of disassembly info
+ * @adjust_watchpoint_address: Perform a target-specific adjustment to an
+ * address before attempting to match it against watchpoints.
  *
  * Represents a CPU family or model.
  */
@@ -XXX,XX +XXX,XX @@ typedef struct CPUClass {
     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 
     void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
+    vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
 } CPUClass;
 
 #ifdef HOST_WORDS_BIGENDIAN
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu);
 /* Callback function for checking if a watchpoint should trigger. */
 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 
+/* Adjust addresses (in BE32 mode) before testing against watchpoint
+ * addresses.
+ */
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
+
 /* Callback function for when a watchpoint or breakpoint triggers. */
 void arm_debug_excp_handler(CPUState *cs);
 
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
         return;
     }
     vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
+    vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
     QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
         if (cpu_watchpoint_address_matches(wp, vaddr, len)
             && (wp->flags & flags)) {
diff --git a/qom/cpu.c b/qom/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
     return cpu->cpu_index;
 }
 
+static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
+{
+    return addr;
+}
+
 static void cpu_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
     k->cpu_exec_enter = cpu_common_noop;
     k->cpu_exec_exit = cpu_common_noop;
     k->cpu_exec_interrupt = cpu_common_exec_interrupt;
+    k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
     dc->realize = cpu_common_realizefn;
     dc->unrealize = cpu_common_unrealizefn;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->gdb_stop_before_watchpoint = true;
     cc->debug_excp_handler = arm_debug_excp_handler;
     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
+#if !defined(CONFIG_USER_ONLY)
+    cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+#endif
 
     cc->disas_set_info = arm_disas_set_info;
 }
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
     return check_watchpoints(cpu);
 }
 
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+
+    /* In BE32 system mode, target memory is stored byteswapped (on a
+     * little-endian host system), and by the time we reach here (via an
+     * opcode helper) the addresses of subword accesses have been adjusted
+     * to account for that, which means that watchpoints will not match.
+     * Undo the adjustment here.
+     */
+    if (arm_sctlr_b(env)) {
+        if (len == 1) {
+            addr ^= 3;
+        } else if (len == 2) {
+            addr ^= 2;
+        }
+    }
+
+    return addr;
+}
+
 void arm_debug_excp_handler(CPUState *cs)
 {
     /* Called by core code when a watchpoint or breakpoint fires;
-- 
2.7.4

In the ARM ldr/str decode path, rather than directly testing
"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
bits out into wbit and pbit local flags. (We will want to
do more tests against them to determine whether we need to
provide syndrome information.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/arm/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             } else {
                 int address_offset;
                 bool load = insn & (1 << 20);
+                bool wbit = insn & (1 << 21);
+                bool pbit = insn & (1 << 24);
                 bool doubleword = false;
                 /* Misc load/store */
                 rn = (insn >> 16) & 0xf;
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 }
 
                 addr = load_reg(s, rn);
-                if (insn & (1 << 24))
+                if (pbit) {
                     gen_add_datah_offset(s, insn, 0, addr);
+                }
                 address_offset = 0;
 
                 if (doubleword) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                    ensure correct behavior with overlapping index registers.
                    ldrd with base writeback is undefined if the
                    destination and index registers overlap.  */
-                if (!(insn & (1 << 24))) {
+                if (!pbit) {
                     gen_add_datah_offset(s, insn, address_offset, addr);
                     store_reg(s, rn, addr);
-                } else if (insn & (1 << 21)) {
+                } else if (wbit) {
                     if (address_offset)
                         tcg_gen_addi_i32(addr, addr, address_offset);
                     store_reg(s, rn, addr);
-- 
2.7.4

Add support for generating the ISS (Instruction Specific Syndrome)
for Data Abort exceptions taken from AArch32. These syndromes are
used by hypervisors for example to trap and emulate memory accesses.

This is the equivalent for AArch32 guests of the work done for AArch64
guests in commit aaa1f954d4cab243.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/arm/translate.h     |  14 ++++
 target/arm/translate-a64.c |  14 ----
 target/arm/translate.c     | 184 +++++++++++++++++++++++++++++++++------------
 3 files changed, 149 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int default_exception_el(DisasContext *s)
             ? 3 : MAX(1, s->current_el);
 }
 
+static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+{
+    /* We don't need to save all of the syndrome so we mask and shift
+     * out unneeded bits to help the sleb128 encoder do a better job.
+     */
+    syn &= ARM_INSN_START_WORD2_MASK;
+    syn >>= ARM_INSN_START_WORD2_SHIFT;
+
+    /* We check and clear insn_start_idx to catch multiple updates.  */
+    assert(s->insn_start_idx != 0);
+    tcg_set_insn_param(s->insn_start_idx, 2, syn);
+    s->insn_start_idx = 0;
+}
+
 /* target-specific extra values for is_jmp */
 /* These instructions trap after executing, so the A32/T32 decoder must
  * defer them until after the conditional execution state has been updated.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
     }
 }
 
-static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
-{
-    /* We don't need to save all of the syndrome so we mask and shift
-     * out uneeded bits to help the sleb128 encoder do a better job.
-     */
-    syn &= ARM_INSN_START_WORD2_MASK;
-    syn >>= ARM_INSN_START_WORD2_SHIFT;
-
-    /* We check and clear insn_start_idx to catch multiple updates.  */
-    assert(s->insn_start_idx != 0);
-    tcg_set_insn_param(s->insn_start_idx, 2, syn);
-    s->insn_start_idx = 0;
-}
-
 static void unallocated_encoding(DisasContext *s)
 {
     /* Unallocated and reserved encodings are uncategorized */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+/* Flags for the disas_set_da_iss info argument:
+ * lower bits hold the Rt register number, higher bits are flags.
+ */
+typedef enum ISSInfo {
+    ISSNone = 0,
+    ISSRegMask = 0x1f,
+    ISSInvalid = (1 << 5),
+    ISSIsAcqRel = (1 << 6),
+    ISSIsWrite = (1 << 7),
+    ISSIs16Bit = (1 << 8),
+} ISSInfo;
+
+/* Save the syndrome information for a Data Abort */
+static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issinfo)
+{
+    uint32_t syn;
+    int sas = memop & MO_SIZE;
+    bool sse = memop & MO_SIGN;
+    bool is_acqrel = issinfo & ISSIsAcqRel;
+    bool is_write = issinfo & ISSIsWrite;
+    bool is_16bit = issinfo & ISSIs16Bit;
+    int srt = issinfo & ISSRegMask;
+
+    if (issinfo & ISSInvalid) {
+        /* Some callsites want to conditionally provide ISS info,
+         * eg "only if this was not a writeback"
+         */
+        return;
+    }
+
+    if (srt == 15) {
+        /* For AArch32, insns where the src/dest is R15 never generate
+         * ISS information. Catching that here saves checking at all
+         * the call sites.
+         */
+        return;
+    }
+
+    syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel,
+                                  0, 0, 0, is_write, 0, is_16bit);
+    disas_set_insn_syndrome(s, syn);
+}
+
 static inline ARMMMUIdx get_a32_user_mem_index(DisasContext *s)
 {
     /* Return the mmu_idx to use for A32/T32 "unprivileged load/store"
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val,      \
                                      TCGv_i32 a32, int index)            \
 {                                                                        \
     gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
+}                                                                        \
+static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s,              \
+                                           TCGv_i32 val,                 \
+                                           TCGv_i32 a32, int index,      \
+                                           ISSInfo issinfo)              \
+{                                                                        \
+    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \
+    disas_set_da_iss(s, OPC, issinfo);                                   \
 }
 
 #define DO_GEN_ST(SUFF, OPC)                                             \
@@ -XXX,XX +XXX,XX @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val,      \
                                      TCGv_i32 a32, int index)            \
 {                                                                        \
     gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
+}                                                                        \
+static inline void gen_aa32_st##SUFF##_iss(DisasContext *s,              \
+                                           TCGv_i32 val,                 \
+                                           TCGv_i32 a32, int index,      \
+                                           ISSInfo issinfo)              \
+{                                                                        \
+    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \
+    disas_set_da_iss(s, OPC, issinfo | ISSIsWrite);                      \
 }
 
 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                 tmp = tcg_temp_new_i32();
                                 switch (op1) {
                                 case 0: /* lda */
-                                    gen_aa32_ld32u(s, tmp, addr,
-                                                   get_mem_index(s));
+                                    gen_aa32_ld32u_iss(s, tmp, addr,
+                                                       get_mem_index(s),
+                                                       rd | ISSIsAcqRel);
                                     break;
                                 case 2: /* ldab */
-                                    gen_aa32_ld8u(s, tmp, addr,
-                                                  get_mem_index(s));
+                                    gen_aa32_ld8u_iss(s, tmp, addr,
+                                                      get_mem_index(s),
+                                                      rd | ISSIsAcqRel);
                                     break;
                                 case 3: /* ldah */
-                                    gen_aa32_ld16u(s, tmp, addr,
-                                                   get_mem_index(s));
+                                    gen_aa32_ld16u_iss(s, tmp, addr,
+                                                       get_mem_index(s),
+                                                       rd | ISSIsAcqRel);
                                     break;
                                 default:
                                     abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                 tmp = load_reg(s, rm);
                                 switch (op1) {
                                 case 0: /* stl */
-                                    gen_aa32_st32(s, tmp, addr,
-                                                  get_mem_index(s));
+                                    gen_aa32_st32_iss(s, tmp, addr,
+                                                      get_mem_index(s),
+                                                      rm | ISSIsAcqRel);
                                     break;
                                 case 2: /* stlb */
-                                    gen_aa32_st8(s, tmp, addr,
-                                                 get_mem_index(s));
+                                    gen_aa32_st8_iss(s, tmp, addr,
+                                                     get_mem_index(s),
+                                                     rm | ISSIsAcqRel);
                                     break;
                                 case 3: /* stlh */
-                                    gen_aa32_st16(s, tmp, addr,
-                                                  get_mem_index(s));
+                                    gen_aa32_st16_iss(s, tmp, addr,
+                                                      get_mem_index(s),
+                                                      rm | ISSIsAcqRel);
                                     break;
                                 default:
                                     abort();
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 bool wbit = insn & (1 << 21);
                 bool pbit = insn & (1 << 24);
                 bool doubleword = false;
+                ISSInfo issinfo;
+
                 /* Misc load/store */
                 rn = (insn >> 16) & 0xf;
                 rd = (insn >> 12) & 0xf;
 
+                /* ISS not valid if writeback */
+                issinfo = (pbit & !wbit) ? rd : ISSInvalid;
+
                 if (!load && (sh & 2)) {
                     /* doubleword */
                     ARCH(5TE);
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     tmp = tcg_temp_new_i32();
                     switch (sh) {
                     case 1:
-                        gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+                        gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
+                                           issinfo);
                         break;
                     case 2:
-                        gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
+                        gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s),
+                                          issinfo);
                         break;
                     default:
                     case 3:
-                        gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
+                        gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s),
+                                           issinfo);
                         break;
                     }
                 } else {
                     /* store */
                     tmp = load_reg(s, rd);
-                    gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+                    gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo);
                     tcg_temp_free_i32(tmp);
                 }
                 /* Perform base writeback before the loaded value to
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                 /* load */
                 tmp = tcg_temp_new_i32();
                 if (insn & (1 << 22)) {
-                    gen_aa32_ld8u(s, tmp, tmp2, i);
+                    gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd);
                 } else {
-                    gen_aa32_ld32u(s, tmp, tmp2, i);
+                    gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd);
                 }
             } else {
                 /* store */
                 tmp = load_reg(s, rd);
                 if (insn & (1 << 22)) {
-                    gen_aa32_st8(s, tmp, tmp2, i);
+                    gen_aa32_st8_iss(s, tmp, tmp2, i, rd);
                 } else {
-                    gen_aa32_st32(s, tmp, tmp2, i);
+                    gen_aa32_st32_iss(s, tmp, tmp2, i, rd);
                 }
                 tcg_temp_free_i32(tmp);
             }
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         tmp = tcg_temp_new_i32();
                         switch (op) {
                         case 0: /* ldab */
-                            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s),
+                                              rs | ISSIsAcqRel);
                             break;
                         case 1: /* ldah */
-                            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s),
+                                               rs | ISSIsAcqRel);
                             break;
                         case 2: /* lda */
-                            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
+                                               rs | ISSIsAcqRel);
                             break;
                         default:
                             abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                         tmp = load_reg(s, rs);
                         switch (op) {
                         case 0: /* stlb */
-                            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s),
+                                             rs | ISSIsAcqRel);
                             break;
                         case 1: /* stlh */
-                            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s),
+                                              rs | ISSIsAcqRel);
                             break;
                         case 2: /* stl */
-                            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+                            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s),
+                                              rs | ISSIsAcqRel);
                             break;
                         default:
                             abort();
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
         int postinc = 0;
         int writeback = 0;
         int memidx;
+        ISSInfo issinfo;
+
         if ((insn & 0x01100000) == 0x01000000) {
             if (disas_neon_ls_insn(s, insn)) {
                 goto illegal_op;
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
                 }
             }
         }
+
+        issinfo = writeback ? ISSInvalid : rs;
+
         if (insn & (1 << 20)) {
             /* Load.  */
             tmp = tcg_temp_new_i32();
             switch (op) {
             case 0:
-                gen_aa32_ld8u(s, tmp, addr, memidx);
+                gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 4:
-                gen_aa32_ld8s(s, tmp, addr, memidx);
+                gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 1:
-                gen_aa32_ld16u(s, tmp, addr, memidx);
+                gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 5:
-                gen_aa32_ld16s(s, tmp, addr, memidx);
+                gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 2:
-                gen_aa32_ld32u(s, tmp, addr, memidx);
+                gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo);
                 break;
             default:
                 tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
             tmp = load_reg(s, rs);
             switch (op) {
             case 0:
-                gen_aa32_st8(s, tmp, addr, memidx);
+                gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 1:
-                gen_aa32_st16(s, tmp, addr, memidx);
+                gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo);
                 break;
             case 2:
-                gen_aa32_st32(s, tmp, addr, memidx);
+                gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo);
                 break;
             default:
                 tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
             addr = tcg_temp_new_i32();
             tcg_gen_movi_i32(addr, val);
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
+                               rd | ISSIs16Bit);
             tcg_temp_free_i32(addr);
             store_reg(s, rd, tmp);
             break;
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 
         switch (op) {
         case 0: /* str */
-            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 1: /* strh */
-            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 2: /* strb */
-            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 3: /* ldrsb */
-            gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 4: /* ldr */
-            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 5: /* ldrh */
-            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 6: /* ldrb */
-            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         case 7: /* ldrsh */
-            gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             break;
         }
         if (op >= 3) { /* load */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         if (insn & (1 << 11)) {
             /* load */
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             store_reg(s, rd, tmp);
         } else {
             /* store */
             tmp = load_reg(s, rd);
-            gen_aa32_st8(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             tcg_temp_free_i32(tmp);
         }
         tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         if (insn & (1 << 11)) {
             /* load */
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             store_reg(s, rd, tmp);
         } else {
             /* store */
             tmp = load_reg(s, rd);
-            gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             tcg_temp_free_i32(tmp);
         }
         tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
         if (insn & (1 << 11)) {
             /* load */
             tmp = tcg_temp_new_i32();
-            gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             store_reg(s, rd, tmp);
         } else {
             /* store */
             tmp = load_reg(s, rd);
-            gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+            gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
             tcg_temp_free_i32(tmp);
         }
         tcg_temp_free_i32(addr);
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
         store_cpu_field(tmp, condexec_bits);
       }
     do {
+        dc->insn_start_idx = tcg_op_buf_count();
         tcg_gen_insn_start(dc->pc,
                            (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
                            0);
-- 
2.7.4

Add a comment documenting the memory map of the SoC devices and which
are not implemented.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1484247815-15279-2-git-send-email-peter.maydell@linaro.org
---
 hw/arm/stellaris.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
         0x40024000, 0x40025000, 0x40026000};
     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
 
+    /* Memory map of SoC devices, from
+     * Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
+     * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
+     *
+     * 40000000 wdtimer (unimplemented)
+     * 40002000 i2c (unimplemented)
+     * 40004000 GPIO
+     * 40005000 GPIO
+     * 40006000 GPIO
+     * 40007000 GPIO
+     * 40008000 SSI
+     * 4000c000 UART
+     * 4000d000 UART
+     * 4000e000 UART
+     * 40020000 i2c
+     * 40021000 i2c (unimplemented)
+     * 40024000 GPIO
+     * 40025000 GPIO
+     * 40026000 GPIO
+     * 40028000 PWM (unimplemented)
+     * 4002c000 QEI (unimplemented)
+     * 4002d000 QEI (unimplemented)
+     * 40030000 gptimer
+     * 40031000 gptimer
+     * 40032000 gptimer
+     * 40033000 gptimer
+     * 40038000 ADC
+     * 4003c000 analogue comparator (unimplemented)
+     * 40048000 ethernet
+     * 400fc000 hibernation module (unimplemented)
+     * 400fd000 flash memory control (unimplemented)
+     * 400fe000 system control
+     */
+
     DeviceState *gpio_dev[7], *nvic;
     qemu_irq gpio_in[7][8];
     qemu_irq gpio_out[7][8];
-- 
2.7.4

Create a new "unimplemented" sysbus device, which simply accepts
all read and write accesses, and implements them as read-as-zero,
write-ignored, with logging of the access as LOG_UNIMP.

This is useful for stubbing out bits of an SoC or board model
which haven't been written yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1484247815-15279-3-git-send-email-peter.maydell@linaro.org
---
 hw/misc/Makefile.objs   |   2 +
 include/hw/misc/unimp.h |  39 ++++++++++++++++++
 hw/misc/unimp.c         | 107 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 148 insertions(+)
 create mode 100644 include/hw/misc/unimp.h
 create mode 100644 hw/misc/unimp.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
 common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
 common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
 
+common-obj-y += unimp.o
+
 obj-$(CONFIG_VMPORT) += vmport.o
 
 # ARM devices
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/unimp.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * "Unimplemented" device
+ *
+ * Copyright Linaro Limited, 2017
+ * Written by Peter Maydell
+ */
+
+#ifndef HW_MISC_UNIMP_H
+#define HW_MISC_UNIMP_H
+
+#define TYPE_UNIMPLEMENTED_DEVICE "unimplemented-device"
+
+/**
+ * create_unimplemented_device: create and map a dummy device
+ * @name: name of the device for debug logging
+ * @base: base address of the device's MMIO region
+ * @size: size of the device's MMIO region
+ *
+ * This utility function creates and maps an instance of unimplemented-device,
+ * which is a dummy device which simply logs all guest accesses to
+ * it via the qemu_log LOG_UNIMP debug log.
+ * The device is mapped at priority -1000, which means that you can
+ * use it to cover a large region and then map other devices on top of it
+ * if necessary.
+ */
+static inline void create_unimplemented_device(const char *name,
+                                               hwaddr base,
+                                               hwaddr size)
+{
+    DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
+
+    qdev_prop_set_string(dev, "name", name);
+    qdev_prop_set_uint64(dev, "size", size);
+    qdev_init_nofail(dev);
+
+    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, base, -1000);
+}
+
+#endif
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/unimp.c
@@ -XXX,XX +XXX,XX @@
+/* "Unimplemented" device
+ *
+ * This is a dummy device which accepts and logs all accesses.
+ * It's useful for stubbing out regions of an SoC or board
+ * map which correspond to devices that have not yet been
+ * implemented. This is often sufficient to placate initial
+ * guest device driver probing such that the system will
+ * come up.
+ *
+ * Copyright Linaro Limited, 2017
+ * Written by Peter Maydell
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/unimp.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+
+#define UNIMPLEMENTED_DEVICE(obj) \
+    OBJECT_CHECK(UnimplementedDeviceState, (obj), TYPE_UNIMPLEMENTED_DEVICE)
+
+typedef struct {
+    SysBusDevice parent_obj;
+    MemoryRegion iomem;
+    char *name;
+    uint64_t size;
+} UnimplementedDeviceState;
+
+static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
+{
+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
+
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+                  "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+                  s->name, size, offset);
+    return 0;
+}
+
+static void unimp_write(void *opaque, hwaddr offset,
+                        uint64_t value, unsigned size)
+{
+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
+
+    qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+                  "(size %d, value 0x%" PRIx64
+                  ", offset 0x%" HWADDR_PRIx ")\n",
+                  s->name, size, value, offset);
+}
+
+static const MemoryRegionOps unimp_ops = {
+    .read = unimp_read,
+    .write = unimp_write,
+    .impl.min_access_size = 1,
+    .impl.max_access_size = 8,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 8,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void unimp_realize(DeviceState *dev, Error **errp)
+{
+    UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(dev);
+
+    if (s->size == 0) {
+        error_setg(errp, "property 'size' not specified or zero");
+        return;
+    }
+
+    if (s->name == NULL) {
+        error_setg(errp, "property 'name' not specified");
+        return;
+    }
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
+                          s->name, s->size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static Property unimp_properties[] = {
+    DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0),
+    DEFINE_PROP_STRING("name", UnimplementedDeviceState, name),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void unimp_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = unimp_realize;
+    dc->props = unimp_properties;
+}
+
+static const TypeInfo unimp_info = {
+    .name = TYPE_UNIMPLEMENTED_DEVICE,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(UnimplementedDeviceState),
+    .class_init = unimp_class_init,
+};
+
+static void unimp_register_types(void)
+{
+    type_register_static(&unimp_info);
+}
+
+type_init(unimp_register_types)
-- 
2.7.4

Use the 'unimplemented' dummy device to cover regions of the
SoC device memory map which we don't have proper device
implementations for yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1484247815-15279-4-git-send-email-peter.maydell@linaro.org
---
 hw/arm/stellaris.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
 #include "hw/char/pl011.h"
+#include "hw/misc/unimp.h"
 
 #define GPIO_A 0
 #define GPIO_B 1
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
             }
         }
     }
+
+    /* Add dummy regions for the devices we don't implement yet,
+     * so guest accesses don't cause unlogged crashes.
+     */
+    create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
+    create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
+    create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
+    create_unimplemented_device("PWM", 0x40028000, 0x1000);
+    create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
+    create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
+    create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
+    create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
+    create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
 }
 
 /* FIXME: Figure out how to generate these from stellaris_boards.  */
-- 
2.7.4

Not very much here, but several people have fallen over
the vector operation segfault bug, so let's get the fix
into master.

thanks
-- PMM

The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:

Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523

for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:

hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)

----------------------------------------------------------------
target-arm queue:
 * exynos4210: QOM'ify the Exynos4210 SoC
 * exynos4210: Add DMA support for the Exynos4210
 * arm_gicv3: Fix writes to ICC_CTLR_EL3
 * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
 * target/arm: Fix vector operation segfault
 * target/arm: Minor improvements to BFXIL, EXTR

----------------------------------------------------------------
Alistair Francis (1):
      target/arm: Fix vector operation segfault

Guenter Roeck (1):
      hw/arm/exynos4210: Add DMA support for the Exynos4210

Peter Maydell (5):
      arm: Move system_clock_scale to armv7m_systick.h
      arm: Remove unnecessary includes of hw/arm/arm.h
      arm: Rename hw/arm/arm.h to hw/arm/boot.h
      hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
      hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3

Philippe Mathieu-Daudé (3):
      hw/arm/exynos4: Remove unuseful debug code
      hw/arm/exynos4: Use the IEC binary prefix definitions
      hw/arm/exynos4210: QOM'ify the Exynos4210 SoC

Richard Henderson (2):
      target/arm: Use extract2 for EXTR
      target/arm: Simplify BFXIL expansion

include/hw/arm/allwinner-a10.h    |  2 +-
 include/hw/arm/aspeed_soc.h       |  1 -
 include/hw/arm/bcm2836.h          |  1 -
 include/hw/arm/{arm.h => boot.h}  | 12 +++------
 include/hw/arm/exynos4210.h       |  9 +++++--
 include/hw/arm/fsl-imx25.h        |  2 +-
 include/hw/arm/fsl-imx31.h        |  2 +-
 include/hw/arm/fsl-imx6.h         |  2 +-
 include/hw/arm/fsl-imx6ul.h       |  2 +-
 include/hw/arm/fsl-imx7.h         |  2 +-
 include/hw/arm/virt.h             |  2 +-
 include/hw/arm/xlnx-versal.h      |  2 +-
 include/hw/arm/xlnx-zynqmp.h      |  2 +-
 include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
 hw/arm/armsse.c                   |  2 +-
 hw/arm/armv7m.c                   |  2 +-
 hw/arm/aspeed.c                   |  2 +-
 hw/arm/boot.c                     |  2 +-
 hw/arm/collie.c                   |  2 +-
 hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
 hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
 hw/arm/highbank.c                 |  2 +-
 hw/arm/integratorcp.c             |  2 +-
 hw/arm/mainstone.c                |  2 +-
 hw/arm/microbit.c                 |  2 +-
 hw/arm/mps2-tz.c                  |  2 +-
 hw/arm/mps2.c                     |  2 +-
 hw/arm/msf2-soc.c                 |  1 -
 hw/arm/msf2-som.c                 |  2 +-
 hw/arm/musca.c                    |  2 +-
 hw/arm/musicpal.c                 |  2 +-
 hw/arm/netduino2.c                |  2 +-
 hw/arm/nrf51_soc.c                |  2 +-
 hw/arm/nseries.c                  |  2 +-
 hw/arm/omap1.c                    |  2 +-
 hw/arm/omap2.c                    |  2 +-
 hw/arm/omap_sx1.c                 |  2 +-
 hw/arm/palm.c                     |  2 +-
 hw/arm/raspi.c                    |  2 +-
 hw/arm/realview.c                 |  2 +-
 hw/arm/spitz.c                    |  2 +-
 hw/arm/stellaris.c                |  2 +-
 hw/arm/stm32f205_soc.c            |  2 +-
 hw/arm/strongarm.c                |  2 +-
 hw/arm/tosa.c                     |  2 +-
 hw/arm/versatilepb.c              |  2 +-
 hw/arm/vexpress.c                 |  2 +-
 hw/arm/virt.c                     |  2 +-
 hw/arm/xilinx_zynq.c              |  2 +-
 hw/arm/xlnx-versal.c              |  2 +-
 hw/arm/z2.c                       |  2 +-
 hw/intc/arm_gicv3_cpuif.c         |  6 ++---
 hw/intc/armv7m_nvic.c             |  1 -
 target/arm/arm-semi.c             |  1 -
 target/arm/cpu.c                  |  1 -
 target/arm/cpu64.c                |  1 -
 target/arm/kvm.c                  |  1 -
 target/arm/kvm32.c                |  1 -
 target/arm/kvm64.c                |  1 -
 target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
 target/arm/translate.c            |  4 +--
 61 files changed, 164 insertions(+), 123 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (96%)

From: Richard Henderson <richard.henderson@linaro.org>

This is, after all, how we implement extract2 in tcg/aarch64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
             } else {
                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
             }
-        } else if (rm == rn) { /* ROR */
-            tcg_rm = cpu_reg(s, rm);
-            if (sf) {
-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
-            } else {
-                TCGv_i32 tmp = tcg_temp_new_i32();
-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
-                tcg_gen_rotri_i32(tmp, tmp, imm);
-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
-                tcg_temp_free_i32(tmp);
-            }
         } else {
-            tcg_rm = read_cpu_reg(s, rm, sf);
-            tcg_rn = read_cpu_reg(s, rn, sf);
-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-            if (!sf) {
-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+            tcg_rm = cpu_reg(s, rm);
+            tcg_rn = cpu_reg(s, rn);
+
+            if (sf) {
+                /* Specialization to ROR happens in EXTRACT2.  */
+                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
+            } else {
+                TCGv_i32 t0 = tcg_temp_new_i32();
+
+                tcg_gen_extrl_i64_i32(t0, tcg_rm);
+                if (rm == rn) {
+                    tcg_gen_rotri_i32(t0, t0, imm);
+                } else {
+                    TCGv_i32 t1 = tcg_temp_new_i32();
+                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
+                    tcg_gen_extract2_i32(t0, t0, t1, imm);
+                    tcg_temp_free_i32(t1);
+                }
+                tcg_gen_extu_i32_i64(tcg_rd, t0);
+                tcg_temp_free_i32(t0);
             }
         }
     }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The mask implied by the extract is redundant with the one
implied by the deposit.  Also, fix spelling of BFXIL.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

From: Alistair Francis <alistair.francis@wdc.com>

Commit 89e68b575 "target/arm: Use vector operations for saturation"
causes this abort() when booting QEMU ARM with a Cortex-A15:

0  0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
1  0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
2  0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
3  0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
4  0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
5  0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
6  0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
7  0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
8  0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
9  0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.

This patch ensures that we don't hit the abort() in the second switch
case in disas_neon_data_insn() as we will return from the first case.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqadd_op : sqadd_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VQSUB:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqsub_op : sqsub_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VMUL: /* VMUL */
             if (u) {
-- 
2.20.1

The system_clock_scale global is used only by the armv7m systick
device; move the extern declaration to the armv7m_systick.h header,
and expand the comment to explain what it is and that it should
ideally be replaced with a different approach.

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-/* Multiplication factor to convert from system clock ticks to qemu timer
-   ticks.  */
-extern int system_clock_scale;
-
 #endif /* HW_ARM_H */
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
     qemu_irq irq;
 } SysTickState;
 
+/*
+ * Multiplication factor to convert from system clock ticks to qemu timer
+ * ticks. This should be set (by board code, usually) to a value
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
+ * in Hz of the CPU.
+ *
+ * This value is used by the systick device when it is running in
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
+ * set how fast the timer should tick.
+ *
+ * TODO: we should refactor this so that rather than using a global
+ * we use a device property or something similar. This is complicated
+ * because (a) the property would need to be plumbed through from the
+ * board code down through various layers to the systick device
+ * and (b) the property needs to be modifiable after realize, because
+ * the stellaris board uses this to implement the behaviour where the
+ * guest can reprogram the PLL registers to downclock the CPU, and the
+ * systick device needs to react accordingly. Possibly this should
+ * be deferred until we have a good API for modelling clock trees.
+ */
+extern int system_clock_scale;
+
 #endif
-- 
2.20.1

The hw/arm/arm.h header now only includes declarations relating
to boot.c code, so it is only needed by Arm board or SoC code.
Remove some unnecessary inclusions of it from target/arm files
and from hw/intc/armv7m_nvic.c.

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
-#include "hw/arm/arm.h"
 #include "hw/intc/armv7m_nvic.h"
 #include "target/arm/cpu.h"
 #include "exec/exec-all.h"
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@
 #else
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
-#include "hw/arm/arm.h"
 #include "qemu/cutils.h"
 #endif
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/hw_accel.h"
 #include "kvm_arm.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "trace.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "hw/pci/pci.h"
 #include "exec/memattrs.h"
 #include "exec/address-spaces.h"
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "qemu/log.h"
 
 static inline void set_feature(uint64_t *features, int feature)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 
 static bool have_guest_debug;
 
-- 
2.20.1

The header file hw/arm/arm.h now includes only declarations
relating to hw/arm/boot.c functionality. Rename it accordingly,
and adjust its header comment.

The bulk of this commit was created via
 perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h

In a few cases we can just delete the #include:
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
include/hw/arm/bcm2836.h did not require it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
---
 include/hw/arm/allwinner-a10.h   | 2 +-
 include/hw/arm/aspeed_soc.h      | 1 -
 include/hw/arm/bcm2836.h         | 1 -
 include/hw/arm/{arm.h => boot.h} | 8 ++++----
 include/hw/arm/fsl-imx25.h       | 2 +-
 include/hw/arm/fsl-imx31.h       | 2 +-
 include/hw/arm/fsl-imx6.h        | 2 +-
 include/hw/arm/fsl-imx6ul.h      | 2 +-
 include/hw/arm/fsl-imx7.h        | 2 +-
 include/hw/arm/virt.h            | 2 +-
 include/hw/arm/xlnx-versal.h     | 2 +-
 include/hw/arm/xlnx-zynqmp.h     | 2 +-
 hw/arm/armsse.c                  | 2 +-
 hw/arm/armv7m.c                  | 2 +-
 hw/arm/aspeed.c                  | 2 +-
 hw/arm/boot.c                    | 2 +-
 hw/arm/collie.c                  | 2 +-
 hw/arm/exynos4210.c              | 2 +-
 hw/arm/exynos4_boards.c          | 2 +-
 hw/arm/highbank.c                | 2 +-
 hw/arm/integratorcp.c            | 2 +-
 hw/arm/mainstone.c               | 2 +-
 hw/arm/microbit.c                | 2 +-
 hw/arm/mps2-tz.c                 | 2 +-
 hw/arm/mps2.c                    | 2 +-
 hw/arm/msf2-soc.c                | 1 -
 hw/arm/msf2-som.c                | 2 +-
 hw/arm/musca.c                   | 2 +-
 hw/arm/musicpal.c                | 2 +-
 hw/arm/netduino2.c               | 2 +-
 hw/arm/nrf51_soc.c               | 2 +-
 hw/arm/nseries.c                 | 2 +-
 hw/arm/omap1.c                   | 2 +-
 hw/arm/omap2.c                   | 2 +-
 hw/arm/omap_sx1.c                | 2 +-
 hw/arm/palm.c                    | 2 +-
 hw/arm/raspi.c                   | 2 +-
 hw/arm/realview.c                | 2 +-
 hw/arm/spitz.c                   | 2 +-
 hw/arm/stellaris.c               | 2 +-
 hw/arm/stm32f205_soc.c           | 2 +-
 hw/arm/strongarm.c               | 2 +-
 hw/arm/tosa.c                    | 2 +-
 hw/arm/versatilepb.c             | 2 +-
 hw/arm/vexpress.c                | 2 +-
 hw/arm/virt.c                    | 2 +-
 hw/arm/xilinx_zynq.c             | 2 +-
 hw/arm/xlnx-versal.c             | 2 +-
 hw/arm/z2.c                      | 2 +-
 49 files changed, 49 insertions(+), 52 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (98%)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "qemu/error-report.h"
 #include "hw/char/serial.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/timer/allwinner-a10-pit.h"
 #include "hw/intc/allwinner-a10-pic.h"
 #include "hw/net/allwinner_emac.h"
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef ASPEED_SOC_H
 #define ASPEED_SOC_H
 
-#include "hw/arm/arm.h"
 #include "hw/intc/aspeed_vic.h"
 #include "hw/misc/aspeed_scu.h"
 #include "hw/misc/aspeed_sdmc.h"
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #ifndef BCM2836_H
 #define BCM2836_H
 
-#include "hw/arm/arm.h"
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
similarity index 98%
rename from include/hw/arm/arm.h
rename to include/hw/arm/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/boot.h
@@ -XXX,XX +XXX,XX @@
 /*
- * Misc ARM declarations
+ * ARM kernel loader.
  *
  * Copyright (c) 2006 CodeSourcery.
  * Written by Paul Brook
@@ -XXX,XX +XXX,XX @@
  *
  */
 
-#ifndef HW_ARM_H
-#define HW_ARM_H
+#ifndef HW_ARM_BOOT_H
+#define HW_ARM_BOOT_H
 
 #include "exec/memory.h"
 #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-#endif /* HW_ARM_H */
+#endif /* HW_ARM_BOOT_H */
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX25_H
 #define FSL_IMX25_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx25_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX31_H
 #define FSL_IMX31_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx31_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6_H
 #define FSL_IMX6_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/misc/imx6_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6UL_H
 #define FSL_IMX6UL_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX7_H
 #define FSL_IMX7_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/misc/imx7_ccm.h"
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/kvm.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #define XLNX_VERSAL_H
 
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gicv3.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #ifndef XLNX_ZYNQMP_H
 
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/registerfields.h"
 #include "hw/arm/armsse.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 /* Format of the System Information block SYS_CONFIG register */
 typedef enum SysConfigFormat {
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "elf.h"
 #include "sysemu/qtest.h"
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "exec/address-spaces.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/boards.h"
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include <libfdt.h>
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/linux-boot-if.h"
 #include "sysemu/kvm.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "strongarm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/sd/sdhci.h"
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
 #include "net/net.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/net/lan9118.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "net/net.h"
 #include "sysemu/kvm.h"
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/misc/arm_integrator_debug.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "hw/net/smc91c111.h"
 #include "hw/boards.h"
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
 #include "exec/address-spaces.h"
 #include "hw/char/serial.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/msf2-soc.h"
 #include "cpu.h"
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armsse.h"
 #include "hw/boards.h"
 #include "hw/char/pl011.h"
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "qemu/error-report.h"
 #include "hw/arm/stm32f205_soc.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 static void netduino2_init(MachineState *machine)
 {
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "hw/misc/unimp.h"
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bswap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/omap.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/irq.h"
 #include "ui/console.h"
 #include "hw/boards.h"
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/soc_dma.h"
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "qemu/timer.h"
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/qtest.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/input/tsc2xxx.h"
 #include "hw/loader.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "hw/boards.h"
 #include "hw/loader.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 
 #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/net/smc91c111.h"
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "hw/pcmcia.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/sysbus.h"
 #include "hw/ssi/ssi.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "qemu/timer.h"
 #include "hw/i2c/i2c.h"
 #include "net/net.h"
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/stm32f205_soc.h"
 
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "strongarm.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "chardev/char-fe.h"
 #include "chardev/char-serial.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/sharpsl.h"
 #include "hw/pcmcia.h"
 #include "hw/boards.h"
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/option.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/arm/virt.h"
 #include "hw/block/flash.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "kvm_arm.h"
 #include "hw/misc/unimp.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/i2c/i2c.h"
 #include "hw/ssi/ssi.h"
 #include "hw/boards.h"
-- 
2.20.1

In ich_vmcr_write() we enforce "writes of BPR fields to less than
their minimum sets them to the minimum" by doing a "read vbpr and
write it back" operation.  A typo here meant that we weren't handling
writes to these fields correctly, because we were reading from VBPR0
but writing to VBPR1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
 
     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
     }
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
     }
 
-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
         cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
     }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/lan9118.h"
 #include "hw/boards.h"
 
-#undef DEBUG
-
-//#define DEBUG
-
-#ifdef DEBUG
-    #undef PRINT_DEBUG
-    #define  PRINT_DEBUG(fmt, args...) \
-        do { \
-            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
-        } while (0)
-#else
-    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
-#endif
-
 #define SMDK_LAN9118_BASE_ADDR      0x05000000
 
 typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_board_binfo.gic_cpu_if_addr =
             EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 
-    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
-            " kernel_filename: %s\n"
-            " kernel_cmdline: %s\n"
-            " initrd_filename: %s\n",
-            exynos4_board_ram_size[board_type] / 1048576,
-            exynos4_board_ram_size[board_type],
-            machine->kernel_filename,
-            machine->kernel_cmdline,
-            machine->initrd_filename);
-
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

It eases code review, unit is explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
 };
 
 static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
+    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
+    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
 };
 
 static struct arm_boot_info exynos4_board_binfo = {
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

QEMU already supports pl330. Instantiate it for Exynos4210.

Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:

/ {
    soc: soc {
        amba {
            pdma0: pdma@12680000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12680000 0x1000>;
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA0>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            pdma1: pdma@12690000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12690000 0x1000>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA1>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            mdma1: mdma@12850000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12850000 0x1000>;
                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_MDMA>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <1>;
            };
        };
    };
};

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
      rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 /* EHCI */
 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 
+/* DMA */
+#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
+#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
+#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
     return (0x9 << ARM_AFF1_SHIFT) | cpu;
 }
 
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
+{
+    SysBusDevice *busdev;
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, "pl330");
+    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
+    qdev_init_nofail(dev);
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, base);
+    sysbus_connect_irq(busdev, 0, irq);
+}
+
 Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
 {
     Exynos4210State *s = g_new0(Exynos4210State, 1);
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
             s->irq_table[exynos4210_get_irq(28, 3)]);
 
+    /*** DMA controllers ***/
+    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
+
     return s;
 }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-5-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/exynos4210.h |  9 +++++++--
 hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
 hw/arm/exynos4_boards.c     |  9 ++++++---
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
 } Exynos4210Irq;
 
 typedef struct Exynos4210State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
     qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
 } Exynos4210State;
 
+#define TYPE_EXYNOS4210_SOC "exynos4210"
+#define EXYNOS4210_SOC(obj) \
+    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
+
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
-
 /* Initialize exynos4210 IRQ subsystem stub */
 qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
     sysbus_connect_irq(busdev, 0, irq);
 }
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
 {
-    Exynos4210State *s = g_new0(Exynos4210State, 1);
+    Exynos4210State *s = EXYNOS4210_SOC(socdev);
+    MemoryRegion *system_mem = get_system_memory();
     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     SysBusDevice *busdev;
     DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
     pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
-
-    return s;
 }
+
+static void exynos4210_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = exynos4210_realize;
+}
+
+static const TypeInfo exynos4210_info = {
+    .name = TYPE_EXYNOS4210_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Exynos4210State),
+    .class_init = exynos4210_class_init,
+};
+
+static void exynos4210_register_types(void)
+{
+    type_register_static(&exynos4210_info);
+}
+
+type_init(exynos4210_register_types)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
 } Exynos4BoardType;
 
 typedef struct Exynos4BoardState {
-    Exynos4210State *soc;
+    Exynos4210State soc;
     MemoryRegion dram0_mem;
     MemoryRegion dram1_mem;
 } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-    s->soc = exynos4210_init(get_system_memory());
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
+    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
+    object_property_set_bool(OBJECT(&s->soc), true, "realized",
+                             &error_fatal);
 
     return s;
 }
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
                                                       EXYNOS4_BOARD_SMDKC210);
 
     lan9215_init(SMDK_LAN9118_BASE_ADDR,
-            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
+            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
     arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
 }
 
-- 
2.20.1