[RFC PATCH 0/3] qemu: Support vCMDQ

Nathan Chen via Devel posted 3 patches 1 week, 6 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/libvirt tags/patchew/20260217232020.2565582-1-nathanc@nvidia.com
docs/formatdomain.rst                         | 13 ++++
src/conf/domain_conf.c                        | 32 ++++++++++
src/conf/domain_conf.h                        |  2 +
src/conf/domain_validate.c                    |  8 ++-
src/conf/schemas/domaincommon.rng             | 10 ++++
src/qemu/qemu_command.c                       |  2 +
...u-smmuv3-pci-bus-cmdqv.aarch64-latest.args | 40 +++++++++++++
...mu-smmuv3-pci-bus-cmdqv.aarch64-latest.xml | 59 +++++++++++++++++++
.../iommu-smmuv3-pci-bus-cmdqv.xml            | 49 +++++++++++++++
tests/qemuxmlconftest.c                       |  1 +
10 files changed, 215 insertions(+), 1 deletion(-)
create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-cmdqv.aarch64-latest.args
create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-cmdqv.aarch64-latest.xml
create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-cmdqv.xml
[RFC PATCH 0/3] qemu: Support vCMDQ
Posted by Nathan Chen via Devel 1 week, 6 days ago
Hi,

This is a follow up to the previous RFC patchset [0] for supporting
Tegra241 vCMDQ, separated out from the series for accelerated SMMUv3.

This patchset is tested with Shameer's v2 qemu series [1] for
vCMDQ support. The accelerated SMMUv3 series for qemu and Libvirt [2]
are pre-requisites for vCMDQ support, as accelerated SMMUv3 must be
enabled alongside vCMDQ.

A new 'cmdqv' <iommu> driver attribute is introduced to toggle
enabling vCMDQ support. An additional 'identifier' <iommu> driver
attribute is introduced to specify an enumeration-independent
SMMUv3 device identifier. This identifier is used so that both
Tegra DSDT and SMMUv3 IORT use the same identifier.

For instance, specifying hostdevs associated with multiple
accelerated SMMUs + CMDQV enabled, configured to be routed to
pcie-expander-bus controllers in a way where VFIO device to SMMUv3
associations are matched with the host:

  <devices>
...
    <controller type='pci' index='1' model='pcie-expander-bus'>
      <model name='pxb-pcie'/>
      <target busNr='252'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0'/>
    </controller>
    <controller type='pci' index='2' model='pcie-expander-bus'>
      <model name='pxb-pcie'/>
      <target busNr='248'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/>
    </controller>
...
    <controller type='pci' index='21' model='pcie-root-port'>
      <model name='pcie-root-port'/>
      <target chassis='21' port='0x0'/>
      <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/>
    </controller>
    <controller type='pci' index='22' model='pcie-root-port'>
      <model name='pcie-root-port'/>
      <target chassis='22' port='0xa8'/>
      <address type='pci' domain='0x0000' bus='0x02' slot='0x00' function='0x0'/>
    </controller>
...
    <hostdev mode='subsystem' type='pci' managed='no'>
      <source>
        <address domain='0x0009' bus='0x01' slot='0x00' function='0x0'/>
      </source>
      <address type='pci' domain='0x0000' bus='0x15' slot='0x00' function='0x0'/>
    </hostdev>
    <hostdev mode='subsystem' type='pci' managed='no'>
      <source>
        <address domain='0x0019' bus='0x01' slot='0x00' function='0x0'/>
      </source>
      <address type='pci' domain='0x0000' bus='0x16' slot='0x00' function='0x0'/>
    </hostdev>
    <iommu model='smmuv3'>
      <driver pciBus='1' accel='on' ats='on' ril='on' ssidSize='20' oas='44' cmdqv='on' identifier='0'/>
    </iommu>
    <iommu model='smmuv3'>
      <driver pciBus='2' accel='on' ats='on' ril='on' ssidSize='20' oas='44' cmdqv='on' identifier='1'/>
    </iommu>
  </devices>

This would get translated to a qemu command line with the arguments
below:

 -device '{"driver":"pxb-pcie","bus_nr":252,"id":"pci.1","bus":"pcie.0","addr":"0x1"}' \
 -device '{"driver":"pxb-pcie","bus_nr":248,"id":"pci.2","bus":"pcie.0","addr":"0x2"}' \
 -device '{"driver":"pcie-root-port","port":0,"chassis":21,"id":"pci.21","bus":"pci.1","addr":"0x0"}' \
 -device '{"driver":"pcie-root-port","port":168,"chassis":22,"id":"pci.22","bus":"pci.2","addr":"0x0"}' \
 -device '{"driver":"arm-smmuv3","primary-bus":"pci.1","id":"iommu0","accel":true,"ats":true,"tegra241-cmdqv":true,"identifier":0,"ril":true,"pasid":true,"oas":44}' \
 -device '{"driver":"arm-smmuv3","primary-bus":"pci.2","id":"iommu1","accel":true,"ats":true,"tegra241-cmdqv":true,"identifier":1,"ril":true,"pasid":true,"oas":44}' \
 -device '{"driver":"vfio-pci","host":"0009:01:00.0","id":"hostdev0","bus":"pci.21","addr":"0x0"}' \
 -device '{"driver":"vfio-pci","host":"0019:01:00.0","id":"hostdev1","bus":"pci.22","addr":"0x0"}' \

This series is on Github:
https://github.com/NathanChenNVIDIA/libvirt/tree/cmdqv-02-26/

Thanks,
Nathan

Changes:
- Support 'identifier' attribute for SMMUv3

[0] https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/message/VRSSX2NUIZJ6LECKSI5KPEYHYQBABYLL/
[1] https://lore.kernel.org/qemu-devel/20260206144823.80655-1-skolothumtho@nvidia.com/
[2] https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/thread/5GG76AQTTDUHW5KRANPY3QUII4ZOEYRP/

Nathan Chen (3):
  qemu: Support NVIDIA Tegra241 CMDQV for SMMUv3
  qemu: Support enumeration-independent SMMUv3 identifier
  tests: qemuxmlconfdata: provide cmdqv sample XML and CLI args

 docs/formatdomain.rst                         | 13 ++++
 src/conf/domain_conf.c                        | 32 ++++++++++
 src/conf/domain_conf.h                        |  2 +
 src/conf/domain_validate.c                    |  8 ++-
 src/conf/schemas/domaincommon.rng             | 10 ++++
 src/qemu/qemu_command.c                       |  2 +
 ...u-smmuv3-pci-bus-cmdqv.aarch64-latest.args | 40 +++++++++++++
 ...mu-smmuv3-pci-bus-cmdqv.aarch64-latest.xml | 59 +++++++++++++++++++
 .../iommu-smmuv3-pci-bus-cmdqv.xml            | 49 +++++++++++++++
 tests/qemuxmlconftest.c                       |  1 +
 10 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-cmdqv.aarch64-latest.args
 create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-cmdqv.aarch64-latest.xml
 create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-cmdqv.xml

-- 
2.43.0
RE: [RFC PATCH 0/3] qemu: Support vCMDQ
Posted by Shameer Kolothum Thodi via Devel 1 week, 5 days ago
Hi Nathan,

> -----Original Message-----
> From: Nathan Chen <nathanc@nvidia.com>
> Sent: 17 February 2026 23:20
> To: devel@lists.libvirt.org
> Cc: Shameer Kolothum Thodi <skolothumtho@nvidia.com>; Nicolin Chen
> <nicolinc@nvidia.com>; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>
> Subject: [RFC PATCH 0/3] qemu: Support vCMDQ
> 
> Hi,
> 
> This is a follow up to the previous RFC patchset [0] for supporting
> Tegra241 vCMDQ, separated out from the series for accelerated SMMUv3.
> 
> This patchset is tested with Shameer's v2 qemu series [1] for
> vCMDQ support. The accelerated SMMUv3 series for qemu and Libvirt [2]
> are pre-requisites for vCMDQ support, as accelerated SMMUv3 must be
> enabled alongside vCMDQ.
> 
> A new 'cmdqv' <iommu> driver attribute is introduced to toggle
> enabling vCMDQ support. An additional 'identifier' <iommu> driver
> attribute is introduced to specify an enumeration-independent
> SMMUv3 device identifier. This identifier is used so that both
> Tegra DSDT and SMMUv3 IORT use the same identifier.

Though QEMU SMMUv3 introduces an additional "identifier" property
for ACPI tables to use, it is not intended for users or management
layer to specify. QEMU internally populates these during SMMUv3
device instance realization. In short, libvirt doesn't have to set this.

In case it needs an id for something, can always use the default
QOM device "id" field.

eg:
-device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1-pxb1,..
 
Thanks,
Shameer
Re: [RFC PATCH 0/3] qemu: Support vCMDQ
Posted by Nathan Chen via Devel 1 week, 5 days ago

On 2/17/2026 11:53 PM, Shameer Kolothum Thodi wrote:
>> A new 'cmdqv' <iommu> driver attribute is introduced to toggle
>> enabling vCMDQ support. An additional 'identifier' <iommu> driver
>> attribute is introduced to specify an enumeration-independent
>> SMMUv3 device identifier. This identifier is used so that both
>> Tegra DSDT and SMMUv3 IORT use the same identifier.
> Though QEMU SMMUv3 introduces an additional "identifier" property
> for ACPI tables to use, it is not intended for users or management
> layer to specify. QEMU internally populates these during SMMUv3
> device instance realization. In short, libvirt doesn't have to set this.
> 
> In case it needs an id for something, can always use the default
> QOM device "id" field.
> 
> eg:
> -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1-pxb1,.

Thanks Shameer, I will remove the identifier attribute in the next revision.

Nathan