[PATCH v7 0/2] qemu: Support accelerated vSMMUs

Nathan Chen via Devel posted 2 patches 2 days, 9 hours ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/libvirt tags/patchew/20260130183707.4148322-1-nathanc@nvidia.com
docs/formatdomain.rst                         |  36 +++++++
src/conf/domain_conf.c                        | 101 +++++++++++++++++-
src/conf/domain_conf.h                        |   6 ++
src/conf/domain_validate.c                    |  36 ++++++-
src/conf/schemas/domaincommon.rng             |  32 ++++++
src/qemu/qemu_command.c                       |  23 ++++
src/util/virpci.h                             |   4 +
...u-smmuv3-pci-bus-accel.aarch64-latest.args |  38 +++++++
...mu-smmuv3-pci-bus-accel.aarch64-latest.xml |  64 +++++++++++
.../iommu-smmuv3-pci-bus-accel.xml            |  54 ++++++++++
tests/qemuxmlconftest.c                       |   1 +
11 files changed, 390 insertions(+), 5 deletions(-)
create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel.aarch64-latest.args
create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel.aarch64-latest.xml
create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel.xml
[PATCH v7 0/2] qemu: Support accelerated vSMMUs
Posted by Nathan Chen via Devel 2 days, 9 hours ago
Hi,

This is a follow up to the sixth RFC patchset [0] for supporting multiple
accelerated vSMMU instances. Support for user-creatable accelerated
SMMUv3 in QEMU has been applied to target-arm.next [1].

For instance, specifying hostdevs associated with multiple accelerated
SMMUs, configured to be routed to pcie-expander-bus controllers in a way
where VFIO device to SMMUv3 associations are matched with the host:

  <devices>
...
    <controller type='pci' index='1' model='pcie-expander-bus'>
      <model name='pxb-pcie'/>
      <target busNr='252'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x01' function='0x0'/>
    </controller>
    <controller type='pci' index='2' model='pcie-expander-bus'>
      <model name='pxb-pcie'/>
      <target busNr='248'/>
      <address type='pci' domain='0x0000' bus='0x00' slot='0x02' function='0x0'/>
    </controller>
...
    <controller type='pci' index='21' model='pcie-root-port'>
      <model name='pcie-root-port'/>
      <target chassis='21' port='0x0'/>
      <address type='pci' domain='0x0000' bus='0x01' slot='0x00' function='0x0'/>
    </controller>
    <controller type='pci' index='22' model='pcie-root-port'>
      <model name='pcie-root-port'/>
      <target chassis='22' port='0xa8'/>
      <address type='pci' domain='0x0000' bus='0x02' slot='0x00' function='0x0'/>
    </controller>
...
    <hostdev mode='subsystem' type='pci' managed='no'>
      <source>
        <address domain='0x0009' bus='0x01' slot='0x00' function='0x0'/>
      </source>
      <vpasidCapOffset>0xff8</vpasidCapOffset>
      <address type='pci' domain='0x0000' bus='0x15' slot='0x00' function='0x0'/>
    </hostdev>
    <hostdev mode='subsystem' type='pci' managed='no'>
      <source>
        <address domain='0x0019' bus='0x01' slot='0x00' function='0x0'/>
      </source>
      <vpasidCapOffset>0xff8</vpasidCapOffset>
      <address type='pci' domain='0x0000' bus='0x16' slot='0x00' function='0x0'/>
    </hostdev>
    <iommu model='smmuv3'>
      <driver parentIdx='1' accel='on' ats='on' ril='off' ssidSize='20' oas='44'/>
    </iommu>
    <iommu model='smmuv3'>
      <driver parentIdx='2' accel='on' ats='on' ril='off' ssidSize='20' oas='44'/>
    </iommu>
  </devices>

This would get translated to a qemu command line with the arguments
below:

 -device '{"driver":"pxb-pcie","bus_nr":252,"id":"pci.1","bus":"pcie.0","addr":"0x1"}' \
 -device '{"driver":"pxb-pcie","bus_nr":248,"id":"pci.2","bus":"pcie.0","addr":"0x2"}' \
 -device '{"driver":"pcie-root-port","port":0,"chassis":21,"id":"pci.21","bus":"pci.1","addr":"0x0"}' \
 -device '{"driver":"pcie-root-port","port":168,"chassis":22,"id":"pci.22","bus":"pci.2","addr":"0x0"}' \
 -device '{"driver":"arm-smmuv3","primary-bus":"pci.1","id":"iommu0","accel":true,"ats":true,"ril":false,"ssidsize":20,"oas":44}' \
 -device '{"driver":"arm-smmuv3","primary-bus":"pci.2","id":"iommu1","accel":true,"ats":true,"ril":false,"ssidsize":20,"oas":44}' \
 -device '{"driver":"vfio-pci","host":"0009:01:00.0","id":"hostdev0","x-vpasid-cap-offset":4088,"bus":"pci.21","addr":"0x0"}' \
 -device '{"driver":"vfio-pci","host":"0019:01:00.0","id":"hostdev1","x-vpasid-cap-offset":4088,"bus":"pci.22","addr":"0x0"}' \

This series is on Github:
https://github.com/NathanChenNVIDIA/libvirt/tree/smmuv3-accel-01-26-v7/

Thanks,
Nathan

Changes from v6:
- Remove smmuv3 'pasid' attribute
- Add smmuv3 'ssidsize' attribute
- Add support for 'vpasidCapOffset' element
- Modify logic for building accel smmuv3 qemu command line to omit ATS,
  RIL, accel flags when not needed (enabled/disabled by default in QEMU
  SMMUv3)

[0] https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/thread/VRSSX2NUIZJ6LECKSI5KPEYHYQBABYLL/
[1] https://lore.kernel.org/qemu-devel/20260126104342.253965-1-skolothumtho@nvidia.com/t/#u

Nathan Chen (2):
  qemu: Add support for HW-accelerated nested SMMUv3
  tests: qemuxmlconfdata: provide HW-accel smmuv3 sample XML and CLI
    args

 docs/formatdomain.rst                         |  36 +++++++
 src/conf/domain_conf.c                        | 101 +++++++++++++++++-
 src/conf/domain_conf.h                        |   6 ++
 src/conf/domain_validate.c                    |  36 ++++++-
 src/conf/schemas/domaincommon.rng             |  32 ++++++
 src/qemu/qemu_command.c                       |  23 ++++
 src/util/virpci.h                             |   4 +
 ...u-smmuv3-pci-bus-accel.aarch64-latest.args |  38 +++++++
 ...mu-smmuv3-pci-bus-accel.aarch64-latest.xml |  64 +++++++++++
 .../iommu-smmuv3-pci-bus-accel.xml            |  54 ++++++++++
 tests/qemuxmlconftest.c                       |   1 +
 11 files changed, 390 insertions(+), 5 deletions(-)
 create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel.aarch64-latest.args
 create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel.aarch64-latest.xml
 create mode 100644 tests/qemuxmlconfdata/iommu-smmuv3-pci-bus-accel.xml

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2.43.0