[libvirt] [PATCHv10 0/2] Add Cascadelake-SP CPU model

Wang Huaqiang posted 2 patches 2 weeks ago
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git fetch https://github.com/patchew-project/libvirt tags/patchew/1543302652-9268-1-git-send-email-huaqiang.wang@intel.com
src/cpu/cpu_x86.c                      | 60 +++++++++++++++++++-----
src/cpu_map/Makefile.inc.am            |  1 +
src/cpu_map/index.xml                  |  1 +
src/cpu_map/x86_Cascadelake-Server.xml | 83 ++++++++++++++++++++++++++++++++++
4 files changed, 133 insertions(+), 12 deletions(-)
create mode 100644 src/cpu_map/x86_Cascadelake-Server.xml

[libvirt] [PATCHv10 0/2] Add Cascadelake-SP CPU model

Posted by Wang Huaqiang 2 weeks ago
Cascadelake-SP is looked as the second generation Intel XEON processor
scalable family while Skylake-SP is the first generation. Both
Skylake-SP and Cascadelake-SP has the same family (6h) and model (55h),
but with difference stepping number.

In the process of identifying candidate CPU, the stepping number is not
irrelevant any more. The CPU refresh from Skylake-SP to Cascadelake-SP
is this kind of example.

These two patches firstly introduce the stepping number as another factor
to identify future Intel CPU, then introduce the Cascadelake-SP cpu model.


Wang Huaqiang (2):
  cpu: Add x86 stepping number as another factor to find candidate CPU
  cpu_map: Add Cascadelake Server CPU model

 src/cpu/cpu_x86.c                      | 60 +++++++++++++++++++-----
 src/cpu_map/Makefile.inc.am            |  1 +
 src/cpu_map/index.xml                  |  1 +
 src/cpu_map/x86_Cascadelake-Server.xml | 83 ++++++++++++++++++++++++++++++++++
 4 files changed, 133 insertions(+), 12 deletions(-)
 create mode 100644 src/cpu_map/x86_Cascadelake-Server.xml

-- 
2.7.4

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