This patch expose cache information to host's capabilites xml.

For l3 cache allocation
<cache>
  <bank id='0' type='l3' size='56320' unit='KiB' cpus='0-21,44-65'>
    <control min='2816' reserved='2816' unit='KiB' scope='L3'/>
  </bank>
  <bank id='1' type='l3' size='56320' unit='KiB' cpus='22-43,66-87'>
    <control min='2816' reserved='2816' unit='KiB' scope='L3'/>
  </bank>
</cache>

For l3 cache allocation supported cdp(seperate data/code):
<cache>
  <bank id='0' type='l3' size='56320' unit='KiB' cpus='0-21,44-65'>
    <control min='2816' reserved='2816' unit='KiB' scope='L3DATA'/>
    <control min='2816' reserved='2816' unit='KiB' scope='L3CODE'/>
  </bank>
  <bank id='1' type='l3' size='56320' unit='KiB' cpus='22-43,66-87'>
    <control min='2816' reserved='2816' unit='KiB' scope='L3DATA'/>
    <control min='2816' reserved='2816' unit='KiB' scope='L3CODE'/>
  </bank>
</cache>

RFC on mailing list.
https://www.redhat.com/archives/libvir-list/2017-January/msg00644.html

Signed-off-by: Eli Qiao <liyong.qiao@intel.com>
---
 src/conf/capabilities.c      | 56 ++++++++++++++++++++++++++++++++++++
 src/conf/capabilities.h      | 23 +++++++++++++++
 src/libvirt_private.syms     |  1 +
 src/qemu/qemu_capabilities.c | 68 ++++++++++++++++++++++++++++++++++++++++++++
 src/qemu/qemu_driver.c       |  4 +++
 5 files changed, 152 insertions(+)

diff --git a/src/conf/capabilities.c b/src/conf/capabilities.c
index 9ab343b..290c25f 100644
--- a/src/conf/capabilities.c
+++ b/src/conf/capabilities.c
@@ -198,6 +198,18 @@ virCapabilitiesClearSecModel(virCapsHostSecModelPtr secmodel)
 }
 
 static void
+virCapabilitiesClearCacheBank(virCapsHostCacheBankPtr cachebank)
+{
+    size_t i;
+    for (i = 0; i < cachebank->ncontrol; i++) {
+        VIR_FREE(cachebank->control[i].scope);
+    }
+    VIR_FREE(cachebank->type);
+    VIR_FREE(cachebank->cpus);
+}
+
+
+static void
 virCapabilitiesDispose(void *object)
 {
     virCapsPtr caps = object;
@@ -221,6 +233,10 @@ virCapabilitiesDispose(void *object)
         virCapabilitiesClearSecModel(&caps->host.secModels[i]);
     VIR_FREE(caps->host.secModels);
 
+    for (i = 0; i < caps->host.ncachebank; i++)
+        virCapabilitiesClearCacheBank(caps->host.cachebank[i]);
+    VIR_FREE(caps->host.cachebank);
+
     VIR_FREE(caps->host.netprefix);
     VIR_FREE(caps->host.pagesSize);
     virCPUDefFree(caps->host.cpu);
@@ -844,6 +860,41 @@ virCapabilitiesFormatNUMATopology(virBufferPtr buf,
     return 0;
 }
 
+static int
+virCapabilitiesFormatCache(virBufferPtr buf,
+                           size_t ncachebank,
+                           virCapsHostCacheBankPtr *cachebank)
+{
+    size_t i;
+    size_t j;
+
+    virBufferAddLit(buf, "<cache>\n");
+    virBufferAdjustIndent(buf, 2);
+
+    for( i = 0 ; i < ncachebank; i++) {
+        virBufferAsprintf(buf,
+                          "<bank id='%u' type='%s' size='%llu' unit='KiB' cpus='%s'>\n",
+                          cachebank[i]->id,
+                          cachebank[i]->type,
+                          cachebank[i]->size,
+                          cachebank[i]->cpus);
+
+        virBufferAdjustIndent(buf, 2);
+        for( j = 0; j < cachebank[i]->ncontrol; j ++) {
+            virBufferAsprintf(buf,
+                              "<control min='%llu' reserved='%llu' unit='KiB' scope='%s'/>\n",
+                              cachebank[i]->control[j].min,
+                              cachebank[i]->control[j].reserved,
+                              cachebank[i]->control[j].scope);
+        }
+        virBufferAdjustIndent(buf, -2);
+        virBufferAddLit(buf, "</bank>\n");
+    }
+    virBufferAdjustIndent(buf, -2);
+    virBufferAddLit(buf, "</cache>\n");
+    return 0;
+}
+
 /**
  * virCapabilitiesFormatXML:
  * @caps: capabilities to format
@@ -931,6 +982,11 @@ virCapabilitiesFormatXML(virCapsPtr caps)
         virBufferAddLit(&buf, "</migration_features>\n");
     }
 
+    if (caps->host.ncachebank &&
+            virCapabilitiesFormatCache(&buf, caps->host.ncachebank,
+                                       caps->host.cachebank) < 0)
+        return NULL;
+
     if (caps->host.netprefix)
         virBufferAsprintf(&buf, "<netprefix>%s</netprefix>\n",
                           caps->host.netprefix);
diff --git a/src/conf/capabilities.h b/src/conf/capabilities.h
index cfdc34a..b446de5 100644
--- a/src/conf/capabilities.h
+++ b/src/conf/capabilities.h
@@ -138,6 +138,25 @@ struct _virCapsHostSecModel {
     virCapsHostSecModelLabelPtr labels;
 };
 
+typedef struct _virCapsHostCacheControl virCapsHostCacheControl;
+typedef virCapsHostCacheControl *virCapsHostCacheControlPtr;
+struct _virCapsHostCacheControl {
+    unsigned long long min;
+    unsigned long long reserved;
+    char* scope;
+};
+
+typedef struct _virCapsHostCacheBank virCapsHostCacheBank;
+typedef virCapsHostCacheBank *virCapsHostCacheBankPtr;
+struct _virCapsHostCacheBank {
+    unsigned int id;
+    char* type;
+    char* cpus;
+    unsigned long long size;
+    size_t ncontrol;
+    virCapsHostCacheControlPtr control;
+};
+
 typedef struct _virCapsHost virCapsHost;
 typedef virCapsHost *virCapsHostPtr;
 struct _virCapsHost {
@@ -160,6 +179,10 @@ struct _virCapsHost {
     size_t nsecModels;
     virCapsHostSecModelPtr secModels;
 
+    size_t ncachebank;
+    size_t ncachebank_max;
+    virCapsHostCacheBankPtr *cachebank;
+
     char *netprefix;
     virCPUDefPtr cpu;
     int nPagesSize;             /* size of pagesSize array */
diff --git a/src/libvirt_private.syms b/src/libvirt_private.syms
index 743e5ac..d93b775 100644
--- a/src/libvirt_private.syms
+++ b/src/libvirt_private.syms
@@ -2316,6 +2316,7 @@ virRandomInt;
 # util/virresctrl.h
 virResCtrlAvailable;
 virResCtrlInit;
+virResCtrlGet;
 
 # util/virrotatingfile.h
 virRotatingFileReaderConsume;
diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
index 3247d25..23f416d 100644
--- a/src/qemu/qemu_capabilities.c
+++ b/src/qemu/qemu_capabilities.c
@@ -45,6 +45,7 @@
 #include "qemu_domain.h"
 #define __QEMU_CAPSRIV_H_ALLOW__
 #include "qemu_capspriv.h"
+#include "virresctrl.h"
 
 #include <fcntl.h>
 #include <sys/stat.h>
@@ -1098,7 +1099,71 @@ virQEMUCapsInitCPU(virCapsPtr caps,
     goto cleanup;
 }
 
+static int
+virQEMUCapsInitCache(virCapsPtr caps)
+{
+    int i, j;
+    virResCtrlPtr resctrl;
+    virCapsHostCacheBankPtr bank;
+
+    for (i = 0; i < RDT_NUM_RESOURCES; i ++)
+    {
+        /* L3DATA and L3CODE share L3 resources */
+        if ( i == RDT_RESOURCE_L3CODE )
+            continue;
 
+        resctrl = virResCtrlGet(i);
+
+        if(resctrl->enabled) {
+            for( j = 0; j < resctrl->num_banks; j++)
+            {
+                if(VIR_RESIZE_N(caps->host.cachebank, caps->host.ncachebank_max,
+                                caps->host.ncachebank, 1) < 0)
+                    return -1;
+
+                if(VIR_ALLOC(bank) < 0)
+                    return -1;
+
+                bank->id = resctrl->cache_banks[j].host_id;
+                if(VIR_STRDUP(bank->type, resctrl->cache_level) < 0)
+                    goto err;
+                if(VIR_STRDUP(bank->cpus, virBitmapFormat(resctrl->cache_banks[j].cpu_mask)) < 0)
+                    goto err;
+                bank->size = resctrl->cache_banks[j].cache_size;
+                /*L3DATA and L3CODE shares L3 cache resources, so fill them to the control element*/
+                if ( i == RDT_RESOURCE_L3DATA ) {
+                    if(VIR_EXPAND_N(bank->control, bank->ncontrol, 2) < 0)
+                        goto err;
+
+                    bank->control[0].min = virResCtrlGet(RDT_RESOURCE_L3DATA)->cache_banks[j].cache_min;
+                    bank->control[0].reserved = bank->control[0].min * (virResCtrlGet(RDT_RESOURCE_L3DATA)->min_cbm_bits);
+                    if(VIR_STRDUP(bank->control[0].scope,
+                                  virResCtrlGet(RDT_RESOURCE_L3DATA)->name) < 0)
+                        goto err;
+
+                    bank->control[1].min = virResCtrlGet(RDT_RESOURCE_L3CODE)->cache_banks[j].cache_min;
+                    bank->control[1].reserved = bank->control[1].min * (virResCtrlGet(RDT_RESOURCE_L3CODE)->min_cbm_bits);
+                    if(VIR_STRDUP(bank->control[1].scope,
+                                  virResCtrlGet(RDT_RESOURCE_L3CODE)->name) < 0)
+                        goto err;
+                }
+                else {
+                    if(VIR_EXPAND_N(bank->control, bank->ncontrol, 1) < 0)
+                        goto err;
+                    bank->control[0].min = resctrl->cache_banks[j].cache_min;
+                    bank->control[0].reserved = bank->control[0].min * resctrl->min_cbm_bits;
+                    if(VIR_STRDUP(bank->control[0].scope, resctrl->name) < 0)
+                        goto err;
+                }
+                caps->host.cachebank[caps->host.ncachebank++] = bank;
+            }
+        }
+    }
+    return 0;
+err:
+    VIR_FREE(bank);
+    return -1;
+}
 static int
 virQEMUCapsInitPages(virCapsPtr caps)
 {
@@ -1144,6 +1209,9 @@ virCapsPtr virQEMUCapsInit(virQEMUCapsCachePtr cache)
     if (virQEMUCapsInitCPU(caps, hostarch) < 0)
         VIR_WARN("Failed to get host CPU");
 
+    if (virQEMUCapsInitCache(caps) < 0)
+        VIR_WARN("Failed to get host cache");
+
     /* Add the power management features of the host */
     if (virNodeSuspendGetTargetMask(&caps->host.powerMgmt) < 0)
         VIR_WARN("Failed to get host power management capabilities");
diff --git a/src/qemu/qemu_driver.c b/src/qemu/qemu_driver.c
index 37ccfdf..520b74d 100644
--- a/src/qemu/qemu_driver.c
+++ b/src/qemu/qemu_driver.c
@@ -105,6 +105,7 @@
 #include "vircgroup.h"
 #include "virperf.h"
 #include "virnuma.h"
+#include "virresctrl.h"
 #include "dirname.h"
 #include "network/bridge_driver.h"
 
@@ -849,6 +850,9 @@ qemuStateInitialize(bool privileged,
         run_gid = cfg->group;
     }
 
+    if(virResCtrlAvailable() && virResCtrlInit() < 0)
+        VIR_WARN("Faild to initialize resource control.");
+
     qemu_driver->qemuCapsCache = virQEMUCapsCacheNew(cfg->libDir,
                                                      cfg->cacheDir,
                                                      run_uid,
-- 
1.9.1

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On Mon, Feb 06, 2017 at 10:23:37AM +0800, Eli Qiao wrote:
> This patch expose cache information to host's capabilites xml.
> 
> For l3 cache allocation
> <cache>
>   <bank id='0' type='l3' size='56320' unit='KiB' cpus='0-21,44-65'>
>     <control min='2816' reserved='2816' unit='KiB' scope='L3'/>
>   </bank>
>   <bank id='1' type='l3' size='56320' unit='KiB' cpus='22-43,66-87'>
>     <control min='2816' reserved='2816' unit='KiB' scope='L3'/>
>   </bank>
> </cache>
> 
> For l3 cache allocation supported cdp(seperate data/code):
> <cache>
>   <bank id='0' type='l3' size='56320' unit='KiB' cpus='0-21,44-65'>
>     <control min='2816' reserved='2816' unit='KiB' scope='L3DATA'/>
>     <control min='2816' reserved='2816' unit='KiB' scope='L3CODE'/>
>   </bank>
>   <bank id='1' type='l3' size='56320' unit='KiB' cpus='22-43,66-87'>
>     <control min='2816' reserved='2816' unit='KiB' scope='L3DATA'/>
>     <control min='2816' reserved='2816' unit='KiB' scope='L3CODE'/>
>   </bank>
> </cache>
> 
> RFC on mailing list.
> https://www.redhat.com/archives/libvir-list/2017-January/msg00644.html
> 
> Signed-off-by: Eli Qiao <liyong.qiao@intel.com>
> ---
>  src/conf/capabilities.c      | 56 ++++++++++++++++++++++++++++++++++++
>  src/conf/capabilities.h      | 23 +++++++++++++++
>  src/libvirt_private.syms     |  1 +
>  src/qemu/qemu_capabilities.c | 68 ++++++++++++++++++++++++++++++++++++++++++++
>  src/qemu/qemu_driver.c       |  4 +++
>  5 files changed, 152 insertions(+)
> 


> diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
> index 3247d25..23f416d 100644
> --- a/src/qemu/qemu_capabilities.c
> +++ b/src/qemu/qemu_capabilities.c
> @@ -45,6 +45,7 @@
>  #include "qemu_domain.h"
>  #define __QEMU_CAPSRIV_H_ALLOW__
>  #include "qemu_capspriv.h"
> +#include "virresctrl.h"
>  
>  #include <fcntl.h>
>  #include <sys/stat.h>
> @@ -1098,7 +1099,71 @@ virQEMUCapsInitCPU(virCapsPtr caps,
>      goto cleanup;
>  }
>  
> +static int
> +virQEMUCapsInitCache(virCapsPtr caps)
> +{
> +    int i, j;
> +    virResCtrlPtr resctrl;
> +    virCapsHostCacheBankPtr bank;
> +
> +    for (i = 0; i < RDT_NUM_RESOURCES; i ++)
> +    {
> +        /* L3DATA and L3CODE share L3 resources */
> +        if ( i == RDT_RESOURCE_L3CODE )
> +            continue;
>  
> +        resctrl = virResCtrlGet(i);
> +
> +        if(resctrl->enabled) {
> +            for( j = 0; j < resctrl->num_banks; j++)
> +            {
> +                if(VIR_RESIZE_N(caps->host.cachebank, caps->host.ncachebank_max,
> +                                caps->host.ncachebank, 1) < 0)
> +                    return -1;
> +
> +                if(VIR_ALLOC(bank) < 0)
> +                    return -1;
> +
> +                bank->id = resctrl->cache_banks[j].host_id;
> +                if(VIR_STRDUP(bank->type, resctrl->cache_level) < 0)
> +                    goto err;
> +                if(VIR_STRDUP(bank->cpus, virBitmapFormat(resctrl->cache_banks[j].cpu_mask)) < 0)
> +                    goto err;
> +                bank->size = resctrl->cache_banks[j].cache_size;
> +                /*L3DATA and L3CODE shares L3 cache resources, so fill them to the control element*/
> +                if ( i == RDT_RESOURCE_L3DATA ) {
> +                    if(VIR_EXPAND_N(bank->control, bank->ncontrol, 2) < 0)
> +                        goto err;
> +
> +                    bank->control[0].min = virResCtrlGet(RDT_RESOURCE_L3DATA)->cache_banks[j].cache_min;
> +                    bank->control[0].reserved = bank->control[0].min * (virResCtrlGet(RDT_RESOURCE_L3DATA)->min_cbm_bits);
> +                    if(VIR_STRDUP(bank->control[0].scope,
> +                                  virResCtrlGet(RDT_RESOURCE_L3DATA)->name) < 0)
> +                        goto err;
> +
> +                    bank->control[1].min = virResCtrlGet(RDT_RESOURCE_L3CODE)->cache_banks[j].cache_min;
> +                    bank->control[1].reserved = bank->control[1].min * (virResCtrlGet(RDT_RESOURCE_L3CODE)->min_cbm_bits);
> +                    if(VIR_STRDUP(bank->control[1].scope,
> +                                  virResCtrlGet(RDT_RESOURCE_L3CODE)->name) < 0)
> +                        goto err;
> +                }
> +                else {
> +                    if(VIR_EXPAND_N(bank->control, bank->ncontrol, 1) < 0)
> +                        goto err;
> +                    bank->control[0].min = resctrl->cache_banks[j].cache_min;
> +                    bank->control[0].reserved = bank->control[0].min * resctrl->min_cbm_bits;
> +                    if(VIR_STRDUP(bank->control[0].scope, resctrl->name) < 0)
> +                        goto err;
> +                }
> +                caps->host.cachebank[caps->host.ncachebank++] = bank;
> +            }
> +        }
> +    }
> +    return 0;
> +err:
> +    VIR_FREE(bank);
> +    return -1;
> +}

I don't think this code should be in the QEMU driver - better to have
it in nodeinfo.c so it is common to all drivers.


Regards,
Daniel
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-- 
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Sent with Sparrow (http://www.sparrowmailapp.com/?sig)


On Tuesday, 7 February 2017 at 12:02 AM, Daniel P. Berrange wrote:

> On Mon, Feb 06, 2017 at 10:23:37AM +0800, Eli Qiao wrote:
> > This patch expose cache information to host's capabilites xml.
> > 
> > For l3 cache allocation
> > <cache>
> > <bank id='0' type='l3' size='56320' unit='KiB' cpus='0-21,44-65'>
> > <control min='2816' reserved='2816' unit='KiB' scope='L3'/>
> > </bank>
> > <bank id='1' type='l3' size='56320' unit='KiB' cpus='22-43,66-87'>
> > <control min='2816' reserved='2816' unit='KiB' scope='L3'/>
> > </bank>
> > </cache>
> > 
> > For l3 cache allocation supported cdp(seperate data/code):
> > <cache>
> > <bank id='0' type='l3' size='56320' unit='KiB' cpus='0-21,44-65'>
> > <control min='2816' reserved='2816' unit='KiB' scope='L3DATA'/>
> > <control min='2816' reserved='2816' unit='KiB' scope='L3CODE'/>
> > </bank>
> > <bank id='1' type='l3' size='56320' unit='KiB' cpus='22-43,66-87'>
> > <control min='2816' reserved='2816' unit='KiB' scope='L3DATA'/>
> > <control min='2816' reserved='2816' unit='KiB' scope='L3CODE'/>
> > </bank>
> > </cache>
> > 
> > RFC on mailing list.
> > https://www.redhat.com/archives/libvir-list/2017-January/msg00644.html
> > 
> > Signed-off-by: Eli Qiao <liyong.qiao@intel.com (mailto:liyong.qiao@intel.com)>
> > ---
> > src/conf/capabilities.c | 56 ++++++++++++++++++++++++++++++++++++
> > src/conf/capabilities.h | 23 +++++++++++++++
> > src/libvirt_private.syms | 1 +
> > src/qemu/qemu_capabilities.c | 68 ++++++++++++++++++++++++++++++++++++++++++++
> > src/qemu/qemu_driver.c | 4 +++
> > 5 files changed, 152 insertions(+)
> > 
> 
> 
> 
> > diff --git a/src/qemu/qemu_capabilities.c b/src/qemu/qemu_capabilities.c
> > index 3247d25..23f416d 100644
> > --- a/src/qemu/qemu_capabilities.c
> > +++ b/src/qemu/qemu_capabilities.c
> > @@ -45,6 +45,7 @@
> > #include "qemu_domain.h"
> > #define __QEMU_CAPSRIV_H_ALLOW__
> > #include "qemu_capspriv.h"
> > +#include "virresctrl.h"
> > 
> > #include <fcntl.h>
> > #include <sys/stat.h>
> > @@ -1098,7 +1099,71 @@ virQEMUCapsInitCPU(virCapsPtr caps,
> > goto cleanup;
> > }
> > 
> > +static int
> > +virQEMUCapsInitCache(virCapsPtr caps)
> > +{
> > + int i, j;
> > + virResCtrlPtr resctrl;
> > + virCapsHostCacheBankPtr bank;
> > +
> > + for (i = 0; i < RDT_NUM_RESOURCES; i ++)
> > + {
> > + /* L3DATA and L3CODE share L3 resources */
> > + if ( i == RDT_RESOURCE_L3CODE )
> > + continue;
> > 
> > + resctrl = virResCtrlGet(i);
> > +
> > + if(resctrl->enabled) {
> > + for( j = 0; j < resctrl->num_banks; j++)
> > + {
> > + if(VIR_RESIZE_N(caps->host.cachebank, caps->host.ncachebank_max,
> > + caps->host.ncachebank, 1) < 0)
> > + return -1;
> > +
> > + if(VIR_ALLOC(bank) < 0)
> > + return -1;
> > +
> > + bank->id = resctrl->cache_banks[j].host_id;
> > + if(VIR_STRDUP(bank->type, resctrl->cache_level) < 0)
> > + goto err;
> > + if(VIR_STRDUP(bank->cpus, virBitmapFormat(resctrl->cache_banks[j].cpu_mask)) < 0)
> > + goto err;
> > + bank->size = resctrl->cache_banks[j].cache_size;
> > + /*L3DATA and L3CODE shares L3 cache resources, so fill them to the control element*/
> > + if ( i == RDT_RESOURCE_L3DATA ) {
> > + if(VIR_EXPAND_N(bank->control, bank->ncontrol, 2) < 0)
> > + goto err;
> > +
> > + bank->control[0].min = virResCtrlGet(RDT_RESOURCE_L3DATA)->cache_banks[j].cache_min;
> > + bank->control[0].reserved = bank->control[0].min * (virResCtrlGet(RDT_RESOURCE_L3DATA)->min_cbm_bits);
> > + if(VIR_STRDUP(bank->control[0].scope,
> > + virResCtrlGet(RDT_RESOURCE_L3DATA)->name) < 0)
> > + goto err;
> > +
> > + bank->control[1].min = virResCtrlGet(RDT_RESOURCE_L3CODE)->cache_banks[j].cache_min;
> > + bank->control[1].reserved = bank->control[1].min * (virResCtrlGet(RDT_RESOURCE_L3CODE)->min_cbm_bits);
> > + if(VIR_STRDUP(bank->control[1].scope,
> > + virResCtrlGet(RDT_RESOURCE_L3CODE)->name) < 0)
> > + goto err;
> > + }
> > + else {
> > + if(VIR_EXPAND_N(bank->control, bank->ncontrol, 1) < 0)
> > + goto err;
> > + bank->control[0].min = resctrl->cache_banks[j].cache_min;
> > + bank->control[0].reserved = bank->control[0].min * resctrl->min_cbm_bits;
> > + if(VIR_STRDUP(bank->control[0].scope, resctrl->name) < 0)
> > + goto err;
> > + }
> > + caps->host.cachebank[caps->host.ncachebank++] = bank;
> > + }
> > + }
> > + }
> > + return 0;
> > +err:
> > + VIR_FREE(bank);
> > + return -1;
> > +}
> > 
> 
> 
> I don't think this code should be in the QEMU driver - better to have
> it in nodeinfo.c so it is common to all drivers.
> 
Sure, I will move it to nodeinfo.c 
> 
> Regards,
> Daniel
> -- 
> |: http://berrange.com -o- http://www.flickr.com/photos/dberrange/ :|
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> 
> 
> 


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