.../Include/Library/AmlLib/AmlLib.h | 33 +++++++++++++++++++ .../AcpiSsdtPcieLibArm/SsdtPcieGenerator.c | 12 +++---- 2 files changed, 39 insertions(+), 6 deletions(-)
AmlCodeGenRdQWordMemory's and AmlCodeGenRdDWordMemory's Cacheable
and MemoryRangeType parameters treat specific values as having
specific meanings. This change adds enums to map those meanings to their
corresponding values.
Signed-off-by: Jeshua Smith <jeshuas@nvidia.com>
---
.../Include/Library/AmlLib/AmlLib.h | 33 +++++++++++++++++++
.../AcpiSsdtPcieLibArm/SsdtPcieGenerator.c | 12 +++----
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
index 510c79a399..6a273059fb 100644
--- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
+++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
@@ -59,6 +59,39 @@ typedef void *AML_DATA_NODE_HANDLE;
#endif // AML_HANDLE
+/** Cacheable parameter values
+
+ Possible values are:
+ 0-The memory is non-cacheable
+ 1-The memory is cacheable
+ 2-The memory is cacheable and supports
+ write combining
+ 3-The memory is cacheable and prefetchable
+
+**/
+typedef enum {
+ AML_MEMORY_NONCACHEABLE = 0,
+ AML_MEMORY_CACHEABLE = 1,
+ AML_MEMORY_CACHEABLE_WC = 2,
+ AML_MEMORY_CACHEABLE_PF = 3
+} AML_MEMORY_CACHEABILITY;
+
+/** MemoryRangeType parameter values
+
+ Possible values are:
+ 0-AddressRangeMemory
+ 1-AddressRangeReserved
+ 2-AddressRangeACPI
+ 3-AddressRangeNVS
+
+**/
+typedef enum {
+ AML_MEMORY_RANGE_TYPE_MEMORY = 0,
+ AML_MEMORY_RANGE_TYPE_RESERVED = 1,
+ AML_MEMORY_RANGE_TYPE_ACPI = 2,
+ AML_MEMORY_RANGE_TYPE_NVS = 3
+} AML_MEMORY_RANGE_TYPE;
+
/** Parse the definition block.
The function parses the whole AML blob. It starts with the ACPI DSDT/SSDT
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
index 9ddaddc198..7df7117352 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
@@ -566,7 +566,7 @@ GeneratePciCrs (
IsPosDecode,
TRUE,
TRUE,
- TRUE,
+ AML_MEMORY_CACHEABLE,
TRUE,
0,
AddrMapInfo->PciAddress,
@@ -575,7 +575,7 @@ GeneratePciCrs (
AddrMapInfo->AddressSize,
0,
NULL,
- 0,
+ AML_MEMORY_RANGE_TYPE_MEMORY,
TRUE,
CrsNode,
NULL
@@ -588,7 +588,7 @@ GeneratePciCrs (
IsPosDecode,
TRUE,
TRUE,
- TRUE,
+ AML_MEMORY_CACHEABLE,
TRUE,
0,
AddrMapInfo->PciAddress,
@@ -597,7 +597,7 @@ GeneratePciCrs (
AddrMapInfo->AddressSize,
0,
NULL,
- 0,
+ AML_MEMORY_RANGE_TYPE_MEMORY,
TRUE,
CrsNode,
NULL
@@ -718,7 +718,7 @@ ReserveEcamSpace (
TRUE,
TRUE,
TRUE,
- FALSE, // non-cacheable
+ AML_MEMORY_NONCACHEABLE,
TRUE,
0,
AddressMinimum,
@@ -727,7 +727,7 @@ ReserveEcamSpace (
AddressMaximum - AddressMinimum + 1,
0,
NULL,
- 0,
+ AML_MEMORY_RANGE_TYPE_MEMORY,
TRUE,
CrsNode,
NULL
--
2.25.1
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On Mon, Oct 02, 2023 at 21:52:52 +0000, Jeshua Smith wrote: > AmlCodeGenRdQWordMemory's and AmlCodeGenRdDWordMemory's Cacheable > and MemoryRangeType parameters treat specific values as having > specific meanings. This change adds enums to map those meanings to their > corresponding values. > > Signed-off-by: Jeshua Smith <jeshuas@nvidia.com> Looks like a nice bit of cleanup. Acked-by: Leif Lindholm <quic_llindhol@quicinc.com> / Leif > --- > .../Include/Library/AmlLib/AmlLib.h | 33 +++++++++++++++++++ > .../AcpiSsdtPcieLibArm/SsdtPcieGenerator.c | 12 +++---- > 2 files changed, 39 insertions(+), 6 deletions(-) > > diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h > index 510c79a399..6a273059fb 100644 > --- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h > +++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h > @@ -59,6 +59,39 @@ typedef void *AML_DATA_NODE_HANDLE; > > #endif // AML_HANDLE > > +/** Cacheable parameter values > + > + Possible values are: > + 0-The memory is non-cacheable > + 1-The memory is cacheable > + 2-The memory is cacheable and supports > + write combining > + 3-The memory is cacheable and prefetchable > + > +**/ > +typedef enum { > + AML_MEMORY_NONCACHEABLE = 0, > + AML_MEMORY_CACHEABLE = 1, > + AML_MEMORY_CACHEABLE_WC = 2, > + AML_MEMORY_CACHEABLE_PF = 3 > +} AML_MEMORY_CACHEABILITY; > + > +/** MemoryRangeType parameter values > + > + Possible values are: > + 0-AddressRangeMemory > + 1-AddressRangeReserved > + 2-AddressRangeACPI > + 3-AddressRangeNVS > + > +**/ > +typedef enum { > + AML_MEMORY_RANGE_TYPE_MEMORY = 0, > + AML_MEMORY_RANGE_TYPE_RESERVED = 1, > + AML_MEMORY_RANGE_TYPE_ACPI = 2, > + AML_MEMORY_RANGE_TYPE_NVS = 3 > +} AML_MEMORY_RANGE_TYPE; > + > /** Parse the definition block. > > The function parses the whole AML blob. It starts with the ACPI DSDT/SSDT > diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c > index 9ddaddc198..7df7117352 100644 > --- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c > +++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c > @@ -566,7 +566,7 @@ GeneratePciCrs ( > IsPosDecode, > TRUE, > TRUE, > - TRUE, > + AML_MEMORY_CACHEABLE, > TRUE, > 0, > AddrMapInfo->PciAddress, > @@ -575,7 +575,7 @@ GeneratePciCrs ( > AddrMapInfo->AddressSize, > 0, > NULL, > - 0, > + AML_MEMORY_RANGE_TYPE_MEMORY, > TRUE, > CrsNode, > NULL > @@ -588,7 +588,7 @@ GeneratePciCrs ( > IsPosDecode, > TRUE, > TRUE, > - TRUE, > + AML_MEMORY_CACHEABLE, > TRUE, > 0, > AddrMapInfo->PciAddress, > @@ -597,7 +597,7 @@ GeneratePciCrs ( > AddrMapInfo->AddressSize, > 0, > NULL, > - 0, > + AML_MEMORY_RANGE_TYPE_MEMORY, > TRUE, > CrsNode, > NULL > @@ -718,7 +718,7 @@ ReserveEcamSpace ( > TRUE, > TRUE, > TRUE, > - FALSE, // non-cacheable > + AML_MEMORY_NONCACHEABLE, > TRUE, > 0, > AddressMinimum, > @@ -727,7 +727,7 @@ ReserveEcamSpace ( > AddressMaximum - AddressMinimum + 1, > 0, > NULL, > - 0, > + AML_MEMORY_RANGE_TYPE_MEMORY, > TRUE, > CrsNode, > NULL > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109285): https://edk2.groups.io/g/devel/message/109285 Mute This Topic: https://groups.io/mt/101722936/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076/xyzzy [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hello Jeshua, just a few NITs: On 10/2/23 23:52, Jeshua Smith wrote: > AmlCodeGenRdQWordMemory's and AmlCodeGenRdDWordMemory's Cacheable > and MemoryRangeType parameters treat specific values as having > specific meanings. This change adds enums to map those meanings to their > corresponding values. > > Signed-off-by: Jeshua Smith <jeshuas@nvidia.com> > --- > .../Include/Library/AmlLib/AmlLib.h | 33 +++++++++++++++++++ > .../AcpiSsdtPcieLibArm/SsdtPcieGenerator.c | 12 +++---- > 2 files changed, 39 insertions(+), 6 deletions(-) > > diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h > index 510c79a399..6a273059fb 100644 > --- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h > +++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h > @@ -59,6 +59,39 @@ typedef void *AML_DATA_NODE_HANDLE; > > #endif // AML_HANDLE > > +/** Cacheable parameter values > + > + Possible values are: > + 0-The memory is non-cacheable > + 1-The memory is cacheable > + 2-The memory is cacheable and supports > + write combining > + 3-The memory is cacheable and prefetchable Is it possible add a reference to ACPI 6.5, s6.4.3.5.5 "Resource Type Specific Flags" for future reference ? Same comment for the other enum. > + > +**/ > +typedef enum { > + AML_MEMORY_NONCACHEABLE = 0, > + AML_MEMORY_CACHEABLE = 1, > + AML_MEMORY_CACHEABLE_WC = 2, > + AML_MEMORY_CACHEABLE_PF = 3 Just for a matter of unification in the package, is is possible to use camelcase enum names, like AmlMemoryNonCacheable ? Also would it be possible to add a AmlMemoryMax enum at the end ? Same comment for the other enum. > +} AML_MEMORY_CACHEABILITY; > + > +/** MemoryRangeType parameter values > + > + Possible values are: > + 0-AddressRangeMemory > + 1-AddressRangeReserved > + 2-AddressRangeACPI > + 3-AddressRangeNVS > + > +**/ > +typedef enum { > + AML_MEMORY_RANGE_TYPE_MEMORY = 0, > + AML_MEMORY_RANGE_TYPE_RESERVED = 1, > + AML_MEMORY_RANGE_TYPE_ACPI = 2, > + AML_MEMORY_RANGE_TYPE_NVS = 3 > +} AML_MEMORY_RANGE_TYPE; > + > /** Parse the definition block. > > The function parses the whole AML blob. It starts with the ACPI DSDT/SSDT > diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c > index 9ddaddc198..7df7117352 100644 > --- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c > +++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c Is is possible to modify the definition/declaration of the modified functions to use the newly created type ? > @@ -566,7 +566,7 @@ GeneratePciCrs ( > IsPosDecode, > TRUE, > TRUE, > - TRUE, > + AML_MEMORY_CACHEABLE, > TRUE, > 0, > AddrMapInfo->PciAddress, > @@ -575,7 +575,7 @@ GeneratePciCrs ( > AddrMapInfo->AddressSize, > 0, > NULL, > - 0, > + AML_MEMORY_RANGE_TYPE_MEMORY, > TRUE, > CrsNode, > NULL > @@ -588,7 +588,7 @@ GeneratePciCrs ( > IsPosDecode, > TRUE, > TRUE, > - TRUE, > + AML_MEMORY_CACHEABLE, > TRUE, > 0, > AddrMapInfo->PciAddress, > @@ -597,7 +597,7 @@ GeneratePciCrs ( > AddrMapInfo->AddressSize, > 0, > NULL, > - 0, > + AML_MEMORY_RANGE_TYPE_MEMORY, > TRUE, > CrsNode, > NULL > @@ -718,7 +718,7 @@ ReserveEcamSpace ( > TRUE, > TRUE, > TRUE, > - FALSE, // non-cacheable > + AML_MEMORY_NONCACHEABLE, > TRUE, > 0, > AddressMinimum, > @@ -727,7 +727,7 @@ ReserveEcamSpace ( > AddressMaximum - AddressMinimum + 1, > 0, > NULL, > - 0, > + AML_MEMORY_RANGE_TYPE_MEMORY, > TRUE, > CrsNode, > NULL Regards, Pierre -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109275): https://edk2.groups.io/g/devel/message/109275 Mute This Topic: https://groups.io/mt/101722936/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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