Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
UefiCpuPkg/Include/Library/MtrrLib.h | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h
index 86cc1aab3b8e..c7d505ac06ed 100644
--- a/UefiCpuPkg/Include/Library/MtrrLib.h
+++ b/UefiCpuPkg/Include/Library/MtrrLib.h
@@ -9,6 +9,8 @@
#ifndef _MTRR_LIB_H_
#define _MTRR_LIB_H_
+#include <Register/Intel/ArchitecturalMsr.h>
+
//
// According to IA32 SDM, MTRRs number and MSR offset are always consistent
// for IA32 processor family
@@ -90,12 +92,12 @@ typedef enum {
CacheInvalid = 7
} MTRR_MEMORY_CACHE_TYPE;
-#define MTRR_CACHE_UNCACHEABLE 0
-#define MTRR_CACHE_WRITE_COMBINING 1
-#define MTRR_CACHE_WRITE_THROUGH 4
-#define MTRR_CACHE_WRITE_PROTECTED 5
-#define MTRR_CACHE_WRITE_BACK 6
-#define MTRR_CACHE_INVALID_TYPE 7
+#define MTRR_CACHE_UNCACHEABLE MSR_IA32_MTRR_CACHE_UNCACHEABLE
+#define MTRR_CACHE_WRITE_COMBINING MSR_IA32_MTRR_CACHE_WRITE_COMBINING
+#define MTRR_CACHE_WRITE_THROUGH MSR_IA32_MTRR_CACHE_WRITE_THROUGH
+#define MTRR_CACHE_WRITE_PROTECTED MSR_IA32_MTRR_CACHE_WRITE_PROTECTED
+#define MTRR_CACHE_WRITE_BACK MSR_IA32_MTRR_CACHE_WRITE_BACK
+#define MTRR_CACHE_INVALID_TYPE MSR_IA32_MTRR_CACHE_INVALID_TYPE
typedef struct {
UINT64 BaseAddress;
--
2.43.0
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> -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Gerd > Hoffmann > Sent: Thursday, January 25, 2024 12:23 AM > To: devel@edk2.groups.io > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Laszlo Ersek > <lersek@redhat.com>; Aktas, Erdem <erdemaktas@google.com>; Michael Roth > <michael.roth@amd.com>; Xu, Min M <min.m.xu@intel.com>; Gerd Hoffmann > <kraxel@redhat.com>; Yao, Jiewen <jiewen.yao@intel.com>; Tom Lendacky > <thomas.lendacky@amd.com>; Oliver Steffen <osteffen@redhat.com> > Subject: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache > type #defines from ArchitecturalMsr.h > > Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> > --- > UefiCpuPkg/Include/Library/MtrrLib.h | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h > b/UefiCpuPkg/Include/Library/MtrrLib.h > index 86cc1aab3b8e..c7d505ac06ed 100644 > --- a/UefiCpuPkg/Include/Library/MtrrLib.h > +++ b/UefiCpuPkg/Include/Library/MtrrLib.h > @@ -9,6 +9,8 @@ > #ifndef _MTRR_LIB_H_ > #define _MTRR_LIB_H_ > > +#include <Register/Intel/ArchitecturalMsr.h> > + > // > // According to IA32 SDM, MTRRs number and MSR offset are always > consistent > // for IA32 processor family > @@ -90,12 +92,12 @@ typedef enum { > CacheInvalid = 7 > } MTRR_MEMORY_CACHE_TYPE; I think the values in the above enum should also use the MSR_IA32_MTRR_CACHE values. > > -#define MTRR_CACHE_UNCACHEABLE 0 > -#define MTRR_CACHE_WRITE_COMBINING 1 > -#define MTRR_CACHE_WRITE_THROUGH 4 > -#define MTRR_CACHE_WRITE_PROTECTED 5 > -#define MTRR_CACHE_WRITE_BACK 6 > -#define MTRR_CACHE_INVALID_TYPE 7 > +#define MTRR_CACHE_UNCACHEABLE MSR_IA32_MTRR_CACHE_UNCACHEABLE > +#define MTRR_CACHE_WRITE_COMBINING > MSR_IA32_MTRR_CACHE_WRITE_COMBINING > +#define MTRR_CACHE_WRITE_THROUGH MSR_IA32_MTRR_CACHE_WRITE_THROUGH > +#define MTRR_CACHE_WRITE_PROTECTED > MSR_IA32_MTRR_CACHE_WRITE_PROTECTED > +#define MTRR_CACHE_WRITE_BACK MSR_IA32_MTRR_CACHE_WRITE_BACK > +#define MTRR_CACHE_INVALID_TYPE MSR_IA32_MTRR_CACHE_INVALID_TYPE > > typedef struct { > UINT64 BaseAddress; > -- > 2.43.0 > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114457): https://edk2.groups.io/g/devel/message/114457 Mute This Topic: https://groups.io/mt/103950481/1787277 Mute #defines:https://edk2.groups.io/g/devel/mutehashtag/defines Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076/xyzzy [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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