The ResetVector decides at runtime (depending on CPU capabilities)
whenever it uses 5-level paging or not.  Firmware builds with 5-level
paging enabled (PcdEnable5LevelPageTable=TRUE) may run run in 4-level
paging mode.  The code handles that just fine, by looking at the la57
bit in cr4 instead of checking PcdEnable5LevelPageTable.

So the ASSERT is too strict.  Change it to ensure the build was
configured with PcdEnable5LevelPageTable=TRUE when running in 5-level
paging mode.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 46528e4f719d..9e194ef8cc55 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -745,7 +745,9 @@ CreateIdentityMappingPageTables (
     //
     Cr4.UintN         = AsmReadCr4 ();
     Page5LevelSupport = (Cr4.Bits.LA57 != 0);
-    ASSERT (PcdGetBool (PcdEnable5LevelPageTable) == Page5LevelSupport);
+    if (Page5LevelSupport) {
+      ASSERT (PcdGetBool (PcdEnable5LevelPageTable));
+    }
   } else {
     //
     // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability.
-- 
2.43.0



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