This series adds the support for RISV-V Sstc extension in EDK2 timer
implementation. Sstc extension allows S-mode software to program the
timer directly without using SBI calls.

Currently, PCD variable is used to detect whether feature is enabled. By
default the feature is enabled and platforms need to set the PCD to
disable the feature if Sstc is not supported.

For RiscVVirtQemu, it is disabled by default (until extension discovery
feature is enabled).

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Sunil V L (4):
  MdePkg.dec: RISC-V: Define override bit for Sstc extension
  MdePkg/BaseLib: RISC-V: Add function to update stimecmp register
  UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc
  OvmfPkg/RiscVVirt: Override Sstc extension

 MdePkg/MdePkg.dec                             |  2 ++
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
 .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf |  1 +
 MdePkg/Include/Library/BaseLib.h              |  5 ++++
 .../Include/Register/RiscV64/RiscVEncoding.h  |  3 ++
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h         |  2 ++
 UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c         | 30 +++++++++++++++++--
 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S    |  7 +++++
 8 files changed, 49 insertions(+), 3 deletions(-)

-- 
2.34.1



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On Wed, Jan 3, 2024 at 1:59 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> This series adds the support for RISV-V Sstc extension in EDK2 timer

nit: RISC-V
> implementation. Sstc extension allows S-mode software to program the
> timer directly without using SBI calls.
>
> Currently, PCD variable is used to detect whether feature is enabled. By
> default the feature is enabled and platforms need to set the PCD to
> disable the feature if Sstc is not supported.
>
> For RiscVVirtQemu, it is disabled by default (until extension discovery
> feature is enabled).

I'm curious, what do you want Sstc for? Is the performance difference
measurable (if so, please post numbers, and add them to the commit)?
Does it have any other advantages?

-- 
Pedro


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Hi Pedro,

On Fri, Jan 05, 2024 at 07:10:40PM +0000, Pedro Falcato wrote:
> On Wed, Jan 3, 2024 at 1:59 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
> >
> > This series adds the support for RISV-V Sstc extension in EDK2 timer
> 
> nit: RISC-V
> > implementation. Sstc extension allows S-mode software to program the
> > timer directly without using SBI calls.
> >
> > Currently, PCD variable is used to detect whether feature is enabled. By
> > default the feature is enabled and platforms need to set the PCD to
> > disable the feature if Sstc is not supported.
> >
> > For RiscVVirtQemu, it is disabled by default (until extension discovery
> > feature is enabled).
> 
> I'm curious, what do you want Sstc for? Is the performance difference
> measurable (if so, please post numbers, and add them to the commit)?
> Does it have any other advantages?
> 
Good question.

Without Sstc, timer needs to be programmed using SBI call. The number of
instructions via SBI call is way more than a simple CSR access. So, when
the CPU supports Sstc, there is no point in using SBI call. The issue
with SBI call will be worse under KVM since it has to emulate the timer.

Supporting Sstc is futuristic. The platforms can decide not to implement
SBI TIME interface at all since they have Sstc. In that case, EDK2 needs
to have option to support either.

Thanks,
Sunil


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