Currently, RiscVVirtQemu supports unified code and variable store
mainly because only one pflash devices was available in qemu for
EDK2. However, this doesn't allow to map the code part as read-only.

With recent qemu enhancements, it is now possible for EDK2 to make
use of both pflash devices in RISC-V virt machine. So, add support
to create code and vars images separately. This also allows easy
firmware code updates without losing the variable store.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
---
 OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc |  2 +-
 OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf |  9 +++++----
 OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 12 +++++-------
 OvmfPkg/RiscVVirt/VarStore.fdf.inc  | 13 ++++++++++---
 4 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
index 414d186179fb..04573bc0f32e 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc
@@ -85,7 +85,7 @@ [LibraryClasses.common]
   QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf
 
   TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
-  VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf
+  VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf
 
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 354c9271d10c..dbe38a135395 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -12,17 +12,18 @@
 !include RiscVVirt.fdf.inc
 
 ################################################################################
-[FD.RISCV_VIRT]
-BaseAddress   = $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
-Size          = $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
+[FD.RISCV_VIRT_CODE]
+BaseAddress   = $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress
+Size          = $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
 ErasePolarity = 1
 BlockSize     = $(BLOCK_SIZE)
-NumBlocks     = $(FW_BLOCKS)
+NumBlocks     = $(CODE_BLOCKS)
 
 0x00000000|$(CODE_SIZE)
 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize
 FV = FVMAIN_COMPACT
 
+################################################################################
 !include VarStore.fdf.inc
 ################################################################################
 
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc
index b0a1c3293f33..7e8165d85778 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc
@@ -10,16 +10,14 @@
 [Defines]
 DEFINE BLOCK_SIZE                  = 0x1000
 
+DEFINE PFLASH0_BASE                = 0x20000000
 DEFINE PFLASH1_BASE                = 0x22000000
 
-DEFINE FW_BASE_ADDRESS             = $(PFLASH1_BASE)
-DEFINE FW_SIZE                     = 0x00800000
-DEFINE FW_BLOCKS                   = 0x800
-
-DEFINE CODE_BASE_ADDRESS           = $(FW_BASE_ADDRESS)
-DEFINE CODE_SIZE                   = 0x00740000
-DEFINE CODE_BLOCKS                 = 0x740
+DEFINE CODE_BASE_ADDRESS           = $(PFLASH0_BASE)
+DEFINE CODE_SIZE                   = 0x00800000
+DEFINE CODE_BLOCKS                 = 0x800
 
+DEFINE VARS_BASE_ADDRESS            = $(PFLASH1_BASE)
 DEFINE VARS_SIZE                    = 0x000C0000
 DEFINE VARS_BLOCK_SIZE              = 0x40000
 DEFINE VARS_BLOCKS                  = 0x3
diff --git a/OvmfPkg/RiscVVirt/VarStore.fdf.inc b/OvmfPkg/RiscVVirt/VarStore.fdf.inc
index 6bc619e50c1a..49293c742b56 100644
--- a/OvmfPkg/RiscVVirt/VarStore.fdf.inc
+++ b/OvmfPkg/RiscVVirt/VarStore.fdf.inc
@@ -10,7 +10,14 @@
 #
 ##
 
-$(VARS_OFFSET)|$(VARS_LIVE_SIZE)
+[FD.RISCV_VIRT_VARS]
+BaseAddress   = $(VARS_BASE_ADDRESS)
+Size          = $(VARS_SIZE)
+ErasePolarity = 1
+BlockSize     = $(VARS_BLOCK_SIZE)
+NumBlocks     = $(VARS_BLOCKS)
+
+0x00000000|$(VARS_LIVE_SIZE)
 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
 #
 # NV_VARIABLE_STORE
@@ -57,7 +64,7 @@
   0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 }
 
-$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
+0x00040000|$(VARS_FTW_WORKING_SIZE)
 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
 #
 #NV_FTW_WORK
@@ -73,7 +80,7 @@
   0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
 }
 
-$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
+0x00080000|$(VARS_FTW_SPARE_SIZE)
 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
 #
 #NV_FTW_SPARE
-- 
2.34.1



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