Update ProcTrace feature code to support enable collect performance
data by generating CYC and TSC packets. Add a new dynamic
PCD to indicate if enable performance collecting. In ProcTrace.c
code, if this new PCD is true, CYC and TSC packets will be
generated by setting the corresponding MSR bits feilds.
Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=4423
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Xiao X Chen <xiao.x.chen@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 1 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++-------------------
UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++
3 files changed, 56 insertions(+), 19 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
index 319c8b4842..e31c1e7317 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
@@ -63,3 +63,4 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdEnableProcessorTraceOnBspOnly ## SOMETIMES_CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.ProcTraceEnablePerformanceCollecting ## SOMETIMES_CONSUMES
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
index f57544bf7d..1a101b7288 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
@@ -171,25 +171,26 @@ ProcTraceInitialize (
IN BOOLEAN State
)
{
- UINT32 MemRegionSize;
- UINTN Pages;
- UINTN Alignment;
- UINTN MemRegionBaseAddr;
- UINTN *ThreadMemRegionTable;
- UINTN Index;
- UINTN TopaTableBaseAddr;
- UINTN AlignedAddress;
- UINTN *TopaMemArray;
- PROC_TRACE_TOPA_TABLE *TopaTable;
- PROC_TRACE_DATA *ProcTraceData;
- BOOLEAN FirstIn;
- MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
- MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
- MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
- MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
- RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
- BOOLEAN IsBsp;
- BOOLEAN EnableOnBspOnly;
+ UINT32 MemRegionSize;
+ UINTN Pages;
+ UINTN Alignment;
+ UINTN MemRegionBaseAddr;
+ UINTN *ThreadMemRegionTable;
+ UINTN Index;
+ UINTN TopaTableBaseAddr;
+ UINTN AlignedAddress;
+ UINTN *TopaMemArray;
+ PROC_TRACE_TOPA_TABLE *TopaTable;
+ PROC_TRACE_DATA *ProcTraceData;
+ BOOLEAN FirstIn;
+ MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
+ MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
+ RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
+ BOOLEAN IsBsp;
+ BOOLEAN EnableOnBspOnly;
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
//
// The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
@@ -510,6 +511,33 @@ ProcTraceInitialize (
CtrlReg.Bits.User = 1;
CtrlReg.Bits.BranchEn = 1;
CtrlReg.Bits.TraceEn = 1;
+
+ AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, &Ebx.Uint32, NULL, NULL);
+
+ //
+ // Generate CYC/TSC timing packets to to collect performance data.
+ //
+ if (PcdGetBool (ProcTraceEnablePerformanceCollecting)) {
+ if (Ebx.Bits.ConfigurablePsb == 1) {
+ CtrlReg.Bits.CYCEn = 1;
+ CtrlReg.Bits.CYCThresh = 5;
+
+ //
+ // Write to TSCEn is always supported
+ //
+ CtrlReg.Bits.TSCEn = 1;
+ } else {
+ DEBUG ((DEBUG_INFO, "ProcTrace: CYC packet is not supported. Failed to enable Performance Collecting \n"));
+ }
+ } else {
+ if (Ebx.Bits.ConfigurablePsb == 1) {
+ CtrlReg.Bits.CYCEn = 0;
+ CtrlReg.Bits.CYCThresh = 0;
+ }
+
+ CtrlReg.Bits.TSCEn = 0;
+ }
+
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 1a4b9333ab..2b0de6d5c3 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -429,5 +429,13 @@
# @Prompt Enable CPU processor trace only on BSP.
gUefiCpuPkgTokenSpaceGuid.PcdEnableProcessorTraceOnBspOnly|FALSE|BOOLEAN|0x60000019
+ ## This PCD indicates if enable performance collecting when CPU processor trace is enabled.<BR><BR>
+ # CYC/TSC timing packets will be generated to collect performance data if this PCD is TRUE.
+ # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
+ # TRUE - Performance collecting will be enabled in processor trace.<BR>
+ # FASLE - Performance collecting will be disabled in processor trace.<BR>
+ # @Prompt Enable performance collecting when processor trace is enabled.
+ gUefiCpuPkgTokenSpaceGuid.ProcTraceEnablePerformanceCollecting|FALSE|BOOLEAN|0x60000020
+
[UserExtensions.TianoCore."ExtraFiles"]
UefiCpuPkgExtra.uni
--
2.39.1.windows.1
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-=-=-=-=-=-=-=-=-=-=-=-1. ProcessorTrace capabilities might differ in different cpu threads.
So, the capabilities detection needs to be done in ProcTraceSupport() which runs on each AP.
2. TSCEn is not guarded by Ebx.Bits.ConfigurablePsb, right?
3. Why do you need to clear the CYCEn/CYCThresh/TSCEn bit when the ProcTraceEnablePerformanceCollecting is FALSE?
4. Please use a PCD name that's consistent with existing ones. Such as: PcdCpuProcTracePerformanceCollecting?
> -----Original Message-----
> From: Tan, Dun <dun.tan@intel.com>
> Sent: Tuesday, April 25, 2023 1:48 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar,
> Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>;
> Chen, Xiao X <xiao.x.chen@intel.com>
> Subject: [PATCH 2/3] UefiCpuPkg: Update PT code to support enable collect
> performance
>
> Update ProcTrace feature code to support enable collect performance
> data by generating CYC and TSC packets. Add a new dynamic
> PCD to indicate if enable performance collecting. In ProcTrace.c
> code, if this new PCD is true, CYC and TSC packets will be
> generated by setting the corresponding MSR bits feilds.
>
> Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=4423
> Signed-off-by: Dun Tan <dun.tan@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Xiao X Chen <xiao.x.chen@intel.com>
> ---
> UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf |
> 1 +
> UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c | 66
> +++++++++++++++++++++++++++++++++++++++++++++++------------------
> -
> UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++
> 3 files changed, 56 insertions(+), 19 deletions(-)
>
> diff --git
> a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> index 319c8b4842..e31c1e7317 100644
> ---
> a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> +++
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> @@ -63,3 +63,4 @@
> gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ##
> SOMETIMES_CONSUMES
> gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ##
> SOMETIMES_CONSUMES
> gUefiCpuPkgTokenSpaceGuid.PcdEnableProcessorTraceOnBspOnly ##
> SOMETIMES_CONSUMES
> + gUefiCpuPkgTokenSpaceGuid.ProcTraceEnablePerformanceCollecting ##
> SOMETIMES_CONSUMES
> diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> index f57544bf7d..1a101b7288 100644
> --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> @@ -171,25 +171,26 @@ ProcTraceInitialize (
> IN BOOLEAN State
> )
> {
> - UINT32 MemRegionSize;
> - UINTN Pages;
> - UINTN Alignment;
> - UINTN MemRegionBaseAddr;
> - UINTN *ThreadMemRegionTable;
> - UINTN Index;
> - UINTN TopaTableBaseAddr;
> - UINTN AlignedAddress;
> - UINTN *TopaMemArray;
> - PROC_TRACE_TOPA_TABLE *TopaTable;
> - PROC_TRACE_DATA *ProcTraceData;
> - BOOLEAN FirstIn;
> - MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
> - MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
> - MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
> - MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
> - RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
> - BOOLEAN IsBsp;
> - BOOLEAN EnableOnBspOnly;
> + UINT32 MemRegionSize;
> + UINTN Pages;
> + UINTN Alignment;
> + UINTN MemRegionBaseAddr;
> + UINTN *ThreadMemRegionTable;
> + UINTN Index;
> + UINTN TopaTableBaseAddr;
> + UINTN AlignedAddress;
> + UINTN *TopaMemArray;
> + PROC_TRACE_TOPA_TABLE *TopaTable;
> + PROC_TRACE_DATA *ProcTraceData;
> + BOOLEAN FirstIn;
> + MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
> + MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
> + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
> + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
> + RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
> + BOOLEAN IsBsp;
> + BOOLEAN EnableOnBspOnly;
> + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
>
> //
> // The scope of the MSR_IA32_RTIT_* is core for below processor type,
> only program
> @@ -510,6 +511,33 @@ ProcTraceInitialize (
> CtrlReg.Bits.User = 1;
> CtrlReg.Bits.BranchEn = 1;
> CtrlReg.Bits.TraceEn = 1;
> +
> + AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE,
> CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, &Ebx.Uint32, NULL,
> NULL);
> +
> + //
> + // Generate CYC/TSC timing packets to to collect performance data.
> + //
> + if (PcdGetBool (ProcTraceEnablePerformanceCollecting)) {
> + if (Ebx.Bits.ConfigurablePsb == 1) {
> + CtrlReg.Bits.CYCEn = 1;
> + CtrlReg.Bits.CYCThresh = 5;
> +
> + //
> + // Write to TSCEn is always supported
> + //
> + CtrlReg.Bits.TSCEn = 1;
> + } else {
> + DEBUG ((DEBUG_INFO, "ProcTrace: CYC packet is not supported. Failed
> to enable Performance Collecting \n"));
> + }
> + } else {
> + if (Ebx.Bits.ConfigurablePsb == 1) {
> + CtrlReg.Bits.CYCEn = 0;
> + CtrlReg.Bits.CYCThresh = 0;
> + }
> +
> + CtrlReg.Bits.TSCEn = 0;
> + }
> +
> CPU_REGISTER_TABLE_WRITE64 (
> ProcessorNumber,
> Msr,
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 1a4b9333ab..2b0de6d5c3 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -429,5 +429,13 @@
> # @Prompt Enable CPU processor trace only on BSP.
>
> gUefiCpuPkgTokenSpaceGuid.PcdEnableProcessorTraceOnBspOnly|FALSE|B
> OOLEAN|0x60000019
>
> + ## This PCD indicates if enable performance collecting when CPU
> processor trace is enabled.<BR><BR>
> + # CYC/TSC timing packets will be generated to collect performance data if
> this PCD is TRUE.
> + # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
> + # TRUE - Performance collecting will be enabled in processor trace.<BR>
> + # FASLE - Performance collecting will be disabled in processor trace.<BR>
> + # @Prompt Enable performance collecting when processor trace is
> enabled.
> +
> gUefiCpuPkgTokenSpaceGuid.ProcTraceEnablePerformanceCollecting|FALSE
> |BOOLEAN|0x60000020
> +
> [UserExtensions.TianoCore."ExtraFiles"]
> UefiCpuPkgExtra.uni
> --
> 2.39.1.windows.1
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Thanks for the comments. Updated inline.
Thanks,
Dun
-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Tuesday, April 25, 2023 2:14 PM
To: Tan, Dun <dun.tan@intel.com>; devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Chen, Xiao X <xiao.x.chen@intel.com>
Subject: RE: [PATCH 2/3] UefiCpuPkg: Update PT code to support enable collect performance
1. ProcessorTrace capabilities might differ in different cpu threads.
So, the capabilities detection needs to be done in ProcTraceSupport() which runs on each AP.
Dun: Sure, I'll add two new fields in PROC_TRACE_DATA and update the fields in ProcTraceSupport().
2. TSCEn is not guarded by Ebx.Bits.ConfigurablePsb, right?
Dun: Yes, Ebx.Bits.ConfigurablePsb is only for CYC. TSCEn is always supported. But I think if CYC is not supported, we don't need to enable CYC, right?
3. Why do you need to clear the CYCEn/CYCThresh/TSCEn bit when the ProcTraceEnablePerformanceCollecting is FALSE?
Dun: Seems this part is not needed. I'll remove the code that clear the the CYCEn/CYCThresh/TSCEn bits.
4. Please use a PCD name that's consistent with existing ones. Such as: PcdCpuProcTracePerformanceCollecting?
Dun: Ok, I'll update it.
> -----Original Message-----
> From: Tan, Dun <dun.tan@intel.com>
> Sent: Tuesday, April 25, 2023 1:48 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>;
> Kumar, Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann
> <kraxel@redhat.com>; Chen, Xiao X <xiao.x.chen@intel.com>
> Subject: [PATCH 2/3] UefiCpuPkg: Update PT code to support enable
> collect performance
>
> Update ProcTrace feature code to support enable collect performance
> data by generating CYC and TSC packets. Add a new dynamic PCD to
> indicate if enable performance collecting. In ProcTrace.c code, if
> this new PCD is true, CYC and TSC packets will be generated by setting
> the corresponding MSR bits feilds.
>
> Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=4423
> Signed-off-by: Dun Tan <dun.tan@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Xiao X Chen <xiao.x.chen@intel.com>
> ---
> UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf |
> 1 +
> UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c | 66
> +++++++++++++++++++++++++++++++++++++++++++++++------------------
> -
> UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++
> 3 files changed, 56 insertions(+), 19 deletions(-)
>
> diff --git
> a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> index 319c8b4842..e31c1e7317 100644
> ---
> a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> +++
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
> @@ -63,3 +63,4 @@
> gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ##
> SOMETIMES_CONSUMES
> gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ##
> SOMETIMES_CONSUMES
> gUefiCpuPkgTokenSpaceGuid.PcdEnableProcessorTraceOnBspOnly ##
> SOMETIMES_CONSUMES
> + gUefiCpuPkgTokenSpaceGuid.ProcTraceEnablePerformanceCollecting ##
> SOMETIMES_CONSUMES
> diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> index f57544bf7d..1a101b7288 100644
> --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
> @@ -171,25 +171,26 @@ ProcTraceInitialize (
> IN BOOLEAN State
> )
> {
> - UINT32 MemRegionSize;
> - UINTN Pages;
> - UINTN Alignment;
> - UINTN MemRegionBaseAddr;
> - UINTN *ThreadMemRegionTable;
> - UINTN Index;
> - UINTN TopaTableBaseAddr;
> - UINTN AlignedAddress;
> - UINTN *TopaMemArray;
> - PROC_TRACE_TOPA_TABLE *TopaTable;
> - PROC_TRACE_DATA *ProcTraceData;
> - BOOLEAN FirstIn;
> - MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
> - MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
> - MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
> - MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
> - RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
> - BOOLEAN IsBsp;
> - BOOLEAN EnableOnBspOnly;
> + UINT32 MemRegionSize;
> + UINTN Pages;
> + UINTN Alignment;
> + UINTN MemRegionBaseAddr;
> + UINTN *ThreadMemRegionTable;
> + UINTN Index;
> + UINTN TopaTableBaseAddr;
> + UINTN AlignedAddress;
> + UINTN *TopaMemArray;
> + PROC_TRACE_TOPA_TABLE *TopaTable;
> + PROC_TRACE_DATA *ProcTraceData;
> + BOOLEAN FirstIn;
> + MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
> + MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
> + MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
> + MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
> + RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
> + BOOLEAN IsBsp;
> + BOOLEAN EnableOnBspOnly;
> + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
>
> //
> // The scope of the MSR_IA32_RTIT_* is core for below processor
> type, only program @@ -510,6 +511,33 @@ ProcTraceInitialize (
> CtrlReg.Bits.User = 1;
> CtrlReg.Bits.BranchEn = 1;
> CtrlReg.Bits.TraceEn = 1;
> +
> + AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE,
> CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, &Ebx.Uint32, NULL, NULL);
> +
> + //
> + // Generate CYC/TSC timing packets to to collect performance data.
> + //
> + if (PcdGetBool (ProcTraceEnablePerformanceCollecting)) {
> + if (Ebx.Bits.ConfigurablePsb == 1) {
> + CtrlReg.Bits.CYCEn = 1;
> + CtrlReg.Bits.CYCThresh = 5;
> +
> + //
> + // Write to TSCEn is always supported
> + //
> + CtrlReg.Bits.TSCEn = 1;
> + } else {
> + DEBUG ((DEBUG_INFO, "ProcTrace: CYC packet is not supported.
> + Failed
> to enable Performance Collecting \n"));
> + }
> + } else {
> + if (Ebx.Bits.ConfigurablePsb == 1) {
> + CtrlReg.Bits.CYCEn = 0;
> + CtrlReg.Bits.CYCThresh = 0;
> + }
> +
> + CtrlReg.Bits.TSCEn = 0;
> + }
> +
> CPU_REGISTER_TABLE_WRITE64 (
> ProcessorNumber,
> Msr,
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 1a4b9333ab..2b0de6d5c3 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -429,5 +429,13 @@
> # @Prompt Enable CPU processor trace only on BSP.
>
> gUefiCpuPkgTokenSpaceGuid.PcdEnableProcessorTraceOnBspOnly|FALSE|B
> OOLEAN|0x60000019
>
> + ## This PCD indicates if enable performance collecting when CPU
> processor trace is enabled.<BR><BR>
> + # CYC/TSC timing packets will be generated to collect performance
> + data if
> this PCD is TRUE.
> + # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
> + # TRUE - Performance collecting will be enabled in processor
> + trace.<BR> # FASLE - Performance collecting will be disabled in
> + processor trace.<BR> # @Prompt Enable performance collecting when
> + processor trace is
> enabled.
> +
> gUefiCpuPkgTokenSpaceGuid.ProcTraceEnablePerformanceCollecting|FALSE
> |BOOLEAN|0x60000020
> +
> [UserExtensions.TianoCore."ExtraFiles"]
> UefiCpuPkgExtra.uni
> --
> 2.39.1.windows.1
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