In previous code logic, when splitting a leaf parent entry to
smaller granularity child page table, if the parent entry
Attribute&Mask(without PageTableBaseAddress field) is equal to the
input attribute&mask(without PageTableBaseAddress field), the split
process won't happen. This may lead to failure in non-1:1 mapping.
For example, there is a page table in which [0, 1G] is mapped(Lv4[0]
,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we
want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the
same attibute. The expected behaviour should be: split Lv3[0,0]
entry into 512 level2 entries and remap the first level2 entry to
cover [0, 2M]. But the split won't happen in previous code since
PageTableBaseAddress of input Attribute is not checked.
So, when checking if a leaf parent entry needs to be splitted, we
should also check if PageTableBaseAddress calculated by parent entry
is equal to the value caculated by input attribute.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
---
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 127b65183f..b94ef07c56 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -274,6 +274,8 @@ PageTableLibMapInLevel (
IA32_MAP_ATTRIBUTE ChildMask;
IA32_MAP_ATTRIBUTE CurrentMask;
IA32_MAP_ATTRIBUTE LocalParentAttribute;
+ UINT64 PhysicalAddrInEntry;
+ UINT64 PhysicalAddrInAttr;
ASSERT (Level != 0);
ASSERT ((Attribute != NULL) && (Mask != NULL));
@@ -341,7 +343,15 @@ PageTableLibMapInLevel (
// This function is called when the memory length is less than the region length of the parent level.
// No need to split the page when the attributes equal.
//
- return RETURN_SUCCESS;
+ if (Mask->Bits.PageTableBaseAddress == 0) {
+ return RETURN_SUCCESS;
+ }
+
+ PhysicalAddrInEntry = IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + MultU64x32 (RegionLength, (UINT32)PagingEntryIndex);
+ PhysicalAddrInAttr = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & (~RegionMask);
+ if (PhysicalAddrInEntry == PhysicalAddrInAttr) {
+ return RETURN_SUCCESS;
+ }
}
ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
--
2.31.1.windows.1
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Reviewed-by: Ray Ni <ray.ni@intel.com> > -----Original Message----- > From: Tan, Dun <dun.tan@intel.com> > Sent: Friday, March 24, 2023 4:52 PM > To: devel@edk2.groups.io > Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, > Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com> > Subject: [Patch V6 04/22] UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 > mapping issue > > In previous code logic, when splitting a leaf parent entry to > smaller granularity child page table, if the parent entry > Attribute&Mask(without PageTableBaseAddress field) is equal to the > input attribute&mask(without PageTableBaseAddress field), the split > process won't happen. This may lead to failure in non-1:1 mapping. > > For example, there is a page table in which [0, 1G] is mapped(Lv4[0] > ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we > want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the > same attibute. The expected behaviour should be: split Lv3[0,0] > entry into 512 level2 entries and remap the first level2 entry to > cover [0, 2M]. But the split won't happen in previous code since > PageTableBaseAddress of input Attribute is not checked. > > So, when checking if a leaf parent entry needs to be splitted, we > should also check if PageTableBaseAddress calculated by parent entry > is equal to the value caculated by input attribute. > > Signed-off-by: Dun Tan <dun.tan@intel.com> > Cc: Eric Dong <eric.dong@intel.com> > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Tested-by: Gerd Hoffmann <kraxel@redhat.com> > Acked-by: Gerd Hoffmann <kraxel@redhat.com> > --- > UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 > +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > index 127b65183f..b94ef07c56 100644 > --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c > @@ -274,6 +274,8 @@ PageTableLibMapInLevel ( > IA32_MAP_ATTRIBUTE ChildMask; > IA32_MAP_ATTRIBUTE CurrentMask; > IA32_MAP_ATTRIBUTE LocalParentAttribute; > + UINT64 PhysicalAddrInEntry; > + UINT64 PhysicalAddrInAttr; > > ASSERT (Level != 0); > ASSERT ((Attribute != NULL) && (Mask != NULL)); > @@ -341,7 +343,15 @@ PageTableLibMapInLevel ( > // This function is called when the memory length is less than the region > length of the parent level. > // No need to split the page when the attributes equal. > // > - return RETURN_SUCCESS; > + if (Mask->Bits.PageTableBaseAddress == 0) { > + return RETURN_SUCCESS; > + } > + > + PhysicalAddrInEntry = > IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + > MultU64x32 (RegionLength, (UINT32)PagingEntryIndex); > + PhysicalAddrInAttr = > (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) > & (~RegionMask); > + if (PhysicalAddrInEntry == PhysicalAddrInAttr) { > + return RETURN_SUCCESS; > + } > } > > ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB); > -- > 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#101786): https://edk2.groups.io/g/devel/message/101786 Mute This Topic: https://groups.io/mt/97819604/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/3901457/1787277/102458076/xyzzy [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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