Simplify the code to set memory used by smm page table as RO.
Since memory used by smm page table are in PageTablePool list,
we only need to set all PageTablePool as ReadOnly in smm page
table itself. Also, we only need to flush tlb once after
setting all page table pool as Read Only.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 123 ---------------------------------------------------------------------------------------------------------------------------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 19 ++++++++++++++++++-
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 170 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
4 files changed, 152 insertions(+), 294 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 26efa71eff..26bbba77b0 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -10,24 +10,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "PiSmmCpuDxeSmm.h"
-/**
- Disable CET.
-**/
-VOID
-EFIAPI
-DisableCet (
- VOID
- );
-
-/**
- Enable CET.
-**/
-VOID
-EFIAPI
-EnableCet (
- VOID
- );
-
/**
Create PageTable for SMM use.
@@ -221,111 +203,6 @@ Exit:
}
/**
- This function sets memory attribute for page table.
-**/
-VOID
-SetPageTableAttributes (
- VOID
- )
-{
- UINTN Index2;
- UINTN Index3;
- UINT64 *L1PageTable;
- UINT64 *L2PageTable;
- UINT64 *L3PageTable;
- UINTN PageTableBase;
- BOOLEAN IsSplitted;
- BOOLEAN PageTableSplitted;
- BOOLEAN CetEnabled;
-
- //
- // Don't mark page table to read-only if heap guard is enabled.
- //
- // BIT2: SMM page guard enabled
- // BIT3: SMM pool guard enabled
- //
- if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {
- DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));
- return;
- }
-
- //
- // Don't mark page table to read-only if SMM profile is enabled.
- //
- if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
- DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));
- return;
- }
-
- DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
-
- //
- // Disable write protection, because we need mark page table to be write protected.
- // We need *write* page table memory, to mark itself to be *read only*.
- //
- CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
- if (CetEnabled) {
- //
- // CET must be disabled if WP is disabled.
- //
- DisableCet ();
- }
-
- AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
-
- do {
- DEBUG ((DEBUG_INFO, "Start...\n"));
- PageTableSplitted = FALSE;
-
- PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
- L3PageTable = (UINT64 *)PageTableBase;
-
- SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
-
- for (Index3 = 0; Index3 < 4; Index3++) {
- L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
- if (L2PageTable == NULL) {
- continue;
- }
-
- SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
-
- for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
- if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
- // 2M
- continue;
- }
-
- L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
- if (L1PageTable == NULL) {
- continue;
- }
-
- SmmSetMemoryAttributesEx (PageTableBase, FALSE, (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
- }
- }
- } while (PageTableSplitted);
-
- //
- // Enable write protection, after page table updated.
- //
- AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
- if (CetEnabled) {
- //
- // re-enable CET.
- //
- EnableCet ();
- }
- mIsReadOnlyPageTable = TRUE;
-
- return;
-}
-
-/**
- This function returns with no action for 32 bit.
@param[out] *Cr2 Pointer to variable to hold CR2 register value.
**/
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index a0daaa1900..5f0a38e400 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -260,7 +260,6 @@ extern UINTN mNumberOfCpus;
extern EFI_SMM_CPU_PROTOCOL mSmmCpu;
extern EFI_MM_MP_PROTOCOL mSmmMp;
extern BOOLEAN m5LevelPagingNeeded;
-extern BOOLEAN mIsReadOnlyPageTable;
///
/// The mode of the CPU at the time an SMI occurs
@@ -279,6 +278,24 @@ typedef struct {
UINTN FreePages;
} PAGE_TABLE_POOL;
+/**
+ Disable CET.
+**/
+VOID
+EFIAPI
+DisableCet (
+ VOID
+ );
+
+/**
+ Enable CET.
+**/
+VOID
+EFIAPI
+EnableCet (
+ VOID
+ );
+
//
// SMM CPU Protocol function prototypes.
//
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 8f0c6410e6..9f091c6485 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -1738,3 +1738,137 @@ EdkiiSmmGetMemoryAttributes (
return EFI_SUCCESS;
}
+
+/**
+ Prevent the memory pages used for SMM page table from been overwritten.
+**/
+VOID
+EnablePageTableProtection (
+ VOID
+ )
+{
+ PAGE_TABLE_POOL *HeadPool;
+ PAGE_TABLE_POOL *Pool;
+ UINT64 PoolSize;
+ EFI_PHYSICAL_ADDRESS Address;
+ UINTN PageTableBase;
+
+ if (mPageTablePool == NULL) {
+ return;
+ }
+
+ PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
+
+ //
+ // ConvertMemoryPageAttributes might update mPageTablePool. It's safer to
+ // remember original one in advance.
+ //
+ HeadPool = mPageTablePool;
+ Pool = HeadPool;
+ do {
+ Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool & PAGE_TABLE_POOL_ALIGN_MASK;
+ PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);
+
+ ConvertMemoryPageAttributes (PageTableBase, m5LevelPagingNeeded, Address, PoolSize, EFI_MEMORY_RO, TRUE, NULL, NULL);
+ Pool = Pool->NextPool;
+ } while (Pool != HeadPool);
+}
+
+/**
+ Return whether memory used by SMM page table need to be set as Read Only.
+
+ @retval TRUE Need to set SMM page table as Read Only.
+ @retval FALSE Do not set SMM page table as Read Only.
+**/
+BOOLEAN
+IfReadOnlyPageTableNeeded (
+ VOID
+ )
+{
+ //
+ // Don't mark page table memory as read-only if
+ // - no restriction on access to non-SMRAM memory; or
+ // - SMM heap guard feature enabled; or
+ // BIT2: SMM page guard enabled
+ // BIT3: SMM pool guard enabled
+ // - SMM profile feature enabled
+ //
+ if (!IsRestrictedMemoryAccess () ||
+ ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||
+ FeaturePcdGet (PcdCpuSmmProfileEnable))
+ {
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+ //
+ // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
+ //
+ ASSERT (
+ !(IsRestrictedMemoryAccess () &&
+ (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
+ );
+
+ //
+ // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
+ //
+ ASSERT (!(IsRestrictedMemoryAccess () && FeaturePcdGet (PcdCpuSmmProfileEnable)));
+ }
+
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ This function sets memory attribute for page table.
+**/
+VOID
+SetPageTableAttributes (
+ VOID
+ )
+{
+ BOOLEAN CetEnabled;
+
+ if (!IfReadOnlyPageTableNeeded ()) {
+ return;
+ }
+
+ DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
+
+ //
+ // Disable write protection, because we need mark page table to be write protected.
+ // We need *write* page table memory, to mark itself to be *read only*.
+ //
+ CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
+ if (CetEnabled) {
+ //
+ // CET must be disabled if WP is disabled.
+ //
+ DisableCet ();
+ }
+
+ AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
+
+ // Set memory used by page table as Read Only.
+ DEBUG ((DEBUG_INFO, "Start...\n"));
+ EnablePageTableProtection ();
+
+ //
+ // Enable write protection, after page table attribute updated.
+ //
+ AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
+ mIsReadOnlyPageTable = TRUE;
+
+ //
+ // Flush TLB after mark all page table pool as read only.
+ //
+ FlushTlbForAll ();
+
+ if (CetEnabled) {
+ //
+ // re-enable CET.
+ //
+ EnableCet ();
+ }
+
+ return;
+}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index d714ca5b5a..3deb1ffd67 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -20,24 +20,6 @@ BOOLEAN m1GPageTableSupport = FALSE;
BOOLEAN mCpuSmmRestrictedMemoryAccess;
X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded;
-/**
- Disable CET.
-**/
-VOID
-EFIAPI
-DisableCet (
- VOID
- );
-
-/**
- Enable CET.
-**/
-VOID
-EFIAPI
-EnableCet (
- VOID
- );
-
/**
Check if 1-GByte pages is supported by processor or not.
@@ -1157,158 +1139,6 @@ Exit:
ReleaseSpinLock (mPFLock);
}
-/**
- This function sets memory attribute for page table.
-**/
-VOID
-SetPageTableAttributes (
- VOID
- )
-{
- UINTN Index2;
- UINTN Index3;
- UINTN Index4;
- UINTN Index5;
- UINT64 *L1PageTable;
- UINT64 *L2PageTable;
- UINT64 *L3PageTable;
- UINT64 *L4PageTable;
- UINT64 *L5PageTable;
- UINTN PageTableBase;
- BOOLEAN IsSplitted;
- BOOLEAN PageTableSplitted;
- BOOLEAN CetEnabled;
- BOOLEAN Enable5LevelPaging;
- IA32_CR4 Cr4;
-
- //
- // Don't mark page table memory as read-only if
- // - no restriction on access to non-SMRAM memory; or
- // - SMM heap guard feature enabled; or
- // BIT2: SMM page guard enabled
- // BIT3: SMM pool guard enabled
- // - SMM profile feature enabled
- //
- if (!mCpuSmmRestrictedMemoryAccess ||
- ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||
- FeaturePcdGet (PcdCpuSmmProfileEnable))
- {
- //
- // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
- //
- ASSERT (
- !(mCpuSmmRestrictedMemoryAccess &&
- (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
- );
-
- //
- // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
- //
- ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable)));
- return;
- }
-
- DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
-
- //
- // Disable write protection, because we need mark page table to be write protected.
- // We need *write* page table memory, to mark itself to be *read only*.
- //
- CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
- if (CetEnabled) {
- //
- // CET must be disabled if WP is disabled.
- //
- DisableCet ();
- }
-
- AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
-
- do {
- DEBUG ((DEBUG_INFO, "Start...\n"));
- PageTableSplitted = FALSE;
- L5PageTable = NULL;
-
- PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
- Cr4.UintN = AsmReadCr4 ();
- Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
-
- if (Enable5LevelPaging) {
- L5PageTable = (UINT64 *)PageTableBase;
- SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
- }
-
- for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof (UINT64) : 1); Index5++) {
- if (Enable5LevelPaging) {
- L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
- if (L4PageTable == NULL) {
- continue;
- }
- } else {
- L4PageTable = (UINT64 *)PageTableBase;
- }
-
- SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
-
- for (Index4 = 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) {
- L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
- if (L3PageTable == NULL) {
- continue;
- }
-
- SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
-
- for (Index3 = 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) {
- if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
- // 1G
- continue;
- }
-
- L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
- if (L2PageTable == NULL) {
- continue;
- }
-
- SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
-
- for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
- if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
- // 2M
- continue;
- }
-
- L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
- if (L1PageTable == NULL) {
- continue;
- }
-
- SmmSetMemoryAttributesEx (PageTableBase, Enable5LevelPaging, (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
- PageTableSplitted = (PageTableSplitted || IsSplitted);
- }
- }
- }
- }
- } while (PageTableSplitted);
-
- //
- // Enable write protection, after page table updated.
- //
- AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
- if (CetEnabled) {
- //
- // re-enable CET.
- //
- EnableCet ();
- }
- mIsReadOnlyPageTable = TRUE;
-
- return;
-}
-
/**
This function reads CR2 register when on-demand paging is enabled.
--
2.31.1.windows.1
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-=-=-=-=-=-=-=-=-=-=-=-> + PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
> +
> + //
> + // ConvertMemoryPageAttributes might update mPageTablePool. It's safer to
> + // remember original one in advance.
> + //
> + HeadPool = mPageTablePool;
> + Pool = HeadPool;
> + do {
> + Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool & PAGE_TABLE_POOL_ALIGN_MASK;
1. When is the Pool not aligned on 128KB boundary? If it's guaranteed, can we remove the "& PAGE_TABLE_POOL_ALIGN_MASK"?
> + PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);
> +
> + ConvertMemoryPageAttributes (PageTableBase, m5LevelPagingNeeded, Address, PoolSize, EFI_MEMORY_RO, TRUE,
> NULL, NULL);
2. Can you please explain in comments that above call is to make the entire pool including header, used-memory, free-memory
as read-only?
3. It's better to use LinkedList library APIs from BaseLib. The comments apply to the first patch as well. But I am fine if you decide not to do it in this patch.
> + {
> + if (sizeof (UINTN) == sizeof (UINT64)) {
> + //
> + // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
> + //
> + ASSERT (
> + !(IsRestrictedMemoryAccess () &&
> + (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
> + );
> +
> + //
> + // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
> + //
> + ASSERT (!(IsRestrictedMemoryAccess () && FeaturePcdGet (PcdCpuSmmProfileEnable)));
> + }
4. I don't think we still need the above two assertions. But let's not clean up the code in your patch. @Wang, Jian J
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Thanks Ray for the comments. I'll modify the code in V2 patch set.
For comments 3, I'll replace the code by LinkedList library APIs from BaseLib in future patches.
Thanks,
Dun
-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Monday, December 19, 2022 3:53 PM
To: Tan, Dun <dun.tan@intel.com>; devel@edk2.groups.io; Wang, Jian J <jian.j.wang@intel.com>
Cc: Dong, Eric <eric.dong@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>
Subject: RE: [PATCH 3/3] UefiCpuPkg: Simplify the code to set smm page table as RO
> + PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
> +
> + //
> + // ConvertMemoryPageAttributes might update mPageTablePool. It's
> + safer to // remember original one in advance.
> + //
> + HeadPool = mPageTablePool;
> + Pool = HeadPool;
> + do {
> + Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool &
> + PAGE_TABLE_POOL_ALIGN_MASK;
1. When is the Pool not aligned on 128KB boundary? If it's guaranteed, can we remove the "& PAGE_TABLE_POOL_ALIGN_MASK"?
> + PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);
> +
> + ConvertMemoryPageAttributes (PageTableBase, m5LevelPagingNeeded,
> + Address, PoolSize, EFI_MEMORY_RO, TRUE,
> NULL, NULL);
2. Can you please explain in comments that above call is to make the entire pool including header, used-memory, free-memory
as read-only?
3. It's better to use LinkedList library APIs from BaseLib. The comments apply to the first patch as well. But I am fine if you decide not to do it in this patch.
> + {
> + if (sizeof (UINTN) == sizeof (UINT64)) {
> + //
> + // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
> + //
> + ASSERT (
> + !(IsRestrictedMemoryAccess () &&
> + (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
> + );
> +
> + //
> + // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
> + //
> + ASSERT (!(IsRestrictedMemoryAccess () && FeaturePcdGet (PcdCpuSmmProfileEnable)));
> + }
4. I don't think we still need the above two assertions. But let's not clean up the code in your patch. @Wang, Jian J
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