[v4] Add support for RISC-V virt machine

[edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 34/34] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file

Posted by Sunil V L 3 years, 3 months ago

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml b/UefiCpuPkg/UefiCpuPkg.ci.yaml
index bbdc44a45b34..ae963e94c8e6 100644
--- a/UefiCpuPkg/UefiCpuPkg.ci.yaml
+++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml
@@ -19,6 +19,7 @@
         ],
         ## Both file path and directory path are accepted.
         "IgnoreFiles": [
+          "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h"
         ]
     },
     "CompilerPlugin": {
-- 
2.38.0



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Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 34/34] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file

Posted by Chang, Abner via groups.io 3 years, 3 months ago

[AMD Official Use Only - General]

Acked-by: Abner Chang <abner.chang@amd.com>

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L
> via groups.io
> Sent: Saturday, October 15, 2022 12:49 AM
> To: devel@edk2.groups.io
> Cc: Eric Dong <eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Rahul
> Kumar <rahul1.kumar@intel.com>
> Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V4 34/34]
> UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> REF:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz
> illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&amp;data=05%7C01%7Ca
> bner.chang%40amd.com%7Cc44fef36461c4b58b7a208daae0497df%7C3dd896
> 1fe4884e608e11a82d994e183d%7C0%7C0%7C638013631999182833%7CUnkn
> own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=0xU0R9o1%2Fh
> CrVLmy61WPYjHJTu9EHmKDNMVlycpklMU%3D&amp;reserved=0
> 
> RISC-V register names do not follow the EDK2 formatting.
> So, add it to ignore list for now.
> 
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml
> b/UefiCpuPkg/UefiCpuPkg.ci.yaml index bbdc44a45b34..ae963e94c8e6
> 100644
> --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml
> +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml
> @@ -19,6 +19,7 @@
>          ],
>          ## Both file path and directory path are accepted.
>          "IgnoreFiles": [
> +          "Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h"
>          ]
>      },
>      "CompilerPlugin": {
> --
> 2.38.0
> 
> 
> 
> 
> 


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