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[edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

Nate DeSimone posted 4 patches 3 years, 8 months ago
There is a newer version of this series
[edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Posted by Nate DeSimone 3 years, 8 months ago 
Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
 .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the CometlakeURvp board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -253,6 +253,13 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   #
   # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
   #
-- 
2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Posted by Sinha, Ankit 3 years, 8 months ago 
Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>

> -----Original Message-----
> From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> Sent: Monday, June 6, 2022 3:50 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Esakkithevar, Kathappan
> <kathappan.esakkithevar@intel.com>
> Subject: [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>  .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> index 589b002d06..68dd08423b 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the CometlakeURvp board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -253,6 +253,13 @@
>    gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>    gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>    #
>    # The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
>    #
> --
> 2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
Posted by Michael Kubacki 3 years, 8 months ago 
Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com>

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register
> and indicate the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
>   .../CometlakeURvp/OpenBoardPkgPcd.dsc                    | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
> index 589b002d06..68dd08423b 100644
> --- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the CometlakeURvp board.
>   #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -253,6 +253,13 @@
>     gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>     gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register
> +  # and indicate the width of the clock duty cycle to OS power management
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>     #
>     # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
>     #


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