Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
devices to the system. For platforms that connect non-discoverable (non-
PCI) devices to IO virtualization block, add a SSDT table to describe
such devices and use PCDs for the memory region and interrupts of these
devices in the table entry.
There are two PL011 UART controllers and two PL330 DMA controllers
connected to the non-PCIe IO virtualization block on RD-N2 and
RD-N2-Cfg1 platforms. List them in the SSDT ACPI table.

While we are adding SSDT table entries for RD-N2 and RD-N2-Cfg1
remove the source file entries for incorrect SSDT and MCFG tables
for RD-N2 and RD-N2-Cfg1 platforms.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
 Platform/ARM/SgiPkg/SgiPlatform.dec                    |  42 ++++
 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc              |  40 ++++
 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf      |  45 ++++-
 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf  |  45 ++++-
 Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203 ++++++++++++++++++++
 5 files changed, 369 insertions(+), 6 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 05079743c452..6b3e28c3a08e 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -95,5 +95,47 @@
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025
   gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026
 
+  # IO virtualization block PL011 UARTs
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0|UINT64|0x0000002C
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0|UINT64|0x0000002D
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0|UINT64|0x0000002E
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|0|UINT32|0x0000002F
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0|UINT64|0x00000030
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0|UINT64|0x00000031
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0|UINT64|0x00000032
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|0|UINT32|0x00000033
+
+  # IO virtualization block PL330 DMA controllers
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base|0|UINT64|0x00000034
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End|0|UINT64|0x00000035
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size|0|UINT32|0x00000036
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh|0|UINT32|0x00000037
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv|0|UINT32|0x00000038
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv|0|UINT32|0x00000039
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv|0|UINT32|0x0000003A
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv|0|UINT32|0x0000003B
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv|0|UINT32|0x0000003C
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv|0|UINT32|0x0000003D
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv|0|UINT32|0x0000003E
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv|0|UINT32|0x0000003F
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv|0|UINT32|0x00000040
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0StreamIDBase|0|UINT32|0x00000041
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base|0|UINT64|0x00000042
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End|0|UINT64|0x00000043
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size|0|UINT32|0x00000044
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh|0|UINT32|0x00000045
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv|0|UINT32|0x00000046
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv|0|UINT32|0x00000047
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv|0|UINT32|0x00000048
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv|0|UINT32|0x00000049
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv|0|UINT32|0x0000004A
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv|0|UINT32|0x0000004B
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv|0|UINT32|0x0000004C
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv|0|UINT32|0x0000004D
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv|0|UINT32|0x0000004E
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase|0|UINT32|0x0000004F
+
 [Ppis]
   gNtFwConfigDtInfoPpiGuid     = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 94be353ca3ab..472795193b9e 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -65,3 +65,43 @@
   gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D0000
   gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x00010000
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|392
+
+  # IO virtualization block PL011 UARTs
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0xC00000000000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0xC0000000FFFF
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0x10000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|492
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0xC00020000000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0xC0002000FFFF
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0x10000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|502
+
+  # IO virtualization block PL330 DMA controllers
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base|0xC00010000000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End|0xC0001000FFFF
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size|0x10000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh|8
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv|493
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv|494
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv|495
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv|496
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv|497
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv|498
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv|499
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv|500
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv|501
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base|0xC00030000000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End|0xC0003000FFFF
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size|0x10000
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh|8
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv|503
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv|504
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv|505
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv|506
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv|507
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv|508
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv|509
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv|510
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv|511
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 25be2e276e85..fe50a7b6e44a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
 ## @file
 #  ACPI table data and ASL sources required to boot the platform.
 #
-#  Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
+#  Copyright (c) 2020-2022, Arm Ltd. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -19,14 +19,13 @@
   Fadt.aslc
   Gtdt.aslc
   Iort.aslc
-  Mcfg.aslc
   RdN2/Dsdt.asl
   RdN2/Madt.aslc
   RdN2/Pptt.aslc
   Spcr.aslc
-  Ssdt.asl
   SsdtRos.asl
   SsdtEvents.asl
+  SsdtNonPciIoVirtBlk.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -71,4 +70,44 @@
   gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
   gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
 
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0StreamIDBase
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase
+
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index 4b36c3e5ceb2..b5612e817d01 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -1,7 +1,7 @@
 ## @file
 #  ACPI table data and ASL sources required to boot the platform.
 #
-#  Copyright (c) 2021, Arm Ltd. All rights reserved.
+#  Copyright (c) 2021-2022, Arm Ltd. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -19,14 +19,13 @@
   Fadt.aslc
   Gtdt.aslc
   Iort.aslc
-  Mcfg.aslc
   RdN2Cfg1/Dsdt.asl
   RdN2Cfg1/Madt.aslc
   RdN2Cfg1/Pptt.aslc
   Spcr.aslc
-  Ssdt.asl
   SsdtRos.asl
   SsdtEvents.asl
+  SsdtNonPciIoVirtBlk.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
@@ -72,4 +71,44 @@
   gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
   gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
 
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0NumCh
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch0Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch1Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch2Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch3Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch4Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch5Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch6Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0Ch7Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0AbortGsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma0StreamIDBase
+
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Base
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1End
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Size
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1NumCh
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch0Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch1Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch2Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch3Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch4Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch5Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch6Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1Ch7Gsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1AbortGsiv
+  gArmSgiTokenSpaceGuid.PcdIoVirtBlkDma1StreamIDBase
+
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
new file mode 100644
index 000000000000..a035186b88db
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
@@ -0,0 +1,203 @@
+/** @file
+  Secondary System Description Table (SSDT) for Non-PCIe IO
+  Virtualization Block.
+
+  The IO virtualization block present on reference design platforms
+  such as RD-N2 and RD-N2-Cfg1 allows connecting PCIe and non-PCIe
+  devices. The non-discoverable (non-PCIe) devices that are connected
+  to the IO virtualization block include two PL011 UART and two PL330
+  DMA controllers.
+
+  Copyright (c) 2022, Arm Ltd. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+    - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System Description Table
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock ("SsdtIoVirtBlk.aml", "SSDT", 2, "ARMLTD", "ARMSGI",
+                 EFI_ACPI_ARM_OEM_REVISION) {
+  Scope (_SB) {
+
+    // IO Virtualization Block - PL011 UART0
+    Device (COM4) {
+      Name (_HID, "ARMH0011")
+      Name (_UID, 4)
+      Name (_STA, 0xF)
+
+      Name (_CRS, ResourceTemplate () {
+        QWordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0,
+          FixedPcdGet64 (PcdIoVirtBlkUart0Base),
+          FixedPcdGet64 (PcdIoVirtBlkUart0End),
+          0x0,
+          FixedPcdGet32 (PcdIoVirtBlkUart0Size),
+          ,
+          ,
+          ,
+          AddressRangeMemory,
+          TypeStatic
+        )
+
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkUart0Interrupt)
+        }
+      })
+    }
+
+    // IO Virtualization Block - PL011 UART1
+    Device (COM5) {
+      Name (_HID, "ARMH0011")
+      Name (_UID, 5)
+      Name (_STA, 0xF)
+
+      Name (_CRS, ResourceTemplate () {
+        QWordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0,
+          FixedPcdGet64 (PcdIoVirtBlkUart1Base),
+          FixedPcdGet64 (PcdIoVirtBlkUart1End),
+          0x0,
+          FixedPcdGet32 (PcdIoVirtBlkUart1Size),
+          ,
+          ,
+          ,
+          AddressRangeMemory,
+          TypeStatic
+        )
+
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkUart1Interrupt)
+        }
+      })
+    }
+
+    // IO Virtualization Block - PL330 DMA0
+    Device (\_SB.DMA0) {
+      Name (_HID, "ARMH0330")
+      Name (_UID, 0)
+      Name (_CCA, 1)
+      Name (_STA, 0xF)
+
+      Name (_CRS, ResourceTemplate () {
+        QWordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0,
+          FixedPcdGet64 (PcdIoVirtBlkDma0Base),
+          FixedPcdGet64 (PcdIoVirtBlkDma0End),
+          0x0,
+          FixedPcdGet32 (PcdIoVirtBlkDma0Size),
+          ,
+          ,
+          ,
+          AddressRangeMemory,
+          TypeStatic
+        )
+
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch0Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch1Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch2Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch3Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch4Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch5Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch6Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0Ch7Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma0AbortGsiv)
+        }
+      })
+    }
+
+    // IO Virtualization Block - PL330 DMA1
+    Device (\_SB.DMA1) {
+      Name (_HID, "ARMH0330")
+      Name (_UID, 1)
+      Name (_CCA, 1)
+      Name (_STA, 0xF)
+
+      Name (_CRS, ResourceTemplate () {
+        QWordMemory (
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          NonCacheable,
+          ReadWrite,
+          0x0,
+          FixedPcdGet64 (PcdIoVirtBlkDma1Base),
+          FixedPcdGet64 (PcdIoVirtBlkDma1End),
+          0x0,
+          FixedPcdGet32 (PcdIoVirtBlkDma1Size),
+          ,
+          ,
+          ,
+          AddressRangeMemory,
+          TypeStatic
+        )
+
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch0Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch1Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch2Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch3Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch4Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch5Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch6Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1Ch7Gsiv)
+        }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
+          FixedPcdGet32 (PcdIoVirtBlkDma1AbortGsiv)
+        }
+      })
+    }
+  } // Scope(_SB)
+}
-- 
2.17.1



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Hello Vivek,
Sorry for the long wait. I think the whole patchset needs to be
rebased on latest master. I just have some comments for patches:
- [PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO virtualization block
- [PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers
The other patches look good to me.

Regards,
Pierre

On 2/14/22 13:13, Vivek Kumar Gautam via groups.io wrote:
> Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have multiple
> IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
> devices to the system. For platforms that connect non-discoverable (non-
> PCI) devices to IO virtualization block, add a SSDT table to describe
> such devices and use PCDs for the memory region and interrupts of these
> devices in the table entry.
> There are two PL011 UART controllers and two PL330 DMA controllers
> connected to the non-PCIe IO virtualization block on RD-N2 and
> RD-N2-Cfg1 platforms. List them in the SSDT ACPI table.
> 
> While we are adding SSDT table entries for RD-N2 and RD-N2-Cfg1
> remove the source file entries for incorrect SSDT and MCFG tables
> for RD-N2 and RD-N2-Cfg1 platforms.
> 
> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
> ---
>   Platform/ARM/SgiPkg/SgiPlatform.dec                    |  42 ++++
>   Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc              |  40 ++++
>   Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf      |  45 ++++-
>   Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf  |  45 ++++-
>   Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203 ++++++++++++++++++++
>   5 files changed, 369 insertions(+), 6 deletions(-)
> 
> diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
> index 05079743c452..6b3e28c3a08e 100644
> --- a/Platform/ARM/SgiPkg/SgiPlatform.dec
> +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
> @@ -95,5 +95,47 @@
>     gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025
>     gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026
>   
> +  # IO virtualization block PL011 UARTs
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0|UINT64|0x0000002C
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0|UINT64|0x0000002D

I think it should be possible to remove all the Pcd*End addresses and
replace them with (PcdIoVirtBlkUart0Base + PcdIoVirtBlkUart0Size - 1).

> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0|UINT64|0x0000002E
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|0|UINT32|0x0000002F
> +
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0|UINT64|0x00000030
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0|UINT64|0x00000031
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0|UINT64|0x00000032
> +  gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|0|UINT32|0x00000033
> +

[...]

>     gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
> new file mode 100644
> index 000000000000..a035186b88db
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
> @@ -0,0 +1,203 @@
> +/** @file
> +  Secondary System Description Table (SSDT) for Non-PCIe IO
> +  Virtualization Block.
> +
> +  The IO virtualization block present on reference design platforms
> +  such as RD-N2 and RD-N2-Cfg1 allows connecting PCIe and non-PCIe
> +  devices. The non-discoverable (non-PCIe) devices that are connected
> +  to the IO virtualization block include two PL011 UART and two PL330
> +  DMA controllers.
> +
> +  Copyright (c) 2022, Arm Ltd. All rights reserved.
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +  @par Specification Reference:
> +    - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System Description Table
> +**/
> +
> +#include "SgiPlatform.h"
> +#include "SgiAcpiHeader.h"
> +
> +DefinitionBlock ("SsdtIoVirtBlk.aml", "SSDT", 2, "ARMLTD", "ARMSGI",
> +                 EFI_ACPI_ARM_OEM_REVISION) {
> +  Scope (_SB) {
> +
> +    // IO Virtualization Block - PL011 UART0
> +    Device (COM4) {
> +      Name (_HID, "ARMH0011")
> +      Name (_UID, 4)
> +      Name (_STA, 0xF)
> +
> +      Name (_CRS, ResourceTemplate () {
> +        QWordMemory (
> +          ResourceProducer,
> +          PosDecode,
> +          MinFixed,
> +          MaxFixed,
> +          NonCacheable,
> +          ReadWrite,
> +          0x0,
> +          FixedPcdGet64 (PcdIoVirtBlkUart0Base),
> +          FixedPcdGet64 (PcdIoVirtBlkUart0End),
> +          0x0,
> +          FixedPcdGet32 (PcdIoVirtBlkUart0Size),
> +          ,
> +          ,
> +          ,
> +          AddressRangeMemory,
> +          TypeStatic
> +        )
> +
> +        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
> +          FixedPcdGet32 (PcdIoVirtBlkUart0Interrupt)
> +        }
> +      })
> +    }
> +
> +    // IO Virtualization Block - PL011 UART1
> +    Device (COM5) {
> +      Name (_HID, "ARMH0011")
> +      Name (_UID, 5)
> +      Name (_STA, 0xF)
> +
> +      Name (_CRS, ResourceTemplate () {
> +        QWordMemory (
> +          ResourceProducer,
> +          PosDecode,
> +          MinFixed,
> +          MaxFixed,
> +          NonCacheable,
> +          ReadWrite,
> +          0x0,
> +          FixedPcdGet64 (PcdIoVirtBlkUart1Base),
> +          FixedPcdGet64 (PcdIoVirtBlkUart1End),
> +          0x0,
> +          FixedPcdGet32 (PcdIoVirtBlkUart1Size),
> +          ,
> +          ,
> +          ,
> +          AddressRangeMemory,
> +          TypeStatic
> +        )
> +
> +        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
> +          FixedPcdGet32 (PcdIoVirtBlkUart1Interrupt)
> +        }
> +      })
> +    }
> +
> +    // IO Virtualization Block - PL330 DMA0
> +    Device (\_SB.DMA0) {
> +      Name (_HID, "ARMH0330")

Is there a specification for the description of this _HID and how
it should be represented in ACPI ?


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Hi Pierre,

On 12/7/22 19:04, Pierre Gondois wrote:
> Hello Vivek,
> Sorry for the long wait. I think the whole patchset needs to be
> rebased on latest master. I just have some comments for patches:
> - [PATCH V1 2/6] Platform/Sgi: add ssdt table for non-discoverable IO 
> virtualization block
> - [PATCH V1 3/6] Platform/Sgi: Initialize additional uart controllers
> The other patches look good to me.
>

Thank you for your review and apologies for responding late. I was able 
to rework the patches and get a cleaner SSDT table implementation. I 
will post the patches soon.

Please see my responses inline.

> Regards,
> Pierre
>
> On 2/14/22 13:13, Vivek Kumar Gautam via groups.io wrote:
>> Arm reference design platforms such as RD-N2 and RD-N2-Cfg1 have 
>> multiple
>> IO virtualization blocks that allow connecting PCIe root bus or non-PCIe
>> devices to the system. For platforms that connect non-discoverable (non-
>> PCI) devices to IO virtualization block, add a SSDT table to describe
>> such devices and use PCDs for the memory region and interrupts of these
>> devices in the table entry.
>> There are two PL011 UART controllers and two PL330 DMA controllers
>> connected to the non-PCIe IO virtualization block on RD-N2 and
>> RD-N2-Cfg1 platforms. List them in the SSDT ACPI table.
>>
>> While we are adding SSDT table entries for RD-N2 and RD-N2-Cfg1
>> remove the source file entries for incorrect SSDT and MCFG tables
>> for RD-N2 and RD-N2-Cfg1 platforms.
>>
>> Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
>> ---
>>   Platform/ARM/SgiPkg/SgiPlatform.dec                    |  42 ++++
>>   Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc              |  40 ++++
>>   Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf      |  45 ++++-
>>   Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf  |  45 ++++-
>>   Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl | 203 
>> ++++++++++++++++++++
>>   5 files changed, 369 insertions(+), 6 deletions(-)
>>
>> diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
>> b/Platform/ARM/SgiPkg/SgiPlatform.dec
>> index 05079743c452..6b3e28c3a08e 100644
>> --- a/Platform/ARM/SgiPkg/SgiPlatform.dec
>> +++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
>> @@ -95,5 +95,47 @@
>>     gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x00000025
>>     gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x00000026
>>   +  # IO virtualization block PL011 UARTs
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Base|0|UINT64|0x0000002C
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0End|0|UINT64|0x0000002D
>
> I think it should be possible to remove all the Pcd*End addresses and
> replace them with (PcdIoVirtBlkUart0Base + PcdIoVirtBlkUart0Size - 1).

I will post the reworked patch-set addressing this.

>
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Size|0|UINT64|0x0000002E
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart0Interrupt|0|UINT32|0x0000002F
>> +
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Base|0|UINT64|0x00000030
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1End|0|UINT64|0x00000031
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Size|0|UINT64|0x00000032
>> + gArmSgiTokenSpaceGuid.PcdIoVirtBlkUart1Interrupt|0|UINT32|0x00000033
>> +
>
> [...]
>
>> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
>> diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl 
>> b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
>> new file mode 100644
>> index 000000000000..a035186b88db
>> --- /dev/null
>> +++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtNonPciIoVirtBlk.asl
>> @@ -0,0 +1,203 @@
>> +/** @file
>> +  Secondary System Description Table (SSDT) for Non-PCIe IO
>> +  Virtualization Block.
>> +
>> +  The IO virtualization block present on reference design platforms
>> +  such as RD-N2 and RD-N2-Cfg1 allows connecting PCIe and non-PCIe
>> +  devices. The non-discoverable (non-PCIe) devices that are connected
>> +  to the IO virtualization block include two PL011 UART and two PL330
>> +  DMA controllers.
>> +
>> +  Copyright (c) 2022, Arm Ltd. All rights reserved.
>> +  SPDX-License-Identifier: BSD-2-Clause-Patent
>> +
>> +  @par Specification Reference:
>> +    - ACPI 6.4, Chapter 5, Section 5.2.11.2, Secondary System 
>> Description Table
>> +**/

[snip]

>>
>> +
>> +    // IO Virtualization Block - PL330 DMA0
>> +    Device (\_SB.DMA0) {
>> +      Name (_HID, "ARMH0330")
>
> Is there a specification for the description of this _HID and how
> it should be represented in ACPI ?

Yes, this can be found in the ACPI specification here [1]. The Linux 
kernel documentation also describes it here [2] as the primary object to 
use in device probing.

[1] 
https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html#device-identification-objects
[2] https://docs.kernel.org/arm64/acpi_object_usage.html


Best regards
Vivek



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