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[edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support

Khasim Mohammed posted 3 patches 4 years, 2 months ago
There is a newer version of this series
[edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Posted by Khasim Mohammed 4 years, 2 months ago 
This patch enables CCIX root complex support by updating
the root complex node info in PciHostBridge library
and enabling PciSegment library for N1Sdp.

Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
---
 .../ConfigurationManagerDxe.inf               |  3 +-
 Platform/ARM/N1Sdp/N1SdpPlatform.dec          |  3 -
 Platform/ARM/N1Sdp/N1SdpPlatform.dsc          |  3 +-
 .../PciHostBridgeLib/PciHostBridgeLib.c       | 71 +++++++++++++++++--
 .../PciHostBridgeLib/PciHostBridgeLib.inf     | 11 ++-
 .../Library/PlatformLib/PlatformLib.inf       |  1 +
 .../Library/PlatformLib/PlatformLibMem.c      |  4 +-
 7 files changed, 81 insertions(+), 15 deletions(-)

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index 027a4202ff..67b0c3a0ea 100644
--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -76,8 +76,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
   gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
 
-  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
-
   gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
   gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
 
@@ -91,6 +89,7 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
index 2ab6c20dcc..98d2d5ba81 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
@@ -34,9 +34,6 @@
   gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
   gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
 
-  # PCIe
-  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
-
   # External memory
   gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
 
diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
index 7488bdc036..75d7871452 100644
--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
@@ -75,7 +75,7 @@
 [LibraryClasses.common.DXE_DRIVER]
   FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
   PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
-  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+  PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
   PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
   PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
 
@@ -127,7 +127,6 @@
   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
 
   # PCIe
-  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
   gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
 
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 9332939f63..c3a14a6c17 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -1,7 +1,7 @@
 /** @file
 *  PCI Host Bridge Library instance for ARM Neoverse N1 platform
 *
-*  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+*  Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -16,6 +16,8 @@
 #include <Protocol/PciHostBridgeResourceAllocation.h>
 #include <Protocol/PciRootBridgeIo.h>
 
+#define ROOT_COMPLEX_NUM 2
+
 GLOBAL_REMOVE_IF_UNREFERENCED
 STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
   L"Mem", L"I/O", L"Bus"
@@ -28,7 +30,7 @@ typedef struct {
 } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
 #pragma pack ()
 
-STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
   // PCIe
   {
     {
@@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
         0
       }
     }
-  }
+  },
+  //CCIX
+  {
+    {
+      {
+        ACPI_DEVICE_PATH,
+        ACPI_DP,
+        {
+          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+        }
+      },
+      EISA_PNP_ID(0x0A09), // CCIX
+      0
+    },
+    {
+      END_DEVICE_PATH_TYPE,
+      END_ENTIRE_DEVICE_PATH_SUBTYPE,
+      {
+        END_DEVICE_PATH_LENGTH,
+        0
+      }
+    }
+  },
 };
 
-STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
+STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
   {
     0,                                              // Segment
     0,                                              // Supports
@@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
       0
     },
     (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
-  }
+  },
+  {
+    1,                                              // Segment
+    0,                                              // Supports
+    0,                                              // Attributes
+    TRUE,                                           // DmaAbove4G
+    FALSE,                                          // NoExtendedConfigSpace
+    FALSE,                                          // ResourceAssigned
+    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
+    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+    {
+      // Bus
+      FixedPcdGet32 (PcdCcixBusMin),
+      FixedPcdGet32 (PcdCcixBusMax)
+    }, {
+      // Io
+      FixedPcdGet64 (PcdCcixIoBase),
+      FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
+    }, {
+      // Mem
+      FixedPcdGet32 (PcdCcixMmio32Base),
+      FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
+    }, {
+      // MemAbove4G
+      FixedPcdGet64 (PcdCcixMmio64Base),
+      FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
+    }, {
+      // PMem
+      MAX_UINT64,
+      0
+    }, {
+      // PMemAbove4G
+      MAX_UINT64,
+      0
+    },
+    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+  },
 };
 
 /**
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 3ff1c592f2..3356c3ad35 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -1,7 +1,7 @@
 ## @file
 #  PCI Host Bridge Library instance for ARM Neoverse N1 platform.
 #
-#  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+#  Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -42,6 +42,15 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
 
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+
 [Protocols]
   gEfiCpuIo2ProtocolGuid
 
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 8e2154aadf..96e590cdd8 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -43,6 +43,7 @@
   gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
   gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 1c4a445c5e..339fa07b32 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // PCIe ECAM Configuration Space
-  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPciExpressBaseAddress);
-  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPciExpressBaseAddress);
+  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPcieExpressBaseAddress);
+  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPcieExpressBaseAddress);
   VirtualMemoryTable[Index].Length          = (FixedPcdGet32 (PcdPcieBusMax) -
                                                FixedPcdGet32 (PcdPcieBusMin) + 1) *
                                               SIZE_1MB;
-- 
2.17.1



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Re: [edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Posted by PierreGondois 4 years, 2 months ago 
Hi Khasim,

On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote:
> This patch enables CCIX root complex support by updating
> the root complex node info in PciHostBridge library
> and enabling PciSegment library for N1Sdp.
>
> Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28
> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
> ---
>  .../ConfigurationManagerDxe.inf               |  3 +-
>  Platform/ARM/N1Sdp/N1SdpPlatform.dec          |  3 -
>  Platform/ARM/N1Sdp/N1SdpPlatform.dsc          |  3 +-
>  .../PciHostBridgeLib/PciHostBridgeLib.c       | 71 +++++++++++++++++--
>  .../PciHostBridgeLib/PciHostBridgeLib.inf     | 11 ++-
>  .../Library/PlatformLib/PlatformLib.inf       |  1 +
>  .../Library/PlatformLib/PlatformLibMem.c      |  4 +-
>  7 files changed, 81 insertions(+), 15 deletions(-)
>
> diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> index 027a4202ff..67b0c3a0ea 100644
> --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
> @@ -76,8 +76,6 @@
>    gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
>    gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
>  
> -  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
> -
>    gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
>    gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
>  
> @@ -91,6 +89,7 @@
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> index 2ab6c20dcc..98d2d5ba81 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
> @@ -34,9 +34,6 @@
>    gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
>    gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
>  
> -  # PCIe
> -  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
> -

I think the "# Remote Chip PCIe" definitions also need to be removed.

Unrelated to this, but it seems there are some hard-coded PCI values at

https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c#L1050

that are also defined as Pcds. Would it be possible to replace the hard coded values ?

>    # External memory
>    gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
>  
> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> index 7488bdc036..75d7871452 100644
> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
> @@ -75,7 +75,7 @@
>  [LibraryClasses.common.DXE_DRIVER]
>    FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
>    PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> -  PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
> +  PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>    PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>    PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
>  
> @@ -127,7 +127,6 @@
>    gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
>  
>    # PCIe
> -  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
>    gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
>    gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
>  
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> index 9332939f63..c3a14a6c17 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -1,7 +1,7 @@
>  /** @file
>  *  PCI Host Bridge Library instance for ARM Neoverse N1 platform
>  *
> -*  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +*  Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
>  *
>  *  SPDX-License-Identifier: BSD-2-Clause-Patent
>  *
> @@ -16,6 +16,8 @@
>  #include <Protocol/PciHostBridgeResourceAllocation.h>
>  #include <Protocol/PciRootBridgeIo.h>
>  
> +#define ROOT_COMPLEX_NUM 2
> +
>  GLOBAL_REMOVE_IF_UNREFERENCED
>  STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
>    L"Mem", L"I/O", L"Bus"
> @@ -28,7 +30,7 @@ typedef struct {
>  } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
>  #pragma pack ()
>  
> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
>    // PCIe
>    {
>      {
> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
>          0
>        }
>      }
> -  }
> +  },
> +  //CCIX
> +  {
> +    {
> +      {
> +        ACPI_DEVICE_PATH,
> +        ACPI_DP,
> +        {
> +          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
> +          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> +        }
> +      },
> +      EISA_PNP_ID(0x0A09), // CCIX
> +      0
> +    },
> +    {
> +      END_DEVICE_PATH_TYPE,
> +      END_ENTIRE_DEVICE_PATH_SUBTYPE,
> +      {
> +        END_DEVICE_PATH_LENGTH,
> +        0
> +      }
> +    }
> +  },
>  };
>  
> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
>    {
>      0,                                              // Segment
>      0,                                              // Supports
> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
>        0
>      },
>      (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
> -  }
> +  },
> +  {
> +    1,                                              // Segment
> +    0,                                              // Supports
> +    0,                                              // Attributes
> +    TRUE,                                           // DmaAbove4G
> +    FALSE,                                          // NoExtendedConfigSpace
> +    FALSE,                                          // ResourceAssigned
> +    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
> +    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
> +    {
> +      // Bus
> +      FixedPcdGet32 (PcdCcixBusMin),
> +      FixedPcdGet32 (PcdCcixBusMax)
> +    }, {
> +      // Io
> +      FixedPcdGet64 (PcdCcixIoBase),
> +      FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
> +    }, {
> +      // MemSilicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +      FixedPcdGet32 (PcdCcixMmio32Base),
> +      FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
> +    }, {
> +      // MemAbove4G
> +      FixedPcdGet64 (PcdCcixMmio64Base),
> +      FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
> +    }, {
> +      // PMem
> +      MAX_UINT64,
> +      0
> +    }, {
> +      // PMemAbove4G
> +      MAX_UINT64,
> +      0
> +    },
> +    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
> +  },
>  };
>  
>  /**
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> index 3ff1c592f2..3356c3ad35 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCI Host Bridge Library instance for ARM Neoverse N1 platform.
>  #
> -#  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +#  Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> @@ -42,6 +42,15 @@
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
>  
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
> +
>  [Protocols]
>    gEfiCpuIo2ProtocolGuid
>  
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> index 8e2154aadf..96e590cdd8 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> @@ -43,6 +43,7 @@
>    gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
> +  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
>    gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> index 1c4a445c5e..339fa07b32 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
> @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
>    VirtualMemoryTable[Index].Attributes      = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>  
>    // PCIe ECAM Configuration Space
> -  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPciExpressBaseAddress);
> -  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPciExpressBaseAddress);
> +  VirtualMemoryTable[++Index].PhysicalBase  = PcdGet64 (PcdPcieExpressBaseAddress);
> +  VirtualMemoryTable[Index].VirtualBase     = PcdGet64 (PcdPcieExpressBaseAddress);
>    VirtualMemoryTable[Index].Length          = (FixedPcdGet32 (PcdPcieBusMax) -
>                                                 FixedPcdGet32 (PcdPcieBusMin) + 1) *
>                                                SIZE_1MB;


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Re: [edk2-devel] [PATCH v2 3/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support
Posted by Khasim Mohammed 4 years, 2 months ago 
On Tue, Nov 30, 2021 at 09:06 AM, PierreGondois wrote:
Hi Pierre,

> 
> Hi Khasim,
> 
> On 11/23/21 1:26 PM, Khasim Mohammed via groups.io wrote:
> 
>> This patch enables CCIX root complex support by updating
>> the root complex node info in PciHostBridge library
>> and enabling PciSegment library for N1Sdp.
>> 
>> Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28
>> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
>> ---
>> .../ConfigurationManagerDxe.inf | 3 +-
>> Platform/ARM/N1Sdp/N1SdpPlatform.dec | 3 -
>> Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 3 +-
>> .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++--
>> .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++-
>> .../Library/PlatformLib/PlatformLib.inf | 1 +
>> .../Library/PlatformLib/PlatformLibMem.c | 4 +-
>> 7 files changed, 81 insertions(+), 15 deletions(-)
>> 
>> diff --git
>> a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
>> b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
>> 
>> index 027a4202ff..67b0c3a0ea 100644
>> ---
>> a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
>> 
>> +++
>> b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
>> 
>> @@ -76,8 +76,6 @@
>> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
>> gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
>> 
>> - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
>> -
>> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
>> gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
>> 
>> @@ -91,6 +89,7 @@
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
>> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
>> b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
>> index 2ab6c20dcc..98d2d5ba81 100644
>> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec
>> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec
>> @@ -34,9 +34,6 @@
>> gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001
>> gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002
>> 
>> - # PCIe
>> -
>> gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|0x00000007
>> 
>> -
> 
> I think the "# Remote Chip PCIe" definitions also need to be removed.

I removed these in v3 posted just now.

> 
> Unrelated to this, but it seems there are some hard-coded PCI values at
> 
> https://github.com/tianocore/edk2-platforms/blob/master/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c#L1050
> 
> 
> that are also defined as Pcds. Would it be possible to replace the hard
> coded values ?

Have removed the hardcoded entries and changed with PCDs.

> 
> 
>> # External memory
>> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x00000029
>> 
>> diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
>> b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
>> index 7488bdc036..75d7871452 100644
>> --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
>> +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc
>> @@ -75,7 +75,7 @@
>> [LibraryClasses.common.DXE_DRIVER]
>> FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
>> PciHostBridgeLib|Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> 
>> -
>> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
>> 
>> +
>> PciSegmentLib|Silicon/ARM/NeoverseN1Soc/Library/PciSegmentLib/PciSegmentLib.inf
>> 
>> PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>> PciExpressLib|Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf
>> 
>> 
>> @@ -127,7 +127,6 @@
>> gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000
>> 
>> # PCIe
>> - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000
>> gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
>> gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
>> 
>> diff --git
>> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> index 9332939f63..c3a14a6c17 100644
>> ---
>> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> +++
>> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> @@ -1,7 +1,7 @@
>> /** @file
>> * PCI Host Bridge Library instance for ARM Neoverse N1 platform
>> *
>> -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
>> +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
>> *
>> * SPDX-License-Identifier: BSD-2-Clause-Patent
>> *
>> @@ -16,6 +16,8 @@
>> #include <Protocol/PciHostBridgeResourceAllocation.h>
>> #include <Protocol/PciRootBridgeIo.h>
>> 
>> +#define ROOT_COMPLEX_NUM 2
>> +
>> GLOBAL_REMOVE_IF_UNREFERENCED
>> STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
>> 
>> L"Mem", L"I/O", L"Bus"
>> @@ -28,7 +30,7 @@ typedef struct {
>> } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
>> #pragma pack ()
>> 
>> -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
>> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH
>> mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
>> // PCIe
>> {
>> {
>> @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH
>> mEfiPciRootBridgeDevicePath[] = {
>> 0
>> }
>> }
>> - }
>> + },
>> + //CCIX
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID(0x0A09), // CCIX
>> + 0
>> + },
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> };
>> 
>> -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
>> +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
>> {
>> 0, // Segment
>> 0, // Supports
>> @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] = {
>> 0
>> },
>> (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
>> - }
>> + },
>> + {
>> + 1, // Segment
>> + 0, // Supports
>> + 0, // Attributes
>> + TRUE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
>> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
>> + {
>> + // Bus
>> + FixedPcdGet32 (PcdCcixBusMin),
>> + FixedPcdGet32 (PcdCcixBusMax)
>> + }, {
>> + // Io
>> + FixedPcdGet64 (PcdCcixIoBase),
>> + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
>> + }, {
>> + // MemSilicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
>> + FixedPcdGet32 (PcdCcixMmio32Base),
>> + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) -
>> 1
>> + }, {
>> + // MemAbove4G
>> + FixedPcdGet64 (PcdCcixMmio64Base),
>> + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) -
>> 1
>> + }, {
>> + // PMem
>> + MAX_UINT64,
>> + 0
>> + }, {
>> + // PMemAbove4G
>> + MAX_UINT64,
>> + 0
>> + },
>> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
>> + },
>> };
>> 
>> /**
>> diff --git
>> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> index 3ff1c592f2..3356c3ad35 100644
>> ---
>> a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> +++
>> b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> @@ -1,7 +1,7 @@
>> ## @file
>> # PCI Host Bridge Library instance for ARM Neoverse N1 platform.
>> #
>> -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
>> +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.<BR>
>> #
>> # SPDX-License-Identifier: BSD-2-Clause-Patent
>> #
>> @@ -42,6 +42,15 @@
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
>> 
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
>> +
>> [Protocols]
>> gEfiCpuIo2ProtocolGuid
>> 
>> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
>> b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
>> index 8e2154aadf..96e590cdd8 100644
>> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
>> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
>> @@ -43,6 +43,7 @@
>> gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
>> + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
>> gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
>> diff --git
>> a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
>> b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
>> index 1c4a445c5e..339fa07b32 100644
>> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
>> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
>> @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap (
>> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> 
>> 
>> // PCIe ECAM Configuration Space
>> - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64
>> (PcdPciExpressBaseAddress);
>> - VirtualMemoryTable[Index].VirtualBase = PcdGet64
>> (PcdPciExpressBaseAddress);
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64
>> (PcdPcieExpressBaseAddress);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64
>> (PcdPcieExpressBaseAddress);
>> VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPcieBusMax) -
>> FixedPcdGet32 (PcdPcieBusMin) + 1) *
>> SIZE_1MB;
> 
>


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