UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 67 +++++++++++++++++++- UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 3 +- UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf | 4 +- UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 1 + UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf | 4 +- 5 files changed, 75 insertions(+), 4 deletions(-)
From: Jason <yun.lou@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3508
Sort the CpuCacheInfo array by the core type values from largest to
smallest.
Signed-off-by: Jason Lou <yun.lou@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 67 +++++++++++++++++++-
UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 3 +-
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf | 4 +-
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 1 +
UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf | 4 +-
5 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index 126ee0da86..fa4850c4fe 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -37,6 +37,69 @@ CpuCacheInfoPrintCpuCacheInfoTable (
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
}
+/**
+ Function to compare core type for use in QuickSort.
+
+ @param[in] Buffer1 pointer to core type poiner to compare
+ @param[in] Buffer2 pointer to second core type pointer to compare
+
+ @retval 0 Buffer1 equal to Buffer2
+ @retval 1 Buffer1 is less than Buffer2
+ @retval -1 Buffer1 is greater than Buffer2
+**/
+INTN
+EFIAPI
+CpuCacheInfoCompareCoreType (
+ IN CONST VOID *Buffer1,
+ IN CONST VOID *Buffer2
+ )
+{
+ if (((CPU_CACHE_INFO*)Buffer1)->CoreType == ((CPU_CACHE_INFO*)Buffer2)->CoreType) {
+ return 0;
+ } else if (((CPU_CACHE_INFO*)Buffer1)->CoreType < ((CPU_CACHE_INFO*)Buffer2)->CoreType) {
+ return 1;
+ } else {
+ return -1;
+ }
+}
+
+/**
+ Sort CpuCacheInfo array by the core type values from largest to smallest.
+
+ @param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.
+ @param[in] CpuCacheInfoCount The length of CpuCacheInfo array.
+
+**/
+VOID
+CpuCacheInfoSort (
+ IN OUT CPU_CACHE_INFO *CpuCacheInfo,
+ IN UINTN CpuCacheInfoCount
+ )
+{
+ UINTN Index;
+ UINTN NextIndex;
+ UINT32 CurrentPackage;
+ UINT8 CacheInfoCountPerPackage;
+
+ for (Index = 0; Index < CpuCacheInfoCount; Index += CacheInfoCountPerPackage) {
+ //
+ // Calculate the number of CpuCacheInfo current processor has.
+ //
+ CurrentPackage = CpuCacheInfo[Index].Package;
+ CacheInfoCountPerPackage = 1;
+ for (NextIndex = Index + 1; NextIndex < CpuCacheInfoCount; NextIndex++) {
+ if (CurrentPackage == CpuCacheInfo[NextIndex].Package) {
+ CacheInfoCountPerPackage++;
+ }
+ }
+
+ //
+ // Sort CpuCacheInfo for current processor by the core type values from largest to smallest.
+ //
+ PerformQuickSort (&CpuCacheInfo[Index], CacheInfoCountPerPackage, sizeof (*CpuCacheInfo), (SORT_COMPARE) CpuCacheInfoCompareCoreType);
+ }
+}
+
/**
Get the total number of package and package ID in the platform.
@@ -325,6 +388,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
if (*CacheInfoCount < LocalCacheInfoCount) {
Status = EFI_BUFFER_TOO_SMALL;
} else {
+ CpuCacheInfoSort (LocalCacheInfo, LocalCacheInfoCount);
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount);
DEBUG_CODE (
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
@@ -340,7 +404,8 @@ CpuCacheInfoCollectCpuCacheInfoData (
}
/**
- Get CpuCacheInfo data array.
+ Get CpuCacheInfo data array. The data array is sorted by CPU package ID from smallest to largest,
+ by core type from largest to smallest and by cache level from smallest to largest.
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.
@param[in, out] CpuCacheInfoCount As input, point to the length of response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
index a66152bce0..d813f53bf7 100644
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -59,7 +59,8 @@ typedef struct {
} CPU_CACHE_INFO;
/**
- Get CpuCacheInfo data array.
+ Get CpuCacheInfo data array. The data array is sorted by CPU package ID from smallest to largest,
+ by core type from largest to smallest and by cache level from smallest to largest.
@param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.
@param[in, out] CpuCacheInfoCount As input, point to the length of response CpuCacheInfo array.
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
index c481080e49..c3d3f1e799 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#
# Provides cache info for each package, core type, cache level and cache type.
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,6 +25,7 @@
[Packages]
MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
@@ -33,6 +34,7 @@
BaseMemoryLib
MemoryAllocationLib
UefiBootServicesTableLib
+ SortLib
[Protocols]
gEfiMpServiceProtocolGuid
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
index b6e6ae5bc5..089d259b3f 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
@@ -17,6 +17,7 @@
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/SortLib.h>
#include <Library/CpuCacheInfoLib.h>
typedef struct {
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
index 0c73015cac..0864497849 100644
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
@@ -3,7 +3,7 @@
#
# Provides cache info for each package, core type, cache level and cache type.
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,6 +25,7 @@
[Packages]
MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
@@ -33,6 +34,7 @@
BaseMemoryLib
MemoryAllocationLib
PeiServicesTablePointerLib
+ SortLib
[Ppis]
gEdkiiPeiMpServices2PpiGuid
--
2.28.0.windows.1
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+ Get CpuCacheInfo data array. The data array is sorted by CPU package ID from smallest to largest, + by core type from largest to smallest and by cache level from smallest to largest. Why is core type sorted from largest to smallest but the other twos are sorted from smallest to largest? What's the issue when sorting the core type value from smallest to largest? Thanks, Ray -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78494): https://edk2.groups.io/g/devel/message/78494 Mute This Topic: https://groups.io/mt/84478491/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Hi Ray, According to the definitions in SDM, the value of "Core" core type(40H) is larger than that of "Atom" core type(20H), if array is sorted by core type value from largest to smallest, “Core” CPU cache info can be placed before "Atom" CPU cache info in the CpuCacheInfo array. No matter how to sort the array by core type value, no issue will occur. The consumer of the array just need use the same sort rule to process the data of the array. [SDM definition] 1AH EAX Enumerates the native model ID and core type. Bits 31-24: Core type 10H: Reserved 20H: Intel Atom® 30H: Reserved 40H: Intel® Core™ -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78497): https://edk2.groups.io/g/devel/message/78497 Mute This Topic: https://groups.io/mt/84478491/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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