Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
In the case where the root bridge's Mem.Limit is the base address of
PCIe MMIO, subtract one to make a valid end address.
This fixes an issue where CpuDxe returns "Length(0x50000001) is not
aligned!" when PciHostBridgeDxe attempts to make this range uncacheable.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
index e231f747019e..0e3fee28b5d1 100644
--- a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
+++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c
@@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges (
if (PcdGet32(PcdPciReservedMemLimit) != 0) {
mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit);
} else {
- mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 (PcdPciExpressBaseAddress);
+ mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 (PcdPciExpressBaseAddress) - 1;
}
mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 (PcdPciReservedMemAbove4GBBase);
--
2.31.1
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Thanks for fixing this issue! Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> > -----Original Message----- > From: Benjamin Doron <benjamin.doron00@gmail.com> > Sent: Friday, July 23, 2021 10:27 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Liming Gao > <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com> > Subject: [PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple: Fix Mem.Limit > assignment > > In the case where the root bridge's Mem.Limit is the base address of PCIe > MMIO, subtract one to make a valid end address. > > This fixes an issue where CpuDxe returns "Length(0x50000001) is not > aligned!" when PciHostBridgeDxe attempts to make this range uncacheable. > > Cc: Chasel Chiu <chasel.chiu@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > Cc: Eric Dong <eric.dong@intel.com> > Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> > --- > > Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostB > ridgeLibSimple.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > index e231f747019e..0e3fee28b5d1 100644 > --- > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/P > +++ ciHostBridgeLibSimple.c > @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges ( > if (PcdGet32(PcdPciReservedMemLimit) != 0) > { mRootBridgeTemplate.Mem.Limit = PcdGet32 > (PcdPciReservedMemLimit); } else {- mRootBridgeTemplate.Mem.Limit = > (UINT32) PcdGet64 (PcdPciExpressBaseAddress);+ > mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 > (PcdPciExpressBaseAddress) - 1; } > mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 > (PcdPciReservedMemAbove4GBBase);-- > 2.31.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78118): https://edk2.groups.io/g/devel/message/78118 Mute This Topic: https://groups.io/mt/84393639/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of > Benjamin Doron > Sent: Thursday, July 22, 2021 7:27 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Liming Gao > <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com> > Subject: [edk2-devel] [PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple: > Fix Mem.Limit assignment > > In the case where the root bridge's Mem.Limit is the base address of PCIe > MMIO, subtract one to make a valid end address. > > This fixes an issue where CpuDxe returns "Length(0x50000001) is not > aligned!" when PciHostBridgeDxe attempts to make this range uncacheable. > > Cc: Chasel Chiu <chasel.chiu@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > Cc: Eric Dong <eric.dong@intel.com> > Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> > --- > > Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostB > ridgeLibSimple.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > index e231f747019e..0e3fee28b5d1 100644 > --- > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHos > tBridgeLibSimple.c > +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/P > +++ ciHostBridgeLibSimple.c > @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges ( > if (PcdGet32(PcdPciReservedMemLimit) != 0) { > mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit); > } else {- mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 > (PcdPciExpressBaseAddress);+ mRootBridgeTemplate.Mem.Limit = > (UINT32) PcdGet64 (PcdPciExpressBaseAddress) - 1; } > mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 > (PcdPciReservedMemAbove4GBBase);-- > 2.31.1 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#78112): https://edk2.groups.io/g/devel/message/78112 > Mute This Topic: https://groups.io/mt/84393639/1767664 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub > [nathaniel.l.desimone@intel.com] -=-=-=-=-=-= > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78318): https://edk2.groups.io/g/devel/message/78318 Mute This Topic: https://groups.io/mt/84393639/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
Patch pushed: 69e6a5e160551fdd09ce367e9c97c25d8683a3ac Thanks, Chasel > -----Original Message----- > From: Benjamin Doron <benjamin.doron00@gmail.com> > Sent: Friday, July 23, 2021 10:27 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L > <nathaniel.l.desimone@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; > Dong, Eric <eric.dong@intel.com> > Subject: [PATCH v2] MinPlatformPkg/PciHostBridgeLibSimple: Fix Mem.Limit > assignment > > In the case where the root bridge's Mem.Limit is the base address of PCIe MMIO, > subtract one to make a valid end address. > > This fixes an issue where CpuDxe returns "Length(0x50000001) is not aligned!" > when PciHostBridgeDxe attempts to make this range uncacheable. > > Cc: Chasel Chiu <chasel.chiu@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Liming Gao <gaoliming@byosoft.com.cn> > Cc: Eric Dong <eric.dong@intel.com> > Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> > --- > > Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBrid > geLibSimple.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBr > idgeLibSimple.c > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBr > idgeLibSimple.c > index e231f747019e..0e3fee28b5d1 100644 > --- > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciHostBr > idgeLibSimple.c > +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/P > +++ ciHostBridgeLibSimple.c > @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges ( > if (PcdGet32(PcdPciReservedMemLimit) != 0) > { mRootBridgeTemplate.Mem.Limit = PcdGet32 (PcdPciReservedMemLimit); } > else {- mRootBridgeTemplate.Mem.Limit = (UINT32) PcdGet64 > (PcdPciExpressBaseAddress);+ mRootBridgeTemplate.Mem.Limit = (UINT32) > PcdGet64 (PcdPciExpressBaseAddress) - 1; } > mRootBridgeTemplate.MemAbove4G.Base = PcdGet64 > (PcdPciReservedMemAbove4GBBase);-- > 2.31.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78319): https://edk2.groups.io/g/devel/message/78319 Mute This Topic: https://groups.io/mt/84393639/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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