If CET shadows stack feature enabled in SMM and stack switch is enabled.
When code execute from SMM handler to SMM exception, CPU will check SMM
exception shadow stack token busy bit if it is cleared or not.
If it is set, it will trigger #DF exception.
If it is not set, CPU will set the busy bit when enter SMM exception.
So, the busy bit should be cleared when return back form SMM exception to
SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF
exception when enter SMM exception next time.
So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the
shadow stack token busy bit before RETF instruction in SMM exception.
Since open CI is using NASM 2.14.02, it has not supported CET instructions
yet. DB-encoded CET instructions will to be removed after open CI update to
 NASM 2.15.01.
In function InitGdt(), SmiPFHandler() and Gen4GPageTable(), it uses
 CpuIndex * mSmmStackSize to get the SMM stack address offset for
 multi processor. It misses the SMM Shadow Stack Size. Each processor
 will use mSmmStackSize + mSmmShadowStackSize in the memory.
It should use CpuIndex * (mSmmStackSize + mSmmShadowStackSize) to get
 this SMM stack address offset. If mSmmShadowStackSize > 0 and multi
 processor enabled, it will get the wrong offset value.
CET shadow stack feature will set the value of mSmmShadowStackSize.

Change from patch v1 to patch v2:
1 Add behavior description in source code comment.
2 Structure interrupt shadow stack memory in InitShadowStack().
3 Update commit comment.

Change from patch v2 to patch v3:
1 Add comment /UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c

Change from patch v3 to patch v4:
Update comment and commit message.

Change from patch v4 to patch v5:
Update commit message.

Change from patch v5 to patch v6:
Patch 1/3 add Review-by
Patch 2/3 add Review-by
Patch 3/3 add a bug fix of SMM stack address offset for muilt processor

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Roger Feng <roger.feng@intel.com>

Sheng Wei (3):
  MdePkg/Include: Add CET instructions to Nasm.inc
  UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy
    bit
  UefiCpuPkg/PiSmmCpuDxeSmm: Fix SMM stack offset is not correct

 MdePkg/Include/Ia32/Nasm.inc                       | 12 ++++++
 MdePkg/Include/X64/Nasm.inc                        | 12 ++++++
 .../DxeCpuExceptionHandlerLib.inf                  |  3 ++
 .../PeiCpuExceptionHandlerLib.inf                  |  3 ++
 .../SecPeiCpuExceptionHandlerLib.inf               |  4 ++
 .../SmmCpuExceptionHandlerLib.inf                  |  3 ++
 .../X64/Xcode5ExceptionHandlerAsm.nasm             | 46 +++++++++++++++++++++-
 .../Xcode5SecPeiCpuExceptionHandlerLib.inf         |  4 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c              |  6 ++-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c            |  4 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c       | 17 +++++++-
 11 files changed, 107 insertions(+), 7 deletions(-)

-- 
2.16.2.windows.1



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