If CET shadows stack feature enabled in SMM and stack switch is enabled.
When code execute from SMM handler to SMM exception, CPU will check SMM
exception shadow stack token busy bit if it is cleared or not.
If it is set, it will trigger #DF exception.
If it is not set, CPU will set the busy bit when enter SMM exception.
The busy bit should be cleared when return back form SMM exception to SMM
handler. Otherwise, keeping busy bit in set state will cause to trigger
#DF exception when enter SMM exception next time.
So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the
shadow stack token busy bit before RETF instruction in SMM exception.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Sheng Wei (2):
MdePkg/Include: Add CET instructions to Nasm.inc
UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy
bit
MdePkg/Include/Ia32/Nasm.inc | 14 ++++++++++-
MdePkg/Include/X64/Nasm.inc | 14 ++++++++++-
.../DxeCpuExceptionHandlerLib.inf | 3 +++
.../PeiCpuExceptionHandlerLib.inf | 3 +++
.../SecPeiCpuExceptionHandlerLib.inf | 4 ++++
.../SmmCpuExceptionHandlerLib.inf | 3 +++
.../X64/Xcode5ExceptionHandlerAsm.nasm | 28 +++++++++++++++++++++-
.../Xcode5SecPeiCpuExceptionHandlerLib.inf | 4 ++++
8 files changed, 70 insertions(+), 3 deletions(-)
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#70896): https://edk2.groups.io/g/devel/message/70896
Mute This Topic: https://groups.io/mt/80205204/1787277
Mute #df:https://edk2.groups.io/g/devel/mutehashtag/df
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org]
-=-=-=-=-=-=-=-=-=-=-=-