MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2989
Long times spent on shadowing oprom from graphics card to system memory. We are currently using 8 bit read cycles.
This needs to be wider, at least 32bit (even 64bit) reads to reduce the time for oprom shadow
Signed-off-by: Sumana Venur <sumana.venur@intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
index c994ed5fe3..fe6c7db417 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c
@@ -521,7 +521,7 @@ LoadOpRomImage (
//
PciDevice->PciRootBridgeIo->Mem.Read (
PciDevice->PciRootBridgeIo,
- EfiPciWidthUint8,
+ EfiPciWidthUint64,
RomBar,
(UINT32) RomImageSize,
Image
--
2.16.2.windows.1
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On 01/07/21 07:29, Sumana Venur wrote: > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2989 > > Long times spent on shadowing oprom from graphics card to system memory. We are currently using 8 bit read cycles. > This needs to be wider, at least 32bit (even 64bit) reads to reduce the time for oprom shadow > > Signed-off-by: Sumana Venur <sumana.venur@intel.com> > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c > index c994ed5fe3..fe6c7db417 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciOptionRomSupport.c > @@ -521,7 +521,7 @@ LoadOpRomImage ( > // > PciDevice->PciRootBridgeIo->Mem.Read ( > PciDevice->PciRootBridgeIo, > - EfiPciWidthUint8, > + EfiPciWidthUint64, > RomBar, > (UINT32) RomImageSize, > Image > This has three bugs: (1) From the UEFI specification v2.8B, EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Mem.Read(): The caller is responsible for satisfying any alignment and memory width restrictions that a PCI Root Bridge on a platform might require. For example on some platforms, width requests of EfiPciWidthUint64 do not work. I don't think the patch ensures that EfiPciWidthUint64 is safe on the particular platform. (2) RomImageSize (the Count parameter) is expressed in bytes, currently. If you scale up the access width, you have to scale down the access count. (3) If you use an access size that is larger than 1 byte, you have to handle the tail separately. For example, if the access width is EfiPciWidthUint32, and the ROM image size is (4*k+3) bytes, then the tail needs to be handled separately. Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#69921): https://edk2.groups.io/g/devel/message/69921 Mute This Topic: https://groups.io/mt/79498239/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
I have submitted an updated patch. 1. Reduced the width to 32 to be safer 2. Sorry about not scaling the count down, missed it while preparing patch. 3. According to Pci Firmware Spec 3.0, section 5.1.2 Expansion Rom Image length is in units of 512 bytes, so I understand that we dont need to handle the tail -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#70004): https://edk2.groups.io/g/devel/message/70004 Mute This Topic: https://groups.io/mt/79498239/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=-=-=-=-=-=-=-=-=-=-=-
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